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pg100 Axi Emc
Chapter 1: Overview
Module Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Appendix C: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
memory devices. The core provides an AXI4 Resources See Table 2-2 to Table 2-4.
Slave Interface that can be connected to AXI4
Master or Interconnect devices in the AXI4 Provided with Core
Systems.
Design Files VHDL
Constraints File
VHDL
XDC
Simulation
• Supports AXI4 Slave Memory Map interface N/A
Model
data width of 32 and 64 bits
Supported
• Supports optional AXI4-Lite Slave data S/W Driver (2)
Standalone
width of 32 bits for Write/Read registers
Tested Design Flows(3)
• Supports AXI4 increment and wrap
transactions Design Entry Vivado® Design Suite
For a list of supported simulators, see the
• Supports AXI4 narrow and unaligned Simulation
Xilinx Design Tools: Release Notes Guide
transfers
Synthesis Vivado Synthesis
• Supports up to four external memory banks
Support
• Supports Synchronous SRAMs with
configurable byte parity check and pipeline Provided by Xilinx at the Xilinx Support web page
stages Notes:
• Supported memory types 1. For a complete list of supported devices, see the Vivado IP
catalog.
° Synchronous SRAM 2. Standalone driver details can be found in the SDK directory
(<install_directory>/SDK/<release>/data/embeddedsw/doc/
° Asynchronous SRAM xilinx_drivers.htm). Linux OS and driver support information is
available from the
Linear Flash (or Parallel NOR Flash) Xilinx Wiki page.
°
3. For the supported versions of the tools, see the
° PSRAM (or Cellular RAM) Xilinx Design Tools: Release Notes Guide.
Overview
The architectural block diagram of the AXI External Memory Controller (EMC) core is shown
in Figure 1-1.
\
X-Ref Target - Figure 1-1
Bank3_MEM
AXI4-Lite SRAM Parity Error Address Registers
Interface
PSRAM/Flash Configuration Registers
X13185
Figure 1-1: Top Level Block Diagram of the AXI EMC Core
The AXI EMC core provides the memory controller functionalities for PSRAM, flash, and
SRAM technologies. The controller supports memory devices from multiple vendors and
also allows interfacing to multiple of these memory technologies (or types) by supporting
up to four memory banks. The core provides an AXI4 Slave interface for addressing and
accessing data from the connected memory devices.
The core also provides optional AXI4-Lite interface for configuring access mechanisms as
defined by the connected memory types. In addition, the controller provides a set of core
generation parameters which defines the memory interface timing for the connected
memories.
Module Descriptions
The AXI EMC operations can be categorized into seven modules:
The AXI4 interface of the core also performs the channel arbitration and address decoding
functionalities. The channel arbitration implements a round robin algorithm and is
applicable only when both AXI4 write channels and AXI4 read channels are active
simultaneously. The address decoding logic utilizes the AXI4 address to determine the bank
address and read/write address in the selected memory bank. For more details on Memory
Address Generation, see Address Map Description in Chapter 3.
The performance of AXI EMC core gets determined by Memory Width, Memory access
latencies and AXI burst size. In general larger AXI4 burst sizes can increase the overall
performance of the core. For more details on EMC core performance, see Performance in
Chapter 2.
Note: The AXI4 FIXED transactions are not supported by the core and when issued can result in
nondeterministic core behavior.
AXI4-Lite Interface
AXI EMC core provides AXI4-Lite slave interface to allow access to Internal Control and
Status registers of the core. The AXI4 slave interface of the core complies with AMBA
AXI4-Lite protocol specifications for 32-bit data width. The AXI4-Lite interface of the core is
optional and is enabled only when the Enable Internal registers option is set. For more
details on Core registers accessible through the AXI-Lite interface, see EMC Register.
The Memory Controller Unit in addition aligns the address and data received from the AXI4
interface module to match the address and data width configured for the bank. Different
data widths for various banks are now only supported when selected memory is
Synchronous/Asynchronous SRAM. For other memory types, data widths have to be same
across banks. The width conversion in this case is performed dynamically as per the width
defined for each memory bank.
The Memory interface timing for the asynchronous memory interfaces are parameterized
and can be set independently for each bank. The Memory Controller Unit maintains internal
counters and registers to match the interface timing as defined by these parameters. For
more details on memory timing parameters, see Customizing and Generating the Core in
Chapter 4. In addition for configuration registers associated with PSRAM/Flash memories,
see Register Description in Chapter 2. For example memory interfaces and associated
memory settings, see Connecting to Memory in Chapter 3.
EMC Register
There are two register sets in the EMC Register Module: the Parity Error Address register
(PERR_ADDR_REG_x) and the PSRAM/Micron ® Technology Flash Configuration register
(PSRAM_FLASH_CONFIG_REG_x). The PERR_ADDR_REG_x registers contain the address for
the parity error that occurred. The PSRAM_FLASH_CONFIG_REG_x register is provided to
configure the PSRAM or flash memory access mechanisms such as operation mode for the
memory. For more details on Configuration and Status registers, see Register Description in
Chapter 2.
I/O Registers
The I/O register module provides additional timing control for synchronous SRAM
memories. All input/output signal on the memory interface is driven on the rising edge of
the EMC clock.
For more information see the UltraScale Architecture Libraries Guide (UG974) [Ref 2].
Application
Figure 1-2 shows an example of the AXI EMC core use case.
mem_a[Max-1:0] A[Max-1:0]
mem_dq[15:0] DQ[15:0]
Async/Page
mem_wen WE# Cellular RAM
LB#/UB# Memory
mem_ben
mem_oen(1)
mem_oen OE#
mem_ce(1) CS#
AXI EMC
Controller
A[Max-1:0]
DQ[15:0]
WE# Async/Page
mem_oen(0) Flash
OE# Memory
mem_ce(0) CS#
BYTE#
X13184
The CellularRAM shown in the use case is a volatile Pseudo SRAM and can be used for
cached or buffered memory applications. The AXI EMC core here allows the flash memory
or Cellular RAM to be dynamically configured for asynchronously read operations or
synchronously page read operations. The low latency and high performance AXI EMC core
in this use case is ideally suited for eXecute In Place (XIP) system memory solutions.
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx
Intellectual Property page. For information on pricing and availability of other Xilinx
LogiCORE IP modules and tools, contact your local Xilinx sales representative.
Product Specification
This chapter contains details about the performance and ports of the core.
Standards Compliance
This core has bus interfaces that comply with the ARM ® AMBA® AXI4 Protocol Specification
Version 1.0 [Ref 1].
Performance
The performance and resource utilization numbers for the AXI EMC core are generated from
a common benchmarking setup implementing a multi-masters/multi-slave AXI4 system.
The AXI EMC core is characterized as per the benchmarking methodology described in
“Vivado IP Optimization (FMax Characterization) appendix,” in the Vivado Design Suite User
Guide: Designing with IP (UG896) [Ref 3].
Maximum Frequencies
The maximum frequencies for AXI EMC are provided in Table 2-1.
Note: Performance numbers for UltraScale™ architecture and Zynq®-7000 devices are expected to
be similar to 7 series device numbers.
Table 2-1: Maximum Frequencies
FMax (MHz)
Family Speed Grade
AXI4 AXI4-Lite
Virtex-7 200 180
Kintex-7 –1 200 180
Artix-7 150 120
Virtex-7 240 200
Kintex-7 –2 240 200
Artix-7 180 140
Resource Utilization
Note: UltraScale architecture results are expected to be similar to 7 series device results.
The AXI EMC resource utilization for various parameter value combinations measured with
a Virtex® -7 device are detailed in Table 2-2.
The AXI EMC resource utilization for various parameter value combinations measured with
a Kintex ®-7 and Zynq-7000 device are detailed in Table 2-3.
Table 2-3: Device Utilization – Kintex-7 and Zynq-7000 (Kintex-7 Based) FPGAs
Parameter Values Device Resources
Enable
Memory AXI Enable No. of
Pipe Parity Data Data Data Memory Internal Memory LUTs FFs Slices FMax
Delay Width Type (MHz)
Matching Width Width Registers Banks
The AXI EMC resource utilization for various parameter combinations measured with an
Artix ®-7 device are detailed in Table 2-4.
Port Descriptions
The I/O signals are listed and described in Table 2-5.
Notes:
1. The same clock and reset signals should be used for both the register and memory interfaces.
2. This clock is used to capture the data from memory. Xilinx recommends that this clock is tied with AXI Clock source.
3. The AXI4-Lite interface is optional and is provided only when the Enable Internal Registers option is set.
4. This pin is only enabled when parity type selected is either odd parity or even parity in the Vivado IDE.
5. Most asynchronous memory devices only use mem_cen. Most synchronous memory devices use both mem_cen and
mem_ce.
6. All mem_* ports have IOB attributes set to TRUE when STARTUP is not included in the design.
7. All mem_* ports except mem_dq_*[3:0] and mem_cen[0] which are connected to STARTUP have IOB attributes set TRUE when
STARTUP is included in the design.
8. Write commands to Flash should be issued with awlen=0.
Register Description
There are four internal registers in the AXI EMC design (Table 2-6). The memory map of the
AXI EMC registers is determined by setting the Base Address in the Address Editor tab of the
Vivado IP integrator. The internal registers of the AXI EMC are at a fixed offset from the base
address and are byte accessible. The AXI EMC internal registers and their offset are listed in
Table 2-6.
Notes:
1. Based upon the no. of banks chosen, only those no. registers are available and accessible for read and write-if allowed.
2. Other registers are considered as nonexistent and AXI transaction returns gracefully if accessed.
3. A write transaction will be executed only when AWVALID and WVALID are asserted. The AWREADY is gated by assertion of
WVALID and vice-versa.
There can be four PARITY_ERR_ADDR_REG registers. Whenever a parity error occurs for a
AXI read operation, the AXI EMC core updates this register with the address at which the
error occurred. The Parity Error Address register is shown in Figure 2-1 and described in
Table 2-7.
X-Ref Target - Figure 2-1
31 0
DS762_04
• PSRAM memory when AXI4-Lite interface is enabled and Memory Type selected for the
bank is PSRAM.
• Flash memories in burst mode when AXI4-Lite interface is enabled, Memory Type
selected for the bank is Micron ® Flash, and Burst mode for Micron Flash memory is
enabled.
The number of such registers depends on the Number of Memory Banks set for the core
and the Memory Type selected in the associated Memory Bank.
IMPORTANT: For Memory Types selected across memory banks, see Allowable Memory Combination in
Chapter 3.
Operational Mode
CRE RM Reserved for Burst Mode
Reserved CRE Drive Signal
31 30 7 6 5-2 1-0
DS762_05
Notes:
1. For Latency configurations and access details, see the respective PSRAM data sheet.
The Read Configuration register is in the flash memory. The address for accessing this
register is set as Memory Bank Base address+ 32’h0000_509F.
Table 2-9: Micron Flash Sync Mode – Read Configuration Register (RCR)
Read Configuration Register (RCR)
Read Latency Count WAIT RES WAIT Burst CLK RES RES Burst Burst Length
Mode Polarity Delay Seq Edge Wrap
RM LC[3:0] WP R WD BS CE R R BW BL[2:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 1 0 0 0 0 1 0 0 1 1 1 1
Note: The RCR settings are specific for the P30 flash family and slower speeds. The Micron P30/P33
and G18F/MT28GU01GAAA1E families should be supported and RCR recommendations referenced.
The guideline for configuring the Sync Read Mode for Micron Flash are as follows. This
process is applicable to the memory bank with Memory Type configured for Micron Flash.
• By default the Micron Flash operates in Asynchronous mode. These settings are
required while switching the read operation of memory from Asynchronous Read to
Synchronous Read.
• Set Bits[31:30] of PSRAM_FLASH_CONFIG_REG_X register for selected memory bank to
1.
• Drive the value of Memory Bank Base address+ 0x0000_589E on AXI write address bus
with 0x0300_0060 on AXI write data bus. This should be of single beat transaction.
• Drive the value of Memory Bank Base address+ 0x0000_589E on AXI write address bus
with 0x6000_0003 on AXI write data bus. This should be of single beat transaction.
• The previous two steps write 589E into the Read Configuration register of the Micron
Flash.
• Reset Bit[31] of the PSRAM_FLASH_CONFIG_REG_X register for selected memory bank
to continue with normal memory read/writes.
• The AXI EMC core behavior is designed on the basis of the above register bit settings,
for any other bit settings the core behavior is not guaranteed.
• While switching from Sync to Async mode, the Sync mode settings of memory should
be disabled by resetting the Read Configuration register (Bit[15]) to 1. After this bit is
reset, set the AXI EMC cores internal registers Bit[30] to 0.
• After both the core and memory are reset with the bit settings mentioned above, the
memory and the core operates in Asynchronous Read mode.
IMPORTANT: When CRE bit in PSRAM_FLASH_CONFIG_REG_X (Bit[31]) is set to “1,” then the core would
ignore value driven in wstrb bus and would always transfer the LSB bytes of wdata bus to the Memory
Interface.
If the pin does not have a pull-down register connected, the WAIT pin is a 3-state output from the flash.
It is recommended to change the polarity of WAIT to active-High in Read Configuration register of the
Micron Flash and connect to EMC through an inverter.
AXI EMC core also supports internal registers for Memory configurations. These registers
are enabled by setting the Enable Internal register option. The memory map for these
internal registers get determined by the Base Address settings for the AXI EMC core in the
Address Editor tab of Vivado IP integrator. For more detail on AXI EMC core internal register
configurations, see Register Description in Chapter 2.
Each row is a group of acceptable memory combinations. Memories between different rows
cannot be mixed within the same Memory Controller.
Note: By default PSRAM/Micron® operate in asynchronous mode. Select the Enable Internal
Registers option while customizing the AXI EMC core if PSRAM/Micron needs to operate in other
modes.
• Byte (8-bit)
• Halfword (16-bit)
• Word (32-bit)
• Doubleword (64-bit)
Data to and from the AXI interface is organized as little-endian. The bit and byte labeling for
the big-endian data types is shown in Figure 3-1.
Bit label 63 0
Bit label 31 0
Bit label 15 0
Byte address n
Bit label 7 0
Connecting to Memory
Clocking Synchronous Memory
The AXI EMC core does not provide a clock output to any synchronous memory. The AXI
clock should be routed through an ODDR module to provide the clock to synchronous
memory. To synchronize the synchronous memory clock to the internal FPGA clock, the
FPGA system design should include a Mixed Mode Clock Manager (MMCM), external to the
AXI EMC core, that uses the synchronous memory clock input as the feedback clock as
shown in Figure 3-2. The synchronous clock output from the FPGA must be routed back to
the FPGA on a clock pin.
)3*$
6B$;,B$&/.
&/.,1 &/. 2''5
([WHUQDO&ON %8)*
&/.)%
6\QFPHPB&ONBIE 'LJLWDO&ORFN0DQDJHU
'&0 $;,(0&
6\QFPHPB&ON
6\QFKURQRXV0HPRU\%DQN
Figure 3-2: Synchronous Memory Bank Clocked by FPGA Output with Feedback
The following constraint has to be added in XDC when clock to Synchronous RAM is
forwarded through ODDR:
Because forwarded clock is 180° out-of-phase, the data is to be latched on second rising
edge, the following constraints need to be set:
If the synchronous memory is clocked by the same external clock as the FPGA, or if the clock
feedback is not available, the DCM shown in Figure 3-3 should be included in the FPGA
external to the AXI EMC core.
)3*$
6B$;,B$&/.
&/.,1 &/. $;,(0&
([WHUQDO&ON %8)*
&/.)%
0L[HG0RGH&ORFN0DQDJHU
00&0
&ON
6\QFKURQRXV0HPRU\%DQN
IMPORTANT: By default, Micron Flash memories operate in asynchronous read mode. To operate
Micron Flash in synchronous mode:
(a) Select Enable Internal Registers option while customizing the AXI EMC core.
(b) See the Core register Configuration and Memory Configuration section.
2. In all IP operating modes, Xilinx recommends that the same clock is connected to both
rdclk and s_axi_aclk ports.
Note: Most asynchronous memory devices only use MEM_CEN, while most synchronous memory
devices use both MEM_CEN and MEM_CE. MEM_CEN is a function of the address decode while
MEM_CE is a function of the state machine logic.
For Address and Data connections to the external memory devices, see Tables 3-3, 3-5, 3-7,
3-9, 3-11, 3-13 and 3-15. In addition, Table 3-2 shows variables used in defining memory
subsystem.
Notes:
1. The value of X depends on variables MW, AU and DW.
Connecting to SRAM
Table 3-3: Core To Memory Interconnect
Description AXI EMC Signals (MSB:LSB) Memory Device Signals (MSB:LSB)
Data bus MEM_DQ(((DN + 1) × DW) – 1:DN × DW) D(DW – 1:0)
Address bus MEM_A(MAW – AS – 1:AS) A(MAW – 1:0)
Chip enable MEM_CEN(BN) CEN
(active-Low)
Output enable MEM_OEN OEN
(active-Low)
Write enable MEM_WEN WEN (for devices that have byte enables)
(active-Low)
Qualified write enable MEM_QWEN(DN × DW/8) WEN (for devices that do not have byte
(active-Low) enables)
Byte enable MEM_BEN((((DN + 1) × DW/8) – 1):(DN × BEN(DW/8 – 1:0)
(active-Low) DW/8))
Table 3-5 shows connection to 32-bit memory using two IDT71V416S (256K × 16-bit) parts.
Table 3-7 shows the connection to 32-bit memory using two IDT71V416S (256K × 16-bit)
parts.
Table 3-9 shows the connection to 32-bit memory using two StrataFlash parts.
Table 3-11 shows the connection to 32-bit memory using four StrataFlash parts.
Table 3-11: Connection to 32-bit Memory Using Four StrataFlash Parts (Cont’d)
Notes:
1. In an x8 configuration, DQ(15:8) are not used and should be treated according to the data sheet of the manufacturer.
Table 3-12: Variables for Page Mode Flash (x16 mode) Example
Variable Value Definition
BN 0 Memory bank number
Memory device number within a bank. The memory device attached to the most
DN 0
significant bit in the memory subsystem is 0.
MW 32 Width in bits of memory subsystem
DW 16 Width in bits of data bus for memory device
MAW 21 Width in bits of address bus for memory device
AU 16 Width in bits of smallest addressable data word on the memory device
AS 1 Address shift for address bus = log 2((MW × AU/DW)/8)
HAW 32 Width in bits of host address bus (for example, AXI)
Table 3-13: Connection to 16-bit Memory Using Page Mode Flash Parts
PagemModeFlash Signals
DN Description AXI EMC Signals (MSB:LSB) (MSB:LSB)
Data bus MEM_DQ(15:0) DQ(15:0)
Address bus MEM_A(22:1) A(21:0)
Chip enable (active-Low) MEM_CEN(0) CE
Output enable (active-Low) MEM_OEN OE#
0
Write enable (active-Low) MEM_QWEN(0) WE#
Reset/Power down (active-Low) MEM_RPN RP#
Byte mode select (active-Low) N/A - tie to VCC BYTE#
Program enable (active-High) N/A - tie to VCC WP#
Connecting to PSRAM
Table 3-14: Variables PSRAM (x16 mode) Example
Variable Value Definition
BN 0 Memory bank number
Memory device number within a bank. The memory device attached to the most
DN 0
significant bit in the memory subsystem is 0.
MW 32 Width in bits of memory subsystem
DW 16 Width in bits of data bus for memory device
MAW 23 Width in bits of address bus for memory device
AU 16 Width in bits of smallest addressable data word on the memory device
AS 1 Address shift for address bus = log 2((MW × AU/DW)/8)
HAW 32 Width in bits of host address bus (for example, AXI)
Software Considerations
Absolute memory addresses are frequently required for specifying command sequences to
flash memory devices.
IMPORTANT: Due to the memory address shift (AS), any absolute addresses that must appear on the
memory device address bus must also have the source AXI address left-shifted to compensate for the
AS.
All of the EMC Memory interface pins except for mem_cre, mem_wait, and mem_a (for
Micron Flash in Sync mode) are registered I/Os. Xilinx recommends having these flops
placed in the FPGA I/O pins.
All of the Memory interface pins which are applicable to connected memory (from Table 3-2
to Table 3-15) except for Address, CRE, and WAIT should be constrained to have the flops
placed. The following is an example of constraint that can be added in XDC:
For ports Address, CRE, and WAIT the constrains can be the following:
See the answer records or the device user guide to understand more about the functionality
and use of the STARTUP primitive.
• The mem_dq_*[3:0] and mem_cen[0] ports from the core are interfaced with the
STARTUP primitive. The STARTUP can also be used in the pre-configuration process of
the FPGA where the external slave memory is configured prior to the FPGA.
• After configuration of the FPGA, the mem_dq_*[3:0] and mem_cen[0] ports drive
the corresponding ports of the primitive which are directly connected to external slave
memory. These signals are not available as the external port of the core.
• Instantiating STARTUP affects the maximum frequency of s_axi_aclk and rdclk.
• As the mem_dq_*[3:0] and mem_cen ports are part of the core and no primitive is
instantiated in the core, these ports are available as external ports of the core and they
are placed in an IOB at a user-configured location.
Timing Diagrams
Figure 3-4 is the read timing representation for Sync SRAM memories.
X-Ref Target - Figure 3-4
Figure 3-4: Read Timing Representation of 32-bit Sync SRAM with Pipeline Delay 2
Figure 3-5 is the write timing representation for Sync SRAM memories.
X-Ref Target - Figure 3-5
Figure 3-5: Write Timing Representation of 32-bit Sync SRAM with Pipeline Delay 2
Figure 3-6 is the read timing representation for Async SRAM memories.
X-Ref Target - Figure 3-6
Figure 3-7 is the write timing representation for Async SRAM memories.
Figure 3-8 is the read timing representation for Linear Flash memories.
X-Ref Target - Figure 3-8
Figure 3-9 is the write timing representation for Linear Flash memories.
X-Ref Target - Figure 3-9
Figure 3-10 is the read timing representation for Page Mode Flash memories.
X-Ref Target - Figure 3-10
Figure 3-10: Read Timing Representation for Page Mode Flash Memories
Figure 3-11 is the read timing representation for Micron Flash memories.
X-Ref Target - Figure 3-11
Figure 3-12 is the write timing representation for Micron Flash memories.
X-Ref Target - Figure 3-12
Figure 3-13 is the Sync Read timing representation for Micron Flash memories.
X-Ref Target - Figure 3-13
Figure 3-13: Sync Read Timing Representation for Micron Flash Memories
The sequence of Read/Write operations is updated to have one cycle difference between
Address bus and CE/CEN and OEN/WEN both during assertion and deassertion from
2015.3.
• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
[Ref 5]
• Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 3]
• Vivado Design Suite User Guide: Getting Started (UG910) [Ref 6]
• Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 7]
If you are customizing and generating the core in the IP integrator, see the Vivado Design
Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 5] for detailed
information. IP integrator might auto-compute certain configuration values when
validating or generating the design. To check whether the values do change, see the
description of the parameter in this chapter. To view the parameter value you can run the
validate_bd_design command in the Tcl Console.
You can customize the IP for use in your design by specifying values for the various
parameters associated with the IP core using the following steps:
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 3] and
the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 6].
Note: Figures in this chapter are illustrations of the Vivado IDE. This layout might vary from the
current version.
Figure 4-1 shows the Customize IP dialog box for AXI EMC.
X-Ref Target - Figure 4-1
AXI ID Width
ID width of AXI interface, allowed values are 0 to 16.
Note: For IP integrator, ID Width is auto-computed which means that you are not allowed to
override it.
Base Address
Per Bank Base Address for the Memory, the base address for each enabled bank must be set
as per the System Address Map requirement. For more details on Memory Address
Generation, see Address Map Description, page 21.
High Address
Per Bank High Address for the Memory, the High address for each enabled bank must be set
as per the System Address Map requirement. For more details on Memory Address
Generation, see Address Map Description, page 21.
This parameter determines if STARTUP Primitive instantiation is within the IP or outside of it.
Figure 4-2 shows the Customize IP dialog box for each memory bank of AXI EMC core.
X-Ref Target - Figure 4-2
Memory Type
Memory Type for the selected bank can configured as Sync SRAM, Async SRAM, Linear
Flash, Page Mode Flash, PSRAM, or Micron Flash. For the supported memory combinations
across memory banks, see Allowable Memory Combination, page 22.
Data Width
Memory data width for the selected bank, Data Width of the Memory connected to the
bank can be set as 8, 16, 32, or 64 bits wide.
Parity
Parity is applicable only when Memory Type selected for the bank is Sync SRAM. Parity for
the memory can be set as No parity, Odd Parity, or Even Parity.
Delay Model
This configuration option is applicable only when Memory Type selected for the bank is
Sync SRAM. The Delay Model for the Sync SRAM can be set as a Flow-Through model or
Pipeline Model. See Timing Diagrams, page 34.
IMPORTANT: Read cycle time for AXI EMC core is determined by Read CE Low to Data Valid Period and
Read Address Valid to Data Valid Period configuration settings and is the Maximum[Read CE Low to
Data Valid Period, Read Address Valid to Data Valid Period].
IMPORTANT: Read cycle recovery to write period for AXI EMC core is determined by Read CE High to
Data Bus HZ Period and Read OE High to Data Bus HZ Period configuration settings and is the
MAXIMUM[Read CE High to Data Bus HZ Period, Read OE High to Data Bus HZ Period].
The AXI EMC core uses this parameter to hold CEN Low for each write at the memory
interface.
The AXI EMC core uses this parameter to hold WEN Low for each write at the memory
interface.
IMPORTANT: CEN Low and WEN Low time generated by the AXI EMC core is determined by Write Cycle
Period and Write Enable Minimum Pulse Width configuration settings. It is the MAXIMUM[Write Cycle
Period, Write Enable Minimum Pulse Width].
The AXI EMC core uses this parameter to determine the number of NOP cycles between two
consecutive writes at the memory side. When this parameter is set to zero, CEN goes High
for one clock cycle between writes.
The AXI EMC core uses this parameter to determine the number of NOP cycles at memory
interface after each AXI WLAST.
RECOMMENDED: You should provide the value for C_AXI_CLK_PERIOD_PS which is equivalent to AXI
clock used. This value is used for internal calibration of counters when Asynchronous memories are
used. By default this is set to 10,000 which is a value corresponding to 100 MHz AXI clock.
If the AXI clock connected is not 100 MHz, the parameter has to be set using command
"set_property CONFIG.C_AXI_CLK_PERIOD_PS {time period in picoseconds of AXI
clock} [get_ips <component name of emc IP created>]" in the Tcl Console.
Figure 4-3 to Figure 4-5 show the AXI EMC timing diagrams.
X-Ref Target - Figure 4-3
Figure 4-6 shows the Customize IP dialog box with the Advanced Configuration tab of AXI
EMC core.
X-Ref Target - Figure 4-6
Figure 4-7 shows the Customize IP dialog box with the Summary tab of AXI EMC core.
X-Ref Target - Figure 4-7
User Parameters
Table 4-1 shows the relationship between the fields in the Vivado IDE and the User
Parameters (which can be viewed in the Tcl Console).
Notes:
1. Parameter values are listed in the table where the Vivado IDE parameter value differs from the user parameter value. Such
values are shown in this table as indented below the associated parameter.
2. Applicable only for Async Memories and flashes should be bases on memory data sheet.
3. “*” depends on number of banks selected, ranges from 0 to “C_NUM_BANKS_MEM – 1.”
Output Generation
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 3].
Required Constraints
If external pull-ups/pull-downs are not available on the MEM_DQ signals, these constraints
should be specified to use pull-up or pull-down resistors, as in this example:
STARTUP is enabled: The operation frequency of AXI EMC is affected when a STARTUP
primitive is enabled. This primitive has its own delay that is not accounted in the entire
implementation/timing process.
STARTUPE3 primitive is used to drive the Data pins to the flash. When using the STARTUP
primitive, the clock-data relationship changes due to the extra delay added in the data pins
path. This delay can vary from as low as 0.1 ns to as high as 7.5 ns based on the device and
speed grade. This value can be found in the FPGA data sheet.
Because this delay is not timed by the tool, you must consider the maximum delay for all
calculations. Assume this delay is called CCLK_DELAY. For K7-2 this value can range from
0.5 ns to 6.7 ns. This puts the first restriction on the frequency of the clock. The frequency
of operation cannot exceed F Max1 = (1/CCLK_DELAY) MHz.
Constraining the IP
To understand how the constraints are added, it is important to understand the logic
structure around the data pins in AXI EMC and BPI flash memory.
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The STARTUP primitive adds delay on the data[3:0] pins. This delay is unaccounted for in the
tool and is not considered in the timing calculation. For the tool, the timing path ends at
data[3:0] internal flops.
To obtain the required constraints you must account for the STARTUP primitive delay.
This takes into account the delay of the flip-flop that generates the data, the routing delay
from that flip-flop to Data pins, and the STARTUP primitive delay. Further, to reduce the
delay on data pins you must ensure that the delay from the flip-flop to pin is as low as
possible. This can be constrained by using set_output_delay and set_input_delay
constraints.
Clock Frequencies
The IP reads the clock frequency value in IPI. This value is then used to calculate the various
timing parameters.
Clock Management
This section is not applicable for this IP core.
Clock Placement
This section is not applicable for this IP core.
Banking
This section is not applicable for this IP core.
Transceiver Placement
This section is not applicable for this IP core.
Simulation
For comprehensive information about Vivado simulation components, as well as
information about using supported third-party tools, see the Vivado Design Suite User
Guide: Logic Simulation (UG900) [Ref 7].
IMPORTANT: For cores targeting 7 series or Zynq-7000 AP SoC devices, UNIFAST libraries are not
supported. Xilinx IP is tested and qualified with UNISIM libraries only.
Example Design
This chapter contains information about the example design provided in the Vivado®
Design Suite.
The top-level example design for the AXI EMC core is <component_name>_exdes.vhd.
The complete example design works as a mini-system to show the AXI EMC functionality by
performing read and write transactions to memory model (Figure 5-1).
X-Ref Target - Figure 5-1
<component_name>_exdes.vhd (top)
clk_n
clk_p Clock
Generator Data Read/Write
reset Logic
X13764
• Clock Generator – EMC example design makes use of the clocking wizard to supply
clocks and resets to all other blocks in the design. The clocking wizard is configured to
provide 100 MHz clock to all the blocks, and the locked signal from the wizard is
appropriately used as Resets.
• Memory – Block Memory Generator (BMG) core is used to serve for memory storage in
the example design. It is configured for 32 × 1,024 memory whose first 256 locations
are initialized using a coefficient file. The example design uses the first half of the BMG
as the source of data to write data to the memory model through EMC, and it uses the
second half to store data read from model through EMC.
• Data Read/Write Path – Example design uses the Central Direct Memory Access
(CDMA) core to generate the required AXI instructions for data flow between BMG and
EMC in both directions. The design uses two instances of CDMA:
° One instance that reads the channel connected to BMG, and writes the channel
connected to EMC. This is called as Write CDMA in design and is used to write data
from BMG to EMC.
° Another CDMA instance that reads the channel connected to EMC and writes the
channel connected to BMG. This is called Read CDMA to read data from EMC and
write to BMG.
• AXI Traffic Generator – Example design makes use of the AXI Traffic Generator (ATG)
core in system test mode to control the transaction sequence. ATG is connected to both
CDMAs to program them for the source address, destination address, and bytes to
transfer registers based on which AXI instructions are generated by the CDMA. The ATG
takes four COE files as input, and gives done and status pins as outputs which
determines the result of the tests. It instantiates IOBUF to take in I, O, and T pins of the
EMC, and gives out a single I/O pin that communicates with the memory model.
IMPORTANT: The example design is not supported when the start-up block is enabled
1. Right-click the core in the Hierarchy window, and select Open IP Example Design.
2. A new window pops up, asking you to specify a directory for the example design. Select
a new directory or keep the default directory.
3. A new project is automatically created in the selected directory and it is opened in a new
Vivado window.
4. In the Flow Navigator (left-side pane), click Run Implementation and follow the
directions.
Table 5-1 shows the files delivered in the example design directory. It contains the
generated example design top files.
Test Bench
This chapter contains information about the test bench provided in the Vivado ® Design
Suite.
Figure 6-1 shows a top-level view of the example design test bench.
X-Ref Target - Figure 6-1
Simulation Status
Check Logic
ATG Status signals
Memory Model
EMC
(Dynamically changes as
Example Design
per user selection)
Mme Signals
X13765
• Generates the clock and reset inputs for the clocking wizard.
• Instantiates the memory model which communicates with EMC. The memory model
used depends on your selection in the Vivado Integrated Design Environment (IDE).
• Instantiates IOBUF to take in I, O, and T pins of the memory model, and give a single
I/O port to connect with EMC.
• Considers the done and status pins from ATG and determines the simulation status.
Simulation Results
The simulation script compiles the AXI EMC example design and supporting simulation
files. It then runs the simulation and checks to ensure that it completed successfully.
If the test fails or does not complete, then the following message is displayed:
Test Hanged
Simulation
The AXI External Memory Controller (EMC) core has been tested with Xilinx® Vivado ®
Design Suite and the Mentor Graphics QuestaSim simulator. For the supported versions of
these tools, see the Xilinx Design Tools: Release Notes Guide (UG631)(3).
The IP is tested using Xilinx proprietary standard AXI Memory Mapped OVM Verification
Components (OVCs).
Hardware Testing
Figure A-1 shows the hardware testing setup for the AXI EMC core.
X-Ref Target - Figure A-1
The AXI EMC core has been hardware validated on a KC705 board using a Kintex®-7 FPGA
with –1 speed grade (325T). The setup uses a AXI4 system implementing a MicroBlaze™
processor, AXI4 interconnects, AXI Interrupt Controller, AXI block RAM and UART peripheral,
in addition to the AXI EMC core. The AXI EMC core in this setup is connected to Linear Flash
Memory and is used to load the device boot code from the flash memory to an internal AXI
block RAM memory. AXI EMC core operation in this setup is set to 100 MHz and Flash
Memory is operated at a frequency of 50 MHz.
Also, the AXI EMC core has been tested on a VCU108 board having a STARTUP block inside
the IP, The following is a snapshot of the timing parameters of the
MT28GU01GAAA1EGC-0SIT flash present on the board.
Debugging
This appendix includes details about resources available on the Xilinx ® Support website,
and about debugging tools.
Documentation
This product guide is the main document associated with the AXI EMC. This guide, along
with documentation related to all products that aid in the design process, can be found on
the Xilinx Support web page or by using the Xilinx Documentation Navigator.
Download the Xilinx Documentation Navigator from the Downloads page. For more
information about this tool and the features available, open the online help after
installation.
Answer Records
Answer Records include information about commonly encountered problems, helpful
information on how to resolve these problems, and any known issues with a Xilinx product.
Answer Records are created and maintained daily ensuring that you have access to the most
accurate information available.
Answer Records for this core can be located by using the Search Support box on the main
Xilinx support web page. To maximize your search results, use proper keywords such as
• Product name
• Tool messages
• Summary of the issue encountered
A filter search is available after results are returned to further target the results.
AR: 54429
Technical Support
Xilinx provides technical support at Xilinx support web page for this LogiCORE™ IP product
when used as described in the product documentation. Xilinx cannot guarantee timing,
functionality, or support if you do any of the following:
• Implement the solution in devices that are not defined in the documentation.
• Customize the solution beyond that allowed in the product documentation.
• Change any section of the design labeled DO NOT MODIFY.
To contact Xilinx Technical Support, navigate to the Xilinx Support web page.
Debug Tools
Vivado Design Suite Debug Feature
The Vivado® Design Suite debug feature inserts logic analyzer (ILA) and virtual I/O (VIO)
cores directly into your design. The Vivado Design Suite debug feature also allows you to set
trigger conditions to capture application and integrated block port signals in hardware.
Captured signals can then be analyzed. This feature in the Vivado IDE is used for logic
debugging and validation of a design running in Xilinx devices.
The Vivado logic analyzer is used with the logic debug IP cores, including:
See the Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref 9].
Interface Debug
AXI4-Lite Interfaces
Read from a register that does not have all 0s as a default to verify that the interface is
functional. Output s_axi_reg_arready asserts when the read address is valid, and
output s_axi_reg_rvalid asserts when the read data/response is valid. If the interface is
unresponsive, ensure that the following conditions are met:
• To access the Async Mode memories (and flash memories), add timing parameters after
referring to the data sheets.
• In case of Sync Mode Linear Flash memory access, core support fixed relation is
between the AXI clock (100 MHz) and the Sync Mode Linear Flash memory clock
(50 MHz).
• Observe the memory interface signals activity when the AXI transactions are accepted
by the core.
Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx
Support.
References
These documents provide supplemental material useful with this product guide:
Revision History
The following table shows the revision history for this document.