pg100 Axi Emc

AXI EMC v3.
LogiCORE IP Product Guide
Vivado Design Suite

PG100 April 5, 2017
Table of Contents
IP Facts
Chapter 1: Overview
Module Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 2: Product Specification

Standards Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chapter 3: Designing with the Core

General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Connecting to Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Using the STARTUPE Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Chapter 4: Design Flow Steps

Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 5: Example Design

Implementing the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Chapter 6: Test Bench

Simulating the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
AXI EMC v3.0 www.xilinx.com Send Feedback

2
PG100 April 5, 2017
Appendix A: Verification, Compliance, and Interoperability
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Hardware Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Appendix B: Migrating and Upgrading

Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Appendix C: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Appendix D: Additional Resources and Legal Notices

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3
PG100 April 5, 2017
IP Facts
Introduction LogiCORE IP Facts Table

Core Specifics
The LogiCORE™ IP AXI External Memory
UltraScale+™ Families,
Controller (EMC) is a soft Xilinx ® IP core for use Supported
UltraScale™ Architecture, Zynq®-7000 All
Device Family (1)
with external memory devices. The adaptable Programmable SoC, 7 Series
block provides memory controller functionality Supported User
AXI4-Lite, AXI4
for SRAM, NOR Flash and PSRAM/CellularRAM Interfaces
memory devices. The core provides an AXI4 Resources See Table 2-2 to Table 2-4.
Slave Interface that can be connected to AXI4
Master or Interconnect devices in the AXI4 Provided with Core
Systems.
Design Files VHDL
Example Design VHDL
Features Test Bench
Constraints File
VHDL
XDC
Simulation
• Supports AXI4 Slave Memory Map interface N/A
Model
data width of 32 and 64 bits
Supported
• Supports optional AXI4-Lite Slave data S/W Driver (2)
Standalone
width of 32 bits for Write/Read registers
Tested Design Flows(3)
• Supports AXI4 increment and wrap
transactions Design Entry Vivado® Design Suite
For a list of supported simulators, see the
• Supports AXI4 narrow and unaligned Simulation
Xilinx Design Tools: Release Notes Guide
transfers
Synthesis Vivado Synthesis
• Supports up to four external memory banks
Support
• Supports Synchronous SRAMs with
configurable byte parity check and pipeline Provided by Xilinx at the Xilinx Support web page
stages Notes:
• Supported memory types 1. For a complete list of supported devices, see the Vivado IP
catalog.
° Synchronous SRAM 2. Standalone driver details can be found in the SDK directory
(<install_directory>/SDK/<release>/data/embeddedsw/doc/
° Asynchronous SRAM xilinx_drivers.htm). Linux OS and driver support information is
available from the
Linear Flash (or Parallel NOR Flash) Xilinx Wiki page.
°
3. For the supported versions of the tools, see the
° PSRAM (or Cellular RAM) Xilinx Design Tools: Release Notes Guide.
• Provides configuration registers to

dynamically change access mechanism for
PSRAM and Micron® Flash memories
• Provides Parity error status register for
Synchronous SRAM memories
AXI EMC v3.0 www.xilinx.com Send Feedback 4

PG100 April 5, 2017 Product Specification
Chapter 1
Overview
The architectural block diagram of the AXI External Memory Controller (EMC) core is shown
in Figure 1-1.
\
X-Ref Target - Figure 1-1
AXI EMC Core
Memory Controller Unit

AXI4
vld/wen Parameter Settings Bank0_MEM
Interface
ack
AXI4 addr Counters

Interface Bank1_MEM
bank Memory control I/O
FSM Reg
wr_data data Optional data
Byte
rd_data data Parity data Bank2_MEM
AXI4 Lite
Interface
Register Module
Bank3_MEM
AXI4-Lite SRAM Parity Error Address Registers
Interface
PSRAM/Flash Configuration Registers
X13185
Figure 1-1: Top Level Block Diagram of the AXI EMC Core
The AXI EMC core provides the memory controller functionalities for PSRAM, flash, and
SRAM technologies. The controller supports memory devices from multiple vendors and
also allows interfacing to multiple of these memory technologies (or types) by supporting
up to four memory banks. The core provides an AXI4 Slave interface for addressing and
accessing data from the connected memory devices.
The core also provides optional AXI4-Lite interface for configuring access mechanisms as
defined by the connected memory types. In addition, the controller provides a set of core
generation parameters which defines the memory interface timing for the connected
memories.

5
PG100 April 5, 2017
Chapter 1: Overview
Module Descriptions
The AXI EMC operations can be categorized into seven modules:
• AXI4 Slave Interface

• AXI4-Lite Interface
• Memory Controller Unit
• Byte Parity Logic
• EMC Register
• I/O Registers
• Flash (Memory) Access through STARTUPE Primitive
AXI4 Slave Interface

AXI EMC core provides AXI4 slave interface to map to AXI4 master or AXI4 interconnect
devices in the FPGA logic. The AXI4 slave interface of the core complies with AMBA® AXI4
protocol specifications for 32-bit and 64 bit data widths. The core supports single beat or
burst AXI4 transactions. The burst transactions for incremental bursts [INCR] can be from 1
beat to 256 beats and the burst transactions for wrapping burst [WRAP] can be 2, 4, 8, or 16
beats. The core also supports AXI4 Narrow and AXI4 Unaligned transfers.
The AXI4 interface of the core also performs the channel arbitration and address decoding
functionalities. The channel arbitration implements a round robin algorithm and is
applicable only when both AXI4 write channels and AXI4 read channels are active
simultaneously. The address decoding logic utilizes the AXI4 address to determine the bank
address and read/write address in the selected memory bank. For more details on Memory
Address Generation, see Address Map Description in Chapter 3.
The performance of AXI EMC core gets determined by Memory Width, Memory access
latencies and AXI burst size. In general larger AXI4 burst sizes can increase the overall
performance of the core. For more details on EMC core performance, see Performance in
Chapter 2.
Note: The AXI4 FIXED transactions are not supported by the core and when issued can result in
nondeterministic core behavior.

6
PG100 April 5, 2017
Chapter 1: Overview
AXI4-Lite Interface
AXI EMC core provides AXI4-Lite slave interface to allow access to Internal Control and
Status registers of the core. The AXI4 slave interface of the core complies with AMBA
AXI4-Lite protocol specifications for 32-bit data width. The AXI4-Lite interface of the core is
optional and is enabled only when the Enable Internal registers option is set. For more
details on Core registers accessible through the AXI-Lite interface, see EMC Register.
Memory Controller Unit

The Memory Controller Unit performs Reads/Writes to the external memories in compliance
with access mechanism defined for the selected memory. It generates the memory chip
select (or bank select) and the control signals associated with the memory in the selected
bank. The Read/Write Address, Write Data and the Bank Address generated for the memory
is as provided by the AXI4 interface module to the Memory Controller Unit.
The Memory Controller Unit in addition aligns the address and data received from the AXI4
interface module to match the address and data width configured for the bank. Different
data widths for various banks are now only supported when selected memory is
Synchronous/Asynchronous SRAM. For other memory types, data widths have to be same
across banks. The width conversion in this case is performed dynamically as per the width
defined for each memory bank.
The Memory interface timing for the asynchronous memory interfaces are parameterized
and can be set independently for each bank. The Memory Controller Unit maintains internal
counters and registers to match the interface timing as defined by these parameters. For
more details on memory timing parameters, see Customizing and Generating the Core in
Chapter 4. In addition for configuration registers associated with PSRAM/Flash memories,
see Register Description in Chapter 2. For example memory interfaces and associated
memory settings, see Connecting to Memory in Chapter 3.
Byte Parity Logic

The Byte Parity Logic is applicable only for the SRAM type and is used to calculate the parity
bit for each data byte written to or read from the memory. This parity bit is attached to the
data byte and is then written to or read from the memory. The parity calculation logic is
valid only when Parity option is set to either Odd Parity or Even Parity. The Parity type has
to be the same across banks. The Parity configuration option allows No Parity, Even Parity
and Odd Parity options. For a memory read, the parity bit is calculated on a read byte and
then compared with the parity bit read from memory. When the parity error occurs, the AXI4
logic responds with an AXI SLVERR response. The error address is updated in the Parity Error
Address register. For more than one SRAM bank, the number of Parity Error Address
registers is defined by the Number of Memory Banks configuration option.

7
PG100 April 5, 2017
Chapter 1: Overview
EMC Register
There are two register sets in the EMC Register Module: the Parity Error Address register
(PERR_ADDR_REG_x) and the PSRAM/Micron ® Technology Flash Configuration register
(PSRAM_FLASH_CONFIG_REG_x). The PERR_ADDR_REG_x registers contain the address for
the parity error that occurred. The PSRAM_FLASH_CONFIG_REG_x register is provided to
configure the PSRAM or flash memory access mechanisms such as operation mode for the
memory. For more details on Configuration and Status registers, see Register Description in
Chapter 2.
I/O Registers
The I/O register module provides additional timing control for synchronous SRAM
memories. All input/output signal on the memory interface is driven on the rising edge of
the EMC clock.
Flash (Memory) Access through STARTUPE Primitive

STARTUP is a primitive in the Xilinx FPGA. This primitive can be used after the FPGA
configuration in the design. For more understanding on the use of this primitive, read the
targeted FPGA user guide, The STARTUPE3 primitive is present in UltraScale™ architecture
and later devices. This primitive has a dedicated clock and data pins that can be used to
provide the clock and partial data interface that is, Bits[3:0] of data bus to the slave memory.
For more information see the UltraScale Architecture Libraries Guide (UG974) [Ref 2].
Application
Figure 1-2 shows an example of the AXI EMC core use case.

8
PG100 April 5, 2017
Chapter 1: Overview
mem_a[Max-1:0] A[Max-1:0]
mem_dq[15:0] DQ[15:0]
Async/Page
mem_wen WE# Cellular RAM
LB#/UB# Memory
mem_ben
mem_oen(1)
mem_oen OE#
mem_ce(1) CS#
AXI EMC
Controller
A[Max-1:0]
DQ[15:0]
WE# Async/Page
mem_oen(0) Flash
OE# Memory
mem_ce(0) CS#
BYTE#
X13184
Figure 1-2: AXI EMC Core Application Diagram

In this use case, AXI EMC core is connected to external NOR Flash and Cellular RAM memory
devices. Both of these memory devices have compatible pin interfaces which allow
maximum pin sharing for reduced off device connectivity. The NOR Flash memory shown in
the use case can be used as a primary nonvolatile storage device containing device boot
code or application code.
The CellularRAM shown in the use case is a volatile Pseudo SRAM and can be used for
cached or buffered memory applications. The AXI EMC core here allows the flash memory
or Cellular RAM to be dynamically configured for asynchronously read operations or
synchronously page read operations. The low latency and high performance AXI EMC core
in this use case is ideally suited for eXecute In Place (XIP) system memory solutions.

9
PG100 April 5, 2017
Chapter 1: Overview
Licensing and Ordering Information

This Xilinx® LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado®
Design Suite under the terms of the Xilinx End User License.
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx
Intellectual Property page. For information on pricing and availability of other Xilinx
LogiCORE IP modules and tools, contact your local Xilinx sales representative.

10
PG100 April 5, 2017
Chapter 2
Product Specification
This chapter contains details about the performance and ports of the core.
Standards Compliance
This core has bus interfaces that comply with the ARM ® AMBA® AXI4 Protocol Specification
Version 1.0 [Ref 1].
Performance
The performance and resource utilization numbers for the AXI EMC core are generated from
a common benchmarking setup implementing a multi-masters/multi-slave AXI4 system.
The AXI EMC core is characterized as per the benchmarking methodology described in
“Vivado IP Optimization (FMax Characterization) appendix,” in the Vivado Design Suite User
Guide: Designing with IP (UG896) [Ref 3].
Maximum Frequencies
The maximum frequencies for AXI EMC are provided in Table 2-1.
Note: Performance numbers for UltraScale™ architecture and Zynq®-7000 devices are expected to
be similar to 7 series device numbers.
Table 2-1: Maximum Frequencies
FMax (MHz)
Family Speed Grade
AXI4 AXI4-Lite
Virtex-7 200 180
Kintex-7 –1 200 180
Artix-7 150 120
Virtex-7 240 200
Kintex-7 –2 240 200
Artix-7 180 140

11
PG100 April 5, 2017
Table 2-1: Maximum Frequencies (Cont’d)

FMax (MHz)
Family Speed Grade
AXI4 AXI4-Lite
Virtex-7 280 220
Kintex-7 –3 280 220
Artix-7 200 160
Resource Utilization
Note: UltraScale architecture results are expected to be similar to 7 series device results.
The AXI EMC resource utilization for various parameter value combinations measured with
a Virtex® -7 device are detailed in Table 2-2.
Table 2-2: Device Utilization – Virtex-7 FPGAs

Parameter Values Device Resources
Enable Memory AXI Enable No. of
Pipe Data Memory FMax
Delay Width Data Data Type Internal Memory LUTs FFs Slices (MHz)
Width Width Registers Banks
Matching
2 0 32 32 1 0 1 628 495 293 288
2 1 16 32 1 0 1 664 469 296 266
2 1 8 32 1 0 1 659 452 267 266
2 0 32 32 0 0 1 564 555 252 296
2 0 32 32 0 1 1 636 656 304 312
2 1 16 32 0 0 1 625 509 264 281
2 1 8 32 0 0 1 589 485 267 258

12
PG100 April 5, 2017
The AXI EMC resource utilization for various parameter value combinations measured with
a Kintex ®-7 and Zynq-7000 device are detailed in Table 2-3.
Table 2-3: Device Utilization – Kintex-7 and Zynq-7000 (Kintex-7 Based) FPGAs
Enable
Memory AXI Enable No. of
Pipe Parity Data Data Data Memory Internal Memory LUTs FFs Slices FMax
Delay Width Type (MHz)
Matching Width Width Registers Banks
2 0 1 8 32 1 0 1 669 452 271 281

2 1 0 32 32 0 0 1 559 555 277 320
2 0 1 16 32 1 0 1 676 469 334 274
2 1 1 8 32 0 0 1 612 482 266 274
2 0 0 32 32 1 0 1 634 495 361 304
2 1 0 32 32 0 1 1 631 656 336 312
2 1 1 16 32 0 0 1 616 506 273 274
The AXI EMC resource utilization for various parameter combinations measured with an
Artix ®-7 device are detailed in Table 2-4.
Table 2-4: Device Utilization – Artix-7 and Zynq-7000 FPGAs

Enable
Pipe Data Memory AXI Memory Enable No. of FMax
Parity Data Data Internal Memory LUTs FFs Slices
Delay Width Width Width Type Registers Banks (MHz)
Matching
2 1 0 32 32 0 0 1 559 555 261 204
2 0 1 16 32 1 0 1 681 469 290 180
2 0 0 32 32 1 0 1 633 495 301 188
2 0 1 8 32 1 0 1 676 452 269 172
2 1 0 32 32 0 1 1 630 656 299 204
2 1 1 16 32 0 0 1 615 506 274 172
2 1 1 8 32 0 0 1 608 482 267 180

13
PG100 April 5, 2017
Port Descriptions
The I/O signals are listed and described in Table 2-5.
Table 2-5: I/O Signal Descriptions
Signal Name Interface I/O Initial Description

State
AXI Global System Signals
s_axi_aclk (1) AXI I – AXI clock
s_axi_aresetn AXI I – AXI reset; active-Low
rdclk (2) System I – Read clock to capture the data from memory
AXI4-Lite Interface Signals(3)
See Appendix A of the Vivado AXI Reference Guide
s_axi_reg* AXI-Lite I –
(UG1037) [Ref 4] for a description of AXI4 signals.
AXI4 Channel Signals
See Appendix A of the Vivado AXI Reference Guide
s_axi_mem* (8) AXI I –
(UG1037) [Ref 4] for a description of AXI4 signals.
External Memory Interface Signals
Memory input data bus.
mem_dq_i External Max Memory Data Width is the maximum memory
I –
[Max Data Width of Memories – 1:0] memory data width configured across all memory banks
and can be set as 8, 16, 32, or 64 bits wide.
Memory output data bus.
mem_dq_o External Max Memory Data Width is the maximum memory
O 0
Memory output 3-state signal.
mem_dq_t External Max Memory Data Width is the maximum memory
O 0
Memory parity input data bits.
mem_dq_parity_i
External Max Memory Data Width is the maximum memory
[Max Data Width of Memories/8 – I –
memory data width configured across all memory banks
1:0](4)
Memory parity output data bits.
mem_dq_parity_o
[Max Data Width of Memories/8 – O 0
1:0](4)
Memory parity 3-state signals.
mem_dq_parity_t
[Max Data Width of Memories/8 – O 0
1:0](4)

14
PG100 April 5, 2017
Table 2-5: I/O Signal Descriptions (Cont’d)

State
External
mem_a[31:0] O 0 Memory address bus.
memory
External
mem_rpn O 1 Memory reset/power down.
memory
mem_cen External Memory chip enables(5); active-Low.
O 1
[No. of Memory Banks – 1:0] memory The valid range for Memory Banks is from 1 to 4.
mem_oen External Memory output enable.
O 1
External
mem_wen O 1 Memory write enable.
memory
Memory qualified write enables.
mem_qwen
[(Max Data Width of Memories/8) – O 1
1:0]
Memory byte enables.
mem_ben
[(Max Data Width of Memories/8) – O 0
1:0]
mem_ce External Memory chip enables(5); active-High.
O 0
External
mem_adv_ldn O 1 Memory advance burst address/load new address.
memory
External
mem_lbon O 1 Memory linear/interleaved burst order.
memory
External
mem_cken O 0 Memory clock enable.
memory
External
mem_rnw O 1 Memory read not write.
memory
External
mem_cre O 0 Command sequence configuration of PSRAM.
memory
Has STARTUP block ports unused by AXI EMC IP.
STARTU
STARTUP_IO Note: See the STARTUP document for complete details
P_IO
of Ports and their functionality.

15
PG100 April 5, 2017
Table 2-5: I/O Signal Descriptions (Cont’d)

State
Input signal from Micron Flash device; This signal
External
mem_wait I – is used only when Memory Type is set to Micron
memory
Flash.
Notes:
1. The same clock and reset signals should be used for both the register and memory interfaces.
2. This clock is used to capture the data from memory. Xilinx recommends that this clock is tied with AXI Clock source.
3. The AXI4-Lite interface is optional and is provided only when the Enable Internal Registers option is set.
4. This pin is only enabled when parity type selected is either odd parity or even parity in the Vivado IDE.
5. Most asynchronous memory devices only use mem_cen. Most synchronous memory devices use both mem_cen and
mem_ce.
6. All mem_* ports have IOB attributes set to TRUE when STARTUP is not included in the design.
7. All mem_* ports except mem_dq_*[3:0] and mem_cen[0] which are connected to STARTUP have IOB attributes set TRUE when
STARTUP is included in the design.
8. Write commands to Flash should be issued with awlen=0.
Register Description
There are four internal registers in the AXI EMC design (Table 2-6). The memory map of the
AXI EMC registers is determined by setting the Base Address in the Address Editor tab of the
Vivado IP integrator. The internal registers of the AXI EMC are at a fixed offset from the base
address and are byte accessible. The AXI EMC internal registers and their offset are listed in
Table 2-6.
Table 2-6: Internal Registers and Offsets

Default
AXI Lite Base Address + Offset Access
(hex) Register Name Type Value Description
(hex)
Bank-0 parity error
Base Address + 0x00 PARITY_ERR_ADDR_REG_0 Read 0x0
address register
Bank-1 parity error
address register
Bank-2 parity error
address register
Bank-3 parity error
Base Address + 0x0C PARITY_ERR_ADDR_REG_3 Read 0x0
address register
Write/ Bank-0 PSRAM/Flash
Base Address + 0x10 PSRAM_FLASH_CONFIG_REG_0 0x24
Read configuration register
Write/ Bank-1 PSRAM/Flash
Write/ Bank-2PSRAM/Flash

16
PG100 April 5, 2017
Table 2-6: Internal Registers and Offsets (Cont’d)
AXI Lite Base Address + Offset Access Default

Register Name Value Description
(hex) Type (hex)
Write/ Bank-3PSRAM/Flash
Base Address + 0x1C PSRAM_FLASH_CONFIG_REG_3 0x24
Notes:
1. Based upon the no. of banks chosen, only those no. registers are available and accessible for read and write-if allowed.
2. Other registers are considered as nonexistent and AXI transaction returns gracefully if accessed.
3. A write transaction will be executed only when AWVALID and WVALID are asserted. The AWREADY is gated by assertion of
WVALID and vice-versa.
PARITY ERROR ADDRESS Register (PARITY_ERR_ADDR_REG_x)

The AXI EMC Parity Error Address registers are read-only registers that provide the AXI
address on which the parity error occurred. These registers are valid only when AXI4-Lite
interface is enabled and Memory Type selected for the bank is Sync/Async SRAM. The
number of such registers depends on the Number of Memory Banks set for the core.
There can be four PARITY_ERR_ADDR_REG registers. Whenever a parity error occurs for a
AXI read operation, the AXI EMC core updates this register with the address at which the
error occurred. The Parity Error Address register is shown in Figure 2-1 and described in
Table 2-7.
31 0
DS762_04
Figure 2-1: AXI EMC Parity Error Address Register
Table 2-7: Parity Error Address Register Description

Bits Name Core Access Reset Value Description
31:0 PARITY_ERR_ADDR_REG_x Read 0x0 Parity error register width
PSRAM/Flash Configuration Register (PSRAM_FLASH_CONFIG_REG_X)

The PSRAM/Flash configuration registers are write and read registers that are used for
configuration of the controller for the PSRAM or flash memories. These registers are used
to configure:
• PSRAM memory when AXI4-Lite interface is enabled and Memory Type selected for the
bank is PSRAM.
• Flash memories in burst mode when AXI4-Lite interface is enabled, Memory Type
selected for the bank is Micron ® Flash, and Burst mode for Micron Flash memory is
enabled.

17
PG100 April 5, 2017
The number of such registers depends on the Number of Memory Banks set for the core
and the Memory Type selected in the associated Memory Bank.
IMPORTANT: For Memory Types selected across memory banks, see Allowable Memory Combination in
Chapter 3.
There can be four PSRAM_FLASH_CONFIG_REG registers. The PSRAM/Micron Flash Burst

mode configuration register is shown in Figure 2-2 and described in Table 2-8.
Operational Mode
CRE RM Reserved for Burst Mode
Reserved CRE Drive Signal
31 30 7 6 5-2 1-0
DS762_05
Figure 2-2: PSRAM/Micron Flash Configuration Register
Table 2-8: PSRAM/Micron Flash Configuration Register (PSRAM_FLASH_CONFIG_REG_X)
Bits Name Core Reset Description

Access Value
• 0x0 = Normal read/writes to Micron Flash
Control register Write/
31 0x0 • 0x1 = Enables Micron flash RCR register configuration
enable (CRE) Read
Note: Valid only if connected memory is Micron Flash.
• 0x0 = Asynchronous Page Mode
Write/
30 Read Mode (RM) 0x0 • 0x1 = Synchronous Burst Mode (Applicable when Micron Flash
Read
is switched to Sync Read Burst Mode)
Reserved. If read, might return undefined value. If written to
29:7 Reserved N/A 0
these bits, is not updated.
• 0x0 = Remove Drive Command for CRE
Write/
6 CRE drive 0 • 0x1 = Drive Command for CRE
Read
Note: Valid only for PSRAM memories.
Write/ Reserved. If read, might return undefined value. If written to
5:2 Reserved 0x9
Read these bits, is not updated.
This bits describe the mode in which PSRAM is configured
(Applicable only when target memory is PSRAM)
Write/
1:0 Operational Mode 0x0 • 0x00 = Asynchronous Mode
Read
• 0x01 = Page Mode
• 0x10 = Reserved for future use (Burst Mode)
Notes:
1. For Latency configurations and access details, see the respective PSRAM data sheet.

18
PG100 April 5, 2017
Configuring the Micron Flash in Sync Burst Read Mode

Table 2-9 provides the required bit settings for Sync Burst Micron Flash Memories Read
Configuration register. When Micron Flash is configured with sync burst read operations,
the register configuration setting must be as provided in this table.
The Read Configuration register is in the flash memory. The address for accessing this
register is set as Memory Bank Base address+ 32’h0000_509F.
Table 2-9: Micron Flash Sync Mode – Read Configuration Register (RCR)
Read Configuration Register (RCR)
Read Latency Count WAIT RES WAIT Burst CLK RES RES Burst Burst Length
Mode Polarity Delay Seq Edge Wrap
RM LC[3:0] WP R WD BS CE R R BW BL[2:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 1 0 0 0 0 1 0 0 1 1 1 1
Note: The RCR settings are specific for the P30 flash family and slower speeds. The Micron P30/P33
and G18F/MT28GU01GAAA1E families should be supported and RCR recommendations referenced.
The guideline for configuring the Sync Read Mode for Micron Flash are as follows. This
process is applicable to the memory bank with Memory Type configured for Micron Flash.
• By default the Micron Flash operates in Asynchronous mode. These settings are
required while switching the read operation of memory from Asynchronous Read to
Synchronous Read.
• Set Bits[31:30] of PSRAM_FLASH_CONFIG_REG_X register for selected memory bank to
1.
• Drive the value of Memory Bank Base address+ 0x0000_589E on AXI write address bus
with 0x0300_0060 on AXI write data bus. This should be of single beat transaction.
• Drive the value of Memory Bank Base address+ 0x0000_589E on AXI write address bus
with 0x6000_0003 on AXI write data bus. This should be of single beat transaction.
• The previous two steps write 589E into the Read Configuration register of the Micron
Flash.
• Reset Bit[31] of the PSRAM_FLASH_CONFIG_REG_X register for selected memory bank
to continue with normal memory read/writes.
• The AXI EMC core behavior is designed on the basis of the above register bit settings,
for any other bit settings the core behavior is not guaranteed.
• While switching from Sync to Async mode, the Sync mode settings of memory should
be disabled by resetting the Read Configuration register (Bit[15]) to 1. After this bit is
reset, set the AXI EMC cores internal registers Bit[30] to 0.

19
PG100 April 5, 2017
• After both the core and memory are reset with the bit settings mentioned above, the
memory and the core operates in Asynchronous Read mode.
IMPORTANT: When CRE bit in PSRAM_FLASH_CONFIG_REG_X (Bit[31]) is set to “1,” then the core would
ignore value driven in wstrb bus and would always transfer the LSB bytes of wdata bus to the Memory
Interface.
If the pin does not have a pull-down register connected, the WAIT pin is a 3-state output from the flash.
It is recommended to change the polarity of WAIT to active-High in Read Configuration register of the
Micron Flash and connect to EMC through an inverter.

20
PG100 April 5, 2017
Chapter 3
Designing with the Core

This chapter includes guidelines and additional information to facilitate designing with the
AXI External Memory Controller (EMC) core.
General Design Guidelines

Address Map Description
The AXI EMC core supports up to four banks of external memory. The number of banks used
is determined by the Number of Memory Banks configuration option and can take values
between 1 and 4. The banks that are used are banks 0 to bank 3. Each bank of memory has
its own independent base address and High address range. The address range of a bank of
memory is restricted to have a size (in bytes) that is a power of 2 and is address-aligned. For
an address-range of size is 2 n, the n least significant bits of the base address is 0 and n least
significant bits of the High address are 1. For example, a memory bank with an addressable
range of 16 MB (224) could have a base address of 0xFF000000 and a High address of
0xFFFFFFFF. A memory bank with an addressable range of 64 kB (2 16) could have a base
address of 0xABCD0000 and a High address of 0xABCDFFFF. The AXI EMC core
transactions must fall between the bank x base address and High address. The addresses for
the memory banks can be configured through per bank Base Address and High Address
configuration options provided in the Customize IP dialog box of the Vivado® IP catalog or
through the Address Editor tab of IP integrator.
AXI EMC core also supports internal registers for Memory configurations. These registers
are enabled by setting the Enable Internal register option. The memory map for these
internal registers get determined by the Base Address settings for the AXI EMC core in the
Address Editor tab of Vivado IP integrator. For more detail on AXI EMC core internal register
configurations, see Register Description in Chapter 2.

21
PG100 April 5, 2017
Allowable Memory Combination

Table 3-1 lists the allowed memory combinations across multiple banks of the AXI EMC
core. Memories can be arranged in any order with a maximum up to four.
Each row is a group of acceptable memory combinations. Memories between different rows
cannot be mixed within the same Memory Controller.
Table 3-1: Allowable Memory Combination

PSRAM (Async Mode) Micron Flash (Async Mode) Linear Flash Async SRAM
PSRAM (Page Mode) Page Mode Flash – –
Sync SRAM Async SRAM – –
Note: By default PSRAM/Micron® operate in asynchronous mode. Select the Enable Internal
Registers option while customizing the AXI EMC core if PSRAM/Micron needs to operate in other
modes.
Memory Data Types and Organization

Memory can be accessed through the AXI EMC core as one of four types:
• Byte (8-bit)
• Halfword (16-bit)
• Word (32-bit)
• Doubleword (64-bit)
Data to and from the AXI interface is organized as little-endian. The bit and byte labeling for
the big-endian data types is shown in Figure 3-1.

22
PG100 April 5, 2017
Byte address n+7 n+6 n+5 n+4 n+3 n+2 n+1 n
Byte label 7 6 5 4 3 2 1 0 Double

Word
Byte significance MS Byte LS Byte
Bit label 63 0
Bit significance MS Bit LS Bit
Byte address n+3 n+2 n+1 n
Byte label 3 2 1 0 Word
Bit label 31 0
Bit significance MS Bit LS Byte
Byte address n+1 n
Byte label 1 0 Halfword
Bit label 15 0
Byte address n
Byte label 0 Byte
Byte significance MS Byte
Bit label 7 0

DS762_06
Figure 3-1: Memory Data Types
Connecting to Memory
Clocking Synchronous Memory
The AXI EMC core does not provide a clock output to any synchronous memory. The AXI
clock should be routed through an ODDR module to provide the clock to synchronous
memory. To synchronize the synchronous memory clock to the internal FPGA clock, the
FPGA system design should include a Mixed Mode Clock Manager (MMCM), external to the
AXI EMC core, that uses the synchronous memory clock input as the feedback clock as
shown in Figure 3-2. The synchronous clock output from the FPGA must be routed back to
the FPGA on a clock pin.

23
PG100 April 5, 2017
)3*$
6B$;,B$&/.
&/.,1 &/. 2''5
([WHUQDO&ON %8)*
&/.)%
6\QFPHPB&ONBIE 'LJLWDO&ORFN0DQDJHU
'&0 $;,(0&
6\QFPHPB&ON
6\QFKURQRXV0HPRU\%DQN
Figure 3-2: Synchronous Memory Bank Clocked by FPGA Output with Feedback
The following constraint has to be added in XDC when clock to Synchronous RAM is
forwarded through ODDR:
create_generated_clock -name clk_forward -source [get_pins -hier *ODDR/C] -invert

-divide_by 1 [get_ports clk_fwd]
Because forwarded clock is 180° out-of-phase, the data is to be latched on second rising
edge, the following constraints need to be set:
set_multicycle_path 2 -setup -from clk_forward -to [get_clocks -of_objects [get_pins

-hierarchical *Mem_DQ_I_int_reg[*]/C]]
set_multicycle_path 1 -hold -end -from clk_forward -to [get_clocks -of_objects
[get_pins -hierarchical *Mem_DQ_I_int_reg[*]/C]]
If Parity is enabled, the following constraints should also be added to XDC:
set_multicycle_path 2 -setup -from clk_forward -to [get_clocks -of_objects [get_pins

-hierarchical *Mem_DQ_PARITY_I_int_reg[*]/C]]
set_multicycle_path 1 -hold -end -from clk_forward -to [get_clocks -of_objects
[get_pins -hierarchical *Mem_DQ_PARITY_I_int_reg[*]/C]]
If the synchronous memory is clocked by the same external clock as the FPGA, or if the clock
feedback is not available, the DCM shown in Figure 3-3 should be included in the FPGA
external to the AXI EMC core.

24
PG100 April 5, 2017
)3*$
6B$;,B$&/.
&/.,1 &/. $;,(0&
([WHUQDO&ON %8)*
&/.)%
0L[HG0RGH&ORFN0DQDJHU
00&0
&ON
6\QFKURQRXV0HPRU\%DQN
Figure 3-3: Synchronous Memory Bank Clocked by External Clock

1. When using Micron ® Flash in synchronous mode, ensure that memory clock interface is
connected to 50 MHz and AXI Clock interface is connected to 100 MHz. Both of these
clocks must originate from same source.
IMPORTANT: By default, Micron Flash memories operate in asynchronous read mode. To operate
Micron Flash in synchronous mode:
(a) Select Enable Internal Registers option while customizing the AXI EMC core.
(b) See the Core register Configuration and Memory Configuration section.
2. In all IP operating modes, Xilinx recommends that the same clock is connected to both
rdclk and s_axi_aclk ports.
Address Bus, Data Bus, and Control Signal Connections

The three primary considerations for connecting the controller to memory devices are the
width of the AXI data bus, the width of the memory subsystem and the number of memory
devices used. The data and address signals at the memory controller are labeled with
little-endian bit labeling (for example, D(31:0) where D(31) is the MSB), and memory
devices are also little-endian.
Note: Most asynchronous memory devices only use MEM_CEN, while most synchronous memory
devices use both MEM_CEN and MEM_CE. MEM_CEN is a function of the address decode while
MEM_CE is a function of the state machine logic.
For Address and Data connections to the external memory devices, see Tables 3-3, 3-5, 3-7,
3-9, 3-11, 3-13 and 3-15. In addition, Table 3-2 shows variables used in defining memory
subsystem.

25
PG100 April 5, 2017
Table 3-2: Variables Used in Defining Memory Subsystem

Allowed
Variable Range Definition
BN 3 down to 0 Memory bank number

Memory device number within a bank. The memory device attached to the most
DN 3 down to 0
significant bit in the memory subsystem is 0 to 3.
MW 8 to 64 Width in bits of memory subsystem (8, 16, 32, and 64 are allowed values)
DW 63 down to 1 Width in bits of data bus for memory device
MAW 32 down to 1 Width in bits of address bus for memory device
AU 63 down to 1 Width in bits of smallest addressable data word on the memory device
(1)
AS X Address shift for address bus = log2((MW × AU/DW)/8)
HAW 32 down to 1 Width in bits of AXI address bus
Notes:
1. The value of X depends on variables MW, AU and DW.
Connecting to SRAM
Table 3-3: Core To Memory Interconnect
Description AXI EMC Signals (MSB:LSB) Memory Device Signals (MSB:LSB)
Data bus MEM_DQ(((DN + 1) × DW) – 1:DN × DW) D(DW – 1:0)
Address bus MEM_A(MAW – AS – 1:AS) A(MAW – 1:0)
Chip enable MEM_CEN(BN) CEN
(active-Low)
Output enable MEM_OEN OEN
(active-Low)
Write enable MEM_WEN WEN (for devices that have byte enables)
(active-Low)
Qualified write enable MEM_QWEN(DN × DW/8) WEN (for devices that do not have byte
(active-Low) enables)
Byte enable MEM_BEN((((DN + 1) × DW/8) – 1):(DN × BEN(DW/8 – 1:0)
(active-Low) DW/8))
Example 1: Connection to 32-bit Memory Using Two IDT71V416S SRAM Parts

Table 3-4 shows variables for a simple SRAM example.

26
PG100 April 5, 2017
Table 3-4: Variables For Simple SRAM Example

Variable Value Definition
BN 0 Memory bank number
1 down
DN significant bit in the memory subsystem is 0; device numbers increase toward the least
to 0
significant bit.
MW 32 Width in bits of memory subsystem
DW 16 Width in bits of data bus for memory device
MAW 18 Width in bits of address bus for memory device
AU 16 Width in bits of smallest addressable data word on the memory device
AS 2 Address shift for address bus = log 2((MW × AU/DW)/8)
HAW 32 Width in bits of host address bus (for example, AXI)
Table 3-5 shows connection to 32-bit memory using two IDT71V416S (256K × 16-bit) parts.
Table 3-5: Connection to 32-bit Memory Using Two IDT71V416S Parts

Memory Device Signals
DN Description AXI EMC Signals (MSB:LSB)
(MSB:LSB)
Data bus MEM_DQ(15:0) I/O(15:0)
Address bus MEM_A(19:2) A(17:0)
Chip enable (active-Low) MEM_CEN(0) CS
0
Output enable (active-Low) MEM_OEN OE
Write enable (active-Low) MEM_WEN WE
Byte enable (active-Low) MEM_BEN(1:0) BHE:BLE
1
Output enable (active-Low) MEM_OEN OE
Byte enable (active-Low) MEM_BEN(3:2) BHE:BLE
Connecting to Byte Parity Memory

Connection to 32-bit Memory Using IS61LVPS25636A Synchronous SRAM
Parts
Table 3-6 shows the variables for a simple SRAM example.

27
PG100 April 5, 2017
Table 3-6: Variables for Simple SRAM Example

DN 0 significant bit in the memory subsystem is 0; device numbers increase toward the least
significant bit.
AS 2 Address shift for address bus = log2 ((MW × AU/DW)/8)
Table 3-7 shows the connection to 32-bit memory using two IDT71V416S (256K × 16-bit)
parts.
Table 3-7: Connection to 32-bit Memory Using Two IDT71V416S Parts

Memory Device Signals
(MSB:LSB)
0 Output enable (active-Low) MEM_OEN OE
Byte enable (active-Low) MEM_BEN(3:0) BWAb, BWBb, BWCb, BWDb
Parity Bits MEM_DQ_PARITY(3:0) I/O(35:32)
Connecting to Intel StrataFlash

StrataFlash parts contain an identifier register, a status register, and a command interface.
Therefore, the bit label ordering for these parts is critical to enable correct operation.
Table 3-8 shows an example of how to connect the big-endian AXI EMC bus to the
little-endian StrataFlash parts. The correct connection ordering is also indicated in a more
general form in Table 3-3. StrataFlash parts have an x8 mode and an x16 mode, selectable
with the BYTE# input pin. To calculate the proper address shift, the minimum addressable
word is 8 bits for both x8 and x16 modes, because A0 always selects a byte.
Example 2: Connection to 32-bit Memory Using Two StrataFlash Parts in x16

Mode
This configuration supports byte read, but not byte write. The smallest data type that can
be written is 16-bit data. Table 3-8 shows the variables for StrataFlash (x16 mode) example.

28
PG100 April 5, 2017
Table 3-8: Variables For StrataFlash (x16 mode) Example

DN 0 to 1 significant bit in the memory subsystem is 0; the device numbers increase toward the
least significant bit.
Table 3-9 shows the connection to 32-bit memory using two StrataFlash parts.
Table 3-9: Connection to 32-bit Memory Using Two StrataFlash Parts

StrataFlash Signals
(MSB:LSB)
Data bus MEM_DQ(15:0) DQ(15:0)
Chip enable (active-Low) GND, GND, MEM_CEN(0) CE(2:0)
Output enable (active-Low) MEM_OEN OE#
0
Write enable (active-Low) MEM_QWEN(0) WE#
Reset/Power down (active-Low) MEM_RPN RP#
Byte mode select (active-Low) N/A – tie to GND BYTE#
Program enable (active-High) N/A – tie to VCC VPEN
1
Program enable (active-High) N/A – tie to VCC VPEN

29
PG100 April 5, 2017
Example 3: Connection to 32-bit Memory Using Four StrataFlash Parts in x8

Mode
This configuration supports byte reads and writes. Table 3-10 shows the variables for the
StrataFlash (x8 mode) example.
Table 3-10: Variables for StrataFlash (x8 mode) Example

DN 0 to 3 significant bit in the memory subsystem is 0; the device numbers increase toward the
least significant bit.
Table 3-11 shows the connection to 32-bit memory using four StrataFlash parts.
Table 3-11: Connection to 32-bit Memory Using Four StrataFlash Parts

StrataFlash Signals
(MSB:LSB)
Data bus MEM_DQ(7:0) DQ(7:0) (1)
0
Program enable (active-High) N/A – tie to VCC V PEN
Data bus MEM_DQ(15:8) DQ(7:0) ()
Chip enable (active-Low) GND,GND, MEM_CEN(0) CE(2:0)
1

30
PG100 April 5, 2017
Table 3-11: Connection to 32-bit Memory Using Four StrataFlash Parts (Cont’d)
DN Description AXI EMC Signals (MSB:LSB) StrataFlash Signals

(MSB:LSB)
2
3
Notes:
1. In an x8 configuration, DQ(15:8) are not used and should be treated according to the data sheet of the manufacturer.
Connecting to Spansion Page Mode Flash S29GL032N

Table 3-12 shows the variables for the Spansion Page Mode Flash (x16 mode) example.
Table 3-12: Variables for Page Mode Flash (x16 mode) Example
DN 0
significant bit in the memory subsystem is 0.

31
PG100 April 5, 2017
Table 3-13: Connection to 16-bit Memory Using Page Mode Flash Parts
PagemModeFlash Signals
DN Description AXI EMC Signals (MSB:LSB) (MSB:LSB)
Chip enable (active-Low) MEM_CEN(0) CE
0
Byte mode select (active-Low) N/A - tie to VCC BYTE#
Program enable (active-High) N/A - tie to VCC WP#
Connecting to PSRAM
Table 3-14: Variables PSRAM (x16 mode) Example
DN 0
significant bit in the memory subsystem is 0.
Table 3-15: Connection to 16-bit Memory Using PSRAM Parts

PageModeFlash Signals
DN Description AXI EMC Signals (MSB:LSB) (MSB:LSB)
Chip enable (active-Low) MEM_CEN(0) CE
0 Write enable (active-Low) MEM_QWEN(0) WE#
Byte Enable (active-Low) Mem_BEN(1:0) UB#, LB#
Control Register Enable Mem_CRE CRE
(active-High)

32
PG100 April 5, 2017
Software Considerations
Absolute memory addresses are frequently required for specifying command sequences to
flash memory devices.
IMPORTANT: Due to the memory address shift (AS), any absolute addresses that must appear on the
memory device address bus must also have the source AXI address left-shifted to compensate for the
AS.
All of the EMC Memory interface pins except for mem_cre, mem_wait, and mem_a (for
Micron Flash in Sync mode) are registered I/Os. Xilinx recommends having these flops
placed in the FPGA I/O pins.
All of the Memory interface pins which are applicable to connected memory (from Table 3-2
to Table 3-15) except for Address, CRE, and WAIT should be constrained to have the flops
placed. The following is an example of constraint that can be added in XDC:
set_property IOB true [get_cells -hierarchical -filter {NAME =~*mem_ben_reg*}]
For ports Address, CRE, and WAIT the constrains can be the following:
set_max_delay -datapath_only -from [get_cells -hier -regexp -filter { REF_NAME =~

FD.* } .*mem_a_reg_reg.*] -to [get_ports linear_flash_addr*] 6.000
Using the STARTUPE Primitive

The Flash access through the STARTUP Primitive parameter is applicable in UltraScale™
architecture and later devices. When this parameter is enabled, STARTUPE3 primitive is
included in the design and becomes part of the core after the configuration of the FPGA.
See the answer records or the device user guide to understand more about the functionality
and use of the STARTUP primitive.
STARTUP Primitive Included in Design

The core behavior and ports are as follows:
• The mem_dq_*[3:0] and mem_cen[0] ports from the core are interfaced with the
STARTUP primitive. The STARTUP can also be used in the pre-configuration process of
the FPGA where the external slave memory is configured prior to the FPGA.
• After configuration of the FPGA, the mem_dq_*[3:0] and mem_cen[0] ports drive
the corresponding ports of the primitive which are directly connected to external slave
memory. These signals are not available as the external port of the core.
• Instantiating STARTUP affects the maximum frequency of s_axi_aclk and rdclk.

33
PG100 April 5, 2017
STARTUP Primitive is Not in Design

The core behavior and ports are as follows:
• As the mem_dq_*[3:0] and mem_cen ports are part of the core and no primitive is
instantiated in the core, these ports are available as external ports of the core and they
are placed in an IOB at a user-configured location.
Timing Diagrams
Figure 3-4 is the read timing representation for Sync SRAM memories.
Figure 3-4: Read Timing Representation of 32-bit Sync SRAM with Pipeline Delay 2

34
PG100 April 5, 2017
Figure 3-5 is the write timing representation for Sync SRAM memories.
Figure 3-5: Write Timing Representation of 32-bit Sync SRAM with Pipeline Delay 2
Figure 3-6 is the read timing representation for Async SRAM memories.
Figure 3-6: Read Timing Representation of 32-bit Async SRAM
Figure 3-7 is the write timing representation for Async SRAM memories.

35
PG100 April 5, 2017
Figure 3-7: Write Timing Representation of 32-bit Async SRAM

36
PG100 April 5, 2017
Figure 3-8 is the read timing representation for Linear Flash memories.
Figure 3-8: Read Timing Representation of Linear Flash Memories
Figure 3-9 is the write timing representation for Linear Flash memories.
Figure 3-9: Write Timing Representation of Linear Flash Memories

37
PG100 April 5, 2017
Figure 3-10 is the read timing representation for Page Mode Flash memories.
Figure 3-10: Read Timing Representation for Page Mode Flash Memories
Figure 3-11 is the read timing representation for Micron Flash memories.
Figure 3-11: Read Timing Representation for Micron Flash Memories

38
PG100 April 5, 2017
Figure 3-12 is the write timing representation for Micron Flash memories.
Figure 3-12: Write Timing Representation for Micron Flash Memories
Figure 3-13 is the Sync Read timing representation for Micron Flash memories.
Figure 3-13: Sync Read Timing Representation for Micron Flash Memories

39
PG100 April 5, 2017
The sequence of Read/Write operations is updated to have one cycle difference between
Address bus and CE/CEN and OEN/WEN both during assertion and deassertion from
2015.3.
Earlier all of these signals set asserted/deasserted at the same edge.

40
PG100 April 5, 2017
Chapter 4
Design Flow Steps

This chapter describes customizing and generating the core, constraining the core, and the
simulation, synthesis and implementation steps that are specific to this IP core. More
detailed information about the standard Vivado® design flows and the Vivado IP integrator
can be found in the following Vivado Design Suite user guides:
• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
[Ref 5]
• Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 3]
• Vivado Design Suite User Guide: Getting Started (UG910) [Ref 6]
• Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 7]
Customizing and Generating the Core

This section includes information about using Xilinx ® tools to customize and generate the
core in the Vivado Design Suite.
If you are customizing and generating the core in the IP integrator, see the Vivado Design
Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 5] for detailed
information. IP integrator might auto-compute certain configuration values when
validating or generating the design. To check whether the values do change, see the
description of the parameter in this chapter. To view the parameter value you can run the
validate_bd_design command in the Tcl Console.
You can customize the IP for use in your design by specifying values for the various
parameters associated with the IP core using the following steps:
1. Select the IP from the Vivado IP catalog.

2. Double-click the selected IP, or select the Customize IP command from the toolbar or
right-click menu.
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 3] and
the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 6].
Note: Figures in this chapter are illustrations of the Vivado IDE. This layout might vary from the
current version.

41
PG100 April 5, 2017
Figure 4-1 shows the Customize IP dialog box for AXI EMC.
Figure 4-1: AXI EMC Customize IP Dialog Box
The AXI EMC options are as follows:
AXI Data Width

If the targeted memory is set to Micron® Flash memory and Sync burst is enabled, the AXI4
Data Bus Width must be set to 32-bit. For any other memory, the AXI4 Data Bus Width can
be set to either 32 or 64 bits.
AXI ID Width
ID width of AXI interface, allowed values are 0 to 16.
Note: For IP integrator, ID Width is auto-computed which means that you are not allowed to
override it.

42
PG100 April 5, 2017
Maximum Data Width

This option should be set to the maximum memory data width configured across all
memory banks. Maximum Data Width option can be set as 8, 16, 32, or 64 bits wide.
No. of Memory Banks

Number of memory banks: The valid range for Memory Banks is from 1 to 4. For each
memory bank a tab is provided for bank specific memory configurations. The tab needs to
set for the memory type and for the timing parameters associated with the selected
memory type.
Base Address
Per Bank Base Address for the Memory, the base address for each enabled bank must be set
as per the System Address Map requirement. For more details on Memory Address
Generation, see Address Map Description, page 21.
High Address
Per Bank High Address for the Memory, the High address for each enabled bank must be set
as per the System Address Map requirement. For more details on Memory Address
Generation, see Address Map Description, page 21.
Flash (Memory) Access through STARTUP Primitive

Includes the STARTUP primitive in the design when checked, omits the primitive when not
checked. The STARTUPE3 primitive is featured in UltraScale™ architecture and later devices.
It is useful in sharing the Data pins and CEN pin with external BPI flash memory. This
parameter selection affects IOB attributes generated in XDC, when enabled IOB Attributes
are not applied to pins directly connected to STARTUP primitive.
This parameter determines if STARTUP Primitive instantiation is within the IP or outside of it.

43
PG100 April 5, 2017
Figure 4-2 shows the Customize IP dialog box for each memory bank of AXI EMC core.
Figure 4-2: Memory Bank of AXI EMC
Memory Type
Memory Type for the selected bank can configured as Sync SRAM, Async SRAM, Linear
Flash, Page Mode Flash, PSRAM, or Micron Flash. For the supported memory combinations
across memory banks, see Allowable Memory Combination, page 22.
Data Width
Memory data width for the selected bank, Data Width of the Memory connected to the
bank can be set as 8, 16, 32, or 64 bits wide.
Parity
Parity is applicable only when Memory Type selected for the bank is Sync SRAM. Parity for
the memory can be set as No parity, Odd Parity, or Even Parity.

44
PG100 April 5, 2017
Delay Model
This configuration option is applicable only when Memory Type selected for the bank is
Sync SRAM. The Delay Model for the Sync SRAM can be set as a Flow-Through model or
Pipeline Model. See Timing Diagrams, page 34.
Read CE Low to Data Valid Period

Read Chip Enable to Data Valid Period specification for the memory in the selected bank.
This configuration option is applicable only when memory type in the bank is
asynchronous. This option is equivalent to tACE for asynchronous SRAM and tELQV for flash
memory in the respective memory device data sheets.
Read Address Valid to Data Valid Period

Read Address Valid to Data Valid Period specification for the memory in the selected bank.
This configuration option is applicable only when memory type in the bank is
asynchronous. This option is equivalent to tAA for asynchronous SRAM and tAVQV for flash
memory in the respective memory device data sheets.
IMPORTANT: Read cycle time for AXI EMC core is determined by Read CE Low to Data Valid Period and
Read Address Valid to Data Valid Period configuration settings and is the Maximum[Read CE Low to
Data Valid Period, Read Address Valid to Data Valid Period].
Page Access Period

Page Access Period specification for the asynchronous flash memory in the selected bank.
This configuration option is applicable only when memory type in the bank is Page Mode
Flash Memory. This option is equivalent to tPACC in the Page Mode Flash device data sheet
and must be assigned only when Memory Type selected for the bank is Page Mode Flash.
Read CE High to Data Bus HZ Period

Read CE High to data bus High impedance period specification for the memory in the
selected bank. This configuration option is applicable only when memory type in the bank
is asynchronous. This option is equivalent to tHZCE for asynchronous SRAM and tEHQZ for
flash memory in the respective memory device data sheets.
Read OE High to Data Bus HZ Period

Read OE High to data bus High impedance period specification for the memory in the
selected bank. This configuration option is applicable only when memory type in the bank
is asynchronous. This option is equivalent to tHZOE for asynchronous SRAM and tGHQZ for
flash memory in the respective memory device data sheets.

45
PG100 April 5, 2017
IMPORTANT: Read cycle recovery to write period for AXI EMC core is determined by Read CE High to
Data Bus HZ Period and Read OE High to Data Bus HZ Period configuration settings and is the
MAXIMUM[Read CE High to Data Bus HZ Period, Read OE High to Data Bus HZ Period].
Write Cycle Period

Write cycle time of the memory bank. This configuration option is applicable only when
memory type in the bank is asynchronous. This option is equivalent to tWC for
asynchronous SRAM and tCW for flash memory in the respective memory device data
sheets.
The AXI EMC core uses this parameter to hold CEN Low for each write at the memory
interface.
Write Enable Minimum Pulse Width

Write enable minimum pulse width duration of the memory bank. This configuration option
is applicable only when memory type in the bank is asynchronous. This option is equivalent
to tWP for Asynchronous SRAM and tPWE for flash memory in the respective memory
device data sheets.
The AXI EMC core uses this parameter to hold WEN Low for each write at the memory
interface.
IMPORTANT: CEN Low and WEN Low time generated by the AXI EMC core is determined by Write Cycle
Period and Write Enable Minimum Pulse Width configuration settings. It is the MAXIMUM[Write Cycle
Period, Write Enable Minimum Pulse Width].
Write Phase Period

Write cycle phase time period of the memory bank. This configuration option is applicable
only when memory type in the bank is asynchronous.
The AXI EMC core uses this parameter to determine the number of NOP cycles between two
consecutive writes at the memory side. When this parameter is set to zero, CEN goes High
for one clock cycle between writes.
Write WE High to Data Bus LZ Period

Write cycle write enable High to data bus Low impedance duration of memory bank. This
configuration option is applicable only when memory type in the bank is asynchronous.
This option is equivalent to tLZWE for asynchronous SRAM and tWHGL for flash memory in
the respective memory device data sheets. This option is also used to meet write recovery
to read time requirements of the memory.

46
PG100 April 5, 2017
Write Recovery Period for Flash Memory

Write recovery period for flash memories of the memory bank. This configuration option is
applicable only when memory type in the bank is any flash memory or PSRAM. This option
is equivalent to tWR for flash memory in the respective memory device data sheets.
The AXI EMC core uses this parameter to determine the number of NOP cycles at memory
interface after each AXI WLAST.
RECOMMENDED: You should provide the value for C_AXI_CLK_PERIOD_PS which is equivalent to AXI
clock used. This value is used for internal calibration of counters when Asynchronous memories are
used. By default this is set to 10,000 which is a value corresponding to 100 MHz AXI clock.
If the AXI clock connected is not 100 MHz, the parameter has to be set using command
"set_property CONFIG.C_AXI_CLK_PERIOD_PS {time period in picoseconds of AXI
clock} [get_ips <component name of emc IP created>]" in the Tcl Console.
Figure 4-3 to Figure 4-5 show the AXI EMC timing diagrams.
Figure 4-3: AXI EMC Read Timing

Notes:
1. Tcedv/Tavqv refers to Maximum of "Read CE Low to Data Valid Period" and "Read Address Valid to Data Valid
Period."
2. Thzce/Thzoe refers to Maximum of "Read CE High to Data Bus HZ Period" and "Read OE High to Data Buz HZ Valid
Period."
Figure 4-4: AXI EMC Write Timing

Notes:
1. Twc/Twp refers to Maximum of "Write Cycle Period" and "Write Enable Minimum Pulse Width."
2. Twrr refers to Maximum of "Write Recovery Period of Flash."

47
PG100 April 5, 2017
Figure 4-5: AXI EMC Page Access Timing
Figure 4-6 shows the Customize IP dialog box with the Advanced Configuration tab of AXI
EMC core.
Figure 4-6: Advanced Configuration of AXI EMC

48
PG100 April 5, 2017
Enable Burst Mode for Micron Flash

When set, enables Burst mode for Micron Flash memory. By default Burst mode is disabled
for Micron Flash memory. This option is not applicable when Micron Flash is selected with
other possible Asynchronous memories.
Enable Internal Registers

When set, includes AXI4-LITE interface for accessing internal core registers. This option is
applicable when Sync SRAM, PSRAM, or Micron Flash memory in Sync mode is set for any
of the memory bank.
Figure 4-7 shows the Customize IP dialog box with the Summary tab of AXI EMC core.
Figure 4-7: Summary of AXI EMC

49
PG100 April 5, 2017
User Parameters
Table 4-1 shows the relationship between the fields in the Vivado IDE and the User
Parameters (which can be viewed in the Tcl Console).
Table 4-1: Vivado IDE Parameter to User Parameter Relationship

Vivado IDE Parameter(1) User Parameter(1) Default Value(1)
AXI Data Width C_S_AXI_MEM_DATA_WIDTH 32
AXI ID Width C_S_AXI_MEM_ID_WIDTH 4
Number of Memory Banks C_NUM_BANKS_MEM 1
0x*0000000
Memory Bank Base Address
“*” depends on bank dealing with
Valid HEX values for number of banks C_S_AXI_MEM*_BASEADDR (3)
starts from A to D.
selected with no overlaps.
A for first bank, B for second, etc.
0x*FFFFFFF
Memory Bank High Address
“*” depends on bank dealing with
Valid HEX values for number of banks C_S_AXI_MEM*_HIGHADDR (3)
starts from A to D.
selected with no overlaps.
A for first bank, B for second, etc.
Memory Type
Value 0 to Sync SRAM
1 to Async SRAM 0
2 to Linear Flash C_MEM*_TYPE (3) This value corresponds to Sync
3 to Page Mode Flash SRAM.
4 to PSRAM
5 to Micron Flash
Data Width
8, 16, 32, and 64 for Sync and Async SRAMs
and fixed value of 16 for other memory
C_MEM*_WIDTH (3) 16
types.
64 is allowed only if
C_S_AXI_MEM_DATA_WIDTH selected is 64.
Parity
Applicable only for Sync SRAM memories
and should be same for all the banks
enabled. C_PARITY_TYPE_MEM_* (3) 0
Value 0 to No Parity
1 to Odd Parity
2 to Even Parity
Delay Model
Applicable only for Sync SRAM memories. C_SYNCH_PIPEDELAY_* (3) 1
Value 1 to flow through 2 to Pipeline Delay.
Read CE Low to Data Valid Period (2) C_TCEDV_PS_MEM_* (3) 15000
(2) (3)
Read Address Valid to Data Valid Period C_TAVDV_PS_MEM_* 15000
(2) (3)
Page Access Period C_TPACC_PS_FLASH_* 25000

50
PG100 April 5, 2017
Table 4-1: Vivado IDE Parameter to User Parameter Relationship (Cont’d)

Vivado IDE Parameter(1) User Parameter(1) Default Value(1)
Read CE High to Data Bus HZ Period (2) C_THZCE_PS_MEM_* (3) 7000
(2) C_THZOE_PS_MEM_* (3)
Read OE High to Data Bus HZ Period 7000
Write Cycle Period (2) C_TWC_PS_MEM_* (3) 15000
Write Enable Min. Pulse Width (2) C_TWP_PS_MEM_* (3) 12000
(2) C_TWPH_PS_MEM_* (3)
Write Phase Period 12000
Write WE High to Data Bus LZ Period (2) C_TLZWE_PS_MEM_* (3) 0
Write Recovery Period for Flash Memory (2) C_WR_REC_TIME_MEM_* (3) 27000
Enable Sync Burst Mode for Micron Flash
Applicable only for Micron Flash. C_LINEAR_FLASH_SYNC_BURST 0
Allowable values are 0 and 1.
Enable Internal Registers
Applicable only when memory selected is
Sync SRAM, Async SRAM, PSRAM, or C_S_AXI_EN_REG 0
Micron Flash.
Allowable values are 0 and 1.
Flash (Memory) access through STARTUP
Primitive possible values are C_USE_STARTUP 0
FALSE: 0 and TRUE: 1
STARTUP Primitive instantiation within or
outside of IP
C_USE_STARTUP_INT 0
STARTUP external to IP: 0
STARTUP internal to IP: 1
Notes:
1. Parameter values are listed in the table where the Vivado IDE parameter value differs from the user parameter value. Such
values are shown in this table as indented below the associated parameter.
2. Applicable only for Async Memories and flashes should be bases on memory data sheet.
3. “*” depends on number of banks selected, ranges from 0 to “C_NUM_BANKS_MEM – 1.”
Output Generation
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 3].

51
PG100 April 5, 2017
Constraining the Core

This section contains information about constraining the core in the Vivado Design Suite.
Required Constraints
If external pull-ups/pull-downs are not available on the MEM_DQ signals, these constraints
should be specified to use pull-up or pull-down resistors, as in this example:
set_property PULLDOWN true [get_ports MEM_DQ[0]]

...
STARTUP is enabled: The operation frequency of AXI EMC is affected when a STARTUP
primitive is enabled. This primitive has its own delay that is not accounted in the entire
implementation/timing process.
STARTUPE3 primitive is used to drive the Data pins to the flash. When using the STARTUP
primitive, the clock-data relationship changes due to the extra delay added in the data pins
path. This delay can vary from as low as 0.1 ns to as high as 7.5 ns based on the device and
speed grade. This value can be found in the FPGA data sheet.
Because this delay is not timed by the tool, you must consider the maximum delay for all
calculations. Assume this delay is called CCLK_DELAY. For K7-2 this value can range from
0.5 ns to 6.7 ns. This puts the first restriction on the frequency of the clock. The frequency
of operation cannot exceed F Max1 = (1/CCLK_DELAY) MHz.
Constraining the IP
To understand how the constraints are added, it is important to understand the logic
structure around the data pins in AXI EMC and BPI flash memory.

52
PG100 April 5, 2017
Figure 4-8 shows the logic structure.

*HQHUDO,QWHUFRQQHFW &)*/RJLF
',>@
4 '
&ORFN
)ODVK
'>@
'2>@
' 4
67$5783
;
Figure 4-8: AXI EMC Logic Structure
The STARTUP primitive adds delay on the data[3:0] pins. This delay is unaccounted for in the
tool and is not considered in the timing calculation. For the tool, the timing path ends at
data[3:0] internal flops.
To obtain the required constraints you must account for the STARTUP primitive delay.
This takes into account the delay of the flip-flop that generates the data, the routing delay
from that flip-flop to Data pins, and the STARTUP primitive delay. Further, to reduce the
delay on data pins you must ensure that the delay from the flip-flop to pin is as low as
possible. This can be constrained by using set_output_delay and set_input_delay
constraints.
#### All the delay numbers have to be provided by the user

#### Max delay constraints are used to instruct the tool to place IP near to STARTUPE3
primitive.
#### If needed adjust the delays appropriately
set_max_delay -to [get_pins -hier {*Mem_DQ_I_v_reg[4]/D} -filter {NAME=~*EMC_CTRL_I/
IO_REGISTERS_I*}] 1.500
set_min_delay -to [get_pins -hier {*Mem_DQ_I_v_reg[4]/D} -filter {NAME=~*EMC_CTRL_I/

53
PG100 April 5, 2017

set_max_delay -to [get_pins -hier {*STARTUP*_inst/DO[*]}] 1.500
set_min_delay -to [get_pins -hier {*STARTUP*_inst/DO[*]}] 0.100
set_max_delay -to [get_pins -hier {*STARTUP*_inst/DTS[*]}] 1.500
set_min_delay -to [get_pins -hier {*STARTUP*_inst/DTS[*]}] 0.100
Device, Package, and Speed Grade Selections

This section is not applicable for this IP core.
Clock Frequencies
The IP reads the clock frequency value in IPI. This value is then used to calculate the various
timing parameters.
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement


54
PG100 April 5, 2017
Simulation
For comprehensive information about Vivado simulation components, as well as
information about using supported third-party tools, see the Vivado Design Suite User
Guide: Logic Simulation (UG900) [Ref 7].
IMPORTANT: For cores targeting 7 series or Zynq-7000 AP SoC devices, UNIFAST libraries are not
supported. Xilinx IP is tested and qualified with UNISIM libraries only.
Synthesis and Implementation

For details about synthesis and implementation, see the Vivado Design Suite User Guide:
Designing with IP (UG896) [Ref 3].

55
PG100 April 5, 2017
Chapter 5
Example Design
This chapter contains information about the example design provided in the Vivado®
Design Suite.
The top-level example design for the AXI EMC core is <component_name>_exdes.vhd.
The complete example design works as a mini-system to show the AXI EMC functionality by
performing read and write transactions to memory model (Figure 5-1).
<component_name>_exdes.vhd (top)
Memory Block DUT

EMC Ports
clk_n
clk_p Clock
Generator Data Read/Write
reset Logic
X13764
Figure 5-1: AXI EMC Example Design Block Diagram

56
PG100 April 5, 2017
The following is the brief description of individual blocks:
• Clock Generator – EMC example design makes use of the clocking wizard to supply
clocks and resets to all other blocks in the design. The clocking wizard is configured to
provide 100 MHz clock to all the blocks, and the locked signal from the wizard is
appropriately used as Resets.
• Memory – Block Memory Generator (BMG) core is used to serve for memory storage in
the example design. It is configured for 32 × 1,024 memory whose first 256 locations
are initialized using a coefficient file. The example design uses the first half of the BMG
as the source of data to write data to the memory model through EMC, and it uses the
second half to store data read from model through EMC.
• Data Read/Write Path – Example design uses the Central Direct Memory Access
(CDMA) core to generate the required AXI instructions for data flow between BMG and
EMC in both directions. The design uses two instances of CDMA:
° One instance that reads the channel connected to BMG, and writes the channel
connected to EMC. This is called as Write CDMA in design and is used to write data
from BMG to EMC.
° Another CDMA instance that reads the channel connected to EMC and writes the
channel connected to BMG. This is called Read CDMA to read data from EMC and
write to BMG.
• AXI Traffic Generator – Example design makes use of the AXI Traffic Generator (ATG)
core in system test mode to control the transaction sequence. ATG is connected to both
CDMAs to program them for the source address, destination address, and bytes to
transfer registers based on which AXI instructions are generated by the CDMA. The ATG
takes four COE files as input, and gives done and status pins as outputs which
determines the result of the tests. It instantiates IOBUF to take in I, O, and T pins of the
EMC, and gives out a single I/O pin that communicates with the memory model.
IMPORTANT: The example design is not supported when the start-up block is enabled
Implementing the Example Design

After following the steps described in Customizing and Generating the Core, page 41 to
generate the core, implement the example design as follows:
1. Right-click the core in the Hierarchy window, and select Open IP Example Design.
2. A new window pops up, asking you to specify a directory for the example design. Select
a new directory or keep the default directory.
3. A new project is automatically created in the selected directory and it is opened in a new
Vivado window.

57
PG100 April 5, 2017
4. In the Flow Navigator (left-side pane), click Run Implementation and follow the
directions.
Example Design Directory Structure

This directory and its subdirectories contain all the source files that are required to create
the AXI EMC example design.
Table 5-1 shows the files delivered in the example design directory. It contains the
generated example design top files.
Table 5-1: Example Design Directory

Name Description
Top-level project directory; the name is
topdirectory
user-defined.
The VHDL example design, test bench and
<component_name>/example design
COE files.
Table 5-2 shows the files delivered in the <project_name>/<project_name>.srcs/

sources_1/ip/ directory.
Table 5-2: Project Files

Name Description
Synth/<component_name>.v|vhd Synthesis wrapper generated by the Vivado tool.
Sim/<component_name>.v|vhd Simulation wrapper generated by the Vivado tool.
Vivado tools project-specific option file; can be used as an
<component_name>.xci
input to the Vivado tools.
<component_name>.vho|veo VHDL or Verilog instantiation template.
<component_name>_ooc.xdc Out of Context constraints for IP.
These files are intended for the usage of example design, and
COE Files after open example design is performed all these are copied
to new project created.
Table 5-3 shows the files delivered in the <component_name>/example design

provided with the core.
Table 5-3: Example Design Files

Name Description
<component_name>_exdes.vhd Example design top file for synthesis.
<component_name>_exdes_tb.vhd Example design top file for simulation.
<memory_model>.vhd Memory model to mimic the behavior in simulation.
Exdes.xdc Constraints for the example design

58
PG100 April 5, 2017
Chapter 6
Test Bench
This chapter contains information about the test bench provided in the Vivado ® Design
Suite.
Figure 6-1 shows a top-level view of the example design test bench.
Demo Test Bench
Simulation Status
Check Logic
ATG Status signals
Memory Model
EMC
(Dynamically changes as
Example Design
per user selection)
Mme Signals
X13765
Figure 6-1: AXI EMC Example Design Test Bench

59
PG100 April 5, 2017
Chapter 6: Test Bench
The demonstration test bench performs the following tasks:
• Generates the clock and reset inputs for the clocking wizard.
• Instantiates the memory model which communicates with EMC. The memory model
used depends on your selection in the Vivado Integrated Design Environment (IDE).
• Instantiates IOBUF to take in I, O, and T pins of the memory model, and give a single
I/O port to connect with EMC.
• Considers the done and status pins from ATG and determines the simulation status.
Simulating the Example Design

Using the AXI EMC example design (delivered as part of the AXI EMC), you can quickly
simulate and observe the behavior of the AXI EMC.
Setting Up the Simulation

The Xilinx® simulation libraries must be mapped into the simulator. If the libraries are not
set for your environment, see the Vivado Design Suite User Guide: Logic Simulation (UG900)
[Ref 7] for assistance compiling Xilinx simulation models and setting up the simulator
environment. To switch simulators, click Simulation Settings in the Flow Navigator (left
pane). In the Simulation options list, change Target Simulator.
Simulation Results
The simulation script compiles the AXI EMC example design and supporting simulation
files. It then runs the simulation and checks to ensure that it completed successfully.
If the test passes, then the following message is displayed:
Test Completed Successfully
If the test fails or does not complete, then the following message is displayed:
Test Hanged
This is the message displayed when example design simulation fails.

60
PG100 April 5, 2017
Appendix A
Verification, Compliance, and

Interoperability
This appendix provides details about how this IP core was tested for compliance.
Simulation
The AXI External Memory Controller (EMC) core has been tested with Xilinx® Vivado ®
Design Suite and the Mentor Graphics QuestaSim simulator. For the supported versions of
these tools, see the Xilinx Design Tools: Release Notes Guide (UG631)(3).
The IP is tested using Xilinx proprietary standard AXI Memory Mapped OVM Verification
Components (OVCs).

61
PG100 April 5, 2017
Hardware Testing
Figure A-1 shows the hardware testing setup for the AXI EMC core.
X-Ref Target - Figure A-1
Figure A-1: AXI EMC Core Hardware Testing
The AXI EMC core has been hardware validated on a KC705 board using a Kintex®-7 FPGA
with –1 speed grade (325T). The setup uses a AXI4 system implementing a MicroBlaze™
processor, AXI4 interconnects, AXI Interrupt Controller, AXI block RAM and UART peripheral,
in addition to the AXI EMC core. The AXI EMC core in this setup is connected to Linear Flash
Memory and is used to load the device boot code from the flash memory to an internal AXI
block RAM memory. AXI EMC core operation in this setup is set to 100 MHz and Flash
Memory is operated at a frequency of 50 MHz.
Also, the AXI EMC core has been tested on a VCU108 board having a STARTUP block inside
the IP, The following is a snapshot of the timing parameters of the
MT28GU01GAAA1EGC-0SIT flash present on the board.

62
PG100 April 5, 2017
X-Ref Target - Figure A-2
Figure A-2: AXI EMC Core Tested on a VCU108 Board

63
PG100 April 5, 2017
Appendix B
Migrating and Upgrading

This appendix contains information about upgrading to a more recent version of the IP
core.
Migrating to the Vivado Design Suite

For information on migrating to the Vivado Design Suite, see the Vivado Design Suite
Migration Methodology Guide (UG911) [Ref 8].
Upgrading in the Vivado Design Suite

There are no port or parameter changes.

64
PG100 April 5, 2017
Appendix C
Debugging
This appendix includes details about resources available on the Xilinx ® Support website,
and about debugging tools.
Finding Help on Xilinx.com

To help in the design and debug process when using the AXI EMC core, the Xilinx Support
web page contains key resources such as product documentation, release notes, answer
records, information about known issues, and links for obtaining further product support.
Documentation
This product guide is the main document associated with the AXI EMC. This guide, along
with documentation related to all products that aid in the design process, can be found on
the Xilinx Support web page or by using the Xilinx Documentation Navigator.
Download the Xilinx Documentation Navigator from the Downloads page. For more
information about this tool and the features available, open the online help after
installation.

65
PG100 April 5, 2017
Answer Records
Answer Records include information about commonly encountered problems, helpful
information on how to resolve these problems, and any known issues with a Xilinx product.
Answer Records are created and maintained daily ensuring that you have access to the most
accurate information available.
Answer Records for this core can be located by using the Search Support box on the main
Xilinx support web page. To maximize your search results, use proper keywords such as
• Product name
• Tool messages
• Summary of the issue encountered
A filter search is available after results are returned to further target the results.
Master Answer Record for the AXI EMC
AR: 54429
Technical Support
Xilinx provides technical support at Xilinx support web page for this LogiCORE™ IP product
when used as described in the product documentation. Xilinx cannot guarantee timing,
functionality, or support if you do any of the following:
• Implement the solution in devices that are not defined in the documentation.
• Customize the solution beyond that allowed in the product documentation.
• Change any section of the design labeled DO NOT MODIFY.
To contact Xilinx Technical Support, navigate to the Xilinx Support web page.
Debug Tools
Vivado Design Suite Debug Feature
The Vivado® Design Suite debug feature inserts logic analyzer (ILA) and virtual I/O (VIO)
cores directly into your design. The Vivado Design Suite debug feature also allows you to set
trigger conditions to capture application and integrated block port signals in hardware.
Captured signals can then be analyzed. This feature in the Vivado IDE is used for logic
debugging and validation of a design running in Xilinx devices.

66
PG100 April 5, 2017
The Vivado logic analyzer is used with the logic debug IP cores, including:
• ILA 2.0 (and later versions)

• VIO 2.0 (and later versions)
See the Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref 9].
Interface Debug
AXI4-Lite Interfaces
Read from a register that does not have all 0s as a default to verify that the interface is
functional. Output s_axi_reg_arready asserts when the read address is valid, and
output s_axi_reg_rvalid asserts when the read data/response is valid. If the interface is
unresponsive, ensure that the following conditions are met:
• The s_axi_aclk and aclk inputs are connected and toggling.

• The interface is not being held in reset, and s_axi_areset is an active-Low reset.
• The interface is enabled, and s_axi_aclk is active-High (if used).
• The main core clocks are toggling and that the enables are also asserted.
• If the simulation has been run, verify in simulation and/or a Vivado Lab tool capture
that the waveform is correct for accessing the AXI4-Lite interface.
• Program the necessary registers for PSRAM and Sync Mode Linear Flash memory as per
guidelines given in Register Description in Chapter 2.
• If any non-existent register is accessed either through read or write AXI transaction, the
core sends ACK and completes the transaction.
AXI4-Memory Mapped Interfaces

• The core supports all AXI transactions, except FIXED transactions.
• The core responds to read and write transactions in round robin fashion. This ensures
that none of the AXI channels are kept in wait mode.
• The core supports single memory access at a given time.
• The AXI read transactions are completed by the core with data and read response.
• In case of any read data error, the particular data response from the core is slave error.
• The AXI write transactions are completed by the core with proper response at the
acceptance of the last AXI transaction (after the actual write transactions to the memory
is over).

67
PG100 April 5, 2017
• To access the Async Mode memories (and flash memories), add timing parameters after
referring to the data sheets.
• In case of Sync Mode Linear Flash memory access, core support fixed relation is
between the AXI clock (100 MHz) and the Sync Mode Linear Flash memory clock
(50 MHz).
• Observe the memory interface signals activity when the AXI transactions are accepted
by the core.

68
PG100 April 5, 2017
Appendix D
Additional Resources and Legal Notices
Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx
Support.
References
These documents provide supplemental material useful with this product guide:
1. ARM AMBA AXI and ACE Specification (ARM IHI 0022D)

2. UltraScale Architecture Libraries Guide (UG974)
3. Vivado Design Suite User Guide: Designing with IP (UG896)
4. Vivado AXI Reference Guide (UG1037)
5. Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
6. Vivado Design Suite User Guide: Getting Started (UG910)
7. Vivado Design Suite User Guide: Logic Simulation (UG900)
8. ISE to Vivado Design Suite Migration Methodology Guide (UG911)
9. Vivado Design Suite User Guide: Programming and Debugging (UG908)
10. LogiCORE IP AXI Interconnect Product Guide (PG059)

69
PG100 April 5, 2017
Revision History
The following table shows the revision history for this document.
Date Version Revision

04/05/2017 3.0 Added AXI4 restriction when using AXI EMC with a flash device.
11/18/2015 3.0 Added support for UltraScale+ families.
09/30/2015 3.0 • Added Flash (Memory) Access through STARTUPE Primitive section.
• Added note #6 and 7 in I/O Signal Descriptions table.
• Added STARTUPE Primitive section.
• Updated figures and added timing diagrams in Customizing and
Generating the Core section.
• Added Flash (Memory) Access through STARTUP Primitive section.
• Updated User Parameters table.
• Added Constraining the IP section.
• Added important note in Example Design.
04/01/2015 3.0 • Updated description in Configuring the Numonyx Flash in Sync Burst Read
Mode section.
• Updated Fig. 3-2: Synchronous Memory Bank Clocked by FPGA Output with
Feedback and added constraints in Clocking Synchronous Memory section.
• Updated Software Considerations section.
• Added UNISIM important note in Simulation section.
11/19/2014 3.0 • Document updates only for revision change.
• Updated Bits[31, 6] description in Table 2-8: PSRAM/Numonyx Flash
Configuration Register (PSRAM_FLASH_CONFIG_REG_X).
• Updated description in Configuring the Numonyx Flash in Sync Burst Read
Mode section.
06/04/2014 3.0 • Updated Note in I/O Signal Descriptions table.
• Updated Note in Allowable Memory Combination section.
• Updated Fig. 4-4: Summary of AXI EMC in Enable Internal Registers section.
• Updated description in Enable Burst Mode for Numonyx Flash.
• Added Recommended Note in Write Recovery Period for Flash Memory
section.
• Added User Parameters in Design Flow Steps chapter.

70
PG100 April 5, 2017
Date Version Revision

04/02/2014 3.0 • Updated IP Facts table.
• Added UltraScale support in Maximum Frequencies section.
• Updated Table 2-1: Maximum Frequencies.
• Added data width description in Memory Controller Unit section.
• Disabled parity feature in Byte Parity Logic section.
• Updated ports, ID width description, and memory parity notes in Table 2-5
I/O Signal Descriptions.
• Added Numonyx Flash description to Clocking Synchronous Memory
section.
• Updated description in Configuring the Numonyx Flash in Sync Burst Read
Mode section.
• Updated description in Allowable Memory Combination section.
• Updated figures and descriptions in Customizing and Generating the Core
chapter.
• Updated Constraining the Core chapter.
• Updated to Test Hanged in Simulation Results section.
• Added Important note in Example Design chapter.
• Updated description in Test Bench chapter.
12/18/2013 2.0 Added UltraScale support.
10/02/2013 2.0 Re-release of document for core v2.0, with the following changes made:
• Added information related to the core design example, and test bench.
• Added Vivado IP integrator support.
• Added the Simulation, and Synthesis and Implementation chapters.
• Added AXI4-memory mapped interface debug information.
03/20/2013 2.0 • Updated to core v2.0 and Vivado Design Suite-only support.
• Updates to modules, and timing diagrams.
• Added Appendix A, Verification, Compliance, and Interoperability.
• Major revisions to Appendix C, Debugging.
12/18/2012 1.0 Initial Xilinx release as a product guide. Replaces LogiCORE IP AXI EMC Data
Sheet, DS762.

71
PG100 April 5, 2017
Please Read: Important Legal Notices

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the
maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS
ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether
in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related
to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special,
incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a
result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised
of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of
updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials
without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to
Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and
support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use
in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical
applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.
AUTOMOTIVE APPLICATIONS DISCLAIMER
AUTOMOTIVE PRODUCTS (IDENTIFIED AS “XA” IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF
AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE (“SAFETY APPLICATION”) UNLESS THERE IS A
SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD (“SAFETY
DESIGN”). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY
TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY
AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT
LIABILITY.
© Copyright 2012–2017 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated
brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of
their respective owners.

72
PG100 April 5, 2017

pg100 Axi Emc

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

pg100 Axi Emc

Uploaded by

Copyright:

Available Formats

AXI EMC v3.

LogiCORE IP Product Guide

Vivado Design Suite

Chapter 2: Product Specification

Chapter 3: Designing with the Core

Chapter 4: Design Flow Steps

Chapter 5: Example Design

Chapter 6: Test Bench

AXI EMC v3.0 www.xilinx.com Send Feedback

Appendix B: Migrating and Upgrading

Appendix D: Additional Resources and Legal Notices

AXI EMC v3.0 www.xilinx.com Send Feedback

Introduction LogiCORE IP Facts Table

Example Design VHDL

Features Test Bench

• Provides configuration registers to

AXI EMC v3.0 www.xilinx.com Send Feedback 4

AXI EMC Core

Memory Controller Unit

AXI4 addr Counters

AXI EMC v3.0 www.xilinx.com Send Feedback

• AXI4 Slave Interface

AXI4 Slave Interface

AXI EMC v3.0 www.xilinx.com Send Feedback

Memory Controller Unit

Byte Parity Logic

AXI EMC v3.0 www.xilinx.com Send Feedback

Flash (Memory) Access through STARTUPE Primitive

AXI EMC v3.0 www.xilinx.com Send Feedback

X-Ref Target - Figure 1-2

Figure 1-2: AXI EMC Core Application Diagram

AXI EMC v3.0 www.xilinx.com Send Feedback

Licensing and Ordering Information

AXI EMC v3.0 www.xilinx.com Send Feedback

AXI EMC v3.0 www.xilinx.com Send Feedback

Table 2-1: Maximum Frequencies (Cont’d)

Table 2-2: Device Utilization – Virtex-7 FPGAs

AXI EMC v3.0 www.xilinx.com Send Feedback

2 0 1 8 32 1 0 1 669 452 271 281

Table 2-4: Device Utilization – Artix-7 and Zynq-7000 FPGAs

AXI EMC v3.0 www.xilinx.com Send Feedback

Table 2-5: I/O Signal Descriptions

Signal Name Interface I/O Initial Description

AXI EMC v3.0 www.xilinx.com Send Feedback

Table 2-5: I/O Signal Descriptions (Cont’d)

Signal Name Interface I/O Initial Description

AXI EMC v3.0 www.xilinx.com Send Feedback

Table 2-5: I/O Signal Descriptions (Cont’d)

Signal Name Interface I/O Initial Description

Table 2-6: Internal Registers and Offsets

AXI EMC v3.0 www.xilinx.com Send Feedback

Table 2-6: Internal Registers and Offsets (Cont’d)

AXI Lite Base Address + Offset Access Default

PARITY ERROR ADDRESS Register (PARITY_ERR_ADDR_REG_x)

Figure 2-1: AXI EMC Parity Error Address Register

Table 2-7: Parity Error Address Register Description

PSRAM/Flash Configuration Register (PSRAM_FLASH_CONFIG_REG_X)

AXI EMC v3.0 www.xilinx.com Send Feedback

There can be four PSRAM_FLASH_CONFIG_REG registers. The PSRAM/Micron Flash Burst

Figure 2-2: PSRAM/Micron Flash Configuration Register

Table 2-8: PSRAM/Micron Flash Configuration Register (PSRAM_FLASH_CONFIG_REG_X)

Bits Name Core Reset Description

AXI EMC v3.0 www.xilinx.com Send Feedback

set_property IOB true [get_cells -hierarchical -filter {NAME =~mem_ben_reg}]