AM26C31 Quadruple Differential Line Driver: 1 Features 3 Description
AM26C31 Quadruple Differential Line Driver: 1 Features 3 Description
AM26C31 Quadruple Differential Line Driver: 1 Features 3 Description
AM26C31
SLLS103O – DECEMBER 1990 – REVISED JUNE 2016
Device Information(1)
2 Applications
PART NUMBER PACKAGE BODY SIZE (NOM)
• Chemical and Gas Sensors AM26C31J CDIP (16) 19.56 mm × 6.92 mm
• Field Transmitters: Temperature Sensors and AM26C31N PDIP (16) 19.30 mm × 6.35 mm
Pressure Sensors AM26C31NS SO (16) 10.30 mm × 5.30 mm
• Military: Radars and Sonars AM26C31W CFP (16) 10.30 mm × 6.73 mm
• Motor Control: Brushless DC and Brushed DC AM26C31D SOIC (16) 9.90 mm × 3.91 mm
• Military and Avionics Imaging AM26C31DB SSOP (16) 6.20 mm × 5.30 mm
• Temperature Sensors and Controllers Using AM26C31PW TSSOP (16) 5.00 mm × 4.40 mm
Modbus AM26C31FK LCCC (20) 8.89 mm × 8.89 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VCC
0.1 PF
16
1A 4A
Input 1 Signal 1 15 Input 4 Signal
1Y 4Y
2 14
Output 1 Output 4
Differential Pair 1Z 4Z Differential Pair
3 13
G G
4 12 Active Low Enable Signal
2Z 3Z
5 11
Output 2 Output 3
Differential Pair 2Y 3Y Differential Pair
6 10
2A 3A
Input 2 Signal 7 9 Input 3 Signal
8
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AM26C31
SLLS103O – DECEMBER 1990 – REVISED JUNE 2016 www.ti.com
Table of Contents
1 Features .................................................................. 1 8 Detailed Description ............................................ 10
2 Applications ........................................................... 1 8.1 Overview ................................................................. 10
3 Description ............................................................. 1 8.2 Functional Block Diagrams ..................................... 10
4 Revision History..................................................... 2 8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Application and Implementation ........................ 12
9.1 Application Information............................................ 12
6.1 Absolute Maximum Ratings ..................................... 4
9.2 Typical Application ................................................. 12
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4 10 Power Supply Recommendations ..................... 13
6.4 Thermal Information .................................................. 5 11 Layout................................................................... 14
6.5 Electrical Characteristics: AM26C31C and 11.1 Layout Guidelines ................................................. 14
AM26C31I .................................................................. 5 11.2 Layout Example .................................................... 14
6.6 Electrical Characteristics: AM26C31Q and 12 Device and Documentation Support ................. 15
AM26C31M ................................................................ 6 12.1 Receiving Notification of Documentation Updates 15
6.7 Switching Characteristics: AM26C31C and 12.2 Community Resources.......................................... 15
AM26C31I .................................................................. 6
12.3 Trademarks ........................................................... 15
6.8 Switching Characteristics: AM26C31Q and
AM26C31M ................................................................ 7 12.4 Electrostatic Discharge Caution ............................ 15
6.9 Typical Characteristics .............................................. 7 12.5 Glossary ................................................................ 15
7 Parameter Measurement Information .................. 8 13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Updated the Features section and added the Applications section, the Device Information table, ESD Ratings table,
Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1
• Deleted Ordering Information table, see POA at the end of the data sheet........................................................................... 1
• Changed Thermal Information table ....................................................................................................................................... 5
VCC
NC
1Y
1A
4A
1A 1 16 VCC
1Y 2 15 4A
1Z 3 14 4Y
3
2
1
20
19
G 4 13 4Z 1Z 4 18 4Y
2Z 5 12 G G 5 17 4Z
2Y 6 11 3Z NC 6 16 NC
2A 7 10 3Y 2Z 7 15 G
GND 8 9 3A 2Y 8 14 3Z
10
12
13
11
9
Not to scale
Not to scale
2A
GND
NC
3A
3Y
Pin Functions
PIN
CDIP, CFP, SOIC, I/O DESCRIPTION
NAME SSOP, SO, PDIP, LCCC
TSSOP
1A 1 2 I Driver 1 input
1Y 2 3 O Driver 1 output
1Z 3 4 O Driver 1 inverted output
2A 7 9 I Driver 2 input
2Y 6 8 O Driver 2 output
2Z 5 7 O Driver 2 inverted output
3A 9 12 I Driver 3 input
3Y 10 13 O Driver 3 output
3Z 11 14 O Driver 3 inverted output
4A 15 19 I Driver 3 input
4Y 14 18 O Driver 3 output
4Z 13 17 O Driver 3 inverted output
G 4 5 I Active high enable
G 12 15 I Active low enable
GND 8 10 — Ground pin
NC (1) — 1, 6, 11, 16 — No internal connection
VCC 16 20 — Power pin
(1) NC – No connection
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage (2) –0.5 7 V
VI Input voltage –0.5 VCC + 0.5 V
VID Differential input voltage –14 14 V
VO Output voltage –0.5 7
IIK
Input or output clamp current ±20 mA
IOK
IO Output current ±150 mA
VCC current 200 mA
GND current –200 mA
TJ Operating virtual junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the network ground terminal.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA) / RθJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
(4) Modelling assumption: MIL-STD-883 for RθJC(top) and RθJC(bot) JESD51 for RθJB.
RL/2
C2 = 40 pF
500 Ω
Input C1 = 1.5 V
40 pF S1
RL/2
C3 = 40 pF
See Note A
TEST CIRCUIT
Input A 3V
(see Note B) 1.3 V
0V
tPLH tPHL
tsk(p) tsk(p)
Figure 3. Propagation Delay Time and Skew Waveforms and Test Circuit
A. C1, C2, and C3 include probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, and
tr, tf ≤ 6 ns.
TEST CIRCUIT
Enable G Input
3V
(see Note C)
1.3 V1.3 V
Enable G Input 0V
1.5 V
Output WIth
VOL + 0.3 V 0.8 V
0 V to A Input
VOL
tPLZ tPZL
VOH
Output WIth VOH - 0.3 V 2V
3 V to A Input
1.5 V
tPHZ tPZH
VOLTAGE WAVEFORMS
Figure 5. Output Enable and Disable Time Waveforms and Test Circuit
8 Detailed Description
8.1 Overview
The AM26C31 is a quadruple differential line driver with complementary outputs. The device is designed to meet
the requirements of TIA/EIA-422-B and ITU (formerly CCITT), and it is generally used to communicate over
relatively long wires in noisy environments.
4
G
12
G 2
1 1Y
1A 3
1Z
6
7 2Y
2A 5
2Z
10
9 3Y
3A 11
3Z
14
15 4Y
4A 13
4Z
Copyright © 2016, Texas Instruments Incorporated
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
Input Output
GND GND
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
VCC
VCC
0.1 PF
16
1A 4A
Input 1 Signal 1 15 Input 4 Signal
1Y 4Y
2 14
Output 1 Output 4
Differential Pair 1Z 4Z Differential Pair
3 13
G G
4 12 Active Low Enable Signal
2Z 3Z
5 11
Output 2 Output 3
Differential Pair 2Y 3Y Differential Pair
6 10
2A 3A
Input 2 Signal 7 9 Input 3 Signal
8
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 8. Differential Terminated Configuration With All Channels and Active Low Enable Used
2
Voltage (V)
±1
±2
Y A/B
±3
0 0.1 0.2 0.3 0.4 0.5
Time ( s) C001
11 Layout
VCC
1 1A VCC 16
2 1Y 4A 15
3 1Z 4Y 14
4 G 4Z 13
AM26C31
Active Low
5 2Z G 12
Differential Enable
Output 2
6 2Y 3Z 11
Input 2 7 2A 3Y 10
8 GND 3A 9
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 14-Oct-2022
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
5962-9163901M2A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9163901M2A
AM26C31M
5962-9163901MEA ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9163901ME Samples
& Green A
AM26C31M
5962-9163901MFA ACTIVE CFP W 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9163901MF Samples
& Green A
AM26C31M
5962-9163901Q2A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9163901Q2A
AM26C31
MFKB
5962-9163901QEA ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9163901QE Samples
& Green A
AM26C31MJB
5962-9163901QFA ACTIVE CFP W 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9163901QF Samples
& Green A
AM26C31MWB
AM26C31CD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C31C Samples
AM26C31CDBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 26C31 Samples
AM26C31CDE4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C31C Samples
AM26C31CDG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C31C Samples
AM26C31CDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C31C Samples
AM26C31CDRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C31C Samples
AM26C31CDRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C31C Samples
AM26C31CN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 AM26C31CN Samples
AM26C31CNSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 26C31 Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
AM26C31ID ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C31I Samples
AM26C31IDBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C31I Samples
AM26C31IDBRE4 ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C31I Samples
AM26C31IDE4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C31I Samples
AM26C31IDG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C31I Samples
AM26C31IDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 AM26C31I Samples
AM26C31IDRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C31I Samples
AM26C31IDRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C31I Samples
AM26C31IN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 AM26C31IN Samples
AM26C31INE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 AM26C31IN Samples
AM26C31INSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C31I Samples
AM26C31IPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C31I Samples
AM26C31IPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 26C31I Samples
AM26C31IPWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C31I Samples
AM26C31MFKB ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9163901Q2A
AM26C31
MFKB
AM26C31MJB ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9163901QE Samples
& Green A
AM26C31MJB
AM26C31MWB ACTIVE CFP W 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9163901QF Samples
& Green A
AM26C31MWB
AM26C31QD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AM26C31Q Samples
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
AM26C31QDG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 26C31Q Samples
AM26C31QDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AM26C31Q Samples
AM26C31QDRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 26C31Q Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
• Catalog : AM26C31
• Enhanced Product : AM26C31-EP, AM26C31-EP
• Military : AM26C31M
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
Width (mm)
H
W
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TUBE
T - Tube
height L - Tube length
W - Tube
width
Pack Materials-Page 3
PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1 4.55
4.9
NOTE 3
8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 -8
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
14X (0.65)
8 9
(5.8)
4220204/A 02/2017
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
14X (0.65)
8 9
(5.8)
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DB0016A SCALE 1.500
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
C
8.2
TYP
A 7.4
0.1 C SEATING
PIN 1 INDEX AREA
PLANE
14X 0.65
16
1
2X
6.5
4.55
5.9
NOTE 3
8
9
0.38
16X
0.22
5.6
B 0.1 C A B
5.0
NOTE 4
0.25
0.09
SEE DETAIL A
2 MAX
0.25
GAGE PLANE
DETAIL A
A 15
TYPICAL
4220763/A 05/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0016A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
1 (R0.05) TYP
16X (0.45) 16
SYMM
14X (0.65)
8 9
(7)
4220763/A 05/2022
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DB0016A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
14X (0.65)
8 9
(7)
4220763/A 05/2022
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
NS0016A SCALE 1.500
SOP - 2.00 mm max height
SOP
10.4 2X
10.0 8.89
NOTE 3
8
9
0.51
16X
5.4 0.35
B 0.25 C A B 2.00 MAX
5.2
NOTE 4
0.15 TYP
SEE DETAIL A
0.25 0.3
GAGE PLANE 0.1
0 - 10
1.05
0.55 DETAIL A
TYPICAL
(1.25)
4220735/A 12/2021
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
NS0016A SOP - 2.00 mm max height
SOP
1 16
16X (0.6)
SYMM
14X (1.27)
8 9
(R0.05) TYP
(7)
4220735/A 12/2021
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
NS0016A SOP - 2.00 mm max height
SOP
1 16
16X (0.6)
SYMM
14X (1.27)
8 9
4220735/A 12/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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