AM26C31 Quadruple Differential Line Driver: 1 Features 3 Description

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AM26C31
SLLS103O – DECEMBER 1990 – REVISED JUNE 2016

AM26C31 Quadruple Differential Line Driver


1 Features 3 Description
1• Meets or Exceeds the Requirements of TIA/EIA- The AM26C31 device is a differential line driver with
422-B and ITU Recommendation V.11 complementary outputs, designed to meet the
requirements of TIA/EIA-422-B and ITU (formerly
• Low Power, ICC = 100 μA Typical CCITT). The 3-state outputs have high-current
• Operates From a Single 5-V Supply capability for driving balanced lines, such as twisted-
• High Speed, tPLH = tPHL = 7 ns Typical pair or parallel-wire transmission lines, and they
provide the high-impedance state in the power-off
• Low Pulse Distortion, tsk(p) = 0.5 ns Typical
condition. The enable functions are common to all
• High Output Impedance in Power-Off Conditions four drivers and offer the choice of an active-high (G)
• Improved Replacement for AM26LS31 Device or active-low (G) enable input. BiCMOS circuitry
• Available in Q-Temp Automotive reduces power consumption without sacrificing
speed.
– High-Reliability Automotive Applications
The AM26C31C device is characterized for operation
– Configuration Control and Print Support
from 0°C to 70°C, the AM26C31I device is
– Qualification to Automotive Standards characterized for operation from –40°C to 85°C, the
• On Products Compliant to MIL-PRF-38535, All AM26C31Q device is characterized for operation over
Parameters Are Tested Unless Otherwise Noted. the automotive temperature range of –40°C to 125°C,
On All Other Products, Production Processing and the AM26C31M device is characterized for
Does Not Necessarily Include Testing of All operation over the full military temperature range of
Parameters. –55°C to 125°C.

Device Information(1)
2 Applications
PART NUMBER PACKAGE BODY SIZE (NOM)
• Chemical and Gas Sensors AM26C31J CDIP (16) 19.56 mm × 6.92 mm
• Field Transmitters: Temperature Sensors and AM26C31N PDIP (16) 19.30 mm × 6.35 mm
Pressure Sensors AM26C31NS SO (16) 10.30 mm × 5.30 mm
• Military: Radars and Sonars AM26C31W CFP (16) 10.30 mm × 6.73 mm
• Motor Control: Brushless DC and Brushed DC AM26C31D SOIC (16) 9.90 mm × 3.91 mm
• Military and Avionics Imaging AM26C31DB SSOP (16) 6.20 mm × 5.30 mm
• Temperature Sensors and Controllers Using AM26C31PW TSSOP (16) 5.00 mm × 4.40 mm
Modbus AM26C31FK LCCC (20) 8.89 mm × 8.89 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Common Application Diagram


VCC

VCC
0.1 PF
16
1A 4A
Input 1 Signal 1 15 Input 4 Signal
1Y 4Y
2 14
Output 1 Output 4
Differential Pair 1Z 4Z Differential Pair
3 13

G G
4 12 Active Low Enable Signal

2Z 3Z
5 11
Output 2 Output 3
Differential Pair 2Y 3Y Differential Pair
6 10
2A 3A
Input 2 Signal 7 9 Input 3 Signal

8
GND
Copyright © 2016, Texas Instruments Incorporated
1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AM26C31
SLLS103O – DECEMBER 1990 – REVISED JUNE 2016 www.ti.com

Table of Contents
1 Features .................................................................. 1 8 Detailed Description ............................................ 10
2 Applications ........................................................... 1 8.1 Overview ................................................................. 10
3 Description ............................................................. 1 8.2 Functional Block Diagrams ..................................... 10
4 Revision History..................................................... 2 8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Application and Implementation ........................ 12
9.1 Application Information............................................ 12
6.1 Absolute Maximum Ratings ..................................... 4
9.2 Typical Application ................................................. 12
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4 10 Power Supply Recommendations ..................... 13
6.4 Thermal Information .................................................. 5 11 Layout................................................................... 14
6.5 Electrical Characteristics: AM26C31C and 11.1 Layout Guidelines ................................................. 14
AM26C31I .................................................................. 5 11.2 Layout Example .................................................... 14
6.6 Electrical Characteristics: AM26C31Q and 12 Device and Documentation Support ................. 15
AM26C31M ................................................................ 6 12.1 Receiving Notification of Documentation Updates 15
6.7 Switching Characteristics: AM26C31C and 12.2 Community Resources.......................................... 15
AM26C31I .................................................................. 6
12.3 Trademarks ........................................................... 15
6.8 Switching Characteristics: AM26C31Q and
AM26C31M ................................................................ 7 12.4 Electrostatic Discharge Caution ............................ 15
6.9 Typical Characteristics .............................................. 7 12.5 Glossary ................................................................ 15
7 Parameter Measurement Information .................. 8 13 Mechanical, Packaging, and Orderable
Information ........................................................... 15

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision N (October 2011) to Revision O Page

• Updated the Features section and added the Applications section, the Device Information table, ESD Ratings table,
Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1
• Deleted Ordering Information table, see POA at the end of the data sheet........................................................................... 1
• Changed Thermal Information table ....................................................................................................................................... 5

Changes from Revision M (June 2008) to Revision N Page

• Changed units to mA from µA to fix units typo....................................................................................................................... 4

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www.ti.com SLLS103O – DECEMBER 1990 – REVISED JUNE 2016

5 Pin Configuration and Functions

J, W, D, DB, NS, N, or PW Package FK Package


16-Pin CDIP, CFP, SOIC, SSOP, SO, PDIP, or TSSOP 20-Pin LCCC
Top View Top View

VCC
NC
1Y
1A

4A
1A 1 16 VCC
1Y 2 15 4A
1Z 3 14 4Y

3
2
1
20
19
G 4 13 4Z 1Z 4 18 4Y
2Z 5 12 G G 5 17 4Z
2Y 6 11 3Z NC 6 16 NC
2A 7 10 3Y 2Z 7 15 G
GND 8 9 3A 2Y 8 14 3Z

10

12
13
11
9
Not to scale

Not to scale

2A
GND
NC
3A
3Y
Pin Functions
PIN
CDIP, CFP, SOIC, I/O DESCRIPTION
NAME SSOP, SO, PDIP, LCCC
TSSOP
1A 1 2 I Driver 1 input
1Y 2 3 O Driver 1 output
1Z 3 4 O Driver 1 inverted output
2A 7 9 I Driver 2 input
2Y 6 8 O Driver 2 output
2Z 5 7 O Driver 2 inverted output
3A 9 12 I Driver 3 input
3Y 10 13 O Driver 3 output
3Z 11 14 O Driver 3 inverted output
4A 15 19 I Driver 3 input
4Y 14 18 O Driver 3 output
4Z 13 17 O Driver 3 inverted output
G 4 5 I Active high enable
G 12 15 I Active low enable
GND 8 10 — Ground pin
NC (1) — 1, 6, 11, 16 — No internal connection
VCC 16 20 — Power pin

(1) NC – No connection

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage (2) –0.5 7 V
VI Input voltage –0.5 VCC + 0.5 V
VID Differential input voltage –14 14 V
VO Output voltage –0.5 7
IIK
Input or output clamp current ±20 mA
IOK
IO Output current ±150 mA
VCC current 200 mA
GND current –200 mA
TJ Operating virtual junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the network ground terminal.

6.2 ESD Ratings


VALUE UNIT
(1)
Electrostatic Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
V(ESD) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions


MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VID Differential input voltage ±7 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current –20 mA
IOL Low-level output current 20 mA
AM26C31C 0 70
AM26C31I –40 85
TA Operating free-air temperature °C
AM26C31Q –40 125
AM26C31M –55 125

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6.4 Thermal Information


AM26C31
D DB PW NS N J W FK
THERMAL METRIC (1) UNIT
(SOIC) (SSOP) (TSSOP) (SO) (PDIP) (CDIP) (CFP) (LCCC)
16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS
Junction-to-ambient
RθJA 75.3 93.1 102.1 75.6 44.5 — — — °C/W
thermal resistance (2) (3)
Junction-to-case (top)
RθJC(top) 35.6 43.8 37.2 32.6 31.1 39.3 (4) 58.9 (4) 37.1 (4) °C/W
thermal resistance
Junction-to-board
RθJB 32.5 43.6 47.0 36.4 24.5 56.4 (4) 109.3 (4) 36.2 (4) °C/W
thermal resistance
Junction-to-top
ψJT characterization 7.1 9.6 2.8 5.7 15.4 — — — °C/W
parameter
Junction-to-board
ψJB characterization 32.3 43.1 46.4 36.0 24.4 — — — °C/W
parameter
Junction-to-case
RθJC(bot) (bottom) thermal n/a n/a n/a n/a n/a 12.0 (4) 5.7 (4) 4.3 (4) °C/W
resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA) / RθJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
(4) Modelling assumption: MIL-STD-883 for RθJC(top) and RθJC(bot) JESD51 for RθJB.

6.5 Electrical Characteristics: AM26C31C and AM26C31I


over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
VOH High-level output voltage IO = –20 mA 2.4 3.4 V
VOL Low-level output voltage IO = 20 mA 0.2 0.4 V
VOD Differential output voltage magnitude RL = 100 Ω, see Figure 2 2 3.1 V
Δ|VOD| Change in magnitude of differential output voltage (2) RL = 100 Ω, see Figure 2 ±0.4 V
VOC Common-mode output voltage RL = 100 Ω, see Figure 2 3 V
Δ|VOC| Change in magnitude of common-mode output voltage (2) RL = 100 Ω, see Figure 2 ±0.4 V
II Input current VI = VCC or GND ±1 μA
VO = 6 V 100
IO(off) Driver output current with power off VCC = 0 μA
VO = –0.25 V –100
IOS Driver output short-circuit current VO = 0 –30 –150 mA
VO = 2.5 V 20
IOZ High-impedance off-state output current μA
VO = 0.5 V –20
VI = 0 or 5 V 100 μA
ICC Quiescent supply current IO = 0
VI = 2.4 V or 0.5 V (3) 1.5 3 mA
Ci Input capacitance 6 pF

(1) All typical values are at VCC = 5 V and TA = 25°C.


(2) Δ|VOD| and Δ|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to
a low level.
(3) This parameter is measured per input. All other inputs are at 0 or 5 V.

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6.6 Electrical Characteristics: AM26C31Q and AM26C31M


over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
VOH High-level output voltage IO = –20 mA 2.2 3.4 V
VOL Low-level output voltage IO = 20 mA 0.2 0.4 V
VOD Differential output voltage magnitude RL = 100 Ω, see Figure 2 2 3.1 V
Δ|VOD| Change in magnitude of differential output voltage (2) RL = 100 Ω, see Figure 2 ±0.4 V
VOC Common-mode output voltage RL = 100 Ω, see Figure 2 3 V
Δ|VOC| Change in magnitude of common-mode output voltage (2) RL = 100 Ω, see Figure 2 ±0.4 V
II Input current VI = VCC or GND ±1 μA
VO = 6 V 100
IO(off) Driver output current with power off VCC = 0 μA
VO = –0.25 V –100
IOS Driver output short-circuit current VO = 0 –170 mA
VO = 2.5 V 20
IOZ High-impedance off-state output current μA
VO = 0.5 V –20
VI = 0 or 5 V 100 μA
ICC Quiescent supply current IO = 0
VI = 2.4 V or 0.5 V (3) 3.2 mA
Ci Input capacitance 6 pF

(1) All typical values are at VCC = 5 V and TA = 25°C.


(2) Δ|VOD| and Δ|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to
a low level.
(3) This parameter is measured per input. All other inputs are at 0 or 5 V.

6.7 Switching Characteristics: AM26C31C and AM26C31I


over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
tPLH Propagation delay time, low-to-high-level output 3 7 12
S1 is open, see Figure 3 ns
tPHL Propagation delay time, high-to-low-level output 3 7 12
tsk(p) Pulse skew time (|tPLH – tPHL|) S1 is open, see Figure 3 0.5 4 ns
tr(OD), tf(OD) Differential output rise and fall times S1 is open, see Figure 4 5 10 ns
tPZH Output enable time to high level 10 19
S1 is closed, see Figure 5 ns
tPZL Output enable time to low level 10 19
tPHZ Output disable time from high level 7 16
S1 is closed, see Figure 5 ns
tPLZ Output disable time from low level 7 16
Cpd Power dissipation capacitance (each driver) (2) S1 is open, see Figure 3 170 pF

(1) All typical values are at VCC = 5 V and TA = 25°C.


(2) Cpd is used to estimate the switching losses according to PD = Cpd × VCC 2 × f, where f is the switching frequency.

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6.8 Switching Characteristics: AM26C31Q and AM26C31M


over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
Propagation delay time, low-to-high-level
tPLH 7 12
output
S1 is open, see Figure 3 ns
Propagation delay time, high-to-low-level
tPHL 6.5 12
output
tsk(p) Pulse skew time (|tPLH – tPHL|) S1 is open, see Figure 3 0.5 4 ns
tr(OD), tf(OD) Differential output rise and fall times S1 is open, see Figure 4 5 12 ns
tPZH Output enable time to high level 10 19
S1 is closed, see Figure 5 ns
tPZL Output enable time to low level 10 19
tPHZ Output disable time from high level 7 16
S1 is closed, see Figure 5 ns
tPLZ Output disable time from low level 7 16
Power dissipation capacitance (each
Cpd S1 is open, see Figure 3 100 pF
driver) (2)

(1) All typical values are at VCC = 5 V and TA = 25°C.


(2) Cpd is used to estimate the switching losses according to PD = Cpd × VCC 2 × f, where f is the switching frequency.

6.9 Typical Characteristics

Figure 1. Supply Current vs Switching Frequency

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7 Parameter Measurement Information

Figure 2. Differential and Common-Mode Output Voltages


A. C1, C2, and C3 include probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, and
tr, tf ≤ 6 ns.

RL/2
C2 = 40 pF
500 Ω
Input C1 = 1.5 V
40 pF S1
RL/2
C3 = 40 pF

See Note A

TEST CIRCUIT

Input A 3V
(see Note B) 1.3 V
0V
tPLH tPHL

Output Y 50% 50%


1.3 V

tsk(p) tsk(p)

Output Z 50% 50%


1.3 V
tPHL tPLH

Figure 3. Propagation Delay Time and Skew Waveforms and Test Circuit
A. C1, C2, and C3 include probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, and
tr, tf ≤ 6 ns.

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Parameter Measurement Information (continued)

Figure 4. Differential-Output Rise- and Fall-Time Waveforms and Test Circuit


A. C1, C2, and C3 include probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, and
tr, tf ≤ 6 ns.
C. Each enable is tested separately.
Output
C2 =
50 Ω
40 pF
0V 500 Ω
Input A C1 = 1.5 V
3V 40 pF S1
C3 =
50 Ω
G 40 pF
Enable Inputs
Output
(see Note B) G See Note A

TEST CIRCUIT

Enable G Input
3V
(see Note C)
1.3 V1.3 V
Enable G Input 0V

1.5 V
Output WIth
VOL + 0.3 V 0.8 V
0 V to A Input
VOL

tPLZ tPZL

VOH
Output WIth VOH - 0.3 V 2V
3 V to A Input
1.5 V
tPHZ tPZH

VOLTAGE WAVEFORMS
Figure 5. Output Enable and Disable Time Waveforms and Test Circuit

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8 Detailed Description

8.1 Overview
The AM26C31 is a quadruple differential line driver with complementary outputs. The device is designed to meet
the requirements of TIA/EIA-422-B and ITU (formerly CCITT), and it is generally used to communicate over
relatively long wires in noisy environments.

8.2 Functional Block Diagrams

4
G
12
G 2
1 1Y
1A 3
1Z

6
7 2Y
2A 5
2Z

10
9 3Y
3A 11
3Z

14
15 4Y
4A 13
4Z
Copyright © 2016, Texas Instruments Incorporated
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.

Figure 6. Logic Diagram (Positive Logic)

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Functional Block Diagrams (continued)

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS


VCC VCC

Input Output

GND GND

Copyright © 2016, Texas Instruments Incorporated

Figure 7. Schematics of Inputs and Outputs

8.3 Feature Description


8.3.1 Active-High and Active-Low
The device can be configured using the G and G logic inputs to select transmitter output. A logic high on the G
pin or a logic low on the G pin enables the device to operate. These pins are simply a way to configure the logic
to match that of the receiving or transmitting controller or microprocessor.

8.3.2 Operates from a Single 5-V Supply


Both the logic and transmitters operate from a single 5-V rail, making designs much more simple. The line drivers
and receivers can operate off the same rail as the host controller or a similar low voltage supply, thus simplifying
power structure.

8.4 Device Functional Modes


Table 1 lists the functional modes of the AM26C31.

Table 1. Function Table (Each Driver) (1)


INPUT ENABLES OUTPUTS
A
G G Y Z
H H X H L
L H X L H
H X L H L
L X L L H
X L H Z Z

(1) H = High level,


L = Low level,
X = Irrelevant,
Z = High impedance (off)

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information


When designing a system that uses drivers, receivers, and transceivers that comply with RS-422, proper cable
termination is essential for highly reliable applications with reduced reflections in the transmission line. Because
RS-422 allows only one driver on the bus, if termination is used, it is placed only at the end of the cable near the
last receiver. Factors to consider when determining the type of termination usually are performance requirements
of the application and the ever-present factor, cost. The different types of termination techniques discussed are
unterminated lines, parallel termination, AC termination, and multipoint termination. For laboratory experiments,
100 feet of 100-Ω, 24-AWG, twisted-pair cable (Bertek) was used. A single driver and receiver, TI AM26C31C
and AM26C32C, respectively, were tested at room temperature with a 5-V supply voltage. To show voltage
waveforms related to transmission-line reflections, the first plot shows output waveforms from the driver at the
start of the cable (A/B); the second plot shows input waveforms to the receiver at the far end of the cable (Y).

9.2 Typical Application

VCC

VCC
0.1 PF
16
1A 4A
Input 1 Signal 1 15 Input 4 Signal
1Y 4Y
2 14
Output 1 Output 4
Differential Pair 1Z 4Z Differential Pair
3 13

G G
4 12 Active Low Enable Signal

2Z 3Z
5 11
Output 2 Output 3
Differential Pair 2Y 3Y Differential Pair
6 10
2A 3A
Input 2 Signal 7 9 Input 3 Signal

8
GND
Copyright © 2016, Texas Instruments Incorporated

Figure 8. Differential Terminated Configuration With All Channels and Active Low Enable Used

9.2.1 Design Requirements


Resistor and capacitor (if used) termination values are shown for each laboratory experiment, but vary from
system to system. For example, the termination resistor, RT, must be within 20% of the characteristic impedance,
Zo, of the cable and can vary from about 80 Ω to 120 Ω.

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Typical Application (continued)


9.2.2 Detailed Design Procedure
Ensure values in Absolute Maximum Ratings are not exceeded.
Supply voltage, VIH, and VIL must comply with Recommended Operating Conditions.

9.2.3 Application Curve

2
Voltage (V)

±1

±2
Y A/B
±3
0 0.1 0.2 0.3 0.4 0.5
Time ( s) C001

Figure 9. Differential 120-Ω Terminated Output Waveforms (Cat 5E Cable)

10 Power Supply Recommendations


Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies.

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11 Layout

11.1 Layout Guidelines


For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.

11.2 Layout Example


Differential
Output 1
Input 1 0.1 PF

VCC

1 1A VCC 16

2 1Y 4A 15

3 1Z 4Y 14

4 G 4Z 13
AM26C31
Active Low
5 2Z G 12
Differential Enable
Output 2
6 2Y 3Z 11

Input 2 7 2A 3Y 10

8 GND 3A 9

Figure 10. Trace Layout on PCB and Recommendations

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12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates


To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.2 Community Resources


The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information


The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

Copyright © 1990–2016, Texas Instruments Incorporated Submit Documentation Feedback 15


Product Folder Links: AM26C31
PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-9163901M2A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9163901M2A
AM26C31M
5962-9163901MEA ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9163901ME Samples
& Green A
AM26C31M
5962-9163901MFA ACTIVE CFP W 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9163901MF Samples
& Green A
AM26C31M
5962-9163901Q2A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9163901Q2A
AM26C31
MFKB
5962-9163901QEA ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9163901QE Samples
& Green A
AM26C31MJB
5962-9163901QFA ACTIVE CFP W 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9163901QF Samples
& Green A
AM26C31MWB
AM26C31CD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C31C Samples

AM26C31CDBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 26C31 Samples

AM26C31CDE4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C31C Samples

AM26C31CDG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C31C Samples

AM26C31CDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C31C Samples

AM26C31CDRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C31C Samples

AM26C31CDRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C31C Samples

AM26C31CN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 AM26C31CN Samples

AM26C31CNSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 26C31 Samples

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

AM26C31ID ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C31I Samples

AM26C31IDBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C31I Samples

AM26C31IDBRE4 ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C31I Samples

AM26C31IDE4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C31I Samples

AM26C31IDG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C31I Samples

AM26C31IDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 AM26C31I Samples

AM26C31IDRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C31I Samples

AM26C31IDRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C31I Samples

AM26C31IN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 AM26C31IN Samples

AM26C31INE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 AM26C31IN Samples

AM26C31INSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C31I Samples

AM26C31IPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C31I Samples

AM26C31IPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 26C31I Samples

AM26C31IPWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C31I Samples

AM26C31MFKB ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9163901Q2A
AM26C31
MFKB
AM26C31MJB ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9163901QE Samples
& Green A
AM26C31MJB
AM26C31MWB ACTIVE CFP W 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9163901QF Samples
& Green A
AM26C31MWB
AM26C31QD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AM26C31Q Samples

Addendum-Page 2
PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

AM26C31QDG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 26C31Q Samples

AM26C31QDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AM26C31Q Samples

AM26C31QDRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 26C31Q Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3
PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

OTHER QUALIFIED VERSIONS OF AM26C31, AM26C31M :

• Catalog : AM26C31
• Enhanced Product : AM26C31-EP, AM26C31-EP
• Military : AM26C31M

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product


• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications

Addendum-Page 4
PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS


K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)


QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AM26C31CDBR SSOP DB 16 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
AM26C31CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
AM26C31CNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
AM26C31IDBR SSOP DB 16 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
AM26C31IDR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
AM26C31IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
AM26C31IDRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
AM26C31INSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
AM26C31IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
AM26C31IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
AM26C31IPWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
AM26C31QDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
AM26C31QDRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
AM26C31CDBR SSOP DB 16 2000 356.0 356.0 35.0
AM26C31CDR SOIC D 16 2500 340.5 336.1 32.0
AM26C31CNSR SO NS 16 2000 356.0 356.0 35.0
AM26C31IDBR SSOP DB 16 2000 356.0 356.0 35.0
AM26C31IDR SOIC D 16 2500 364.0 364.0 27.0
AM26C31IDR SOIC D 16 2500 340.5 336.1 32.0
AM26C31IDRG4 SOIC D 16 2500 340.5 336.1 32.0
AM26C31INSR SO NS 16 2000 356.0 356.0 35.0
AM26C31IPWR TSSOP PW 16 2000 367.0 367.0 35.0
AM26C31IPWR TSSOP PW 16 2000 364.0 364.0 27.0
AM26C31IPWRG4 TSSOP PW 16 2000 367.0 367.0 35.0
AM26C31QDR SOIC D 16 2500 350.0 350.0 43.0
AM26C31QDRG4 SOIC D 16 2500 340.5 336.1 32.0

Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal


Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-9163901M2A FK LCCC 20 1 506.98 12.06 2030 NA
5962-9163901MFA W CFP 16 1 506.98 26.16 6220 NA
5962-9163901Q2A FK LCCC 20 1 506.98 12.06 2030 NA
5962-9163901QFA W CFP 16 1 506.98 26.16 6220 NA
AM26C31CD D SOIC 16 40 507 8 3940 4.32
AM26C31CDE4 D SOIC 16 40 507 8 3940 4.32
AM26C31CDG4 D SOIC 16 40 507 8 3940 4.32
AM26C31CN N PDIP 16 25 506 13.97 11230 4.32
AM26C31ID D SOIC 16 40 507 8 3940 4.32
AM26C31IDE4 D SOIC 16 40 507 8 3940 4.32
AM26C31IDG4 D SOIC 16 40 507 8 3940 4.32
AM26C31IN N PDIP 16 25 506 13.97 11230 4.32
AM26C31INE4 N PDIP 16 25 506 13.97 11230 4.32
AM26C31IPW PW TSSOP 16 90 530 10.2 3600 3.5
AM26C31MFKB FK LCCC 20 1 506.98 12.06 2030 NA
AM26C31MWB W CFP 16 1 506.98 26.16 6220 NA
AM26C31QD D SOIC 16 40 505.46 6.76 3810 4
AM26C31QDG4 D SOIC 16 40 505.46 6.76 3810 4

Pack Materials-Page 3
PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM


(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE


EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK


METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN


ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK


DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.


7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM


(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE


BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
PACKAGE OUTLINE
DB0016A SCALE 1.500
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C SEATING
PIN 1 INDEX AREA
PLANE
14X 0.65
16
1

2X
6.5
4.55
5.9
NOTE 3

8
9
0.38
16X
0.22
5.6
B 0.1 C A B
5.0
NOTE 4

0.25
0.09

SEE DETAIL A
2 MAX
0.25
GAGE PLANE

0.95 0.05 MIN


0 -8 0.55

DETAIL A
A 15

TYPICAL

4220763/A 05/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-150.

www.ti.com
EXAMPLE BOARD LAYOUT
DB0016A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

16X (1.85) SYMM

1 (R0.05) TYP

16X (0.45) 16

SYMM

14X (0.65)

8 9

(7)

LAND PATTERN EXAMPLE


EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK


METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN


ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK


DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220763/A 05/2022
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.


6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DB0016A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

16X (1.85) SYMM


(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(7)

SOLDER PASTE EXAMPLE


BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220763/A 05/2022
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
PACKAGE OUTLINE
NS0016A SCALE 1.500
SOP - 2.00 mm max height
SOP

8.2 SEATING PLANE


TYP
7.4
A PIN 1 ID 0.1 C
AREA
14X 1.27
16
1

10.4 2X
10.0 8.89
NOTE 3

8
9
0.51
16X
5.4 0.35
B 0.25 C A B 2.00 MAX
5.2
NOTE 4

0.15 TYP

SEE DETAIL A
0.25 0.3
GAGE PLANE 0.1

0 - 10
1.05
0.55 DETAIL A
TYPICAL
(1.25)

4220735/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

www.ti.com
EXAMPLE BOARD LAYOUT
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SEE


SYMM DETAILS

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP

(7)

LAND PATTERN EXAMPLE


SCALE:7X

SOLDER MASK SOLDER MASK METAL


METAL OPENING OPENING

0.07 MAX 0.07 MIN


ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK


DEFINED DEFINED

SOLDER MASK DETAILS

4220735/A 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.


6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SYMM

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP (7)

SOLDER PASTE EXAMPLE


BASED ON 0.125 mm THICK STENCIL
SCALE:7X

4220735/A 12/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
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