TPS386000

TPS386040
www.ti.com SBVS105D – SEPTEMBER 2009 – REVISED SEPTEMBER 2013

Quad Supply Voltage Supervisor

with Adjustable Delay and Watchdog Timer
Check for Samples: TPS386000, TPS386040

1FEATURES DESCRIPTION
•
2 Four Independent Voltage Supervisors The TPS3860x0 family of supply voltage supervisors
(SVSs) can monitor four power rails that are greater
• Channels 1, 2, 3: Adjustable Threshold Down than 0.4V and one power rail less than 0.4V
to 0.4V (including negative voltage) with a 0.25% (typical)
• Channel 4: Adjustable Threshold at Any threshold accuracy. Each of the four supervisory
Positive/Negative Voltage circuits (SVS-n) assert a RESETn or RESETn output
• Adjustable Delay Time: 1.4ms to 10s signal when the SENSEm input voltage drops below
the programmed threshold. With external resistors,
• Threshold Accuracy: 0.25% typ the threshold of each SVS-n can be programmed
• Very Low Quiescent Current: 11μA typ (where n = 1, 2, 3, 4 and m = 1, 2, 3, 4L, 4H).
• Channel 1: Manual Reset (MR) Input Each SVS-n has a programmable delay before
• Channel 4: Window Comparator releasing RESETn or RESETn. The delay time can
• Watchdog Timer with Dedicated Output be set independently for each SVS from 1.4ms to 10s
through the CTn pin connection. Only SVS-1 has an
• Well-Controlled Output During Power-Up active-low manual reset (MR) input; a logic-low input
• TPS386000: Open-Drain RESETn and WDO to MR asserts RESET1 or RESET1.
• TPS386040: Push-Pull RESETn and WDO SVS-4 monitors the threshold window using two
• Package: 4mm x 4mm, 20-pin QFN comparators. The extra comparator can be
configured as a fifth SVS to monitor negative voltage
APPLICATIONS with voltage reference output VREF.
• All DSP and Microcontroller Applications The TPS3860x0 has a very low quiescent current of
11μA (typical) and is available in a small, 4mm x
• All FPGA/ASIC Applications
4mm, QFN-20 package.
• Telecom/Wireless Infrastructure
• Industrial Equipment
• Analog Sequencing

TPS386000 Typical Application Circuit

VCC1
VCC2

VCC3

VCC4

RS1H
VCC

MR

VCC1

VCC2

VCC3

VCC4

TPS386000

SENSE1 RESET1 RST

RS2H
VCC2 SENSE2 RESET2
RS3H Microprocessor
VCC3 SENSE3 RESET3 DSP
RS4H FPGA
VCC4 SENSE4L RESET4

RS1L SENSE4H WDO

RS2L
VREF WDI GPIO
RS3L
GND

CT1

CT2

CT3

CT4

RS4L

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS386000
TPS386040
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION (1)

PRODUCT DESCRIPTION
TPS3860x0yyyz x is device configuration option
xxx = 0: Open-drain, active low
xxx = 4: Push-pull, active low
yyy is package designator
z is package quantity

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS (1)

Over operating junction temperature range, unless otherwise noted.
TPS3860x0 UNIT
Input voltage range, VVCC –0.3 to 7.0 V
CT pin voltage range, VCT1, VCT2, VCT3, VCT4 –0.3 to VVCC + 0.3 V
Other voltage ranges: VRESET1, VRESET2, VRESET3, VRESET4, VMR, VSENSE1,
–0.3 to 7.0 V
VSENSE2, VSENSE3, VSENSE4L, VSENSE4H, VWDI, VWDO
RESETn , RESETn, WDO, WDO, VREF pin current 5 mA
Continuous total power dissipation See Dissipation Ratings Table
(2)
Operating virtual junction temperature range, TJ –40 to +150 °C
Operating ambient temperature range –40 to +125 °C
Storage temperature range, TSTG –65 to +150 °C
Human body model (HBM) 2 kV
ESD rating
Charged device model (CDM) 500 V

(1) Stresses beyond those listed under the Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the recommended
operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.

DISSIPATION RATINGS
TA < +25°C DERATING FACTOR TA = +70°C TA = +85°C
PACKAGE POWER RATING ABOVE TA > +25°C POWER RATING POWER RATING
RGP 2.86W 28.6mW/°C 1.57W 1.24W

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ELECTRICAL CHARACTERISTICS
Over the operating temperature range of TJ = –40°C to +125°C, 1.8V < VVCC < 6.5V, RRESETn (n = 1, 2, 3, 4) = 100kΩ to VVCC
(TPS386000 only), CRESETn (n = 1, 2, 3, 4L, 4H) = 50pF to GND, RWDO = 100kΩ to VVCC, CWDO = 50pF to GND, VMR = 100kΩ
to VVCC, WDI = GND, and CTn (n = 1, 2, 3, 4) = open, unless otherwise noted. Typical values are at TJ = +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VVCC Input supply range 1.8 6.5 V
VVCC = 3.3V, RESETn or RESETn not
asserted, WDI toggling (1), no output load, 11 19 μA
and VREF open
IVCC Supply current (current into VCC pin)
VVCC = 6.5V, RESETn or RESETn not
asserted, WDI toggling (1), no output load, 13 22 μA
and VREF open
Power-up reset voltage (2) (3) VOL (max) = 0.2V, IRESETn = 15μA 0.9 V
VITN Negative-going input threshold voltage SENSE1, SENSE2, SENSE3, SENSE4L 396 400 404 mV
VITP Positive-going input threshold voltage SENSE4H 396 400 404 mV
VHYSN Hysteresis (positive-going) on VITN SENSE1, SENSE2, SENSE3, SENSE4L 3.5 10 mV
VHYSP Hysteresis (negative-going) on VITP SENSE4H 3.5 10 mV
ISENSE Input current at SENSEm pin VSENSEm = 0.42V –25 ±1 +25 nA
(4)
CTn pin charging CT1 CCT1 > 220pF, VCT1 = 0.5V 245 300 355 nA
ICT
current CT2, CT3, CT4 CCTn > 220pF, VCTn = 0.5V (4) 235 300 365 nA
VTH(CTn) CTn pin threshold CCTn > 220pF 1.180 1.238 1.299 V
VIL MR and WDI logic low input 0 0.3VVCC V
VIH MR and WDI logic high input 0.7VVCC V
IOL = 1mA 0.4 V
Low-level RESETn or RESETn output
voltage SENSEn = 0V, 1.3V < VVCC < 1.8V,
VOL 0.3 V
IOL = 0.4mA (2)
Low-level WDO output voltage IOL = 1mA 0.4 V
High-level RESETn
TPS386040
or RESETn output IOL = –1mA VVCC – 0.4 V
only
voltage
VOH
IOL = –1mA VVCC – 0.4 V
High-level WDO TPS386040
output voltage only SENSEn = 0V, 1.3V < VVCC < 1.8V,
VVCC – 0.3 V
IOL = –0.4mA (2)
RESETn, RESETn,
TPS386000 VRESETn = 6.5V, RESETn, RESETn, WDO,
ILKG WDO, and WDO –300 300 nA
only and WDO are logic high
leakage current
VREF Reference voltage output 1μA < IVREF < 0.2mA (source only, no sink) 1.18 1.20 1.22 V
CIN Input pin capacitance CTn: 0V to VVCC, other pins: 0V to 6.5V 5 pF
SENSEm: 1.05VITN → 0.95VITN or
Input pulse width to SENSEm and MR 0.95VITP → 1.05VITP 4 μs
tW
pins
MR: 0.7VCC → 0.3VVCC 1 ns
CTn = open 14 20 24 ms
tD RESETn or RESETn delay time
CTn = VVCC 225 300 375 ms
Start from RESET1 or RESET1 release or
tWDT Watchdog timer timeout period 450 600 750 ms
last WDI transition

(1) Toggling WDI for a period less than tWDT negatively affects IVCC.
(2) These specifications are beyond the recommended VVCC range, and only define RESETn or RESETn output performance during VCC
ramp up.
(3) The lowest supply voltage (VVCC) at which RESETn or RESETn becomes active; tRISE(VCC) ≥ 15μs/V.
(4) CTn (where n = 1, 2, 3, or 4) are constant current charging sources working from a range of 0V to VTH(CTn), and the device is tested at
VCTn = 0.5V. For ICT performance between 0V and VTH(CTn), see Figure 23.

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PIN CONFIGURATIONS

RGP PACKAGE
QFN-20
(TOP VIEW)

RESET4

RESET3

RESET2
WDO
WDI
20

19

18

17

16
MR 1 15 RESET1

CT4 2 14 VCC
TPS386000
CT3 3 13 VREF
TPS386040
CT2 4 12 GND
(Thermal Pad)
CT1 5 11 NC

10
6

9
SENSE4H

SENSE4L

SENSE3

SENSE2

SENSE1

PIN ASSIGNMENTS
PIN
NAME NO. DESCRIPTION
VCC 14 Supply voltage. Connecting a 0.1μF ceramic capacitor close to this pin is recommended.
GND 12 Ground
When the voltage at this terminal drops below the
SENSE1 10 Monitor voltage input to SVS-1
threshold voltage (VITN), RESET1 is asserted.
When the voltage at this terminal drops below the
SENSE2 9 Monitor voltage input to SVS-2
threshold voltage (VITN), RESET2 is asserted.
When the voltage at this terminal drops below the
SENSE3 8 Monitor voltage input to SVS-3
threshold voltage (VITN), RESET3 is asserted.
Falling monitor voltage input to SVS-4. When the voltage at this terminal drops below the threshold
SENSE4L 7
voltage (VITN), RESET4 or RESET4 is asserted.
Rising monitor voltage input to SVS-4. When the voltage at this terminal exceeds the threshold voltage
SENSE4H 6 (VITP), RESET4 or RESET4 is asserted. This pin can also be used to monitor the negative voltage rail
in combination with VREF pin. Connect to GND if not being used.
CT1 5 Reset delay programming pin for SVS-1 Connecting this pin to VCC through a 40kΩ to
200kΩ resistor, or leaving it open, selects a fixed
CT2 4 Reset delay programming pin for SVS-2
delay time (see the Electrical Characteristics).
CT3 3 Reset delay programming pin for SVS-3 Connecting a capacitor > 220pF between this pin
and GND selects the programmable delay time
CT4 2 Reset delay programming pin for SVS-4 (see the Reset Delay Time section).
Reference voltage output. By connecting a resistor network between this pin and the negative power
VREF 13 rail, SENSE4H can monitor the negative power rail. This pin is intended to only source current into
resistor(s). Do not connect resistor(s) to a voltage higher than 1.2V. Do not connect only a capacitor.
MR 1 Manual reset input for SVS-1. Logic low level of this pin asserts RESET1 or RESET1.
Watchdog timer (WDT) trigger input. Inputting either a positive or negative logic edge every 610ms (typ)
WDI 20 prevents WDT time out at the WDO or WDO pin. Timer starts from releasing event of RESET1 or
RESET1.
NC 11 Not connected. It is recommended to connect this pin to the GND pin (pin 12), which is next to this pin.
This is the IC substrate. This pad must be connected only to GND or to the floating thermal pattern on
(Thermal Pad) (PAD)
the printed circuit board (PCB).

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PIN ASSIGNMENTS (continued)

PIN
NAME NO. DESCRIPTION
TPS386000
RESET1 15 Active low reset output of SVS-1 RESETn is an open-drain output pin. When
RESET2 16 Active low reset output of SVS-2 RESETn is asserted, this pin remains in a low-
impedance state. When RESETn is released, this
RESET3 17 Active low reset output of SVS-3 pin goes to a high-impedance state after the delay
RESET4 18 Active low reset output of SVS-4 time programmed by CTn.
Watchdog timer output. This is an open-drain output pin. When WDT times out, this pin goes to a low-
WDO 19
impedance state to GND. If there is no WDT timeout, this pin stays in a high-impedance state.
TPS386040
RESET1 15 Active low reset output of SVS-1 RESETn is a push-pull logic buffer output pin.
RESET2 16 Active low reset output of SVS-2 When RESETn is asserted, this pin remains logic
low. When RESETn is released, this pin goes to
RESET3 17 Active low reset output of SVS-3 logic high after the delay time programmed by
RESET4 18 Active low reset output of SVS-4 CTn.
Watchdog timer output. This is a push-pull output pin. When WDT times out, this pin goes to logic low.
WDO 19
If there is no WDT timeout, this pin stays in logic high.

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FUNCTIONAL BLOCK DIAGRAMS

VCC

WDO

WDI
WDT

VREF
VREF

SENSE1 RESET1

Delay

0.4V

MR

CT1
RESET2
SENSE2
Delay

0.4V

CT2
RESET3
SENSE3
Delay

0.4V

CT3

SENSE4L RESET4

Delay

0.4V

SENSE4H

CT4

GND

Figure 1. TPS386000 Block Diagram

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VCC

WDI WDO
WDT

VREF
VREF

SENSE1

Delay
RESET1

0.4V

MR

CT1

SENSE2
Delay
RESET2

0.4V

CT2

SENSE3
Delay
RESET3

0.4V

CT3

SENSE4L

Delay
RESET4

0.4V

SENSE4H

CT4

GND

Figure 2. TPS386040 Block Diagram

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TYPICAL CHARACTERISTICS
At TA = +25°C, and VCC = 3.3V, with both options (TPS386000 and TPS386040) having the same characteristics, unless
otherwise noted.
TPS386040 TPS386040
SUPPLY CURRENT vs SUPPLY VOLTAGE RESETn TIMEOUT PERIOD vs CTn
20 10000
+125°C
18
+85°C +105°C
16
1000

RESETn Delay (ms)

14
12 +85°C
ICC (mA)

10 100 +25°C
0°C +25°C 0°C
8 +125°C
-40°C
6
10
4
2 -40°C
NOTE: UVLO released at approximately 1.5V.
0 1
0 1 2 3 4 5 6 7 0.0001 0.001 0.01 0.1 1
VCC (V) CT (mF)
Figure 3. Figure 4.

TPS386040 (CTn = Open) TPS386040 (CTn = VCC)

RESETn TIMEOUT PERIOD vs TEMPERATURE RESETn TIMEOUT PERIOD vs TEMPERATURE
25 360

CT1 CT3
340
20
RESETn Delay (ms)

RESETn Delay (ms)

CT2 CT4 320

15 CT1 CT3
300
10 CT2 CT4
280

5
260

0 240
-50 -30 -10 10 30 50 70 90 110 130 -50 -30 -10 10 30 50 70 90 110 130
Temperature (°C) Temperature (°C)
Figure 5. Figure 6.

TPS386040 (CTn = 0.1µF) TPS386040

RESETn TIMEOUT PERIOD vs TEMPERATURE WDO TIMEOUT PERIOD vs TEMPERATURE
550 700
680
500
660
RESETn Delay (ms)

640
WDO Delay (ms)

450 VCC = 3.3V VCC = 1.8V

CT3 CT4 620
400 600
CT1 CT2 580
350 VCC = 6.5V
560
540
300
NOTE: These curves contain variance of capacitor values. 520
250 500
-50 -30 -10 10 30 50 70 90 110 130 -50 -30 -10 10 30 50 70 90 110 130
Temperature (°C) Temperature (°C)
Figure 7. Figure 8.

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C, and VCC = 3.3V, with both options (TPS386000 and TPS386040) having the same characteristics, unless
otherwise noted.
TPS386040
SENSEn MINIMUM PULSE WIDTH TPS386040
vs SENSEn THRESHOLD OVERDRIVE VOLTAGE SENSE1 THRESHOLD VOLTAGE vs TEMPERATURE
100 408
2mV » 0.5%
406
SENSEn Pulse Width (ms)

VITN, (VITN + VHYSN) (mV)

VITN + VHYSN, VCC = 6.5V
SENSE4H
10 404
SENSE4L VITN + VHYSN, VCC = 1.8V
SENSE2 402
SENSE1 VITN + VHYSN, VCC = 3.3V
SENSE3 VITN, VCC = 6.5V
1 400
VITN, VCC = 1.8V VITN, VCC = 3.3V
398
NOTE: See Figure 27 for the measurement technique.
0.1 396
0.1 1 10 100 -50 -30 -10 10 30 50 70 90 110 130
Overdrive (%) Temperature (°C)
Figure 9. Figure 10.

TPS386040 TPS386040
SENSE2 THRESHOLD VOLTAGE vs TEMPERATURE SENSE3 THRESHOLD VOLTAGE vs TEMPERATURE
408 408
2mV » 0.5% 2mV » 0.5%
406 406
VITN, (VITN + VHYSN) (mV)

VITN, (VITN + VHYSN) (mV)

VITN + VHYSN, VCC = 6.5V VITN + VHYSN, VCC = 6.5V

VITN + VHYSN, VCC = 3.3V
404 404
VITN + VHYSN, VCC = 1.8V VITN + VHYSN, VCC = 1.8V
402 402
VITN + VHYSN, VCC = 3.3V
VITN, VCC = 3.3V
400 400
VITN, VCC = 1.8V VITN, VCC = 3.3V VITN, VCC = 6.5V
398 398
VITN, VCC = 6.5V VITN, VCC = 1.8V
396 396
-50 -30 -10 10 30 50 70 90 110 130 -50 -30 -10 10 30 50 70 90 110 130
Temperature (°C) Temperature (°C)
Figure 11. Figure 12.

TPS386040 TPS386040
SENSE4L THRESHOLD VOLTAGE vs TEMPERATURE SENSE4H THRESHOLD VOLTAGE vs TEMPERATURE
408 404
2mV » 0.5% 2mV » 0.5%
406 402
VITP + VHYSP, VCC = 3.3V
VITN, (VITN + VHYSN) (mV)

VITP, (VITP + VHYSP) (mV)

VITN + VHYSN, VCC = 6.5V

VITN + VHYSN, VCC = 3.3V VITP + VHYSP, VCC = 6.5V
404 400
VITN + VHYSN, VCC = 1.8V VITP, VCC = 1.8V VITP + VHYSP, VCC = 1.8V
402 398
VITN, VCC = 1.8V
400 396
VITN, VCC = 3.3V VITN, VCC = 6.5V VITP, VCC = 6.5V
398 394
VITP, VCC = 6.5V
396 392
-50 -30 -10 10 30 50 70 90 110 130 -50 -30 -10 10 30 50 70 90 110 130
Temperature (°C) Temperature (°C)
Figure 13. Figure 14.

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C, and VCC = 3.3V, with both options (TPS386000 and TPS386040) having the same characteristics, unless
otherwise noted.
OUTPUT VOLTAGE LOW vs OUTPUT CURRENT OUTPUT VOLTAGE LOW AT 1mA vs TEMPERATURE
0.200 0.200
All RESETn, RESETn, WDO, and WDO All RESETn, RESETn, WDO, and WDO
0.180 0.180
0.160 0.160
VCC = 1.8V
0.140 0.140
VCC = 1.8V, +25°C VCC = 3.3V
0.120 0.120
VOL (V)

VOL (V)
0.100 0.100
VCC = 3.3V, +25°C
0.080 0.080
0.060 0.060
VCC = 6.5V
0.040 0.040
0.020 0.020
VCC = 6.5V, +25°C
0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -50 -30 -10 10 30 50 70 90 110 130
Output Sink Current (mA) Temperature (°C)
Figure 15. Figure 16.

OUTPUT VOLTAGE HIGH vs OUTPUT CURRENT OUTPUT VOLTAGE HIGH AT 1mA vs TEMPERATURE
0 0
VCC = 6.5V, +25°C All RESETn, RESETn, WDO, and WDO
VCC = 6.5V
-0.050 -0.050

VCC = 1.8V, +25°C

VCC - VOH (V)

VCC - VOH (V)

-0.100 -0.100
VCC = 3.3V, +25°C
VCC = 3.3V
-0.150 -0.150

VCC = 1.8V
-0.200 -0.200

All RESETn, RESETn, WDO, and WDO

-0.250 -0.250
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -50 -30 -10 10 30 50 70 90 110 130
Output Source Current (mA) Temperature (°C)
Figure 17. Figure 18.

TPS386040 TPS386040
VREF OUTPUT LOAD REGULATION (VCC = 1.8V) VREF OUTPUT LOAD REGULATION (VCC = 3.3V)
1.200 1.200
0°C

1.198 1.198
0°C
1.196 1.196
+25°C -40°C +25°C +85°C
VREF (V)

VREF (V)

+85°C +105°C -40°C +105°C

1.194 1.194
+125°C +125°C
1.192 1.192

1.190 1.190
NOTE: Y-Axis (1.188V to 1.2V) is 1% of 1.2V. NOTE: Y-Axis (1.188V to 1.2V) is 1% of 1.2V.
1.188 1.188
0 50 100 150 200 250 300 350 400 0 50 100 150 200 250 300 350 400
Load (mA) Load (mA)
Figure 19. Figure 20.

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C, and VCC = 3.3V, with both options (TPS386000 and TPS386040) having the same characteristics, unless
otherwise noted.
TPS386040 TPS386040
VREF OUTPUT LOAD REGULATION (VCC = 6.5V) VREF AT 0µA vs TEMPERATURE
1.207 1.207
NOTE: Y-Axis (1.195V to 1.207V) is 1% of 1.2V. NOTE: Y-Axis (1.195V to 1.207V) is 1% of 1.2V.
1.205 1.205
0°C VCC = 6.5V
1.203 1.203
VREF (V)

VREF (V)
1.201 1.201
VCC = 3.3V
1.199 1.199
+25°C -40°C +85°C VCC = 1.8V
+105°C
1.197 1.197
+125°C
1.195 1.195
0 50 100 150 200 250 300 350 400 -50 -30 -10 10 30 50 70 90 110 130
Load (mA) Temperature (°C)
Figure 21. Figure 22.

TPS386040
CT1 TO CT4 PIN CHARGING CURRENT vs TEMPERATURE OVER CT PIN VOLTAGE
0.33

0.32
0.1V
0.31
Current (mA)

0V 0.3V
0.5V
0.30

1.1V
0.29
0.9V
0.7V
0.28

NOTE: Min and max values of Y-axis are ±10% of 0.3mA.

0.27
-50 -30 -10 10 30 50 70 90 110 130
Temperature (°C)
Figure 23.

PARAMETRIC MEASUREMENT INFORMATION

TEST CIRCUIT

Z1
VITN = 0.42V X1 = ´ 100 (%)
0.4
VITN = 0.4V Z2
´ 100 (%)
SENSEn Voltage (V)

X2 =
Y1 Y2 0.4
Z1
X1 and X2 are overdrive (%) values calculated
from actual SENSEn voltage amplitudes
Z2 measured as Z1 and Z2.
YN is the minimum pulse width that gives
RESETn or RESETn transition.
Greater ZN produces shorter YN.

For SENSE4H, this graph should be inverted

180 degrees on the voltage axis.
Time

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GENERAL DESCRIPTION
user-configurable delay time after the event of reset
The TPS3860x0 multi-channel supervisory device release (see the Reset Delay Time section). Each
family combines four complete SVS function sets into SENSEm (m = 1, 2, 3, 4L) pin can be set to any
one IC, along with a watchdog timer, a window voltage threshold above 0.4V using an external
comparator, and negative voltage sensing. The resistor divider. The SENSE4H pin can be used for
design of each SVS channel is based on the single- any overvoltage detection greater than 0.4V, or for
channel supervisory device series, TPS3808. The negative voltage detection using an external resistor
TPS3860x0 is designed to assert RESETn or divider (see the Sensing Voltage Less Than 0.4V
RESETn signals, as shown in Table 1, Table 2, section). A broad range of voltage threshold and
Table 3, and Table 4. The RESETn or RESETn reset delay time adjustments can be supported,
outputs remain asserted during a allowing these devices to be used in a wide array of
applications.

Table 1. SVS-1 Truth Table

CONDITION OUTPUT STATUS
MR = Low SENSE1 < VITN RESET1 = Low Reset asserted
MR = Low SENSE1 > VITN RESET1 = Low Reset asserted
MR = High SENSE1 < VITN RESET1 = Low Reset asserted
MR = High SENSE1 > VITN RESET1 = High Reset released after delay

Table 2. SVS-2 Truth Table

CONDITION OUTPUT STATUS
SENSE2 < VITN RESET2 = Low Reset asserted
SENSE2 > VITN RESET2 = High Reset released after delay

Table 3. SVS-3 Truth Table

CONDITION OUTPUT STATUS
SENSE3 < VITN RESET3 = Low Reset asserted
SENSE3 > VITN RESET3 = High Reset released after delay

Table 4. SVS-4 Truth Table

CONDITION OUTPUT STATUS
SENSE4L < VITN SENSE4H > VITP RESET4 = Low Reset asserted
SENSE4L < VITN SENSE4H < VITP RESET4 = Low Reset asserted
SENSE4L > VITN SENSE4H > VITP RESET4 = Low Reset asserted
SENSE4L > VITN SENSE4H < VITP RESET4 = High Reset released after delay

Table 5. Watchdog Timer (WDT) Truth Table

CONDITION
RESET1 OR
WDO WDO RESET1 WDI PULSE INPUT OUTPUT STATUS
Low High Asserted Toggling WDO = low Remains in WDT timeout
Low High Asserted 610ms after last WDI↑ or WDI↓ WDO = low Remains in WDT timeout
Low High Released Toggling WDO = low Remains in WDT timeout
Low High Released 610ms after last WDI↑ or WDI↓ WDO = low Remains in WDT timeout
High Low Asserted Toggling WDO = high Normal operation
High Low Asserted 610ms after last WDI↑ or WDI↓ WDO = high Normal operation
High Low Released Toggling WDO = high Normal operation
High Low Released 610ms after last WDI↑ or WDI↓ WDO = low Enters WDT timeout

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RESET OUTPUT minimal propagation delay. Figure 26 describes

relationship between threshold voltages (VITN and
In a typical TPS3860x0 application, RESETn or VHYSN) and SENSEm voltage; and all SVS-1, SVS-2,
RESETn outputs are connected to the reset input of a SVS-3, and SVS-4 have the same behavior of
processor (DSP, CPU, FPGA, ASIC, etc.), or Figure 26.
connected to the enable input of a voltage regulator
(DC-DC, LDO, etc.)
VCC
The TPS386000 provides open-drain reset outputs.
Pull-up resistors must be used to hold these lines
high when RESETn is not asserted, or when RESETn
0.9V
is asserted. By connecting pull-up resistors to the
proper voltage rails (up to 6.5V), RESETn or RESETn
output nodes can be connected to the other devices t
at the correct interface voltage levels. The pull-up
resistor should be no smaller than 10kΩ because of
the safe operation of the output transistors. By using SENSE1
wired-OR logic, any combination of RESETn can be
merged into one logic signal. VHYSN
VITN
The TPS386040 provides push-pull reset outputs.
The logic high level of the outputs is determined by
the VCC voltage. With this configuration, pull-up t
resistors are not required and some board area can
be saved. However, all the interface logic levels
should be examined. All RESETn or RESETn MR
connections must be compatible with the VCC logic
level.
The RESETn or RESETn outputs are defined for
VCC voltage higher than 0.9V. To ensure that the
target processor(s) are properly reset, the VCC
t
supply input should be fed by the available power rail
as early as possible in application circuits. Table 1,
Table 2, Table 3, and Table 4 are truth tables that RESET1
describe how the outputs are asserted or released.
Figure 24, Figure 25, Figure 26, and Figure 27 show
the SVS-n timing diagrams. When the condition(s) tD tD
are met, the device changes the state of SVS-n from
asserted to released after a user-configurable delay
time. However, the transitions from released-state to t
asserted-state are performed almost immediately with
Figure 24. SVS-1 Timing Diagram

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VCC VCC

0.9V 0.9V

t t

SENSE2 SENSE3

VHYSN VHYSN
VITN VITN

t t

RESET2 RESET3

tD tD tD

t t

Figure 25. SVS-2 Timing Diagram Figure 26. SVS-3 Timing Diagram

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VCC MR

0.9V t
RESET1

SENSE4L
t
WDI

VHYSN
VITN

t
t (Internal timer)

Timeout
SENSE4H tWDT

Zero

VITP VHYSP t
WDO

t
t
RESET4
Figure 28. WDT Timing Diagram

tD

Figure 27. SVS-4 Timing Diagram

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SENSE INPUT design practice to place a 1nF to 10nF bypass

capacitor at the SENSEm input in order to reduce
The SENSEm inputs are pins that allow any system sensitivity to transients, layout parasitics, and
voltages to be monitored. If the voltage at the interference between power rails monitored by this
SENSE1, SENSE2, SENSE3, or SENSE4L pins device. A typical connection of resistor dividers are
drops below VITN, then the corresponding reset shown in Figure 29. All the SENSEm pins can be
outputs are asserted. If the voltage at the SENSE4H used to monitor voltage rails down to 0.4V. Threshold
pin exceeds VITP, then RESET4 or RESET4 is voltages can be calculated by following equations:
asserted. The comparators have a built-in hysteresis
to ensure smooth reset output assertions and VCC1_target = (1 + RS1H/RS1L) × 0.4 (V) (1)
deassertions. Although not required in most cases, VCC2_target = (1 + RS2H/RS2L) × 0.4 (V) (2)
for extremely noise applications, it is good analog VCC3_target = (1 + RS3H/RS3L) × 0.4 (V) (3)

Sequence: VIN VCC4 VCC3 VCC2 VCC1

VIN DC-DC VCC4

LDO
VCC3

VCC2

EN4 DC-DC VCC1

LDO

RP5 RP4 RP3 RP2 RP1

VCC
EN3 DC-DC MR VREF
LDO VCC1 VCC2 VCC3 VCC4
WDI WDO
DSP
RS4H RS3H RS2H RS1H SENSE1 RESET1 RESET CPU CLK
EN2 DC-DC SENSE2 FPGA
TPS386000 RESET2
LDO
SENSE3 RESET3

SENSE4L RESET4

SENSE4H
CT1 CT2 CT3 CT4 GND
RS4M

CT1 CT2 CT3 CT4

RS4L RS3L RS2L RS1L

Figure 29. Typical Application Circuit

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WINDOW COMPARATOR
voltage lower than 0.4V. Figure 31 shows this usage
The comparator at the SENSE4H pin has the in an application circuit. SVS-4 monitors the positive
opposite comparison polarity to the other SENSEm and negative voltage power rail (for example, +15V
pins. In the configuration shown in Figure 30, this and –15V supply to an op amp) and the RESET4 or
comparator monitors overvoltage of the VCC4 node; RESET4 output status continues to be as described
combined with the comparator at SENSE4L, SVS-4 in Table 4. Note that RS42H is located at higher
forms a window comparator. voltage position than RS42L. The threshold voltage
VCC4_target1 = {1+ RS4H/(RS4M + RS4L)} × 0.4 (V) (4) calculations are shown in the following equations:
VCC4_target2 = {1+ (RS4H + RS4M)/RS4L} × 0.4 (V) (5) VCC41_target = (1+RS41H/RS41L) × 0.4 (V) (6)
VCC42_target = (1+RS42L/RS42H) × 0.4 – RS42L/RS42H × VREF
Where VCC4_target1 is the undervoltage threshold, (7)
and VCC4_target2 is the overvoltage threshold.
= 0.4 – (RS42L/RS42H × 0.8 (V)) (8)
SENSING VOLTAGE LESS THAN 0.4V
By using voltage reference output VREF, the SVS-4
comparator can monitor negative voltage or positive

VCC
VCC4
(1.8V to 6.5V)
(3.0V to 3.6V)

RP4
RS41H VCC
316kW
SENSE4L RESET4
RS41M
CT4
8.06kW
SENSE4H
RS41L
40.2kW GND

Figure 30. SVS-4: Window Comparator

VCC
VCC42 VCC41 (1.8V to 6.5V)
(-15V) (+15V)

RP4
RS41H VCC
7.32MW
SENSE4L RESET4
RS42L RS41L
3.83MW CT4
200kW
SENSE4H VREF
RS42H
200kW GND

Figure 31. SVS4: Negative Voltage Sensing

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RESET DELAY TIME primary reset source. A logic low at MR causes

RESET1 or RESET1 to assert. After MR returns to a
Each of the SVS-n channels can be configured logic high and SENSE1 is above its reset threshold,
independently in one of three modes. Table 6 RESET1 or RESET1 is released after the user-
describes the delay time settings. configured reset delay time. Note that unlike the
TPS3808 series, the TPS3860x0 does not integrate
Table 6. Delay Timing Selection an internal pull-up resistor between MR and VCC.
CTn CONNECTION DELAY TIME
To control the MR function from more than one logic
Pull-up to VCC 300ms (typ)
signal, the logic signals can be combined by wired-
Open 20 ms (typ) OR into the MR pin using multiple NMOS transistors
Capacitor to GND Programmable and one pull-up resistor.

To select the 300ms fixed delay time, the CTn pin WATCHDOG TIMER
should be pulled up to VCC using a resistor from
40kΩ to 200kΩ. Please note that there is a pulldown The TPS3860x0 provides a watchdog timer with a
transistor from CTn to GND that turns on every time dedicated watchdog error output, WDO or WDO. The
the device powers on to determine and confirm CTn WDO or WDO output enables application board
pin status; therefore, a direct connection of CTn to designers to easily detect and resolve the hang-up
VCC causes a large current flow. To select the 20ms status of a processor. As with MR, the watchdog
fixed delay time, the CTn pin should be left open. To timer function of the device is also tied to SVS-1.
program a user-defined adjustable delay time, an Figure 28 shows the timing diagram of the WDT
external capacitor must be connected between CTn function. Once RESET1 or RESET1 is released, the
and GND. The adjustable delay time can be internal watchdog timer starts its countdown. Inputting
calculated by the following equation: a logic level transition at WDI resets the internal timer
CCT (nF) = [tDELAY (ms) – 0.5(ms)] × 0.242 (9)
count and the timer restarts the countdown. If the
TPS3860x0 fails to receive any WDI rising or falling
Using this equation, a delay time can be set to edge within the WDT period, the WDT times out and
between 1.4ms to 10s. The external capacitor should asserts WDO or WDO. After WDO or WDO is
be greater than 220pF (nominal) so that the asserted, the device holds the status with the internal
TPS3860x0 can distinguish it from an open CT pin. latch circuit. To clear this timeout status, a reset
The reset delay time is determined by the time it assertion of RESET1 or RESET is required. That is, a
takes an on-chip, precision 300nA current source to negative pulse to MR, a SENSE1 voltage less than
charge the external capacitor to 1.24V. When the VITN, or a VCC power-down is required.
RESETn or RESETn outputs are asserted, the
corresponding capacitors are discharged. When the To reset the processor by WDT timeout, WDO can be
condition to release RESETn or RESETn occurs, the combined with RESET1 by using the wired-OR with
internal current sources are enabled and begin to the TPS386000 option.
charge the external capacitors. When the CTn For legacy applications where the watchdog timer
voltage on a capacitor reaches 1.24V, the timeout causes RESET1 to assert, connect WDO to
corresponding RESETn or RESETn pins are MR; see Figure 29 for the connections and see
released. Note that a low leakage type capacitor Figure 32 and Figure 33 for the timing diagram.
(such as ceramic) should be used, and that stray
capacitance around this pin may cause errors in the IMMUNITY TO SENSEn VOLTAGE
reset delay time. TRANSIENTS
MANUAL RESET The TPS3860x0 is relatively immune to short
negative transients on the SENSEn pin. Sensitivity to
The manual reset (MR) input allows external logic transients depends on threshold overdrive, as shown
signal from other processors, logic circuits, and/or in the typical performance graph TPS386040
discrete sensors to initiate a device reset. Because SENSEn Minimum Pulse Width vs SENSEn
MR is connected to SVS-1, the RESET1 or RESET1 Threshold Overdrive Voltage (Figure 9).
pin is intended to be connected to processor(s) as a

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WDI Event 1 Event 2 Event 3 WDI

Event 1

t
RESET1 RESET1

t
MR = WDO
MR = WDO tD

tWDT

t
(Internal timer)
(Internal timer)

Figure 32. Legacy WDT Configuration Timing

Diagram Figure 33. Enlarged View of Event 1 from
Figure 32

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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (August 2011) to Revision D Page

• Deleted TPS386020 and TPS386060 devices from data sheet ........................................................................................... 1

Changes from Revision B (March 2011) to Revision C Page

• Changed Figure 2 ................................................................................................................................................................. 7

Changes from Revision A (January 2010) to Revision B Page

• Changed data sheet title ....................................................................................................................................................... 1

• Changed Features bullets ..................................................................................................................................................... 1
• Changed Applications bullets ............................................................................................................................................... 1
• Changed first sentence of second paragraph in Description text ......................................................................................... 1
• Changed low quiescent current value in last paragraph of Description text from 12µA to 11µA ......................................... 1
• Changed front-page typical application circuit figure ............................................................................................................ 1
• Added sentence to pin 6 description in Pin Assignments table ............................................................................................ 4
• Changed last sentence of pin 13 description in Pin Assignments table ............................................................................... 4
• Added text to first sentence of first paragraph of General Description section. ................................................................. 12
• Changed caption for Figure 29 ........................................................................................................................................... 16
• Changed link in Window Comparator section to new Figure 30 ......................................................................................... 17
• Deleted typo in Equation 4 and moved Equation 4 to Window Comparator section .......................................................... 17
• Deleted typo in Equation 5 and moved Equation 5 to Window Comparator section .......................................................... 17
• Changed link in Sensing Voltage Less Than 0.4V section to new Figure 31 ..................................................................... 17
• Added Figure 30 ................................................................................................................................................................. 17
• Added Figure 31 ................................................................................................................................................................. 17

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 PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples
(1) Drawing Qty (2) (3) (4)

TPS386000RGPR ACTIVE QFN RGP 20 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS
& no Sb/Br) 386000
TPS386000RGPT ACTIVE QFN RGP 20 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS
& no Sb/Br) 386000
TPS386040RGPR ACTIVE QFN RGP 20 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS
& no Sb/Br) 386040
TPS386040RGPT ACTIVE QFN RGP 20 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS
& no Sb/Br) 386040

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

OTHER QUALIFIED VERSIONS OF TPS386000 :

• Automotive: TPS386000-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS386000RGPR QFN RGP 20 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS386000RGPT QFN RGP 20 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS386040RGPR QFN RGP 20 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS386040RGPT QFN RGP 20 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS386000RGPR QFN RGP 20 3000 367.0 367.0 35.0
TPS386000RGPT QFN RGP 20 250 210.0 185.0 35.0
TPS386040RGPR QFN RGP 20 3000 367.0 367.0 35.0
TPS386040RGPT QFN RGP 20 250 210.0 185.0 35.0

Pack Materials-Page 2
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