Micro 8086
Micro 8086
5.1 INTRODUCTION:
8086 Microprocessor is an enhanced version of 8085Microprocessor that was
designed by Intel in 1976.
It is a 16-bit Microprocessor having 20 address lines and16 data lines that
provides up to 1MB storage.
It consists of powerful instruction set, which provides operations like
multiplication and division easily.
It supports two modes of operation, i.e. Maximum mode and Minimum mode.
Maximum mode is suitable for system having multiple processors and Minimum
mode is suitable for system having a single processor.
It is 16-bit microprocessor
It has a 16-bit data bus, so it can read data from or write data to memory and
ports either 16-bit or 8-bit at a time.
It has 20 bit address bus and can access up to 220 memory locations (1 MB).
It can support up to 64K I/O ports
It provides 14, 16-bit registers
It has multiplexed address and data bus AD0-AD15 & A16-A19
It requires single phase clock with 33% duty cycle to provide internal timing.
Pre fetches up to 6 instruction bytes from memory and queues them in order to
speed up the processing.
8086 supports 2 modes of operation
1. Minimum mode
2. Maximum mode
It is available in 3 versions based on the frequency of operation −
1. 8086 → 5MHz
2. 8086-2 → 8MHz
3. (c)8086-1 → 10 MHz
It uses two stages of pipelining, i.e. fetch Stage and Execute Stage, which
improves performance.
Fetch stage can pre fetch up to 6 bytes of instructions and stores them in the
queue.
Execute stage executes these instructions.
It has 256 vectored interrupts.
It consists of 29,000 transistors.
5.3 REGISTER ORGANIZATION:
8086 has a powerful set of registers known as general purpose registers and
special purpose registers.
All of them are 16-bit registers.
General purpose registers:
These registers can be used as either 8-bit registers or 16-bit registers.
They may be either used for holding data, variables and intermediate results
temporarily or for other purposes like a counter or for storing offset address
for some particular addressing modes etc.
Special purpose registers:
These registers are used as segment registers, pointers, index registers or as
offset storage registers for particular addressing modes.
The registers AX, BX, CX and DX are the general purpose 16-bit registers.
AX is used as 16-bit accumulator. The lower 8-bit is designated as AL and
higher 8-bit is designated as AH.
AL Can be used as an 8-bit accumulator for 8-bit operation.
All data register can be used as either 16 bit or 8 bit. BX is a 16 bit register,
but BL indicates the lower 8-bit of BX and BH indicates the higher 8-bit of BX.
The register BX is used as offset storage for forming physical address in case
of certain addressing modes.
The register CX is used default counter in case of string and loop instructions.
DX register is a general purpose register which may be used as an implicit
operand or destination in case of a few instructions.
2. Segment Registers:
The 8086 architecture uses the concept of segmented memory. 8086 able
to address a memory capacity of 1 megabyte and it is byte organized. This 1
megabyte memory is divided into 16 logical segments. Each segment
contains 64 Kbytes of memory.
The 8086 flag register contents indicate the results of computation in the ALU.
It also contains some flag bits to control the CPU operations.
The condition code flag register is the lower byte of the 16-bit flag register.
The condition code flag register is identical to 8085 flag register, with an
additional overflow flag.
The control flag register is the higher byte of the flag register. It contains
three flags namely direction flag (D), interrupt flag (I) and trap flag (T).
SF (Sign Flag):
This flag is set, when the result of any computation is negative. For signed
computations the sign flag equals the MSB of the result.
ZF (Zero Flag):
PF (Parity Flag):
This flag is set to 1, if the lower byte of the result contains even number of 1’s.
CF (Carry Flag):
This flag is set, when there is a carry out of MSB in case of addition or a borrow
in case of subtraction.
TF (Tarp Flag):
If this flag is set, the processor enters the single step execution mode. The
processor executes the current instruction and the control is transferred to the
Trap interrupt service routine.
IF (Interrupt Flag):
If this flag is set, the mask able interrupts are recognized by the CPU, otherwise
they are ignored.
D (Direction Flag):
This is used by string manipulation instructions. If this flag bit is ‘0’, the string
is processed beginning from the lowest address to the highest address, i.e.,
auto incrementing mode. Otherwise, the string is processed from the highest
address towards the lowest address, i.e., auto decrementing mode.
5.4 ARCHITECTURE OF 8086 MICROPROCESSOR:
As shown in the below figure, the 8086 CPU is divided into two independent
functional parts
Bus Interface Unit(BIU)
Execution Unit(EU)
The execution unit of the 8086 tells the BIU where to fetch instructions or data
from, decodes instructions, and executes instructions.
The EU contains control circuitry, which directs internal operations.
A decoder in the EU translates instructions fetched from memory into a series
of actions, which the EU carries out.
The EU has a 16-bit arithmetic logic unit (ALU) which can add, subtract, AND,
OR, XOR, increment, decrement, complement or shift binary numbers.
The BIU sends out addresses, fetches instructions from memory, reads data
from ports and memory, and writes data to ports and memory.
In simple words, the BIU handles all transfers of data and addresses on the
buses for the execution unit.
Or
BIU takes care of all data and addresses transfers on the buses for the EU like
sending addresses, fetching instructions from the memory, reading data from
the ports and the memory as well as writing data to the ports and the memory.
EU has no direction connection with System Buses so this is possible with the
BIU. EU and BIU are connected with the Internal Bus.
AD0-AD15:
Address/Data bus. These are low order address bus. They are multiplexed with
data. When AD lines are used to transmit memory address the symbol A is used
instead of AD, for example A0-A15. When data are transmitted over AD lines the
symbol D is used in place of AD, for example D0-D7, D8-D15 or D0-D15.
A16-A19:
High order address bus. These are multiplexed with status signals.
S2 S1 S0 Characteristics
0 0 0 Interrupt
acknowledge
0 1 1 Halt
1 0 0 Code access1 0
1 Read memory
1 1 0 Write memory
1 1 1 Passive State
BHE’/S7:
Bus High Enable/Status. During T1 it is low. It is used to enable data onto the
most significant half of data bus, D8-D15.
8-bit device connected to upper half of the data bus use BHE (Active Low)
signal.
It is multiplexed with status signal S7.
S7 signal is available during T2, T3 and T4.
RD’:
This is used for read operation. It is an output signal. It is active when low.
READY:
This is the acknowledgement from the memory or slow device that they have
completed the data transfer. The signal made available by the devices is
synchronized by the 8284A clock generator to provide ready input to the
microprocessor. The signal is active high (1).
INTR:
Interrupt Request. This is triggered input. This is sampled during the last clock
cycles of each instruction for determining the availability of the request. If any
interrupt request is found pending, the processor enters the interrupt
acknowledge cycle. This can be internally masked after resulting the interrupt
enable flag. This signal is active high (1) and has been synchronized internally.
NMI:
Non maskable interrupt. This is an edge triggered input which results in a type
II interrupt. A subroutine is then vectored through an interrupt vector lookup
table which is located in the system memory. NMI is non-maskable internally by
software. A transition made from low (0) to high (1) initiates the interrupt at
the end of the current instruction. This input has been synchronized internally.
INTA:
Interrupt acknowledge. It is active low (0) during T2, T3 and Tw of each
interrupt acknowledge cycle.
MN/MX’:
Minimum/Maximum. This pin signal indicates what mode the processor will
operate in.
RQ’/GT1′, RQ’/GT0′:
These are the Request/Grant signals used by the other processors requesting
the CPU to release the system bus. When the signal is received by CPU, then it
sends acknowledgment. RQ/GT0 has a higher priority than RQ/GT 1.
LOCK’:
It’s an active low pin. It indicates that other system bus masters have not
been allowed to gain control of the system bus while LOCK’ is active low
(0). The LOCK signal will be active until the completion of the next
instruction.
When this signal is active, it indicates to the other processors not to ask the
CPU to leave the system bus. It is activated using the LOCK prefix on any
instruction
RESET:
This pin requires the microprocessor to terminate its present activity
immediately. The signal must be active high (1) for at least four clock cycles.
TEST’:
This examined by a ‘WAIT’ instruction. If the TEST pin goes low (0), execution
will continue, else the processor remains in an idle state. The input is
internally synchronized during each of the clock cycle on leading edge of the
clock.
CLK:
Clock Input. The clock input provides the basic timing for processing
operation and bus control activity. It’s an asymmetric square wave with a
33% duty cycle.
Vcc:
Power Supply (+5V D.C.)
GND:
Ground
QS1, QS0:
Queue Status. These signals indicate the status of the internal 8086 instruction
queue according to the table shown below
QS0 QS1 Status
0 0 No operation
DT/R:
Data Transmit/Receive. This pin is required in minimum systems that want to
use an 8286 or 8287 data bus transceiver. The direction of data flow is
controlled through the transceiver.
DEN:
Data enable. This pin is provided as an output enable for the 8286/8287 in a
minimum system which uses transceiver. DEN is active low (0) during each
memory and input-output access and for INTA cycles.
HOLD/HOLDA:
HOLD indicates that another master has been requesting a local bus .This is an
active high (1). The microprocessor receiving the HOLD request will issue
HLDA (high) as an acknowledgement in the middle of a T4 or T1 clock cycle.
ALE:
Address Latch Enable. ALE is provided by the microprocessor to latch the
address into the 8282 or 8283 address latch. It is an active high (1) pulse
during T1 of any bus cycle. ALE signal is never floated, is always integer.
The 8086 has a combined address and data bus commonly referred as a time
multiplexed address and data bus.
The main reason behind multiplexing address and data over the same pins is the
maximum utilization of processor pins and it facilitates the use of 40 pin standard
DIP package.
The bus can be de multiplexed using a few latches and transceivers, whenever
required.
Basically, all the processor bus cycles consist of at least four clock cycles. These are
referred to as T1, T2, T3, and T4. The address is transmitted by the processor
during T1. It is present on the bus only for one cycle.
The negative edge of this ALE pulse is used to separate the address and the data or
status information. In maximum mode, the status lines S0, S1 and S2 are used to
indicate the type of operation.
Status bits S3 to S7 are multiplexed with higher order address bits and the BHE
signal. Address is valid during T1 while status bits S3 to S7 are valid during T2
through T4.
Maximum mode
In the maximum mode, the 8086 is operated by strapping the MN/MX pin to
ground.
In this mode, the processor derives the status signal S2, S1, S0. Another chip called
bus controller derives the control signal using this status information.
In the maximum mode, there may be more than one microprocessor in the system
configuration.
Minimum mode
In a minimum mode 8086 system, the microprocessor 8086 is operated in
minimum mode by strapping its MN/MX pin to logic 1.
In this mode, all the control signals are given out by the microprocessor chip
itself.
There is a single microprocessor in the minimum mode system.
5.7 8086 MEMORY ORGANIZATION:
Segmented Memory Two types of memory organization are used:
Linear addressing where the entire memory is available to the processor at all the
times (Motorola 68000 family).
Segmented addressing where the memory space is divided into several segments
and the processor is limited to access program instructions and data in specific
segments.
8086 Memory Organization Each memory location 8086 is a byte while the 8086
is a 16-bits microprocessor.
Memory Segmentation:
The memory in an 8086 based system is organized as segmented memory.
The CPU 8086 is able to access 1MB of physical memory. The complete 1MB of
memory can be divided into 16 segments, each of 64KB size and is addressed by
one of the segment register.
The 16-bit contents of the segment register actually point to the starting location of
a particular segment. The address of the segments may be assigned as 0000H to
F000h respectively.
To address a specific memory location within a segment, we need an offset address.
The offset address values are from 0000H to FFFFH so that the physical addresses
range from 00000H to FFFFFH.
Timing Diagrams:
The best way to analyze a timing diagram such as the one to think of time as a
vertical line moving from left to right across the diagram.
The read cycle begins in T1 with the assertion of the address latch enable (ALE)
signal and also M/IO’ signal.
During the negative going edge of this signal, the valid address is latched on the local
bus. The BHE’ and A0 signals address low, high or both bytes.
From T1 to T4, the M/IO’ signal indicate a memory or I/O operation. At T 2, the
address is removed from the local bus and is sent to the output. The bus is then
tristated. The read (RD’) control signal is also activated in T2.
The read (RD’) signal causes the addressed device to enable its data bus driver. After
goes low, the valid data is available on the data bus. The addressed device will drive
the READY line high. When the processor returns the read signal to high level, the
addressed device will again tristate its bus drivers.
Write cycle timing diagram for Minimum mode:
A write cycle also begins with the assertion of ALE and the emission of the address.
The M/IO’ signal is again asserted to indicate a memory or I/O operation.
In T2, after sending the address in T 1, the processor sends the data to be written to
the addressed location. The data remains on the bus until middle of T 4 state. The
WR’ becomes active at the beginning of T2 (unlike RD’ is somewhat delayed in T2 to
provide time for floating).
The BHE’ and A0 signals are used to select the proper byte or bytes of memory or
I/O word to be read or written.
The M/IO’, RD’ and WR’ signals indicate the types of data transfer as specified in
Table.
5.9 MAXIMUM MODE &TIMINGS
In the maximum mode, the 8086 is operated by strapping the MN/MX’ pin to
ground. In this mode, the processor derives the status signals S2’, S1’ and S0’.
Another chip called bus controller derives the control signals using this status
information.
In the maximum mode, there may be more than one microprocessor in the system
configuration. The other components in the system are the same as in the minimum
mode system. The general system organization is as shown in the below figure. The
basic functions of the bus controller chip IC8288, is to derive control signals like RD’
and WR’ (for memory and I/O devices), DEN, DT/R’, ALE, etc. using the information
made available by the processor on the status lines.
The bus controller chip has input lines S2’, S1’ and S0’ and CLK. These inputs to 8288
are driven by the CPU. It derives the outputs ALE, DEN, DT/R’, MWTC’, MRDC’, IORC’,
IOWC’ and INTA’.
INTA’ pin is used to issue two interrupt acknowledge pulses to the interrupt
controller or to an interrupting device.
IORC*, IOWC* are I/O read command and I/O write command signals
respectively. These signals enable an IO interface to read or write the data from or
to the addressed port. The MRDC*, MWTC* are memory read command and memory
write command signals respectively and may be used as memory read and write
signals. All these command signals instruct the memory to accept or send data from
or to the bus.
The maximum mode system timing diagrams are also divided in two portions as
read (input) and write (output) timing diagrams. The address/data and
address/status timings are similar to the minimum mode. ALE is asserted in T1,
just like minimum mode. The only difference lies in the status signals used and the
available control and advanced command signals.
Read cycle timing diagram for Maximum mode:
Write cycle timing diagram for Maximum mode:
5.10 INTERRUPTS:
Definition:
The meaning of „interrupts‟ is to break the sequence of operation. While the CPU
is executing a program, on „interrupt‟ breaks the normal sequence of execution
of instructions, diverts its execution to some other program called Interrupt
Service Routine (ISR).After executing ISR , the control is transferred back again
to the main program. Interrupt processing is an alternative to polling.
Or
Interrupt is the method of creating a temporary halt during program execution
and allows peripheral devices to access the microprocessor. The microprocessor
responds to that interrupt with an ISR (Interrupt Service Routine), which is a
short program to instruct the microprocessor on how to handle the interrupt.
The following image shows the types of interrupts we have in a 8086
microprocessor −
Need for Interrupt:
Interrupts are particularly useful when interfacing I/O devices that provide or
require data at relatively low data transfer rate.
Types of Interrupts:
There are two types of Interrupts in 8086.
1. Hardware Interrupts
2. Software Interrupts
HARDWARE INTERRUPTS:
Hardware interrupt is caused by any peripheral device by sending a signal
through a specified pin to the microprocessor.
The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-
maskable interrupt and INTR is a maskable interrupt having lower priority.
One more interrupt pin associated is INTA called interrupt acknowledge.
NMI (non-maskable):
It is a single non-maskable interrupt pin (NMI) having higher priority than the
maskable interrupt request pin (INTR) and it is of type 2 interrupt.
When this interrupt is activated, these actions take place: −
Completes the current instruction that is in progress.
Pushes the Flag register values on to the stack.
Pushes the CS (code segment) value and IP (instruction pointer) value of the
return address on to the stack.
IP is loaded from the contents of the word location 00008H.
CS is loaded from the contents of the next word location 0000AH.
Interrupt flag and trap flag are reset to 0.
INTR (Maskable):
The INTR is a maskable interrupt because the microprocessor will be
interrupted only if interrupts are enabled using set interrupt flag instruction.
It should not be enabled using clear interrupt Flag instruction.
The INTR interrupt is activated by an I/O port. If the interrupt is enabled and
NMI is disabled, then the microprocessor first completes the current execution
and sends ‘0’ on INTA pin twice. The first ‘0’ means INTA informs the external
device to get ready and during the second ‘0’ the microprocessor receives the
8 bit, say X, from the programmable interrupt controller.
These actions are taken by the microprocessor: −
First completes the current instruction.
Activates INTA output and receives the interrupt type, say X.
Flag register value, CS value of the return address and IP value of the return
address are pushed on to the stack.
IP value is loaded from the contents of word location X × 4
CS is loaded from the contents of the next word location.
Interrupt flag and trap flag is reset to 0
SOFTWARE INTERRUPTS:
Some instructions are inserted at the desired position into the program to
create interrupts. These interrupt instructions can be used to test the working
of various interrupt handlers. It includes: −
The interrupts from Type 5 to Type 31 are reserved for other advanced
microprocessors, and interrupts from 32 to Type 255 are available for
hardware and software interrupts.
2. Register mode:
In this type of addressing mode both the operands are registers.
Or
It means that the register is the source of an operand for an instruction.
Example:
MOV CX, AX ; copies the contents of the 16-bit AX register into
the 16-bit CX register
ADD BX, AX
Example:
MOV AX, [DISP]
MOV AX, [0500]
Example
MOV AX, [BX] ; Suppose the register BX contains 4895H, then the
contents 4895H are moved to AX
In this type of addressing mode the effective address is the sum of index
register, base register and displacement.
Offset= [BX+BP] + [SI or DI] +8-bit or 16-bit displacement.
Example:
MOV AX, [BX+SI+05] an example of 8-bit displacement.
MOV AX, [BX+SI+1235H] an example of 16-bit displacement.
MOV AL, [SI+BP+2000]
MOV DS, CX ;
Move the content of CX to DS
PUSH instruction:
The PUSH instruction decrements the stack pointer by two and copies the
word from source to the location where stack pointer now points. Here the
source must of word size data. Source can be a general purpose register,
segment register or a memory location.
The PUSH instruction first pushes the most significant byte to sp-1, then the
least significant to the sp-2.
Example:-
PUSH CX ; Decrements SP by 2, copy content of CX to the stack (figure
shows execution of this instruction)
PUSH DS ; Decrement SP by 2 and copy DS to stack
POP instruction:
The POP instruction copies a word from the stack location pointed by the stack
pointer to the destination. The destination can be a General purpose register, a
segment register or a memory location. Here after the content is copied the stack
pointer is automatically incremented by two.
Example:
POP CX; Copy a word from the top of the stack to CX and increment SP by 2.
The IN instruction will copy data from a port to the accumulator. If 8 bit is read
the data will go to AL and if 16 bit then to AX. Similarly OUT instruction is used to
copy data from accumulator to an output port.
Both IN and OUT instructions can be done using direct and indirect addressing
modes.
Example:
XCHG instruction
The XCHG instruction exchanges contents of the destination and source. Here
destination and source can be register and register or register and memory
location, but XCHG cannot interchange the value of 2 memory locations.
Example:
ADD instruction:
Add instruction is used to add the current contents of destination with that of
source and store the result in destination. Here we can use register and/or
memory locations.
AF, CF, OF, PF, SF, and ZF flags are affected.
ADD Destination, Source
Example:
o ADD AL, 0FH ; Add the immediate content, 0FH to the content of
AL and store the result in AL
o ADD AX, BX ; AX <= AX+BX
o ADD AX,0100H – IMMEDIATE
o ADD AX,BX – REGISTER
o ADD AX,[SI] – REGISTER INDIRECT OR INDEXED
o ADD AX, [5000H] – DIRECT
o ADD [5000H], 0100H – IMMEDIATE
o ADD 0100H – DESTINATION AX (IMPLICT)
This instruction performs the same operation as ADD instruction, but adds
the carry flag bit (which may be set as a result of the previous calculation) to the
result. All the condition code flags are affected by this instruction. The examples
of this instruction along with the modes are as follows:
Example:
SUB instruction:
Example:
o SUB AL, 0FH ; subtract the immediate content, 0FH from the content
of AL and store the result in AL
o SUB AX, BX ; AX <= AX-BX
o SUB AX,0100H – IMMEDIATE (DESTINATION AX)
o SUB AX,BX – REGISTER
o SUB AX,[5000H] – DIRECT
o SUB [5000H], 0100H – IMMEDIATE
The result is stored in the destination operand. All the flags are affected
(condition code) by this instruction. The examples of this instruction are as
follows:
Example:
CMP: COMPARE:
The instruction compares the source operand, which may be a register
or an immediate data or a memory location, with a destination operand
that may be a register or a memory location.
For comparison, it subtracts the source operand from the destination
operand but does not store the result anywhere. The flags are affected
depending upon the result of the subtraction.
If both of the operands are equal, zero flag is set. If the source operand is
greater than the destination operand, carry flag is set or else, carry flag
is reset. The examples of this instruction are as follows:
Example:
CMP BX, 0100H – IMMEDIATE
CMP AX, 0100H – IMMEDIATE
CMP [5000H], 0100H – DIRECT
CMP BX,[SI] – REGISTER INDIRECT OR INDEXED
1. INC and DEC instructions are used to increment and decrement the
content of the specified destination by one. AF, CF, OF, PF, SF, and ZF
flags are affected.
2. Example:
INC AL ; ALAL + 1
INC AX ; AXAX + 1
DEC AL ; AL AL – 1
DEC AX ; AXAX – 1
AND instruction:
This instruction logically ANDs each bit of the source byte/word with the
corresponding bit in the destination and stores the result in destination. The
source can be an immediate number, register or memory location, register can
be a register or memory location.
The CF and OF flags are both made zero, PF, ZF, SF are affected by the
operation and AF is undefined.
AND Destination, Source
Example:
AND BL, AL; suppose BL=1000 0110 and AL = 1100 1010 then after the
operation BL would be BL= 1000 0010.
AND CX, AX; CX CX AND AX
AND CL, 08; CL CL AND (0000 1000)
OR instruction:
This instruction logically ORs each bit of the source byte/word with the
corresponding bit in the destination and stores the result in destination. The
source can be an immediate number, register or memory location, register can
be a register or memory location.
The CF and OF flags are both made zero, PF, ZF, SF are affected by the
operation and AF is undefined.
OR Destination, Source
Example:
OR BL, AL ; suppose BL=1000 0110 and AL = 1100 1010 then after the
operation BL would be BL= 1100 1110.
OR CX, AX ; CXAX AND AX
OR CL, 08 ; CLCL AND (0000 1000)
NOT instruction:
The NOT instruction complements (inverts) the contents of an operand
register or a memory location, bit by bit. The examples are as follows:
1. Example:
2. NOT AX (BEFORE AX= (1011)2= (B) 16 AFTER EXECUTION AX=
(0100)2= (4)16).
3. NOT [5000H]
XOR instruction:
The XOR operation is again carried out in a similar way to the AND and OR
operation. The constraints on the operands are also similar. The XOR
operation gives a high output, when the 2 input bits are dissimilar. Otherwise,
the output is zero. The example instructions are as follows:
Example:
2) There are two type of shifts logical shifting and arithmetic shifting, later is used with
signed numbers while former with unsigned.
SHL/SAL instruction:
Both the instruction shifts each bit to left, and places the MSB in CF and LSB is made
0. The destination can be of byte size or of word size, also it can be a register or a
memory location. Number of shifts is indicated by the count.
All flags are affected.
SAL/SHL destination, count
Example:
Before Execution,
CY B7 B6 B5 B4 B3 B2 B1 B0
0 1 0 1 1 0 1 1 1
After Execution,
CY B7 B6 B5 B4 B3 B2 B1 B0
1 0 1 1 0 1 1 1 0
SHR instruction:
This instruction shifts each bit in the specified destination to the right and 0
is stored in the MSB position. The LSB is shifted into the carry flag. The
destination can be of byte size or of word size, also it can be a register or a
memory location. Number of shifts is indicated by the count.
CY 1 0 1 1 0 1 1 1 0
After execution,
B7 B6 B5 B4 B3 B 2 B 1 B0 CY
0 1 0 1 1 0 1 1 1
ROL instruction:
This instruction rotates all the bits in a specified byte or word to the left
some number of bit positions. MSB is placed as a new LSB and a new CF. The
destination can be of byte size or of word size, also it can be a register or a
memory location. Number of shifts is indicated by the count.
ROL BL, 1 ; rotates the content of BL register one place to the left.
Before Execution:
CY B B7 B B5 B B B B1 B
6 4 3 2 0
0 1 0 1 1 0 1 1 1
1 0 1 1 0 1 1 1 1
ROR instruction:
This instruction rotates all the bits in a specified byte or word to the right
some number of bit positions. LSB is placed as a new MSB and a new CF. The
destination can be of byte size or of word size, also it can be a register or a
memory location. Number of shifts is indicated by the count.
ROR BL, 1 ; shift the content of BL register one place to the right.
Before execution,
B7 B6 B5 B4 B3 B2 B 1 B0 CY
1 0 1 1 0 1 1 1 0
After execution,
B7 B6 B5 B4 B3 B2 B 1 B0 CY
1 1 0 1 1 0 1 1 1
RCR instruction
This instruction rotates all the bits in a specified byte or word to the right some
number of bit positions along with the carry flag. LSB is placed in a new CF
and previous carry is placed in the new MSB. The destination can be of byte
size or of word size, also it can be a register or a memory location. Number
of shifts is indicated by the count.
Example:
MOV BL, B7H ; BL is made B7H
Before execution,
B7 B6 B5 B4 B3 B2 B 1
B0 CY 1 0 1 1 0 1 1
1 0
After execution,
B7 B6 B5 B4 B3 B2 B 1
B0 CY 0 1 0 1 1 0 1
1 1
A near CALL is a call to a procedure which is in the same code segment as the
CALL instruction. 8086 when encountered a near call, it decrements the SP by 2
and copies the offset of the next instruction after the CALL on the stack. It loads
the IP with the offset of the procedure then to start the execution of the
procedure.
A far CALL is the call to a procedure residing in a different segment. Here value
of CS and offset of the next instruction both are backed up in the stack. And
then branches to the procedure by changing the content of CS with the segment
base containing procedure and IP with the offset of the first instruction of the
procedure.
Example:
Near call
Far call
CALL DWORD PTR [8X]; New values for CS and IP are fetched from four
Memory locations in the DS. The new value for CS is fetched from [8X] and [8X+1],
the new IP is fetched from [8X+2] and [8X+3].
RET instruction:
RET instruction will return execution from a procedure to the next instruction
after the CALL instruction in the calling program. If it was a near call, then IP is
replaced with the value at the top of the stack, if it had been a far call, then
another POP of the stack is required. This second popped data from the stack is
put in the CS, thus resuming the execution of the calling program.
RET instruction does not affect any flags.
JMP INSTRUCTION:
Example:
HLT instruction
The HLT instruction will cause the 8086 microprocessor to fetching and executing
instructions.
The 8086 will enter a halt state. The processor gets out of this Halt signal upon
an interrupt signal in INTR pin/NMI pin or a reset signal on RESET input
WAIT instruction
When this instruction is executed, the 8086 enters into an idle state. This idle
state is continued till a high is received on the TEST input pin or a valid interrupt
signal is received. Wait affects no flags. It generally is used to synchronize the
8086 with a peripheral device(s).
ESC instruction
This instruction is used to pass instruction to a coprocessor like 8087. There is a
6 bit instruction for the coprocessor embedded in the ESC instruction. In most
cases the 8086 treats ESC and a NOP, but in some cases the 8086 will access data
items in memory for the coprocessor
LOCK instruction
In multiprocessor environments, the different microprocessors share a system
bus, which is needed to access external devices like disks. LOCK Instruction is
given as prefix in the case when a processor needs exclusive access of the
system bus for a particular instruction.
It affects no flags.
NOP instruction
At the end of NOP instruction, no operation is done other than the fetching and
decoding of the instruction. It takes 3 clock cycles. NOP is used to fill in time
delays or to provide space for instructions while trouble shooting. NOP affects
no flags.
STC instruction
This instruction sets the carry flag. It does not affect any other flag.
CLC instruction
This instruction resets the carry flag to zero. CLC does not affect any other flag.
CMC instruction
This instruction complements the carry flag. CMC does not affect any other flag.
STD instruction
This instruction is used to set the direction flag to one so that SI and/or DI can be
decremented automatically after execution of string instruction. STD does not
affect any other flag.
CLD instruction
This instruction is used to reset the direction flag to zero so that SI and/or DI can
be incremented automatically after execution of string instruction. CLD does not
affect any other flag.
STI instruction
This instruction sets the interrupt flag to 1. This enables INTR interrupt of the
8086. STI does not affect any other flag.
CLI instruction
This instruction resets the interrupt flag to 0. Due to this the 8086 will not
respond to an interrupt signal on its INTR input. CLI does not affect any other
flag.
MOVS/MOVSB/MOVSW
These instructions copy a word or byte from a location in the data segment
to a location in the extra segment. The offset of the source is in SI and that of
destination is in DI. For multiple word/byte transfers the count is stored in
the CX register.
REP/REPE/REP2/REPNE/REPNZ
REP is used with string instruction; it repeats an instruction until the
specified condition becomes false.
Example: Comments
REP CX=0
LODS/LODSB/LODSW
This instruction copies a byte from a string location pointed to by SI to AL or a
word from a string location pointed to by SI to AX.LODS does not affect any flags.
LODSB copies byte and LODSW copies word.
Example:
STOS/STOSB/STOSW
The STOS instruction is used to store a byte/word contained in AL/AX to the offset
contained in the DI register. STOS does not affect any flags. After copying the
content DI is automatically incremented or decremented, based on the value of
direction flag.
Example:
5. CMPS/CMPSB/CMPSW
CMPS is used to compare the strings, byte wise or word wise. The comparison is
affected by subtraction of content pointed by DI from that pointed by SI. The AF, CF,
OF, PF, SF and ZF flags are affected by this instruction, but neither operand is
affected.
Example: Comments
MOV SI, OFFSET ; Point first string
STRING_A
MOV DI, OFFSET ; Point second string
STRING_B
MOV CX, 0AH ; Set the counter as 0AH
CLD ; Clear direction flag to auto
increment
REPE CMPSB
; Repeatedly compare till
unequal or counter =0
VALUE DB 50H
This statement directs the assembler to reserve 50H memory bytes and
leave them uninitialized for the variable named VALUE.
DD:
Define Double word - used to declare a double word type variable or to
reserve memory locations that can be accessed as double word.
E.g.: ARRAY _POINTER DD 25629261H declares a
double word named ARRAY_POINTER.
DQ -Define Quad word:
This directive is used to direct the assembler to reserve 4 words (8 bytes) of
memory for the specified variable and may initialize it with the specified values.
NUMBER1 DW 1245H
This makes the assembler reserve one word in memory.
END-End of Program:
The END directive marks the end of an assembly language program. When the
assembler comes across this END directive, it ignores the source lines available
later on. Hence, it should be ensured that the END statement should be the last
statement in the file and should not appear in between. Also, no useful program
statement should lie in the file, after the END statement.
ENDP:
End Procedure - Used along with the name of the procedure to indicate the
end of a procedure.
E.g.: SQUARE_ROOT PROC: start of procedure
SQUARE_ROOT ENDP: End of procedure
ENDS-End of Segment:
This directive marks the end of a logical segment. The logical segments are
assigned with the names using the ASSUME directive. The names appear with the
ENDS directive as prefixes to mark the end of those particular segments.
Whatever are the contents of the segments, they should appear in the program
before ENDS. Any statement appearing after ENDS will be neglected from the
segment. The structure shown below explains the fact more clearly.
EQU:
Equate - Used to give a name to some value or symbol. Each time the assembler
finds the given name in the program, it will replace the name with the vale.
E.g.: CORRECTION_FACTOR EQU 03H MOV
AL, CORRECTION_FACTOR
EVEN:
Tells the assembler to increment the location counter to the next even address if
it is not already at an even address.
Used because the processor can read even addressed data in one clock cycle
EXTRN:
Tells the assembler that the names or labels following the directive are in some
other assembly module.
For example if a procedure in a program module assembled at a different time
from that which contains the CALL instruction ,this directive is used to tell the
assembler that the procedure is external
GLOBAL:
Can be used in place of a PUBLIC directive or in place of an EXTRN directive.
LABEL:
Used to give a name to the current value in the location counter.
This directive is followed by a term that specifies the type you want associated
with that name.
E.g: ENTRY_POINT LABEL FAR
NAME:
Used to give a specific name to each assembly module when programs
consisting of several modules are written.
E.g.: NAME PC_BOARD
OFFSET:
Used to determine the offset or displacement of a named data item or
procedure from the start of the segment which contains it.
E.g.: MOV BX, OFFSET PRICES
ORG:
The location counter is set to 0000 when the assembler starts reading a
segment. The ORG directive allows setting a desired value at any point in
the program.
E.g.: ORG 2000H
PROC:
Used to identify the start of a procedure.
E.g.:SMART_DIVIDE PROC FAR identifies the start of a procedure named
SMART_DIVIDE and tells the assembler that the procedure is far
PTR:
Used to assign a specific type to a variable or to a label.
E.g.: NC BYTE PTR[BX]tells the assembler that we want to increment the
byte pointed to by BX
PUBLIC:
Used to tell the assembler that a specified name or label will be accessed
from other modules.
E.g.: PUBLIC DIVISOR, DIVIDEND makes the two variables DIVISOR and
DIVIDEND available to other assembly modules.
SEGMENT:
Used to indicate the start of a logical segment.
E.g.: CODE SEGMENT indicates to the assembler the start of a logical segment
called CODE
SHORT:
Used to tell the assembler that only a 1 byte displacement is needed to code a
jump instruction.
E.g.: JMP SHORT NEARBY_LABEL
TYPE:
Used to tell the assembler to determine the type of a specified variable.
E.g.: ADD BX, TYPE WORD_ARRAY is used where we want to increment BX to
point to the next word in an array of words.
PROGRAM-1: (ADDITION)
PROGRAM-2: (SUBTRACTION)
PROGRAM-4: (DIVISION)
Loop instructions:
These instructions can be used to implement unconditional and
conditional loops. The LOOP, LOOP NZ, LOOP Z instructions belong to this
category.
MICROPROCESSOR:
MICROCONTROLLER:
Microcontroller is like a mini computer with a CPU along with RAM,
ROM, serial ports, timers, and IO peripherals all embedded on a
single chip.
It’s designed to perform application specific tasks that require a
certain degree of control such as a TV remote, LED display panel,
smart watches, vehicles, traffic light control, temperature control,
etc.
It’s a high-end device with a microprocessor, memory, and
input/output ports all on a single chip.
It’s the brains of a computer system which contains enough circuitry
to perform specific functions without external memory.
Since it lacks external components, the power consumption is less
which makes it ideal for devices running on batteries.
Simple speaking, a microcontroller is complete computer system
with less external hardware.
DIFFERENCE BETWEEN MICROPROCESSOR AND MICROCONTROLLER:
MICROPROCESSOR MICROCONTROLLER
Microprocessor contains ALU, General Microcontroller contains the circuitry of
purpose registers, stack pointer, microprocessor, and in addition it has built
program counter, clock timing circuit, in ROM, RAM, I/O Devices,
interrupt circuit Timers/Counters etc.
It has many instructions to move data It has few instructions to move data
between memory and CPU between memory and CPU
Few bit handling instruction It has many bit handling instructions
Less number of pins are multifunctional More number of pins are multifunctional
Single memory map for data and Separate memory map for data and code
code (program) (program)
Access time for memory and IO are Less access time for built in memory and IO.
more
Microprocessor based system requires It requires less additional hardware’s
additional hardware
More flexible in the design point of view Less flexible since the additional circuits
which is residing inside the microcontroller
is fixed for a particular microcontroller
Large number of instructions with Limited number of instruction with few
flexible addressing modes addressing modes
6.2 8 BIT & 16 BIT MICROCONTROLLER:
8 bit Microcontroller:
RISC CISC
Instruction takes one or two cycles Instruction takes multiple cycles
Only load/store instructions are used to In additions to load and store
access memory instructions, memory access is possible
with other instructions also.
Instructions executed by hardware Instructions executed by the micro
program
Fixed format instruction Variable format instructions
Few addressing modes Many addressing modes
Few instructions Complex instruction set
Most of the have multiple register banks Single register bank
Highly pipelined Less pipelined
Complexity is in the compiler Complexity in the microprogram
6.4 ARCHITECTURE OF 8051 MICROCONTROLLER:
Alternate diagram …
8051 is a microcontroller. This means it has an internal
processor, internal memory and an I/O section. The architecture
of 8051 is thus divided into three main sections:
The CPU
Internal Memory
I/O components.
CPU:
8051 has an 8 bit CPU.
This is where all 8-bot arithmetic and logic operations are
performed.
It has the following components.
Example:
ADD A, R0 ; Adds contents of A register and R0
register and stores the result in A register.
ANL A, R0 ; Logically ANDs contents of A
register and R0 register and stores the result in A register.
CPL P0.0 ; Complements the value of P0.0 pin.
A – REGISTER (ACCUMULATOR):
It is an 8-bit register.
In most arithmetic and logic operations, A register hold the first
operand and also gets the result of the operation.
Moreover, it is the only register to be used for data transfers to
and from external memory.
Example:
ADD A, R1 ; Adds contents of A register and R1
register and stores the result in A register.
MOVX A, @DPTR ; A gets the data from External RAM
location pointed by DPTR
B – REGISTER:
It is an 8-bit register.
It is dedicated for Multiplication and Division.
It can also be used in other operations.
Example:
MUL AB; Multiplies contents of A and B registers. Stores 16-
bit result in B and A registers.
DIV AB; Divides contents of A by those of B. Stores quotient
in A and remainder in B.
PC – PROGRAM COUNTER
It is a 16-bit register.
It holds address of the next instruction in program memory
(ROM).
PC gets automatically incremented as soon as any instruction
is fetched.
That’s what makes the program move ahead in a sequential
manner.
In the case of a branch, a new address is loaded into PC.
SP – STACK POINTER
It is an 8-bit register.
It contains address of the top of stack. The Stack is present in the
Internal RAM.
Internal RAM has 8-bit addresses from 00H… 7FH. Hence SP is an
8-bit register.
It is affected during Push and Pop operations. During a Push, SP
gets incremented.
During a Pop, SP gets decremented.
Example:
SETB PSW.3 ; Makes PSW.3 1
CLR PSW.4 ; Makes PSW.40
ALE:
It is used to enable the latching of the address. The address and
data buses are multiplexed.
This is done to reduce the number of pins on the 8051 IC.
Once out of the chip, address and data have to be separated that
is called de-multiplexing.
This is done by a latch, with the help of ALE signal. ALE is “1”
when the bus carries address and “0” when the bus carries data.
This informs the latch, when the bus is carrying address so that
the latch captures only address and not the data.
EA’
It decides whether the first 4 KB of program memory space
(0000H… 0FFFH) will be assigned to internal ROM or External
ROM.
If EA = 0, the External ROM begins from 0000H.
In this case the Internal ROM is discarded. 8051 now uses only
External ROM.
If EA = 1, the External ROM begins from 1000H.
In this case the Internal ROM is used. It occupies the space
0000H…0FFFH.
In modern FLASH ROM versions, this pin also acts as VPP (12
Volt programming voltage) to write into the FLASH ROM.
PSEN’
8051 has a 16-bit address bus (A15 -A0).
This should allow 8051 to access 64 KB of external Memory as
216 = 64 KB. Interestingly though, 8051 can access 64 KB of
External ROM and 64 KB of External RAM, making a total of 128
KB.
Both have the same address range 0000H to FFFFH.
This does not lead to any confusion because there are separate
control signals for External RAM and External ROM.
RD and WR are control signals for External RAM.
PSEN is the READ signal for External ROM.
It is called Program Status Enable as it allows reading from ROM
also known as Program Memory. Having separate control
signals for External RAM and External ROM actually allows us to
double the size of the external memory to a total of 128 KB from
the original 64 KB.
P0.0-P0.7
These are 8 pins of Port 0.
We can perform a byte operation (8-bit) on the whole port 0.
We can also access every bit of port 0 individually by performing
bit operations like set, clear, complement etc.
The bits are called P0.0… P0.7.
Additionally, Port 0 also has an alternate function.
It carries the multiplexed address data lines.
A0-A7 (the lower 8 bits of address) and D0-D7 (8 bits of data) are
multiplexed into AD0-AD7.
In any operation address and data are not issued simultaneously.
First, address is given, then data is transferred. Using a common
bus for both, reduces the number of pins.
To identify if the bus is carrying address or data, we look at the
ALE signal. If ALE = 1, the bus carries address,
If ALE = 0, the bus carries data.
P1.0-P1.7
These are 8 pins of Port 1.
We can perform a byte operation (8-bit) on the whole port 1.
We can also access every bit of port 1 individually by performing
bit operations like set, clear, complement etc. on P1.0… P1.7.
Port 1 also has NO alternate function
P2.0-P2.7
These are 8 pins of Port 2.
We can perform a byte operation (8-bit) on the whole port 2.
We can also access every bit of port 2 individually by performing
bit operations like set, clear, complement etc. on P2.0… P2.7.
Additionally, Port 2 also has an alternate function. It carries the
higher order address lines A8-A15.
P3.0-P3.7
These are 8 pins of Port 3.
We can perform a byte operation (8-bit) on the whole port 3. We
can also access every bit of port 3 individually.
The bits are called P0.0… P0.7.
The various pins of Port 3 have a lot of alternate functions.
Internal ROM
External ROM
Internal RAM
External RAM
8051 has a 128 Bytes of internal RAM. These are 128 locations of
1 Byte each.
The address range is 00H… 7FH.
This RAM is used for storing data.
It is divided into three main parts: Register Banks, Bit
addressable area and a general purpose area.
REGISTER BANKS:
The first 32 locations (Bytes) of the Internal RAM from 00H…
1FH, are used by the programmer as general purpose registers.
Having so many general purpose registers makes programming
easier and faster.
But as a downside, this also vastly increases the number of
opcodes (refer my class lectures for detailed understanding of
this).
Hence the 32 registers are divided into 4 banks, each having 8
Registers R0… R7.
The first 8 locations 00H… 07H are registers R0… R7 of bank 0.
Similarly locations 08H… 0FH are registers R0… R7 of bank 1 and
so on. A register can be addressed using its name, or by its
address.
E.g. Location 00H can be accessed as R0, if Bank 0 is the active
bank.
MOV A, R0; “A” register gets data from register R0.
It can also be accessed as Location 00H, irrespective of which
bank is the active bank.
MOV A, 00H; “A” register gets data from Location 00H.
The appropriate bank is selected by the RS1, RS0 bits of PSW.
Since PSW is available to the programmer, any Bank can be
selected at run-time.
Bank 0 is selected by default, on reset.
Here is something very interesting to know and will also help you
understand further topics. The entire internal RAM is of 128
bytes so the address range is 00H… 7FH.
The bit addressable area has 128 bits so its bit addresses are also
00h… 7FH.
This means every address 00H… 7FH can have two meanings, it
could be a byte address or a bit address.
SETB, CLR etc. are bit ops whereas ADD, SUB etc. are byte
operations.
SETB 00H; this is a bit operation. It will make Bit location
00H contain a value “1”.
MOV A, 00H; this is a byte operation. A” register will get 8-bit data
from byte location 00H.
STACK OF 8051:
Another important element of the Internal RAM is the Stack.
Stack is a set of memory locations operating in Last in First out
(LIFO) manner.
It is used to store return addresses during ISRs and also used by
the programmer to store data during programs.
In 8051, the Stack can only be present in the Internal RAM.
This is because, SP which is an 8-bit register, can only contain an
8-bit address and External RAM has 16-bit address. (#Viva)
On reset SP gets the value 07H.
Thereafter SP is changed by every PUSH or POP operation in the
following manner:
PUSH: POP:
SP SP + 1 Data [SP]
[SP] New data SPSP – 1
The reset value of SP is 07H because, on the first PUSH, SP gets
incremented and then data is pushed on to the stack. This means
the very first data will be stored at location 08H.
This does not affect the default bank (0) and still gives the stack,
the maximum space to grow.
E.g. SETB P0.0; this refers to bit address 80H that’s Port0.0
Types of Registers:
The B0, B1, B2, and B3 stand for banks and each bank contains eight
general purpose registers ranging from ‘R0’ to ‘R7’.
All these registers are byte-addressable registers. Data transfer
between general purpose registers to general purpose registers is
not possible. These banks are selected by the Program Status Word
(PSW) register.
FLAG REGISTER (PSW) OF 8051:
CY - CARRY FLAG
It indicates the carry out of the MSB, after any arithmetic operation.
If CY = 1, There was a carry out of the MSB
If CY = 0, There was no carry out of the MSB
P - PARITY FLAG
It indicates the Parity of the result.
Parity is determined by the number of 1’s in the result.
If PF = 1, The result has ODD parity
If PF = 0, The result has EVEN parity
Example 2:
39 H0011 1001
27 H0010 0111
60 H0110 0000
Flag Affected: CY=0, AC=1, OVR=0, P=0
Example 3:
42 H0100 0010
44 H0100 0100
86 H1000 0110
Flag Affected: CY=0, AC=0, OVR=1, P=1
The result 86H is out of range for a “Signed” Number as it has
become greater than +7FH.
Such an event is called a “Signed Overflow”.
In such a case the MSB of the result gives a wrong sign.
Though the result is +ve (+86H) the MSB is “1” indicating that the
result is –ve.
Overflow is determined by doing an Ex-Or between the 2nd last Carry
and the last Carry.
Here the 2nd last Carry (the one coming into the MSB) is “1”.
The final carry (The one going out of the MSB) is “0”. As “1” Ex-Or
“0” = “1”, the Overflow flag is “1”.
Example 1:
Example 2:
Reset
Reset is the highest priority interrupt, upon reset 8051
microcontroller start executing code from 0x0000 address.
Internal interrupt (Timer Interrupt)
8051 has two internal interrupts namely timer0 and timer1.
Whenever timer overflows, timer overflow flags (TF0/TF1) are set.
Then the microcontroller jumps to their vector address to serve the
interrupt. For this, global and timer interrupt should be enabled.
Serial Port Interrupt (Common for RI or TI)
All interrupts are vectored i.e. they cause the program to execute an
ISR from a pre-determined address in the Program Memory.
Interrupts are controlled mainly by IE and IP SFR's and also by some
bits of TCON SFR.
Interrupt priority
Priority to the interrupt can be assigned by using interrupt priority
register (IP)
Interrupt priority after Reset:
Priority Interrupt source Intr. bit / flag
In the table, interrupts priorities upon reset are shown. As per 8051
interrupt priorities, lowest priority interrupts are not served until
microcontroller is finished with higher priority ones. In a case when
two or more interrupts arrives microcontroller queues them
according to priority.
Or
OR
Bit 3- IE1:
External Interrupt 1 edge flag, set by hardware when interrupt on
INT1 pin occurred and cleared by hardware when interrupt get
processed.
Bit 2- IT1:
This bit selects external interrupt event type on INT1 pin,
1= sets interrupt on falling edge
0= sets interrupt on low level
Bit 1- IE0:
Interrupt0 edge flag, set by hardware when interrupt on INT0 pin
occurred and cleared by hardware when an interrupt is processed.
Bit 0 - IT0:
This bit selects external interrupt event type on INT0 pin.
1= sets interrupt on falling edge
0= sets interrupt on low level
Example
Let’s program the external interrupt of AT89C51 such that, when
falling edge is detected on INT0 pin then the microcontroller will
toggle the P1.0 pin.
T T T T I I I I
F R F R E T E T
1 1 0 0 1 1 0 0
Timer 1 Timer 0
C/T: (Counter/Timer)
Set (1) - Acts as Counter (Counts external frequency on T1 and T0
pin inputs).
Cleared (0) - Acts as Timer (Counts internal clock frequency,
fosc/12).
All 16-bits of the Counter are used (8 bits of THX and 8 bits of TLX).
On each count the 16-bit Timer increments.
The timer overflow flag TFX is set when the Timer rolls-over from
FFFFH to 0000H. Max Count => 216 = 16K = 65536 (FFFFH). Hence
Max Delay 65536(12/f).
Example 2:
WAP to generate a Square wave of 1 KHz from the TxD pin of
8051, Q11 usingTimer1. Assume Clock Frequency of 12 MHz
Example 3:
WAP to generate a Rectangular wave of 1 KHz, having a 25% Duty
Cycle from the TxD pin of 8051, using Timer1. Assume XTAL of 12
MHz
NOTE: For a Rectangular wave of 1 KHz, having 25% Duty Cycle: TON = 250
µsec; TOFF = 750 µsec.
Example 4:
WAP to generate a delay of 1 SECOND using Timer1. Assume
Clock Frequency of 12 MHz (Popular Question in College!)
NOTE: Max delay if XTAL is of 12 MHz … is 65536 µsec è 65.536 msec. Hence
to get a delay of 1 second, we will have to perform the counting
repeatedly in a loop.
Let’s keep the Desired Count 50000. (50 msec delay)
Now 50000d = C350H
Count = Max Count – Desired Count + 1 Count = FFFF – C350 + 1
Count = 3CB0H
We will have to perform this counting 1sec/50msec times è 20 times
Example
MOV A, 35 ; AContents of RAM location 35H
MOV A, 80H ; Acontents of port 0 (SFR at address 80H)
MOV 20H, 30H ; [20H][30H]
i.e. Location 20H gets the contents of location
30H.
Example
MOVX A, @DPTR ; A [DPTR] ^
; A gets the contents of External RAM location whose address is given
by DPTR.
; If DPTR=2000H, then A gets contents of location 0025H from the
external RAM
MOVX @DPTR, A ; [DPTR] ^A
; i.e. A is stored at the External RAM location whose address is given
by DPTR.
Example
5. Write a program to store data FFH into RAM memory locations 50H to
58H using indirect addressing mode.
ORG 0000H ; Set program counter 0000H
MOV A, #0FFH ; Load FFH into A
MOV RO, #50H ; Load pointer, R0-50H
MOV R5, #08H ; Load counter, R5-08H
Start: MOV @RO, A ; Copy contents of A to RAM pointed by R0
INC RO ; Increment pointer
DJNZ R5, start ; Repeat until R5 is zero
END
11. Write a program to count the number of and o's of 8 bit data stored in
location 6000H.
ORG 00008 ; Set program counter 00008
MOV DPTR, #6000h ; Copy address 6000H to DPTR
MOVX A, @DPTR ; Copy number to A
MOV R0, #08 ; Copy 08 in RO
MOV R2, #00 ; Copy 00 in R2
MOV R3, #00 ; Copy 00 in R3
CLR C ; Clear carry flag
BACK: RLC A ; Rotate A through carry flag
JC NEXT ; If CF=1, branch to next
INC R2 ; If CF=0, increment R2 AJMP NEXT2
NEXT: INC R3 ; If CF=1, increment R3
NEXT2: DJNZ RO, BACK ; Repeat until R0 is zero
END
DATA COMMUNICATION:
The 8051 microcontroller is parallel device that transfers eight bits of data
simultaneously over eight data lines to parallel I/O devices.
Parallel data transfer over a long is very expensive. Hence, a serial
communication is widely used in long distance communication.
In serial data communication, 8-bit data is converted to serial bits using a parallel
in serial out shift register and then it is transmitted over a single data line.
The data byte is always transmitted with least significant bit first.
Transmitter Receiver
Transmitter Receiver
Receiver Transmitter
Receiver Transmitter
Baud rate:
The rate at which the data is transmitted is called baud or transfer rate.
The baud rate is the reciprocal of the time to send one bit.
In asynchronous transmission, baud rate is not equal to number of bits per
second.
This is because; each byte is preceded by a start bit and followed by parity and
stop bit.
For example, in synchronous transmission, if data is transmitted with 9600
baud it means that 9600 bits are transmitted in one second.
For bit transmission time = 1 second/ 9600 = 0.104 ms.
8051 SERIAL COMMUNICATION:
The 8051 supports a full duplex serial port.
Three special function registers support serial communication.
1. SBUF Register:
Serial Buffer (SBUF) register is an 8-bit register. It has separate SBUF
registers for data transmission and for data reception. For a byte of data to
be transferred via the TXD line, it must be placed in SBUF register.
Similarly, SBUF holds the 8-bit data received by the RXD pin and read to
accept the received data.
2. SCON register:
The contents of the Serial Control (SCON) register are shown below. This
register contains mode selection bits, serial port interrupt bit (TI and RI)
and also the ninth data bit for transmission and reception (TB8 and RB8).
3. PCON register:
The SMOD bit (bit 7) of PCON register controls the baud rate in
asynchronous mode transmission.
SERIAL COMMUNICATION MODES:
1. Mode 0
In this mode serial port runs in synchronous mode. The data is transmitted
and received through RXD pin and TXD is used for clock output. In this mode
the baud rate is 1/12 of clock frequency.
2. Mode 1
In this mode SBUF becomes a 10 bit full duplex transceiver. The ten bits are
1 start bit, 8 data bit and 1 stop bit. The interrupt flag TI/RI will be set once
transmission or reception is over. In this mode the baud rate is variable and
is determined by the timer 1 overflow rate.
Baud rate = [2smod/32] x Timer 1 overflow Rate
= [2smod/32] x [Oscillator Clock Frequency] / [12 x [256 – [TH1]]]
3. Mode 2
This is similar to mode 1 except 11 bits are transmitted or received. The 11 bits
are, 1 start bit, 8 data bit, a programmable 9 th data bit, 1 stop bit.
Baud rate = [2smod/64] x Oscillator Clock Frequency
4. Mode 3
This is similar to mode 2 except baud rate is calculated as in mode 1
CONNECTIONS TO RS-232
RS-232 standards:
To allow compatibility among data communication equipment made by
various manufactures, and interfacing standard called RS232 was set by the
Electronics Industries Association (EIA) in 1960. Since the standard was set
long before the advent of logic family, its input and output voltage levels are
not TTL compatible.
In RS232, a logic one (1) is represented by -3 to -25V and referred as MARK
while logic zero (0) is represented by +3 to +25V and referred as SPACE. For
this reason to connect any RS232 to a microcontroller system we must use
voltage converters such as MAX232 to convert the TTL logic level to RS232
voltage levels and vice-versa. MAX232 IC chips are commonly referred as
line drivers.
In RS232 standard we use two types of connectors. DB9 connector or DB25
connector.
ORG 0000H
LJMP START
ORG 0030H
START: MOV TMOD, #20H ; select timer 1 mode 2
MOV TH1, #0FAH ; load count to get baud rate of 4800
MOV SCON, #50H ; initialize UART in mode 2
; 8 bit data and 1 stop bit
SETB TR1 ; start timer
AGAIN: MOV SBUF, #'A' ; load char ‘A’ in SBUF
BACK: JNB TI, BACK ; Check for transmit interrupt flag
CLR TI ; Clear transmit interrupt flag
SJMP AGAIN
END
Example 2. Write a program for the 8051 to transfer the message ‘EARTH’
serially at 9600 baud, 8 bit data, and 1 stop bit continuously.
ORG 0000H
LJMP START
ORG 0030H
START: MOV TMOD, #20H ; select timer 1 mode 2
MOV TH1, #0FDH ; load count to get required baud rate of 9600 MOV
SCON, #50H ; initialize uart in mode 2
; 8 bit data and 1 stop bit
SETB TR1 ; start timer
LOOP: MOV A, #'E' ; load 1st letter ‘E’ in a
ACALL LOAD ; call load subroutine
MOV A, #'A' ; load 2nd letter ‘A’ in a
ACALL LOAD ; call load subroutine
MOV A, #'R' ; load 3rd letter ‘R’ in a
ACALL LOAD ; call load subroutine
MOV A, #'T' ; load 4th letter ‘T’ in a
ACALL LOAD ; call load subroutine
MOV A, #'H' ; load 4th letter ‘H’ in a
ACALL LOAD ; call load subroutine
SJMP LOOP ; repeat steps
END
6.15 INTERFACING:
Interfacing is the process of connecting devices together so that they can
exchange the information and that proves to be easier to write the programs.
There are different type of input and output devices as for our requirement such
as LEDs, LCDs, 7segment, keypad, motors and other devices.
Light Emitting Diodes are the semiconductor light sources. Commonly used
LEDs will have a cut-off voltage of 1.7V and current of 10mA. When an LED is
applied with its required voltage and current it glows with full intensity.
The Light Emitting Diode is similar to the normal PN diode but it emits energy
in the form of light. The color of light depends on the band gap of the
semiconductor. The following figure shows “how an LED glows?”
Thus, LED is connected to the AT89C51 microcontroller with the help of a
current limiting resistor. The value of this resistor is calculated using the
following formula.
The main principle of this circuit is to interface LEDs to the 8051 family micro
controller. Commonly, used LEDs will have voltage drop of 1.7v and current of
10mA to glow at full intensity. This is applied through the output pin of the
micro controller.
Circuit Diagram
Circuit Design
Structure
Stepper motors have a permanent magnet called rotor (also called the
shaft) surrounded by a stator. The most common stepper motors have four
stator windings that are paired with a center-tap. This type of stepper motor is
commonly referred to as a four-phase or unipolar stepper motor. The center
tap allows a change of current direction in each of two coils when a winding is
grounded, thereby resulting in a polarity change of the stator.
Interfacing
Even a small stepper motor require a current of 400 mA for its operation.
But the ports of the microcontroller cannot source this much amount of
current. If such a motor is directly connected to the
microprocessor/microcontroller ports, the motor may draw large current from
the ports and damage it. So a suitable driver circuit is used with the
microprocessor/microcontroller to operate the motor.
Motor Driver Circuit (ULN2003)
Stepper motor driver circuits are available readily in the form of ICs.
ULN2003 is one such driver IC which is a High-Voltage High-Current Darlington
transistor array and can give a current of 500mA.This current is sufficient to
drive a small stepper motor. Internally, it has protection diodes used to protect
the motor from damage due to back e.m.f. and large eddy currents. So, this
ULN2003 is used as a driver to interface the stepper motor to the
microcontroller.
Operation:
The important parameter of a stepper motor is the step angle.
It is the minimum angle through which the motor rotates in response
to each excitation pulse.
In a four phase motor if there are 200 steps in one complete rotation
then then the step angle is 360/200 = 1.8O .
So to rotate the stepper motor we have to apply the excitation pulse.
For this the controller should send a hexa decimal code through one of its
ports.
The hex code mainly depends on the construction of the stepper
motor. So, all the stepper motors do not have the same Hex code for their
rotation.
For example, let us consider the hex code for a stepper motor to rotate
in clockwise direction is 77H, BBH, DDH and EEH.
This hex code will be applied to the input terminals of the driver
through the assembly language program.
To rotate the stepper motor in anti-clockwise direction the same code
is applied in the reverse order.
Stepper Motor interface- Schematic Diagram (for 8051)