EEE Software Lab Report On Pspice
EEE Software Lab Report On Pspice
Circuit Diagram:
ex1Fig2.CIR
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V1 1 0 DC 20V
1 0 2 DC 0.1A
R1 2 1 3
R2 3 2 3
R3 3 1 10
R4 4 0 2
E1 3 4 2 1 3
.DC V1 20 20 1
.PRINT DC I(E1)
.END
Simulation Output File:
ex1Fig2.CIR
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V1 I(E1)
2.000E+01 1.557E+02
JOB CONCLUDED
Circuit Diagram:
ex2Fig5b.CIR
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V1 1 0 DC 10V
V2 5 6 DC 0V
V3 7 2 DC 0V
R1 1 2 8
R2 3 4 20
R3 4 0 8
R4 2 5 16
R5 6 0 4
F1 3 7 V2 0.5
.DC V1 10 10 1
.PRINT DC V(F1)
.END
ex2Fig5b.CIR
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V1 V(F1)
1.000E+01 -1.417E+01
ex2Fig5b.CIR
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V1 I(V2) I(V3)
Exercise 3
Circuit Diagram:
Netlist Simulation Input:
ex3Fig6b.CIR
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V1 1 0 DC 100V
V2 3 6 DC 0V
R1 1 2 10
R2 2 3 5
R3 2 4 10
R4 6 0 10
R5 3 5 5
G1 4 0 2 3 10
H1 5 0 V2 10
.END
ex3Fig6b.CIR
ex3Fig6b.CIR
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V1 I(H1)
1.000E+02 0.000E+00
ex3Fig6b.CIR
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JOB CONCLUDED
Calculation: