Slides Part III

Elements of Power Electronics
PART III: Digital control
Fabrice Frébel ([email protected])
September 19th , 2022
ELEC0055: Elements of Power Electronics - Fall 2020

PART III: Digital control
I Chapter 1: Continuous-Time Averaged Modeling of DC-DC

Converters
I Chapter 2: The Digital Control Loop
I Hands-on: The complete design process
I Current Mode Control
PART III is based on the reference book [1] with same chapter
numbering.
Chapter 1: Continuous-Time Averaged Modeling of
DC-DC Converters
I Digitally controlled switched-mode converters
I Converters transfer function
I Solving the time variance problem: averaging
I Solving the non-linearity problem: converter linearization
I Transfer function: buck converter example
I Another example: buck-boost converter
I Averaged small-signal models of basic converters
I Boost transfer function and right half-plane zero (RHPZ)
I State-space averaging
I The pulse width modulator
I Closed loop system
I Definition of the loop gain
I Loop including external perturbation
I Closed loop gain
I Relation between phase margin and stability
I Analog control loop design procedure
Digitally controlled switched-mode converters
Excerpt of [1]:

Pulse width modulated converter
Excerpt of [1]:
I We have tools to study LTI (Linear Time Invariant) systems

but,
I pulse width modulated converter are non-linear (M(D) is often
not linear) and time variant (switching).

Solving the time variance problem: averaging
Excerpt of [1]:
To solve the time variance, we

apply the moving average
operator with period T :
Z t+T /2
1
hx(t)iT , x(τ )dτ.
T t−T /2
The goal is to obtain a model of

averaged variables over a
switching period, this yields for
vo (t):
v̄o (t) , hvo (t)iTs .

Converter averaging: buck converter example
Excerpt of [1]:
The buck converter of figure (a)

can be averaged:
v̄x (t) ≈d(t)v̄g (t),

i¯g (t) ≈d(t)i¯L (t).
The resulting averaged model is

shown on figure (b).

Solving the non-linearity problem: converter linearization
Let us first define circuit variables as follows:
x̄(t) = X + x̄ˆ(t)
x̄(t): averaged value of variable x

X: dc compopent of variable x (= operating point)
x̄ˆ(t): small-signal value of variable x around X
Products of variables (source of non linearities) can be linearized:
x̄(t)ȳ (t) =(X + x̄ˆ(t))(Y + ȳˆ (t))

=XY + X ȳˆ (t) + x̄ˆ(t)Y + x̄ˆ(t)ȳˆ (t)
≈XY + X ȳˆ (t) + x̄ˆ(t)Y .

Converter linearization: buck converter example
Excerpt of [1]:
The buck converter of figure (b)
can then be linearized:
v̄x (t) =Vx + v̄ˆx (t)

ˆ
=(D + d(t))(V ˆg (t))
g + v̄
ˆ
≈DVg + D v̄ˆg (t) + d(t)V g.
Therefore,
ˆ
v̄ˆx (t) ≈ D v̄ˆg (t) + d(t)Vg.
In the same way,

î̄ (t) ≈ Dî̄ (t) + d(t)I
ˆ L.
g L
The result of the linearization is shown on figure (c).
Transfer function: buck converter example
Excerpt of [1]:
The small-signal transfer function of the buck converter is:
v̄ô (s)

1 + srC C
Gvd (s) , =Vg
ˆ
d(s)
v̄ˆ =0,î̄ =0 1 + s(rC + rL )C + s 2 LC
g o
s
1+ ωESR
=Gvd0 s s2
.
1+ Qω0 + ω02

Transfer function: buck converter example
In the previous equation, the constants are defined as follows:
Gvd0 ,Vg ,
1
ωESR , ,
rC C
1
ω0 , √ ,
LC
r
1 L
Q, .
rC + rL C

Another example: buck-boost converter
To obtain the small-signal model of the buck-boost:

I write averaged values of v̄x (t), i¯x (t) and i¯g (t),
I linearize the averaged values to get v̄ˆx (t), î̄x (t) and î̄g (t),
I draw the circuit that matches these linearized relationship.
Write the equations and draw the model

Summary: averaged small-signal models of basic converters
Excerpt of [1]:
(a) Buck
(b) Boost
(c) Buck-Boost

Boost transfer function and right half-plane zero (RHPZ)
The small-signal transfer function of the boost converter is also

obtained by solving the above circuit, but two controlled sources
are involved in this case (using superposition is a fast way to find
the solution):
(V 0 0
v̄ô (s)

D 0 − rL IL ) − sL IL
o
Gvd (s) , =
ˆ v̄ˆ
d(s) ˆ
g =0,īo =0
1 + srL0 C + s 2 L0 C
rL
rL0 = D 02
, L0 = L
D 02
.
Interpretation with exponential response, step response and frequency domain

State-space averaging: time variant model
State-space averaging is a generalization of the averaged
small-signal modeling. Let us consider a converter that evolves
between two structures S0 and S1 . The structure depends on the
switches positions. The state-space equations are:
dx
=Ac x(t) + Bc v (t),
dt
y (t) =Cc x(t) + Ec v (t).
x, v and y represent respectively the state, input and output

vectors. Ac , Bc , Cc , Ec are matrices that model the converter for
each switch position c ∈ {0, 1}. Let us now use define the PWM
signal c(t) and its complement c 0 (t) = 1 − c(t). We can now
rewrite the above equations.
Side note: in the LCS course E matrix is named D. We keep here
the E notation to avoid confusion with the duty-cycle.
Example: see [1] eq 1.39, 1.40, 1.41, 1.42, 1.43, 1.44

State-space averaging: time invariant model
dx
=c(t)[A1 x(t) + B1 v (t)] + c 0 (t)[A0 x(t) + B0 v (t)],
dt
y (t) =c(t)[C1 x(t) + E1 v (t)] + c 0 (t)[C0 x(t) + E0 v (t)].
We can apply the averaging operator h.iTs on both sides of the

equation and with the small ripple approximation, we get the
averaged large-signal state-space equations:
d x̄
=[d(t)A1 + d 0 (t)A0 ]x̄(t) + [d(t)B1 + d 0 (t)B0 ]v̄ (t),
dt
ȳ =[d(t)C1 + d 0 (t)C0 ]x̄(t) + [d(t)E1 + d 0 (t)E0 ]v̄ (t).
Thanks to the averaging, the time varying nature of the system

has been removed but the equations are still non-linear.

State-space averaging: operating point
The operating point can be found by solving the above equations
for ddtx̄ = 0:
0 =[DA1 + D 0 A0 ]X + [DB1 + D 0 B0 ]V ,
Y =[DC1 + D 0 C0 ]X + [DE1 + D 0 E0 ]V .
With the following definition,
A ,DA1 + D 0 A0 , B , DB1 + D 0 B0 ,
C ,DC1 + D 0 C0 , E , DE1 + D 0 E0 ,
we get:
X = −A−1 BV , Y = [−CA−1 B + E ]V .
The above solution is equivalent to apply the inductors volt-second
balance and the capacitors charge balance under the small-ripple
approximation. Example: see [1] eq 1.45, 1.46, 1.47
State-space averaging: small signal model
The state equation can be linearized by defining small signals
around the operating point:
x̄ˆ(t) , x̄(t) − X , dˆ , d(t) − D, v̄ˆ(t) , v̄ (t) − V .
Introducing the above definitions in the averaged large-signal

state-space equations, we get the small-signal equations:
d x̄ˆ ˆ + B v̄ˆ(t),
=Ax̄ˆ(t) + F d(t)
dt
ˆ + E v̄ˆ(t),
ȳˆ(t) =C x̄ˆ(t) + G d(t)
where,
F ,(A1 X + B1 V ) − (A0 X + B0 V ),
G ,(C1 X + E1 V ) − (C0 X + E0 V ).

State-space averaging: solving the small signal model
We can solve the small-signal equations in the Laplace domain:

ˆ + B v̄ˆ(s),
s x̄ˆ(s) =Ax̄ˆ(s) + F d(s)
ˆ + E v̄ˆ(s),
ȳˆ(s) =C x̄ˆ(s) + G d(s)
⇒ ȳˆ(s) =(C (sI − A)−1 F + G )d(s)
ˆ + (C (sI − A)−1 B + E )v̄ˆ(s)
The control transfer matrix is:

ȳˆ(s)

W (s) , = C (sI − A)−1 F + G .
ˆ
d(s) v̄ˆ(s)=0

The disturbance transfer matrix is:

ȳˆ(s)

WD (s) , = C (sI − A)−1 B + E .
v̄ˆ(s) d(s)=0
ˆ
Example: see [1] eq 1.48, 1.49, the boost transfer function has a RHZ (Right Half-Plane Zero).

State-space averaging: solving the small signal model
I Link with the LCS course: each term of W (s) and WD (s)
represents the transfer function that models the effect of
external inputs (duty-cycle, input voltage....) on outputs.
Because there are multiple outputs and multiple inputs the
system is called MIMO.
The pulse width modulator
In order to transform the duty-cycle (continuous variable that has

a value between 0 and 1) into binary (”ON/OFF”) signals that
control power switches, we need a building block called
”modulator”.
There are two main families of PWM modulators:

NSPWM: naturally sampled pulse width modulator. They
process a continuous time modulating signal u(t).
They are typically used in analog controllers.
USPWM: uniformly sampled pulse width modulator. They
process a sampled signal u[k] and generate a PWM
signal updated every switching period. They are
typically used in digital controllers.
Naturally sampled pulse width modulator
Excerpt of [1]:
u(tk ) dˆ 1
d[k] = ⇒ GPWM (s) , = (1)
Vr û Vr

Closed loop system
Excerpt of [1]:
The above figure shows a block diagram of a closed loop system.

GPWM (s) is the transfer function of the PWM modulator. Gvd (s)
models the converter behavior. Gc (s) is the compensator function
to be designed. H(s) is the output voltage (current) sensor
transfer function.
Definition of the loop gain
Excerpt of [1]:

ûy (s)
T (s) , − = Gc (s)GPWM (s)Gvd (s)H(s)
ûx (s) v̂ref =0
Tu (s) , GPWM (s)Gvd (s)H(s) (2)
For the buck converter, we obtain:

s
1 1 + ωESR
Tu (s) = Gvd0 s2
H(s).
Vr 1+ s + Qω0 ω02

Link with LCS course
I In the LCS course, the system to be controlled is called the

plant and has a transfer function P(s). In a power converter,
the plant consists of the PWM modulator, the power
electronics circuit and the measurement circuit:
P(s) = GPWM (s)Gvd (s)H(s) (3)
I In the LCS course, the controller has a transfer function C (s)

that is named here Gc (s).
I In the LSC course, the loop gain is called L(s), here it is
called T (s).
Loop including external perturbation
Excerpt of [1]:

Closed loop gain
I The uncompensated loop phase margin (at the crossover

frequency) gives a stability criteria and allows to design the
compensator Gc (s).
I The reference setpoint to the output transfer function is given
by:
v̄ô (s)

1 T (s)
Gvvref ,cl (s) , = ,
v̄ˆref v̄ˆg (s)=0,î̄o =0
H(s) 1 + T (s)

Closed loop gain
I The sensitivity characteristics to external perturations is

reduced by increasing the loop gain. Refering to the figure on
the previous slide, the closed loop characteristics can be
derived from the open loop characteristics:
v̄ô (s)

Gvg (s)
Gvg ,cl (s) , = ,
ˆ
v̄g (s) v̄ˆref =0,î̄o =0
1 + T (s)
v̄ô (s)

Zo (s)
Zo,cl (s) , − = .
î̄ (s) v̄ˆ =0,v̄ˆ =0
1 + T (s)
o ref g
From the above relations, the goal is to get T (s) as large as

possible on a large bandwidth while maintaining a good phase
margin.

Relation between phase margin and stability
Excerpt of [2]:
For open loop characteristics with a loop gain that falls by -20
dB/decade when T (s) amplitude approaches 1, the phase margin
directly affects the quality factor of the closed loop (second order)
system response.
Relation between phase margin and stability
Excerpt of [2]:
The step response of the closed loop (second order) system is

directy related to the quality factor. The choice of a phase margin
of 52◦ is now explained.
Analog control loop design procedure
1. Determine GPWM (s) using equation 1.
2. Determine H(s) based on the specifications/design of your
sensor.
3. Detemine the transfer function of your converter with the
presented modeling techniques.
4. Trace the Bode Plots (MATALB) for Tu (s) (equation 2) for
different operating points (input voltage, load).
5. Choose the cross-over frequency fc typically 1/10 of the
switching frequency.
6. Choose the target phase margin φm typically > 52◦ .
7. Choose your compensator:
I if DC error has to be canceled, use a PI or PID,
I if phase margin has to be increased, use a PD or PID,
I if phase margin is already 90◦ , use a P or PI.
8. For the integrator term, choose a corner frequency that is
1/10 of the choosen cross-over frequency fc .
Chapter 2: The Digital Control Loop
I Analog vs. digital control

I Example: digital voltage-mode control
I A/D conversion
I The digital compensator
I The digital PID controller (additive form)
I Bilinear mapping
I PID transformation with the bilinear mapping
I PID controller in multiplicative form
I The digital pulse width modulator
I Loop delays
I Digital control loop design procedure
I The integral windup problem
I Unit conversion
Analog vs. digital control
Digital control of switched mode converters introduces two

differences in comparison to analog control:
Time quantization: the controller samples values of analog
variables, processes them to evaluate the modulation
(duty-cycle) and apply it for one sampling period.
Amplitude quantization: analog variables are sampled with finite
resolution analog-to-digital converters, they are
therefore quantized.
There are different approaches to model switching converters. The
approach presented here is based on the averaged model.

Example: digital voltage-mode control
Excerpt of [1]:
The sampled signal is defined by:

vs [k] , vs (tk ).
The most common choice for the sampling period is :
T = Ts , where Ts is the switching period.

A/D conversion
Excerpt of [1]:
I Sampling process
I Amplitude quantization
I Conversion delay tA/D
The sampling process moves the modeling problem from the

analog to the digital world. The amplitude quantization makes the
problem non linear. The delay modifies the dynamics.
Example: show captured data.

Sampling rate different from fs
Excerpt of [1]:
I Alias of the high frequency

content of the analog signal
is present in the sampled
signal (for example at fs ).
I Large digital filtering efforts
are therefore required.

Sampling rate equal to fs
Excerpt of [1]:
I Alias of the high frequency

content of the analog signal
is present in the sampled
signal but only at DC.
I No filtering efforts is needed,
only DC compensation is
required.
Sampling strategy to avoid DC alias
Excerpt of [1]:
For triangular waveforms, the most common solution is to sample

the analog signal in the middle of the ramp. This suppresses DC
aliasing effect.
Amplitude quantization
Excerpt of [1]:
The A/D converter linear range
is divided into 2nA/D bins. Each
(A/D)
bin is qvs volts wide:
(A/D) VFS
qvs = (4)
2nA/D
where VFS is the full scale
voltage.
The figure shows the quantization characteristic QA/D [.]:
(A/D)
vs [k] , QA/D [vs [k]] = qvs ṽs [k]
where vs [k] is the quantized signal, vs [k] is the analog signal and
ṽs [k] is the binary coded signal.
The controller
Excerpt of [1]:
The analog signal vs (t) is

sampled and quantized in vs [k]
after the tA/D conversion delay .
The compensator uses this
sampled signal to generate the
new PWM command u[k] after
the calculation delay tcalc .
A linear and time-invariant compensation law is described by a

difference equation:
u[k] = − a1 u[k − 1] − a2 u[k − 2] − ... − aN u[k − N]
+ b0 e[k] + b1 e[k − 1] + b2 e[k − 2] + ... + bM e[k − M]
The PID compensation law is a praticular case of the above
equation and will be presented.
The digital PID controller (additive form)
Excerpt of [1]:
The PID law is given by:
up [k] =Kp e[k],

ui [k] =ui [k − 1] + Ki e[k],
ud [k] =Kd (e[k] − e[k − 1]),
u[k] =up [k] + ui [k] + ud [k].
The z-transform of the above laws gives the transfer function of

the PID compensator:
U(z) Ki
GPID (z) , = Kp + + Kd (1 − z −1 )
E (z) 1 − z −1
How can we determine the digital coefficients Kp , Ki and Kd ?

Bilinear mapping
The coefficients can be determined by using the classical
compensation techniques in the s-domain. For that purpose the
GPID (z) function can be transformed using:
z = e sT (5)
This transformation is not adequate because it transforms GPID (z)
in a transcendental function of s. A good approximation is:
T
sT e +s 2 1 + s T2 + · · · 1 + s T2
z(s) = e = T = ≈ (6)
e −s 2 1 − s T2 + · · · 1 − s T2
It is called the bilinear transformation:
1 + s T2 2 1 − z −1
z(s) ≈ ⇔ s(z) ≈ (7)
1− s T2 T 1 + z −1

Bilinear mapping interpretation: trapezoidal approximation
In time domain:
Z
v (τ )dτ = p(t)
In s-domain:
1
V (s) = P(s) ⇒ V (s) = s P(s)
s
We can write in discrete time:
v [k − 1] + v [k]
p[k] − p[k − 1] = trapeze surface = T
2
In z-domain:
z −1 V (z) + V (z) 2 1 − z −1
P(z) − z −1 P(z) = T ⇒ V (z) = P(z)
2 T 1 + z −1

Bilinear mapping
The bilinear mapping has the following properties:
I It is a rational transformation.
I Stability limits are conserved: the unit circle (|z| = 1) in the
z-domain is mapped on the y axis in the s-domain.
I Some frequency wrapping is introduced (due to the
approximation) but it yields less than 10% error for
frequencies below 16 T1 .
Excerpt of [1]:

PID transformation with the bilinear mapping
Application of the bilinear transformation allows us to work in the

s-domain and to use the classical analog design tools.
U(z) Ki
GPID (z) , = Kp + + Kd (1 − z −1 )
E (z) 1 − z −1
is transformed to
s
0 U(s) K i 1 + ωp s
GPID (s) , = Kp + + Kd T ,
E (s) T s 1 + ωsp
where ωp , T2 .
It should be noted that ωp appears when converting GPID (z) in the
s-domain and there is no freedom on the value of ωp .

PID transformation with the bilinear mapping
I On the previous slide, Ki is the digital coefficient of the integrator.

In the s-domain, it is divided by T . This can be explained physically
as follows: if T is for example increased, the digital accumulation
(ui [k] = ui [k − 1] + Ki e[k]) will be performed less often due to the
larger sampling period T . This is equivalent to a slower integral in
the s-domain that is represented by a lower analog integrator gain.
I In a similar way, Kd is the digital coefficient for the derivative part.
When transformed in the s-domain, it is multiplied by T . This can
be explained physically as follows: if T is for example increased, the
digital derivative term (ud [k] = Kd (e[k] − e[k − 1])) will performed
on a larger sampling period T . Therefore, the estimation of the
error variation will be taken on sample e[k] and e[k − 1] that are
more spaced in time. This will amplify the value of e[k] − e[k − 1]
which is equivalent to a multiplication by T in the s-domain.
I The multiplicative form of the PID compensator is easier to use and
equivalence relation exists (see next slides).
PID controller in multiplicative form
s
0 K i 1 + ωp s
GPID (s) = Kp + + Kd T (8)
T s 1 + ωsp
is equivalent to
s
0 0 ωPI 0 1 + ωPD
GPID (s) = GPI ∞ (1 + )GPD0
s 1 + ωsp
with,
0 0 ωPI 2ωPI
Kp =GPI ∞ GPD0 (1 + − ), (9)
ωPD ωp
0 0 ωPI
Ki =2GPI ∞ GPD0 , (10)
ωp
1 0 0 ωPI ωp
Kd = GPI ∞ GPD0 (1 − )( − 1). (11)
2 ωp ωPD

PID bode plot
Excerpt of [1]:

PI (lag) compensator in multiplicative form
s
0 Ki 1 + ωp
GPI (s) = Kp + (12)
T s
is equivalent to
0 0 ωPI
GPI (s) = GPI ∞ (1 + )
s
with,
0 ωPI
Kp =GPI ∞ (1 − ), (13)
ωp
0 ωPI
Ki =2GPI ∞ . (14)
ωp

PD (lead) compensator in multiplicative form
0 s
GPD (s) = Kp + Kd T (15)
1 + ωsp
is equivalent to
s
0 0
1+ ωPD
GPD (s) = GPD0
1 + ωsp
with,
0
Kp =GPD0 , (16)
1 0 ωp
Kd = GPD0 ( − 1). (17)
2 ωPD

The digital pulse width modulator
Excerpt of [1]:
Digital modulator are based on a

digital counter. The higher the
counter clock (Tclk ), the higher
the resolution.
The behavior of the digital PWM
is given by:
Ts =Nr Tclk , (18)

u[k]
d[k] = , (19)
Nr
Tclk 1
qD = = . (20)
Ts Nr
Loop delays
Different delays exist between the sampling of the analog signal up

to the generation of the PWM:
I Control delay (tcntrl ):
I FPGA based controller: all calculations are performed in //,
the processing delay is negligible and the only delay is the A/D
conversion delay occuring between the sampling of the analog
signal and the availability of the sampled version vs [k].
I DSP (CPU) based controller: several instructions are needed
and there is an extra delay to be taken into account.
I Modulation delay (tDPWM ): the PWM modulator has an
intrinsic delay due to the PWM process itself.
The total delay induced by the control process is modeled:
td = tcntrl + tDPWM ⇒ e −std .

Loop delays
Excerpt of [1]:
A typical software based

controller is shown.
The A/D sampling and the
controller calculations are
performed during one
switching period (= tcntrl ).
The PWM delay (tDPWM )
occurs after the control delay.

DPWM delay
Excerpt of [1]:

Total loop delay
The total loop delay is defined by:
td , tcntrl + tDPWM .
This total delay is modeled in the s-domain with e −std . Before

estimating compensation factors, the loop gain is corrected to take
this delay into account:
Tu† (s) , Tu (s)e −std .

Digital control loop design procedure
1. Model the loop as in the analog control loop design but with
the delay corrected loop gain Tu† (s).
2. Design the compensation as in the analog control loop design
using the chosen compensator (equation 8, 12 or 15).
3. Once the controller coefficient are determined, transform
them to their digital version (equation 9 to 11, 13 to 14 or 16
to 17).
4. Implement the control law in the digital processor.
It should be noted that the above design procedure is valid if the
sampled signal is a good representation of the averaged signal.
This assumption is the small-aliasing approximation expressed
mathematically by:
vs [k] ≈ v̄s (tk ).
If it is not the case, discrete-time modeling techniques have to be
used.
The integral windup problem (example)
Excerpt of [1]:
For Vg = 4V , at 0µs, the
current rises to 10 A. The
controller reacts quickly to
the induced vo (t) change and
u[k] quickly reaches its
saturation point. However,
vo (t) is still under the set
point and the integrator
continues to integrate.
When vo (t) starts to rise
again, the integrator is well
above 1 and forces u[k] to
stay at 1 and creates an
unexpected lag in the reaction
of the crontroller finally
creating a vo (t) overshoot.
Actuator saturation and integral anti-windup
The solution to the windup problem is to:
I Saturate all variables to avoid numeric issues. Especially
saturate u[k] between the min/max duty-cycle.
I Stop integration when u[k] reaches its saturation limits:

0 if 0 ≤ uPID [k] ≤ 1,
sat[k] =
1 otherwise.
Excerpt of [1]:

Unit conversion
Excerpt of [1]:
I Kp , Ki and Kd on slide ”The PID compensator (additive

form)” have physical units: V1 .
I In the processor, vs [k] and u[k] are represented by integer
numbers related to the respective resolutions 2nA/D (equation
4) and Nr (equation 20).

Unit conversion: from physical to digital representation
Design (physical unit) Digital representation

u[k] 0→1 0 → Nr
vs [k] 0 → VFS 0 → 2nA/D
Kp , Ki , Kd in V1 multiply by 2VnA/D
FS
Nr
Table: Conversion from physical to digital representation.
I The above table is also valid for current measurements

because the current is transformed in a voltage by the
measurement device. This is modeled by H(s).
I Ki is often lower than Kp yielding to quantification errors.
ui [k] = ui [k − 1] + Ki e[k] can be performed in two steps:
accumulator [k] = accumulator [k − 1] + e[k],

ui [k] = Ki accumulator [k]

Unit conversion: example
I The PWM generator runs at 16MHz and generate a 20kHz
signal ⇒ Nr = 16MHz
20kHz = 800.
I ADC of 8 bits resolution over 5V ⇒ VFS = 5V and
2nA/D = 256.
I Kp = 0.32/V ⇒ digital value of Kp is Kp VnA/D
FS
Nr = 5.
2
I Clearly document the variables regarding their physical

meaning.
I Multiplication by Kp , Ki , Kd can often be replaced by shift.
Hands-on: The complete design process
I Controller design (script) with some approximations:

I averaging,
I linearization.
I Controller verification (LTSpice) with a more accurate model:
I time variance,
I non linearities (including quantization).
Current Mode Control
I Current mode control: general principle

I Hysteretic control
I Principle
I Operating frequency
I Current programmed control
I Principle
I Stability analysis
I Compensation
I External voltage loop
Current mode control: general principle
I The plan to be controlled is a

variable structure circuit.
I Current mode control takes
advantage of the variable structure
nature of the circuit.
I The s(xs , ref ) function directly
changes the circuit structure by
acting on the switches state.
I Current mode control is a special case of a sliding mode
controller (see [3]).
I The PWM modulator is replaced here by a direct action on
the circuit structure based on a function of the state of the
system and the reference.

Hysteretic control: principle
I iL (s) = state of the

system
I s function =
comparison with ich ,
icl
I The hysteresis ich − icl is introduced to avoid infinite switching

frequency.
Example: see 1 HystereticControl.asc

Hysteretic control: operating frequency
L L
Ts =d[k]Ts + d 0 [k]Ts = (ich − icl ) + (ich − icl )
Vg − Vo Vo
1 1 Vg
=(ich − icl )L( + ) = (ich − icl )L
Vg − Vo Vo (Vg − Vo )Vo
L 1
=(ich − icl )
Vg ( Vg − Vo ) Vo
Vg Vg Vg
L 1 Vo
=(ich − icl ) , D,
Vg (1 − D)D Vg

Hysteretic control: discussion
I The inductor average current icl + ich −i

2
cl
= ich +i
2
cl
⇒ The average current in the inductor is perfectly controlled.

I Bipolar operation is natural (current can be > 0 or < 0).
I The switching period is function of Vg and D
⇒ The switching frequency varies over a large range.
The variation of the switching frequency can be dangerous because
the switching frequency can be equal to the resonance frequency of
the input or output filter for some operating point. Dangerous
resonance can occur.
Therefore, fixed operating frequency is often preferred.

Current programmed control: principle
Fixed switching frequency is

achieved:
I The switch gate is
controlled by a
set/reset flip-flop.
I A pulse generator
periodically activates
the gate at the
switching frequency
(set).
I The inductor current iL (t) is permanently compared to the setpoint

ic (t).
I Once inductor current iL (t) is higher than the setpoint ic (t), the
gate is deactivated (reset).

Current programmed control: stability analysis procedure
Instead of using the average model to analyze the control loop, it is possible to
directly work in the z-domain. The procedure is as follows:
1. select all state variables (iL (t)),
2. select the sampling instant and name it using ”k” index (iL [k]),
3. express the state evolution (matrix form) from ”k” to ”k+1” (iL [k + 1] as
a function of iL [k], ic [k]),
4. apply linearization (ic [k] = Ic + iˆc [k], iL [k] = IL + iˆL [k]),
5. linearization gives steady-state and small-signal equations,
6. apply z-transform to small-signal equation by ”replacing” k + 1 by z,
k + 2 by z 2 ...
7. extract the poles of the z-domain transfer function to access stability,
8. trace the step function and the bode plot to evaluate the performances.
Current programmed control: time domain equation
Vg − Vo L
ic [k] − iL [k] =d[k]Ts ⇒ d[k] = (ic [k] − iL [k]) , (21)
L Ts (Vg − Vo )
−Vo Vo
iL [k + 1] − ic [k] =d 0 [k]Ts ⇒ iL [k + 1] = ic [k] − (1 − d[k])Ts . (22)
L L
Introducing (21) in (22) yields:
Vo Vo Vo
iL [k + 1] = ic [k](1 + ) − iL [k] − Ts . (23)
Vg − Vo Vg − Vo L

Current programmed control: small signal and steady state
Let us define:
ic [k] =Ic + iˆc [k], (24)
iL [k] =IL + iˆL [k]. (25)
Equation (23) becomes:

Vo Vo
iˆL [k + 1] =iˆc [k](1 + ) − iˆL [k] ,
Vg − Vo Vg − Vo
Vo Vo Vo
IL =Ic (1 + ) − Ts − IL .
Vg − Vo L Vg − Vo
Vo
Introducing D = Vg in the above equations yields:
1 D
iˆL [k + 1] =iˆc [k] − iˆL [k] , (26)
1−D 1−D
Vo
IL =Ic − Ts (1 − D). (27)
L

Current programmed control: stability analysis
Taking the z-transform of equation (26):
1 D
z IˆL (z) = Iˆc (z) − IˆL (z) , (28)
1−D 1−D
1 D
IˆL (z) = Iˆc (z) , pz = − . (29)
z(1 − D) + D 1−D
Example: see 2 CurrentProgrammedControl.asc

Current programmed control: compensation
Cecil W. Deisch (Bell

Laboratories, see [4]) observed
that this instability was related
to the slope of the current.
I At high duty-cycle, the rising slope is ”too low” and leads to

instabilities.
I A small change in current, creates a large change in duty-cycle.
I Compensation is performed by adding an artificial ramp to the
current (or by adding the opposite ramp to the reference point, see
dotted box on the figure).
Compensation: time domain equation
Vg
IR , δTs
L
Vg − Vo Vg
iL [k] + d[k]Ts = ic [k] − d[k]δTs (30)
L L
1
⇒ d[k] = (ic [k] − iL [k]) Vg −Vo V
, (31)
Ts L + δTs Lg
Vg Vo
iL [k + 1] = ic [k] − d[k]δTs − (1 − d[k])Ts . (32)
L L
Compensation: small signal and steady state
Eliminating d[k] by inserting (31) in (32) yields:
Vo −δVg Vo −δVg Vo
iL [k + 1] = ic [k](1 + ) − iL [k]( ) − Ts
Vg − Vo +δVg Vg − Vo +δVg L
Using Equation (24) and (25), the previous equation becomes:
Vo −δVg Vo −δVg
iˆL [k + 1] =iˆc [k](1 + ) − iˆL [k] ,
Vg − Vo +δVg Vg − Vo +δVg
Vo −δVg Vo Vo −δVg
IL =Ic (1 + ) − Ts − IL .
Vg − Vo +δVg L Vg − Vo +δVg
Vo
Introducing D = Vg
in the above equations yields:
1 D−δ
iˆL [k + 1] =iˆc [k] − iˆL [k] , (33)
1 − (D−δ) 1 − (D−δ)
Vo
IL =Ic − Ts (1 − (D−δ)). (34)
L

Compensation: stability analysis
Taking the z-transform of equation (33):
1 D−δ
z IˆL (z) = Iˆc (z) − IˆL (z) , (35)
1 − (D−δ) 1 − (D−δ)
1 D−δ
IˆL (z) = Iˆc (z) , pz = − . (36)
z(1 − (D−δ)) + (D−δ) 1 − (D−δ)

Compensation: discussion
I δ shifts the poles position, δ > 0.5 guarantees stability ∀D.

I Poles show the speed of convergence of the remaining error at each
switching cycle.
I Therefore, a real negative pole in the z-domain corresponds to
sub-harmonic oscillation.
I In practice, when the system is unstable, chaotic behavior appears
because large signal operation is non-linear.
I Typically, δ ∈ [0.5, 1.0] is enough to achieve stability, too large δ
decreases the bandwidth of current mode control.
External voltage loop: principle
Excerpt of [2]
I The internal loop is built with the current programmed controller, its
setpoint is ic (t).
I The external control loop computes the voltage error between the set
point voltage vref and the output voltage v (t).
I The voltage error is used by the compensator to drive ic (t).

External voltage loop: simple approximation
Excerpt of [2]
Over one switching period, the The current control loop is assumed to
averaged values are related by d(t) in be perfect (simple approximation):
CCM:
v¯2 (t) =d(t)v¯1 (t), i¯2 (t) = i¯c (t).

i¯1 (t) =d(t)i¯2 (t).
⇒ v¯1 (t)i¯1 (t) = v¯2 (t)i¯2 (t) = v¯2 (t)i¯c (t) = p̄(t)
The output port is a current source, the input port is a dependent current sink.

Current programmed control: averaged model
i¯1 (t) i¯2 (t) i¯L (t)

+ + +
+ L
C
R v̄ (t)
v¯g (t) v¯1 (t) v¯2 (t)
i¯c (t)
- - - -
p̄(t)
The switch is replaced by its averaged model:

I the output port is a controlled current source: i¯c (t),
I the input port reflects this current with power preservation:
i¯1 (t)v¯1 (t) = i¯c (t)v¯2 (t) = p̄(t).
⇒ linearization has to be applied.
Note: similar reasoning can be applied to other topologies yielding
similar models.
Current programmed control: linearized averaged model
Power conservation can be rewritten:

v¯1 (t) =V1 + vˆ
¯1 (t),
¯1 (t))(I1 + iˆ
(V1 + vˆ ¯2 (t))(Ic + iˆ
¯1 (t)) = (V2 + vˆ ¯c (t))
i¯1 (t) =I1 + iˆ
¯1 (t),
v¯2 (t) =V2 + vˆ
¯2 (t), The input port current is given by:
i¯2 (t) =I2 + iˆ

¯2 (t),
iˆ ¯c (t) V2 +vˆ
¯1 (t) = iˆ Ic
¯2 (t) −vˆ
¯1 (t)
I1
V1 V1 V1
i¯c (t) =Ic + iˆ
¯c (t).
ˆ (t) = iˆ
The output port current is: i¯ ¯c (t)
2
iˆ
¯g = iˆ
¯1 iˆ¯2 iˆ
¯L
+ + +
L
C
R
vˆ
¯g = vˆ
¯1 iˆ¯c V
V1
2 − VI11 vˆ¯2 VIc1 vˆ¯2 v̄ˆ
iˆ¯c
- - -
Controlled sources function of input and output voltages
iˆ
¯g = iˆ
¯1 iˆ¯2 iˆ
¯L
+ + +
L
C
R
vˆ
¯g = vˆ
¯1 iˆ¯c V
V1
2 − VI11 vˆ¯2 VIc1 vˆ¯2 v̄ˆ
iˆ¯c
- - -
V2 I1 V2 Ic Ic D
=D, = D, = R, = V2 = ,
V1 I2 I2 V1 D
R
V2
V1 R Ic ¯c ) D = v̄ˆ D + iˆ
¯c D sL .
− =− D = − 2, vˆ
¯2 =(v̄ˆ + sLiˆ
I1 I2 D D V1 R R R
iˆ¯g iˆ¯L
+ +
L
C
R v̄ˆ
vˆ¯g iˆ
¯c D(1 + sL
R)
− DR2 v̄ˆ D
R
iˆ
¯c
- -
Current programmed control: transfer functions
iˆ¯g iˆ¯L
+ +
L
C
R v̄ˆ
vˆ¯g iˆ
¯c D(1 + sL
R)
− DR2 v̄ˆ D
R
iˆ
¯c
- -
v̄ˆ (s)

1 R
Gvc,cpc (s) , = (R|| ) = →1st order, easy compensator design,
ˆ
¯
ic (s) v¯g =0

ˆ sC 1 + sRC
v̄ˆ (s)

Gvg ,cpc (s) , =0 →no sensitivity to input voltage,
vˆ¯g (s) iˆ¯c =0
ˆg (s)

v¯ R
Zg ,cpc (s) , =− 2 →stability concern.
ˆ
¯ ˆ¯
i (s) i =0,v̄ˆ=0 D
g c
Note: the negative resistance − DR2 is a small-signal negative resistance

affecting stability of the source that supplies the converter.
Current programmed control: summary of key points
I Output voltage can be controlled by implementing a control loop.
I Theory of chapter 1 and 2 can be applied by replacing:
Tu (s) , GPWM (s)Gvd (s)H(s) → Tu (s) , Gvc,cpc (s)H(s)
I Instead of controlling d, the new controller controls i¯c , this is easier

because the phase of Gvc,cpc (s) is 90◦ higher compared to GPWM (s)Gvd (s).
I Current programmed control is a particular case of sliding mode control,
this kind of control reduces by one the order of the controlled system, this
explains the ”gain” of 90◦ when comparing to Gvd (s).
I The above procedure can be applied to other topologies: boost,
buck-boost...
I The small-signal negative resistance appears in all high efficiency
converters where output power/current is controlled (nearly always the
case).
I The small-signal negative resistance affects the stability of the sources
powering the converter.
I Bandwidth of current programmed control is excellent yielding to
unsurpassed over-current protection.
References
[1] P. M. Luca Corradini, Dragan Maksimović and R. Zane, Digital

Control of High-Frequency Switched-Mode Power Converters.
Wiley-IEEE Press, 2015.
[2] R. W. Erickson and D. Maksimović, Fundamentals of Power
Electronics.
Kluwer Academic Publishers, second ed., 2001.
[3] Hansruedi Bűhler, Réglage par mode de glissement.
Presses Polytechniques Romandes, 1986.
[4] C. W. Deisch, “Simple switching control method changes
power converter into a current source,” in 1978 IEEE Power
Electronics Specialists Conference, pp. 300–306, 1978.

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Elements of Power Electronics

PART III: Digital control

Fabrice Frébel ([email protected])

September 19th , 2022

ELEC0055: Elements of Power Electronics - Fall 2020

I Chapter 1: Continuous-Time Averaged Modeling of DC-DC

ELEC0055: Elements of Power Electronics - Fall 2020

I We have tools to study LTI (Linear Time Invariant) systems

ELEC0055: Elements of Power Electronics - Fall 2020

To solve the time variance, we

The goal is to obtain a model of

v̄o (t) , hvo (t)iTs .

ELEC0055: Elements of Power Electronics - Fall 2020

The buck converter of figure (a)

v̄x (t) ≈d(t)v̄g (t),

The resulting averaged model is

ELEC0055: Elements of Power Electronics - Fall 2020

Let us first define circuit variables as follows:

x̄(t): averaged value of variable x

x̄(t)ȳ (t) =(X + x̄ˆ(t))(Y + ȳˆ (t))

ELEC0055: Elements of Power Electronics - Fall 2020

v̄x (t) =Vx + v̄ˆx (t)

In the same way,

The small-signal transfer function of the buck converter is:

ELEC0055: Elements of Power Electronics - Fall 2020

In the previous equation, the constants are defined as follows:

ELEC0055: Elements of Power Electronics - Fall 2020

To obtain the small-signal model of the buck-boost:

ELEC0055: Elements of Power Electronics - Fall 2020

ELEC0055: Elements of Power Electronics - Fall 2020

The small-signal transfer function of the boost converter is also

ELEC0055: Elements of Power Electronics - Fall 2020

x, v and y represent respectively the state, input and output

ELEC0055: Elements of Power Electronics - Fall 2020

We can apply the averaging operator h.iTs on both sides of the

Thanks to the averaging, the time varying nature of the system

ELEC0055: Elements of Power Electronics - Fall 2020

With the following definition,

x̄ˆ(t) , x̄(t) − X , dˆ , d(t) − D, v̄ˆ(t) , v̄ (t) − V .

Introducing the above definitions in the averaged large-signal

ELEC0055: Elements of Power Electronics - Fall 2020

We can solve the small-signal equations in the Laplace domain:

The control transfer matrix is:

The disturbance transfer matrix is:

ELEC0055: Elements of Power Electronics - Fall 2020

In order to transform the duty-cycle (continuous variable that has

There are two main families of PWM modulators:

ELEC0055: Elements of Power Electronics - Fall 2020

The above figure shows a block diagram of a closed loop system.

Tu (s) , GPWM (s)Gvd (s)H(s) (2)

For the buck converter, we obtain:

ELEC0055: Elements of Power Electronics - Fall 2020

I In the LCS course, the system to be controlled is called the

P(s) = GPWM (s)Gvd (s)H(s) (3)

I In the LCS course, the controller has a transfer function C (s)

ELEC0055: Elements of Power Electronics - Fall 2020

I The uncompensated loop phase margin (at the crossover

ELEC0055: Elements of Power Electronics - Fall 2020

I The sensitivity characteristics to external perturations is

From the above relations, the goal is to get T (s) as large as

ELEC0055: Elements of Power Electronics - Fall 2020

The step response of the closed loop (second order) system is