ch5 CPU Scheduling
ch5 CPU Scheduling
Operating System Concepts – 10th Edition Silberschatz, Galvin and Gagne ©2018
Outline
▪ Scheduling Criteria
▪ Scheduling Algorithms
▪ Multi-Processor Scheduling
▪ Real-Time CPU Scheduling
▪ Algorithm Evaluation
Operating System Concepts – 10th Edition 5.2 Silberschatz, Galvin and Gagne ©2018
Introduction
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CPU Scheduler
▪ The CPU scheduler selects from among the processes in ready
queue, and allocates a CPU core to one of them
• Queue may be ordered in various ways
▪ CPU scheduling decisions may take place when a process:
1. Switches from running to waiting state
2. Switches from running to ready state
3. Switches from waiting to ready
4. Terminates
▪ For situations 1 and 4, there is no choice in terms of scheduling. A
new process (if one exists in the ready queue) must be selected
for execution.
▪ For situations 2 and 3, however, there is a choice.
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Model of Process Execution
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Preemptive and Nonpreemptive Scheduling
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Voluntary CPU sharing (nonpreemptive)
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Involuntarily CPU sharing (preemptive)
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Thread may cease using CPU because:
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Scheduling Mechanism
• In an OS, the CPU scheduling mechanism depends on the features
in the hardware → configured with a clock device
• The scheduling mechanism is composed of several different parts
(process scheduler organization):
enqueuer
dispatcher
context switcher
Operating System Concepts – 10th Edition 5.10 Silberschatz, Galvin and Gagne ©2018
Scheduling Mechanism
Operating System Concepts – 10th Edition 5.11 Silberschatz, Galvin and Gagne ©2018
Dispatcher
▪ Dispatcher module gives control of the
CPU to the process selected by the CPU
scheduler; this involves:
• Switching context
• Switching to user mode
• Jumping to the proper location in the
user program to restart that program
▪ Dispatch latency – time it takes for the
dispatcher to stop one process and start
another running
Operating System Concepts – 10th Edition 5.12 Silberschatz, Galvin and Gagne ©2018
The Scheduler
From
Other
States
Process
Ready Process
Place a pointer to the Descriptor
process/thread
descriptor
into a list of processes
that are waiting for the
CPU Save the content of all
Context
Dispatcher CPU
Switcher
Running Process
Allocate the CPU to Remove one process
the process/thread from the CPU and place
another on it
Operating System Concepts – 10th Edition 5.13 Silberschatz, Galvin and Gagne ©2018
Saving the Context
▪ Whenever the CPU is multiplexed, the old process is removed from the
CPU and a new process is installed to begin using the CPU
▪ When a process’s execution is paused, the contents of all of the CPU
registers must be saved in that process’s descriptor so that just before
the process resumes execution, those register contents can be copied
back into the physical CPU registers
Operating System Concepts – 10th Edition 5.14 Silberschatz, Galvin and Gagne ©2018
Context Switching
• The context switch is the operation that saves one
process’s copy of information that stored in the CPU Old Thread
registers, and writes the corresponding information
for another process into the registers.
Descriptor
• Descriptors used to hold a copy of the CPU registers
while a process is not running
CPU
Operating System Concepts – 10th Edition 5.15 Silberschatz, Galvin and Gagne ©2018
Scheduling Criteria
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Preemptive Scheduling and Race Conditions
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Nonpreemptive Strategies
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First- Come, First-Served (FCFS) Scheduling
P1 P2 P3
0 24 27 30
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FCFS Scheduling (Cont.)
P2 P3 P1
0 3 6 30
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First-Come-First-Served
i t(pi)
0 350
1 125
2 475
3 250
4 75 0 350
p0
Operating System Concepts – 10th Edition 5.21 Silberschatz, Galvin and Gagne ©2018
First-Come-First-Served
i t(pi)
0 350
1 125
2 475
3 250
4 75 350 475
p0 p1
Operating System Concepts – 10th Edition 5.22 Silberschatz, Galvin and Gagne ©2018
First-Come-First-Served
i t(pi)
0 350
1 125
2 475
3 250
4 75 350 475 950
p0 p1 p2
Operating System Concepts – 10th Edition 5.23 Silberschatz, Galvin and Gagne ©2018
First-Come-First-Served
i t(pi)
0 350
1 125
2 475
3 250
4 75 350 475 950 1200
p0 p1 p2 p3
Operating System Concepts – 10th Edition 5.24 Silberschatz, Galvin and Gagne ©2018
First-Come-First-Served
i t(pi)
0 350
1 125
2 475
3 250
4 75 350 475 950 1200 1275
p0 p1 p2 p3 p4
Operating System Concepts – 10th Edition 5.25 Silberschatz, Galvin and Gagne ©2018
FCFS Average Wait Time
Operating System Concepts – 10th Edition 5.26 Silberschatz, Galvin and Gagne ©2018
Shortest-Job-First (SJF) Scheduling
▪ Associate with each process the length of its next CPU burst
• Use these lengths to schedule the process with the shortest time
▪ SJF is optimal – gives minimum average waiting time for a given set
of processes
• The difficulty is knowing the length of the next CPU request
• Could ask the user
Operating System Concepts – 10th Edition 5.27 Silberschatz, Galvin and Gagne ©2018
Shortest-Job-First (SJF) Scheduling
▪ Associate with each process the length of its next CPU burst
• Use these lengths to schedule the process with the
shortest time
▪ SJF is optimal – gives minimum average waiting time for a
given set of processes
▪ Preemptive version called shortest-remaining-time-first
▪ How do we determine the length of the next CPU burst?
• Could ask the user
• Estimate
Operating System Concepts – 10th Edition 5.28 Silberschatz, Galvin and Gagne ©2018
Example of SJF
P4 P1 P3 P2
0 3 9 16 24
Operating System Concepts – 10th Edition 5.29 Silberschatz, Galvin and Gagne ©2018
Shortest Job First
i t(pi)
0 350
1 125
2 475
3 250
4 75 0 75
p4
Operating System Concepts – 10th Edition 5.30 Silberschatz, Galvin and Gagne ©2018
Shortest Job First
i t(pi)
0 350
1 125
2 475
3 250
4 75 0 75 200
p4 p1
Operating System Concepts – 10th Edition 5.31 Silberschatz, Galvin and Gagne ©2018
Shortest Job First
i t(pi)
0 350
1 125
2 475
3 250
4 75 0 75 200 450
p4 p1 p3
Operating System Concepts – 10th Edition 5.32 Silberschatz, Galvin and Gagne ©2018
Shortest Job First
i t(pi)
0 350
1 125
2 475
3 250
4 75 0 75 200 450 800
p4 p1 p3 p0
Operating System Concepts – 10th Edition 5.33 Silberschatz, Galvin and Gagne ©2018
Shortest Job First
i t(pi)
0 350
1 125
2 475
3 250
4 75 0 75 200 450 800 1275
p4 p1 p3 p0 p2
Operating System Concepts – 10th Edition 5.34 Silberschatz, Galvin and Gagne ©2018
Shortest Job First
P1 P2 P4 P1 P3
0 1 5 10 17 26
Operating System Concepts – 10th Edition 5.36 Silberschatz, Galvin and Gagne ©2018
Shortest Job Next (Preemptive SJF)
P1 P2 P3 P2 P4 P1
0 2 4 5 7 11 16
• Waiting time =
P1 = 11 - 2 = 9
P2 = 5 - 4 = 1
P3 = 4 - 4 = 0
P4 = 7 - 5 = 2
• average Waiting time = (9 + 1 + 0 +2)/4 = 3
Operating System Concepts – 10th Edition 5.37 Silberschatz, Galvin and Gagne ©2018
Round Robin (RR)
▪ Each process gets a small unit of CPU time (time quantum q),
usually 10-100 milliseconds. After this time has elapsed, the
process is preempted and added to the end of the ready queue.
▪ If there are n processes in the ready queue and the time quantum
is q, then each process gets 1/n of the CPU time in chunks of at
most q time units at once. No process waits more than (n-1)q
time units.
▪ Timer interrupts every quantum to schedule next process
▪ Performance
• q large FIFO
• q small q must be large with respect to context switch,
otherwise overhead is too high
Operating System Concepts – 10th Edition 5.38 Silberschatz, Galvin and Gagne ©2018
Example of RR with Time Quantum = 4
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Round Robin (TQ=20)
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Round Robin (TQ=50)
i t(pi)
0 350
1 125
2 475
3 250 0 50
p0
4 75
W(p0) = 0
Operating System Concepts – 10th Edition 5.41 Silberschatz, Galvin and Gagne ©2018
Round Robin (TQ=50)
i t(pi)
0 350
1 125
2 475
3 250 0 100
p0 p1
4 75
W(p0) = 0
W(p1) = 50
Operating System Concepts – 10th Edition 5.42 Silberschatz, Galvin and Gagne ©2018
Round Robin (TQ=50)
i t(pi)
0 350
1 125
2 475
3 250 0 100
p0 p1 p2
4 75
W(p0) = 0
W(p1) = 50
W(p2) = 100
Operating System Concepts – 10th Edition 5.43 Silberschatz, Galvin and Gagne ©2018
Round Robin (TQ=50)
i t(pi)
0 350
1 125
2 475
3 250 0 100 200
p0 p1 p2 p3
4 75
W(p0) = 0
W(p1) = 50
W(p2) = 100
W(p3) = 150
Operating System Concepts – 10th Edition 5.44 Silberschatz, Galvin and Gagne ©2018
Round Robin (TQ=50)
i t(pi)
0 350
1 125
2 475
3 250 0 100 200
p0 p1 p2 p3 p4
4 75
W(p0) = 0
W(p1) = 50
W(p2) = 100
W(p3) = 150
W(p4) = 200
Operating System Concepts – 10th Edition 5.45 Silberschatz, Galvin and Gagne ©2018
Round Robin (TQ=50)
i t(pi)
0 350
1 125
2 475
3 250 0 100 200 300
p0 p1 p2 p3 p4 p0
4 75
W(p0) = 0
W(p1) = 50
W(p2) = 100
W(p3) = 150
W(p4) = 200
Operating System Concepts – 10th Edition 5.46 Silberschatz, Galvin and Gagne ©2018
Round Robin (TQ=50)
i t(pi)
0 350
1 125
2 475
3 250 0 100 200 300 400 475
p0 p1 p2 p3 p4 p0 p1 p2 p3 p4
4 75
W(p0) = 0
W(p1) = 50
W(p2) = 100
W(p3) = 150
TTRnd(p4) = 475 W(p4) = 200
Operating System Concepts – 10th Edition 5.47 Silberschatz, Galvin and Gagne ©2018
Round Robin (TQ=50)
i t(pi)
0 350
1 125
2 475
3 250 0 100 200 300 400 475 550
p0 p1 p2 p3 p4 p0 p1 p2 p3 p4 p0 p1
4 75
W(p0) = 0
TTRnd(p1) = 550 W(p1) = 50
W(p2) = 100
W(p3) = 150
TTRnd(p4) = 475 W(p4) = 200
Operating System Concepts – 10th Edition 5.48 Silberschatz, Galvin and Gagne ©2018
Round Robin (TQ=50)
i t(pi)
0 350
1 125
2 475
3 250 0 100 200 300 400 475 550 650
p0 p1 p2 p3 p4 p0 p1 p2 p3 p4 p0 p1 p2 p3
4 75
650 750 850 950
p0 p2 p3 p0 p2 p3
W(p0) = 0
TTRnd(p1) = 550 W(p1) = 50
W(p2) = 100
TTRnd(p3) = 950 W(p3) = 150
TTRnd(p4) = 475 W(p4) = 200
Operating System Concepts – 10th Edition 5.49 Silberschatz, Galvin and Gagne ©2018
Round Robin (TQ=50)
i t(pi)
0 350
1 125
2 475
3 250 0 100 200 300 400 475 550 650
p0 p1 p2 p3 p4 p0 p1 p2 p3 p4 p0 p1 p2 p3
4 75
650 750 850 950 1050
p0 p2 p3 p0 p2 p3 p0 p2 p0
Operating System Concepts – 10th Edition 5.50 Silberschatz, Galvin and Gagne ©2018
Round Robin (TQ=50)
i t(pi)
0 350
1 125
2 475
3 250 0 100 200 300 400 475 550 650
p0 p1 p2 p3 p4 p0 p1 p2 p3 p4 p0 p1 p2 p3
4 75
650 750 850 950 1050 1150 1250 1275
p0 p2 p3 p0 p2 p3 p0 p2 p0 p2 p2 p2 p2
Operating System Concepts – 10th Edition 5.51 Silberschatz, Galvin and Gagne ©2018
Priority Scheduling
▪ The CPU is allocated to the process with the highest priority (smallest
integer highest priority)
• Preemptive
• Nonpreemptive
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Example of Priority Scheduling
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Priority Scheduling
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Multiple-Processor Scheduling
▪ CPU scheduling more complex when multiple CPUs are available
▪ Multiprocess may be any one of the following architectures:
• Multicore CPUs
• Multithreaded cores
• NUMA systems
• Heterogeneous multiprocessing
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Multiple-Processor Scheduling
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Multicore Processors
▪ Recent trend to place multiple processor cores on same physical chip
▪ Faster and consumes less power
▪ Multiple threads per core also growing
• Takes advantage of memory stall to make progress on another
thread while memory retrieve happens
▪ Figure
Operating System Concepts – 10th Edition 5.58 Silberschatz, Galvin and Gagne ©2018
Multithreaded Multicore System
▪ Each core has > 1 hardware threads.
▪ If one thread has a memory stall, switch to another thread!
▪ Figure
Operating System Concepts – 10th Edition 5.59 Silberschatz, Galvin and Gagne ©2018
Multithreaded Multicore System
▪ Chip-multithreading (CMT)
assigns each core multiple
hardware threads. (Intel refers
to this as hyperthreading.)
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Multithreaded Multicore System
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Multiple-Processor Scheduling – Load Balancing
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Multiple-Processor Scheduling – Processor Affinity
▪ When a thread has been running on one processor, the cache contents
of that processor stores the memory accesses by that thread.
▪ We refer to this as a thread having affinity for a processor (i.e.,
“processor affinity”)
▪ Load balancing may affect processor affinity as a thread may be moved
from one processor to another to balance loads, yet that thread loses
the contents of what it had in the cache of the processor it was moved
off of.
▪ Soft affinity – the operating system attempts to keep a thread running
on the same processor, but no guarantees.
▪ Hard affinity – allows a process to specify a set of processors it may
run on.
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NUMA and CPU Scheduling
If the operating system is NUMA-aware, it will assign memory closes
to the CPU the thread is running on.
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Real-Time CPU Scheduling
▪ Can present obvious challenges
▪ Soft real-time systems – Critical real-time tasks have the highest
priority, but no guarantee as to when tasks will be scheduled
▪ Hard real-time systems – task must be serviced by its deadline
Operating System Concepts – 10th Edition 5.65 Silberschatz, Galvin and Gagne ©2018
Real-Time CPU Scheduling
▪ Event latency – the amount of
time that elapses from when
an event occurs to when it is
serviced.
▪ Two types of latencies affect
performance
1. Interrupt latency – time
from arrival of interrupt to
start of routine that
services interrupt
2. Dispatch latency – time
for schedule to take
current process off CPU
and switch to another
Operating System Concepts – 10th Edition 5.66 Silberschatz, Galvin and Gagne ©2018
Interrupt Latency
Operating System Concepts – 10th Edition 5.67 Silberschatz, Galvin and Gagne ©2018
Dispatch Latency
▪ Conflict phase of
dispatch latency:
1. Preemption of
any process
running in kernel
mode
2. Release by low-
priority process
of resources
needed by high-
priority
processes
Operating System Concepts – 10th Edition 5.68 Silberschatz, Galvin and Gagne ©2018
Priority-based Scheduling
▪ For real-time scheduling, scheduler must support preemptive, priority-
based scheduling
• But only guarantees soft real-time
▪ For hard real-time must also provide ability to meet deadlines
▪ Processes have new characteristics: periodic ones require CPU at
constant intervals
• Has processing time t, deadline d, period p
• 0≤t≤d≤p
• Rate of periodic task is 1/p
Operating System Concepts – 10th Edition 5.69 Silberschatz, Galvin and Gagne ©2018
Algorithm Evaluation
▪ How to select CPU-scheduling algorithm for an OS?
▪ Determine criteria, then evaluate algorithms
▪ Deterministic modeling
• Type of analytic evaluation
• Takes a particular predetermined workload and defines
the performance of each algorithm for that workload
▪ Consider 5 processes arriving at time 0:
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Deterministic Evaluation
• RR is 23ms:
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End of Chapter 5
Operating System Concepts – 10th Edition Silberschatz, Galvin and Gagne ©2018