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CPARCH1L – COE201
Engr. JC Z. Apduhan
0 0 0 0 0 0 0
0 0 1 0 1 0 0
0 1 0 0 1 1 0
0 1 1 1 0 0 1
1 0 0 0 1 1 0
1 0 1 1 0 0 1
1 1 0 1 0 1 1
1 1 1 1 1 1 1
= (A B) C + (A B) C
=A B C
= AB + (AB + AB) C
= AB + (A B) C
2. Design, construct and test a combination of full adder circuit implementation of ripple
carry adder. Draw your logic diagram inside the box.
B. Using a combination of half adder and full adders.
1. Derive the truth table of ripple carry adder using full adder and half adder implementation:
A B SUM CARRY
Cin A3 A2 A1 A0 B3 B2 B1 0 S3 S2 S1 S0 Cout
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 1 0 0 1 0 0
0 0 0 1 0 0 0 1 0 0 1 0 0 0
0 0 0 1 1 0 0 1 1 0 1 1 0 0
0 0 1 0 0 0 1 0 0 1 0 0 0 0
0 0 1 0 1 0 1 0 1 1 0 1 0 0
0 0 1 1 0 0 1 1 0 1 1 0 0 0
0 0 1 1 1 0 1 1 1 1 1 1 0 0
0 1 0 0 0 1 0 0 0 0 0 0 0 1
0 1 0 0 1 1 0 0 1 0 0 1 0 1
0 1 0 1 0 1 0 1 0 0 1 0 0 1
0 1 0 1 1 1 0 1 1 0 1 1 0 1
0 1 1 0 0 1 1 0 0 1 0 0 0 1
0 1 1 0 1 1 1 0 1 1 0 1 0 1
0 1 1 1 0 1 1 1 0 1 1 0 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0 1
2. Design, construct and test a combination of full and half adder circuit implementation of ripple
carry adder. Draw your logic diagram inside the box.
A1 A2 A3 A4 B4 B3 B2 B1 S4 S3 S2 S1 CARRY
0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 1 0 0 1 0 0 0 0
1 0 0 0 1 0 0 0 0 0 0 0 1
1 0 1 0 1 0 1 0 0 1 0 0 1
1 1 0 0 1 1 0 0 1 0 0 0 1
1 1 1 0 1 1 1 0 1 1 0 0 1
1 1 1 1 1 1 1 1 1 1 1 0 1
OBSERVATION:
Experiment #2 appears to have included building a Ripple Adder Carry using only full adders. A complete
adder is a digital circuit that takes three inputs (two operands and a carry-in) and adds them to create a sum
and a carry-out.
One thing to keep in mind when employing solely full adders in a Ripple Adder Carry is that it might cause
considerable delays in carry propagation. Because the carry-out from each complete adder is dependent on the
carry-in from the previous stage, the carry signal must pass through each stage sequentially.
CONCLUSION:
Adding binary integers with solely complete adders in a Ripple Adder Carry can be an acceptable strategy. It
is a simplistic implementation that is simple to understand and create.
The propagation delay of the carry signal through each step is one possible downside of this system. This
delay can reduce the adder's speed and render it unsuitable for high-performance applications.
Furthermore, as compared to other types of adders, employing solely complete adders might result in a bigger
circuit, which can increase complexity and expense.
NATIONAL UNIVERSITY
RUBRIC FOR LABORATORY PERFORMANCE
Evaluated by:
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Printed Name and Signature of Faculty Member
Date:_____________________________