a 16-Bit 100 kSPS

Sampling ADC
AD677
FEATURES FUNCTIONAL BLOCK DIAGRAM
Autocalibrating
On-Chip Sample-Hold Function
A CHIP
Serial Output VIN 10
16-BIT
9 DAC COMP
16 Bits No Missing Codes AGND SENSE INPUT
VR E F
61 LSB INL 11 BUFFERS
CAL
AGND 8 DAC
–99 dB THD
LOGIC TIMING
92 dB S/(N+D)
1 MHz Full Power Bandwidth LEVEL TRANSLATORS

15 BUSY

14 SCLK

CAL 16 SAR 3 SDATA

MICROCODED
CLK 2 CONTROLLER ALU

SAMPLE 1 RAM
D CHIP

AD677

PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS

The AD677 is a multipurpose 16-bit serial output analog-to- 1. Autocalibration provides excellent dc performance while
digital converter which utilizes a switched-capacitor/charge eliminating the need for user adjustments or additional exter-
redistribution architecture to achieve a 100 kSPS conversion nal circuitry.
rate (10 µs total conversion time). Overall performance is opti- 2. ± 5 V to ± 10 V input range (± VREF).
mized by digitally correcting internal nonlinearities through
on-chip autocalibration. 3. Available in 16-pin 0.3" skinny DIP or 28-lead SOIC.
The AD677 circuitry is segmented onto two monolithic chips— 4. Easy serial interface to standard ADI DSPs.
a digital control chip fabricated on Analog Devices DSP CMOS 5. TTL compatible inputs/outputs.
process and an analog ADC chip fabricated on our BiMOS II
6. Excellent ac performance: –99 dB THD, 92 dB S/(N+D)
process. Both chips are contained in a single package.
peak spurious –101 dB.
The AD677 is specified for ac (or “dynamic”) parameters such
7. Industry leading dc performance: 1.0 LSB INL, ± 1 LSB full
as S/(N+D) Ratio, THD and IMD which are important in sig-
scale and offset.
nal processing applications. In addition, dc parameters are
specified which are important in measurement applications.
The AD677 operates from +5 V and ± 12 V supplies and typi-
cally consumes 450 mW using a 10 V reference (360 mW with
5 V reference) during conversion. The digital supply (VDD) is
separated from the analog supplies (VCC, VEE) for reduced digi-
tal crosstalk. An analog ground sense is provided to remotely
sense the ground potential of the signal source. This can be use-
ful if the signal has to be carried some distance to the A/D con-
verter. Separate analog and digital grounds are also provided.
The AD677 is available in a 16-pin narrow plastic DIP, 16-pin
narrow side-brazed ceramic package, or 28-lead SOIC. A paral-
lel output version, the AD676, is available in a 28-pin ceramic
or plastic DIP. All models operate over a commercial tempera-
ture range of 0°C to +70°C or an industrial range of –40°C to
+85°C.

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
AD677–SPECIFICATIONS
AC SPECIFICATIONS (T MIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)1
AD677J/A AD677K/B
Parameter Min Typ Max Min Typ Max Units
Total Harmonic Distortion (THD)2
@ 83 kSPS, TMIN to TMAX –97 –92 –99 –95 dB
@ 100 kSPS, +25°C –97 –92 –99 –95 dB
@ 100 kSPS, TMIN to TMAX –93 –95 dB
Signal-to-Noise and Distortion Ratio (S/(N+D))2, 3
@ 83 kSPS, TMIN to TMAX 89 91 90 92 dB
@ 100 kSPS, +25°C 89 91 90 92 dB
@ 100 kSPS, TMIN to TMAX 89 90 dB
Peak Spurious or Peak Harmonic Component –101 –101 dB
Intermodulation Distortion (IMD)4
2nd Order Products –102 –102 dB
3rd Order Products –98 –98 dB
Full Power Bandwidth 1 1 MHz
Noise 160 160 µV rms

DIGITAL SPECIFICATIONS (for all grades T MIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)
Parameter Test Conditions Min Typ Max Units
LOGIC INPUTS
VIH High Level Input Voltage 2.0 VDD + 0.3 V
VIL Low Level Input Voltage –0.3 0.8 V
IIH High Level Input Current VIH = VDD –10 +10 µA
IIL Low Level Input Current VIL = 0 V –10 +10 µA
CIN Input Capacitance 10 pF
LOGIC OUTPUTS
VOH High Level Output Voltage IOH = 0.1 mA VDD – 1 V V
IOH = 0.5 mA 2.4 V
VOL Low Level Output Voltage IOL = 1.6 mA 0.4 V
NOTES
1
VREF = 10.0 V, Conversion Rate = 100 kSPS, f lN = 1.0 kHz, V IN = –0.05 dB, Bandwidth = 50 kHz unless otherwise indicated. All measurements referred to a 0 dB
(20 V p-p) input signal. Values are post-calibration.
2
For other input amplitudes, refer to Figure 12.
3
For dynamic performance with different reference values see Figure 11.
4
fa = 1008 Hz, fb = 1055 Hz. See Definition of Specifications section and Figure 16.
Specifications subject to change without notice.

–2– REV. A
 AD677
DC SPECIFICATIONS (T MIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 1O%)
1

AD677J/A AD677K/B
Parameter Min Typ Max Min Typ Max Units
TEMPERATURE RANGE
J, K Grades 0 +70 0 +70 °C
A, B Grades –40 +85 –40 +85 °C
ACCURACY
Resolution 16 16 Bits
Integral Nonlinearity (INL)
@ 83 kSPS, TMIN to TMAX ±1 ±1 ± 1.5 LSB
@ 100 kSPS, +25°C ±1 +1 ± 1.5 LSB
@ 100 kSPS, TMIN to TMAX ±2 ±2 LSB
Differential Nonlinearity (DNL)–No Missing Codes 16 16 Bits
Bipolar Zero Error2 ±2 ±4 ±1 ±3 LSB
Positive, Negative FS Errors2
@ 83 kSPS ±2 ±4 ±1 ±3 LSB
@ 100 kSPS, +25°C ±2 ±4 ±1 ±3 LSB
@ 100 kSPS ±4 ±4 LSB
TEMPERATURE DRIFT3
Bipolar Zero ± 0.5 ± 0.5 LSB
Postive Full Scale ± 0.5 ± 0.5 LSB
Negative Full Scale ± 0.5 ± 0.5 LSB
VOLTAGE REFERENCE INPUT RANGE4 (VREF) 5 10 5 10 V
5
ANALOG INPUT
Input Range (VIN) ± VREF ± VREF V
Input Impedance * *
Input Settling Time 2 2 µs
Input Capacitance During Sample 50* 50* pF
Aperture Delay 6 6 ns
Aperture Jitter 100 100 ps
POWER SUPPLIES
Power Supply Rejection6
VCC = +12 V ± 5% ± 0.5 ± 0.5 LSB
VEE = –12 V ± 5% ± 0.5 ± 0.5 LSB
VDD = +5 V ± 10% ± 0.5 ± 0.5 LSB
Operating Current
VREF = +5 V
ICC 14.5 18 14.5 18 mA
IEE 14.5 18 14.5 18 –mA
IDD 3 5 3 5 mA
Power Consumption 360 480 360 480 mW
VREF = +10 V
ICC 18 24 18 24 mA
IEE 18 24 18 24 –mA
IDD 3 5 3 5 mA
Power Consumption 450 630 450 630 mW
NOTES
1
VREF = 10.0 V, Conversion Rate = 100 kSPS unless otherwise noted. Values are post-calibration.
2
Values shown apply to any temperature from T MIN to TMAX after calibration at that temperature at nominal supplies.
3
Values shown are based upon calibration at +25°C with no additional calibration at temperature. Values shown are the typical variation from the value at +25 °C.
4
See “APPLICATIONS” section for recommended voltage reference circuit, and Figure 11 for dynamic performance with other reference voltage values.
5
See “APPLICATIONS” section for recommended input buffer circuit.
6
Typical deviation of bipolar zero, –full scale or +full scale from min to max rating.
*For explanation of input characteristics, see “ANALOG INPUT” section.
Specifications subject to change without notice.

REV. A –3–
AD677
TIMING SPECIFICATIONS (T MIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)1
Parameter Symbol Min Typ Max Units
Conversion Period 2, 3
tC 10 1000 µs
CLK Period4 tCLK 480 ns
Calibration Time tCT 85532 tCLK
Sampling Time tS 2 µs
Last CLK to SAMPLE Delay5 tLCS 2.1 µs
SAMPLE Low tSL 100 ns
SAMPLE to Busy Delay tSS 30 75 ns
1st CLK Delay tFCD 50 ns
CLK Low6 tCL 50 ns
CLK High6 tCH 50 ns
CLK to BUSY Delay tCB 180 300 ns
CLK to SDATA Valid tCD 50 100 175 ns
CLK to SCLK High tCSH 100 180 300 ns
SCLK Low tSCL 50 80 ns
SDATA to SCLK High tDSH 50 80 ns
CAL High Time tCALH 50 ns
CAL to BUSY Delay tCALB 15 50 ns
NOTES
1
See the “CONVERSION CONTROL” and “AUTOCALIBRATION” sections for detailed explanations of the above timing.
2
Depends upon external clock frequency; includes acquisition time and conversion time. The maximum conversion period is specified to account for the droop of the
internal sample/hold function. Operation at slower rates may degrade performance.
3
tC = tFCD + 16 × tCLK + tLCS.
4
580 ns is recommended for optimal accuracy over temperature (not necessary during calibration cycle).
5
If SAMPLE goes high before the 17th CLK pulse, the device will start sampling approximately 100 ns after the rising edge of the 17th CLK pulse.
6
tCH + tCL = tCLK and must be greater than 480 ns.

tCALH tCT
CAL
(INPUT)

tCALB
BUSY
(OUTPUT)
tFCD
tCB
CLK*
(INPUT) 1 2 3

tCH 85530 85531 85532

tCL

tCLK
*SHADED PORTIONS OF INPUT SIGNALS ARE OPTIONAL. FOR BEST PERFORMANCE, WE
RECOMMEND THAT THESE SIGNALS BE HELD LOW EXCEPT WHEN EXPLICITY SHOWN HIGH.

Figure 1. Calibration Timing

tS tC
SAMPLE*
tSL
(INPUT) tS
tSB
BUSY
(OUTPUT)
tFCD tCB
tLCS
tCH
CLK*
1 2 tCL 3 15 16 17
(INPUT)
tCLK
tCSH
SCLK
(OUTPUT)
tSCL
tCD tDSH
SDATA BIT BIT BIT BIT BIT
OLD BIT 16 MSB
(OUTPUT) 2 13 14 15 16

*SHADED PORTIONS OF INPUT SIGNALS ARE OPTIONAL. FOR BEST PERFORMANCE, WE

RECOMMEND THAT THESE SIGNALS BE HELD LOW EXCEPT WHEN EXPLICITY SHOWN HIGH.

Figure 2. General Conversion Timing

–4– REV. A
 AD677
ORDERING GUIDE

Temperature Package
Model Range S/(N+D) Max INL Package Description Option*
AD677JN 0°C to +70°C 89 dB Typ Only Plastic 16-Pin DIP N-16
AD677KN 0°C to +70°C 90 dB ± 1.5 LSB Plastic 16-Pin DIP N-16
AD677JD 0°C to +70°C 89 dB Typ Only Ceramic 16-Pin DIP D-16
AD677KD 0°C to +70°C 90 dB ± 1.5 LSB Ceramic 16-Pin DIP D-16
AD677JR 0°C to +70°C 89 dB Typ Only Plastic 28-Lead SOIC R-28
AD677KR 0°C to +70°C 90 dB ± 1.5 LSB Plastic 28-Lead SOIC R-28
AD677AD –40°C to +85°C 89 dB Typ Only Ceramic 16-Pin DIP D-16
AD677BD –40°C to +85°C 90 dB ± 1.5 LSB Ceramic 16-Pin DIP D-16
*D = Ceramic DIP; N = Plastic DIP; R = Small Outline IC (SOIC).

ABSOLUTE MAXIMUM RATINGS*

VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +26.4 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Vcc to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V
VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V
Digiul Inputs to DGND . . . . . . . . . . . . . . . . . . . . . . 0 to +5.5 V
Analog Inputs, VREF to AGND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . (VCC +0.3 V) to (VEE –0.3 V)
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD677 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

REV. A –5–
AD677
PIN DESCRIPTION

DIP Pin SOIC Pin Type Name Description

1 1 SAMPLE DI VIN Acquisition Control Pin. Active HIGH. During conversion, SAMPLE
controls the suite of the internal sample-hold amplifier and the falling edge
initiates conversion. During calibration, SAMPLE should be held LOW. If
HIGH during calibration, diagnostic information will appear on SDATA.
2 2 CLK DI Master Clock Input. The AD677 requires 17 clock pulses to execute a
conversion. CLK is also used to derive SCLK.
3 3 SDATA DO Serial Output Data Controlled by SCLK.
4 6, 7 DGND P Digital Ground.
5 8 VCC P +12 V Analog Supply Voltage.
8 12 AGND P Analog Ground.
.9 15 AGND SENSE AI Analog Ground Sense.
10 16 VIN AI Analog Input Voltage.
11 17 VREF AI External Voltage Reference Input.
12 21 VEE P –12 V Analog Supply Voltage.
13 22, 23 VDD P +5 V Logic Supply Voltage.
14 26 SCLK DO Clock Output for Data Read, derived from CLK.
15 27 BUSY DO Status Line for Converter. Active HIGH, indicating a conversion or
calibration in progress.
16 28 CAL DI Calibration Control Pin.
6, 7 4, 5, 9, 10, 11, NC _ No Connection. No connections should be made to these pins.
13, 14, 18, 19,
20, 24, 25
Type: AI = Analog Input
DI = Digital Input
DO = Digital Output
P = Power

SAMPLE 1 16 CAL SAMPLE 1 28 CAL

15 BUSY CLK 2 27 BUSY

CLK 2
SDATA 3 26 SCLK
SDATA 3 14 SCLK
NC 4 25 NC
DGND 4 AD677 13 VDD
TOP VIEW NC 5 24 NC
VCC 5 12 VEE
(Not to Scale)
DGND1 6 23 VDD1
NC 6 11 VREF
DGND2 7 AD677 22 VDD2
NC 7 10 VIN TOP VIEW
VCC 8 21 VEE
(Not to Scale)
AGND 8 9 AGND
NC 9 20 NC
SENSE
NC = NO CONNECT NC 10 19 NC

DIP Pinout NC 11 18 NC

AGND 12 17 VREF

NC 13 16 VIN

NC 14 15 AGND
SENSE

NC = NO CONNECT

SOIC Pinout

–6– REV. A
 Definition of Specifications–AD677
NYQUIST FREQUENCY INTERMODULATION DISTORTION (IMD)
An implication of the Nyquist sampling theorem, the “Nyquist With inputs consisting of sine waves at two frequencies, fa and
frequency’’ of a converter is that input frequency which is one fb, any device with nonlinearities will create distortion products,
half the sampling frequency of the converter. of order (m+n), at sum and difference frequencies of mfa ± nfb,
where m, n = 0, 1, 2, 3 . . . . Intermodulation terms are those
TOTAL HARMONIC DISTORTION for which m or n is not equal to zero. For example, the second
Total harmonic distortion (THD) is the ratio of the rms sum of order terms are (fa + fb) and (fa – fb), and the third order terms
the harmonic components to the rms value of a full-scale input are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). The IMD
signal and is expressed in percent (%) or decibels (dB). For in- products are expressed as the decibel ratio of the rms sum of the
put signals or harmonics that are above the Nyquist frequency, measured input signals to the rms sum of the distortion terms.
the aliased components are used. The two signals applied to the converter are of equal amplitude,
and the peak value of their sum is –0.5 dB from full scale. The
SIGNAL-TO-NOISE PLUS DISTORTION RATIO IMD products are normalized to a 0 dB input signal.
Signal-to-noise plus distortion is defined to be the ratio of the
rms value of the measured input signal to the rms sum of all APERTURE DELAY
other spectral components below the Nyquist frequency, includ- Aperture delay is the time required after SAMPLE pin is taken
ing harmonics but excluding dc. LOW for the internal sample-hold of the AD677 to open, thus
holding the value of VIN.
+/– FULL-SCALE ERROR
The last + transition (from 011 . . . 10 to 011 . . . 11) should APERTURE JITTER
occur for an analog voltage 1.5 LSB below the nominal full Aperture jitter is the variation in the aperture delay from sample
scale (4.99977 volts for a ± 5 V range). The full-scale error is to sample.
the deviation of the actual level of the last transition from the
ideal level. POWER SUPPLY REJECTION
DC variations in the power supply voltage will affect the overall
BIPOLAR ZERO ERROR transfer function of the ADC, resulting in zero error and full-
Bipolar zero error is the difference between the ideal midscale scale error changes. Power supply rejection is the maximum
input voltage (0 V) and the actual voltage producing the mid- change in either the bipolar zero error or full-scale error value.
scale output code. Additionally, there is another power supply variation to con-
sider. AC ripple on the power supplies can couple noise into the
DIFFERENTIAL NONLINEARITY (DNL) ADC, resulting in degradation of dynamic performance. This is
In an ideal ADC, code transitions are one LSB apart. Differen- displayed in Figure 15.
tial nonlinearity is the maximum deviation from this ideal value.
It is often specified in terms of resolution for which no missing INPUT SETTLING TIME
codes are guaranteed. Settling time is a function of the SHA’s ability to track fast
slewing signals. This is specified as the maximum time required
INTEGRAL NONLINEARITY (INL) in track mode after a full-scale step input to guarantee rated
The ideal transfer function for an ADC is a straight line bisect- conversion accuracy.
ing the center of each code drawn between “zero” and “full
scale.” The point used as “zero” occurs 1/2 LSB before the NOISE/DC CODE UNCERTAINTY
most negative code transition. “Full scale” is defined as a level Ideally, a fixed dc input should result in the same output code
1.5 LSB beyond the most positive code transition. Integral non- for repetitive conversions. However, as a consequence of un-
linearity is the worst-case deviation of a code center average avoidable circuit noise within the wideband circuits in the ADC,
from the straight line. there is a range of output codes which may occur for a given in-
put voltage. If you apply a dc signal to the ADC and record a
BANDWIDTH large number of conversions, the result will be a distribution of
The full-power bandwidth is that input frequency at which the codes. If you fit a Gaussian probability distribution to the histo-
amplitude of the reconstructed fundamental is reduced by 3 dB gram, the standard deviation is approximately equivalent to the
for a full-scale input. rms input noise of the ADC.

REV. A –7–
AD677
FUNCTIONAL DESCRIPTION In most applications, it is sufficient to calibrate the AD677 only
The AD677 is a multipurpose 16-bit analog-to-digital converter upon power-up, in which case care should be taken that the
and includes circuitry which performs an input sample/hold power supplies and voltage reference have stabilized first. If
function, ground sense, and autocalibration. These functions calibration is not performed, the AD677 may come up in an un-
are segmented onto two monolithic chips—an analog signal pro- known state, or performance could degrade to as low as 10 bits.
cessor and a digital controller. Both chips are contained within
the AD677 package. CONVERSION CONTROL
The AD677 is controlled by two signals: SAMPLE and CLK,
The AD677 employs a successive-approximation technique to
as shown in Figure 2. It is assumed that the part has been cali-
determine the value of the analog input voltage. However, in-
brated and the digital I/O pins have the levels shown at the start
stead of the traditional laser-trimmed resistor-ladder approach,
of the timing diagram.
this device uses a capacitor-array, charge redistribution tech-
nique. Binary-weighted capacitors subdivide the input sample to A conversion consists of an input acquisition followed by 17
perform the actual analog-to-digital conversion. The capacitor clock pulses which execute the 16-bit internal successive ap-
array eliminates variation in the linearity of the device due to proximation routine. The analog input is acquired by taking the
temperature-induced mismatches of resistor values. Since a SAMPLE line HIGH for a minimum sampling time of tS. The
capacitor array is used to perform the data conversions, the actual sample taken is the voltage present on VIN one aperture
sample/hold function is included without the need for additional delay after the SAMPLE line is brought LOW, assuming the
external circuitry. previous conversion has completed (signified by BUSY going
LOW). Care should be taken to ensure that this negative edge is
Initial errors in capacitor matching are eliminated by an
well defined and jitter free in ac applications to reduce the un-
autocalibration circuit within the AD677. This circuit employs
certainty (noise) in signal acquisition. With SAMPLE going
an on-chip microcontroller and a calibration DAC to measure
LOW, the AD677 commits itself to the conversion—the input
and compensate capacitor mismatch errors. As each error is
at VIN is disconnected from the internal capacitor array, BUSY
determined, its value is stored in on-chip memory (RAM).
goes HIGH, and the SAMPLE input will be ignored until the
Subsequent conversions use these RAM values to improve con-
conversion is completed (when BUSY goes LOW). SAMPLE
version accuracy. The autocalibration routine may be invoked
must be held LOW for a minimum period of time tSL. A period
at any time. Autocalibration insures high performance while
of time tFCD after bringing SAMPLE LOW, the 17 CLK cycles
eliminating the need for any user adjustments and is described
are applied; CLK pulses that start before this period of time are
in detail below.
ignored. BUSY goes HIGH tSB after SAMPLE goes LOW, sig-
The microcontroller controls all of the various functions within nifying that a conversion is in process, and remains HIGH until
the AD677. These include the actual successive approximation the conversion is completed. As indicated in Figure 2, the twos
algorithm, the autocalibration routine, the sample/hold opera- complement output data is presented MSB first. This data may
tion, and the internal output data latch. be captured with the rising edge of SCLK or the falling edge of
CLK, beginning with pulse #2. The AD677 will ignore CLK
AUTO CALIBRATION after BUSY has gone LOW and SDATA or SCLK will not
The AD677 achieves rated performance without the need for change until a new sample is acquired.
user trims or adjustments. This is accomplished through the use
of on-chip autocalibration. CONTINUOUS CONVERSION
In the autocalibration sequence, sample/hold offset is nulled by For maximum throughput rate, the AD677 can be operated in a
internally connecting the input circuit to the ground sense cir- continuous convert mode. This is accomplished by utilizing the
cuit. The resulting offset voltage is measured and stored in fact that SAMPLE will no longer be ignored after BUSY goes
RAM for later use. Next, the capacitor representing the most LOW, so an acquisition may be initiated even during the HIGH
significant bit (MSB) is charged to the reference voltage. This time of the 17th CLK pulse for maximum throughput rate
charge is then transferred to a capacitor of equal size (composed while enabling full settling of the sample/hold circuitry. If
of the sum of the remaining lower weight bits). The voltage that SAMPLE is already HIGH during the rising edge of the 17th
results represents the amount of capacitor mismatch. A calibra- CLK, then an acquisition is immediately initiated approxi-
tion digital-to-analog converter (DAC) adds an appropriate mately 100 ns after the rising edge of the 17th clock pulse.
value of error correction voltage to cancel this mismatch. This Care must be taken to adhere to the minimum/maximum tim-
correction factor is also stored in RAM. This process is repeated ing requirements in order to preserve conversion accuracy.
for each of the eight remaining capacitors representing the top
nine bits. The accumulated values in RAM are then used during GENERAL CONVERSION GUIDELINES
subsequent conversions to adjust conversion results accordingly. During signal acquisition and conversion, care should be taken
As shown in Figure 1, when CAL is taken HIGH the AD677 with the logic inputs to avoid digital feedthrough noise. It is
internal circuitry is reset, the BUSY pin is driven HIGH, and possible to run CLK continuously, even during the sample
the ADC prepares for calibration. This is an asynchronous hard- period. However, CLK edges during the sampling period, and
ware reset and will interrupt any conversion or calibration cur- especially when SAMPLE goes LOW, may inject noise into the
rently in progress. Actual calibration begins when CAL is taken sampling process. The AD677 is tested with no CLK cycles
LOW and completes in 85,532 clock cycles, indicated by BUSY during the sampling period. The BUSY signal can be used to
going LOW. During calibration, it is preferable for SAMPLE to prevent the clock from running during acquisition, as illustrated
be held LOW. If SAMPLE is HIGH, diagnostic data will appear
on SDATA. This data is of no value to the user.

–8– REV. A
 AD677
in Figure 3. In this circuit BUSY is used to reset the circuitry Table I. Serial Output Coding Format (Twos Complement)
which divides the system clock down to provide the AD677
CLK. This serves to interrupt the clock until after the input sig- VIN Output Code
nal has been acquired, which has occurred when BUSY goes <Full Scale 011 . . . 11
HIGH. When the conversion is completed and BUSY goes Full Scale 011 . . . 11
LOW, the circuit in Figure 3 truncates the 17th CLK pulse Full Scale – 1 LSB 011 . . . 10
width which is tolerable because only its rising edge is critical. Midscale + 1 LSB 000 . . . 01
Midscale 000 . . . 00
11 3Q 2Q 7 Midscle – 1 LSB 111 . . . 11
4 1D 3D 12 –Full Scale + 1 LSB 100 . . . 01
12.288MHz –Full Scale 100 . . . 00
SYSTEM 9 CLK CLR 1 BUSY
<–Full Scale 100 . . . 00
CLOCK
1Q 2 CLK

2D 5 POWER SUPPLIES AND DECOUPLING

74HC175 AD677 The AD677 has three power supply input pins. VCC and VEE
provide the supply voltages to operate the analog portions of the
AD677 including the capacitor DAC, input buffers and com-
1 1CLK parator. VDD provides the supply voltage which operates the
2QC 9 SAMPLE digital portions of the AD677 including the data output buffers
13 2CLK
2QD 8 and the autocalibration controller.
6 1QD
As with most high performance linear circuits, changes in the
12 2CLR
power supplies can produce undesired changes in the perfor-
2 1CLR mance of the circuit. Optimally, well regulated power supplies
74HC393 with less than 1% ripple should be selected. The ac output im-
pedance of a power supply is a complex function of frequency,
and in general will increase with frequency. In other words, high
Figure 3.
frequency switching such as that encountered with digital cir-
Figure 3 also illustrates the use of a counter (74HC393) to de- cuitry requires fast transient currents which most power supplies
rive the AD677 SAMPLE command from the system clock cannot adequately provide. This results in voltage spikes on the
when a continuous convert mode is desirable. Pin 9 (2QC) pro- supplies. If these spikes exceed the ± 5% tolerance of the ± 12 V
vides a 96 kHz sample rate for the AD677 when used with a supplies or the ± 10% limits of the +5 V supply, ADC perfor-
12.288 MHz system clock. Alternately, Pin 8 (2QD) could be mance will degrade. Additionally, spikes at frequencies higher
used for a 48 kHz rate. than 100 kHz will also degrade performance. To compensate for
the finite ac output impedance of the supplies, it is necessary to
If a continuous clock is used, then the user must avoid CLK store “reserves” of charge in bypass capacitors. These capacitors
edges at the instant of disconnecting VIN which occurs at the
can effectively lower the ac impedance presented to the AD677
falling edge of SAMPLE (see tFCD specification). The duty cycle power inputs which in turn will significantly reduce the magni-
of CLK may vary, but both the HIGH (tCH) and LOW (tCL) tude of the voltage spikes. For bypassing to be effective, certain
phases must conform to those shown in the timing specifica-
guidelines should be followed. Decoupling capacitors, typically
tions. The internal comparator makes its decisions on the rising 0.1 µF, should be placed as closely as possible to each power
edge of CLK. To avoid a negative edge transition disturbing the supply pin of the AD677. It is essential that these capacitors be
comparator’s settling, tCL should be at least half the value of
placed physically close to the IC to minimize the inductance of
tCLK. It is not recommended that the SAMPLE pin change state the PCB trace between the capacitor and the supply pin. The
toward the end of a CLK cycle, in order to avoid transitions dis- logic supply (VDD) should be decoupled to digital common and
turbing the internal comparator’s settling.
the analog supplies (VCC and VEE) to analog common. The ref-
During a conversion, internal dc error terms such as comparator erence input is also considered as a power supply pin in this re-
voltage offset are sampled, stored on internal capacitors and gard and the same decoupling procedures apply. These points
used to correct for their corresponding errors when needed. Be- are displayed in Figure 4.
cause these voltages are stored on capacitors, they are subject to
leakage decay and so require refreshing. For this reason there is
a maximum conversion time tC (1000 µs). From the time +5V VDD AD677
SAMPLE goes HIGH to the completion of the 17th CLK pulse, DGND AGND VCC VEE VREF
no more than 1000 µs should elapse for specified performance.
0.1µF
However, there is no restriction to the maximum time between
0.1µF
individual conversions. 0.1µF

Output coding for the AD677 is twos complement as shown in 0.1µF

Table I. The AD677 is designed to limit output coding in the SYSTEM SYSTEM
event of out-of-range input. DIGITAL ANALOG +12V –12V
COMMON COMMON

Figure 4. Grounding and Decoupling the AD677

REV. A –9–
AD677
Additionally, it is beneficial to have large capacitors (>47 µF)
AD677
located at the point where the power connects to the PCB with
10 µF capacitors located in the vicinity of the ADC to further SOURCE
VIN

reduce low frequency ripple. In systems that will be subjected to VS

particularly harsh environmental noise, additional decoupling
∆V AGND
may be necessary. RC-filtering on each power supply combined
with dedicated voltage regulation can substantially decrease TO POWER
power supply ripple effects (this is further detailed in Figure 7). GROUND LEAD
SUPPLY GND
IGROUND > 0

BOARD LAYOUT Figure 5a. Input to the A/D is Corrupted by IR Drop in

Designing with high resolution data converters requires careful Ground Leads: VIN = VS + ∆V.
attention to board layout. Trace impedance is a significant issue.
A 1.22 mA current through a 0.5 Ω trace will develop a voltage SHIELDED CABLE AD677
drop of 0.6 mV, which is 4 LSBs at the 16-bit level for a 10 V VIN
full-scale span. In addition to ground drops, inductive and capaci- SOURCE
VS AGND
tive coupling need to be considered, especially when high accu- SENSE
racy analog signals share the same board with digital signals.
AGND
Analog and digital signals should not share a common return
path. Each signal should have an appropriate analog or digital TO POWER
SUPPLY GND
return routed close to it. Using this approach, signal loops en- GROUND LEAD I GROUND > 0
close a small area, minimizing the inductive coupling of noise.
Figure 5b. AGND SENSE Eliminates the Problem in
Wide PC tracks, large gauge wire, and ground planes are highly
Figure 5a.
recommended to provide low impedance signal paths. Separate
analog and digital ground planes are also desirable, with a single
shielded in a noisy environment to avoid capacitive coupling. If
interconnection point at the AD677 to minimize interference
inductive (magnetic) coupling is expected to be dominant such
between analog and digital circuitry. Analog signals should be
as where motors are present, twisted-pair wires should be used
routed as far as possible from digital signals and should cross
instead.
them, if at all, only at right angles. A solid analog ground plane
around the AD677 will isolate it from large switching ground The digital ground pin is the reference point for all of the digital
currents. For these reasons, the use of wire wrap circuit con- signals that operate the AD677. This pin should be connected
struction will not provide adequate performance; careful printed to the digital common point in the system. As Figure 4 illus-
circuit board construction is preferred. trated, the analog and digital grounds should be connected
together at one point in the system, preferably at the AD677.
GROUNDING
The AD677 has three grounding pins, designated ANALOG VOLTAGE REFERENCE
GROUND (AGND), DIGITAL GROUND (DGND) and The AD677 requires the use of an external voltage reference.
ANALOG GROUND SENSE (AGND SENSE). The analog The input voltage range is determined by the value of the refer-
ground pin is the “high quality” ground reference point for the ence voltage; in general, a reference voltage of n volts allows an
device, and should be connected to the analog common point in input range of ± n volts. The AD677 is specified for a voltage
the system. reference between +5 V and +10 V. A 10 V reference will typi-
cally require support circuitry operated from ± 15 V supplies; a
AGND SENSE is intended to be connected to the input signal
5.0 V reference may be used with ± 12 V supplies. Signal-to-
ground reference point. This allows for slight differences in level
noise performance is increased proportionately with input signal
between the analog ground point in the system and the input
range (see Figure 12). In the presence of a fixed amount of sys-
signal ground point. However no more than 100 mV is recom-
tem noise, increasing the LSB size (which results from increas-
mended between the AGND and the AGND SENSE pins for
ing the reference voltage) will increase the effective S/(N+D)
specified performance.
performance. Figure 11 illustrates S/(N+D) as a function of ref-
Using AGND SENSE to remotely sense the ground potential of erence voltage. In contrast, dc accuracy will be optimal at lower
the signal source can be useful if the signal has to be carried reference voltage values (such as 5 V) due to capacitor nonlin-
some distance to the A/D converter. Since all IC ground cur- earity at higher voltage values.
rents have to return to the power supply and no ground leads
During a conversion, the switched capacitor array of the AD677
are free from resistance and inductance, there are always some
presents a dynamically changing current load at the voltage ref-
voltage differences from one ground point in a system to another.
erence as the successive-approximation algorithm cycles through
Over distance this voltage difference can easily amount to sev- various choices of capacitor weighting. (See the following sec-
eral LSBs (in a 10 V input span, 16-bit system each LSB is tion “Analog Input” for a detailed discussion of the VREF input
about 0.15 mV). This would directly corrupt the A/D input sig- characteristics.) The output impedance of the reference circuitry
nal if the A/D measures its input with respect to power ground must be low so that the output voltage will remain sufficiently
(AGND) as shown in Figure 5a. To solve this problem the constant as the current drive changes. In some applications, this
AD677 offers an AGND SENSE pin. Figure 5b shows how the may require that the output of the voltage reference be buffered
AGND SENSE can be used to eliminate the problem in Figure by an amplifier with low impedance at relatively high frequen-
5a. Figure 5b also shows how the signal wires should be cies. In choosing a voltage reference, consideration should be

–10– REV. A
 AD677
made for selecting one with low noise. A capacitor connected regulator prevents very large voltage spikes from entering the
between REF IN and AGND will reduce the demands on the regulators. Any power line noise which the regulators cannot
reference by decreasing the magnitude of high frequency com- eliminate will be further filtered by an RC filter (10 Ω/10 µF)
ponents required to be sourced by the reference. having a –3 dB point at 1.6 kHz. For best results the regulators
Figures 6 and 7 represent typical design approaches. should be within a few centimeters of the AD677.

+12V ANALOG INPUT

As previously discussed, the analog input voltage range for the
2 AD677 is ± VREF. For purposes of ground drop and common
VIN mode rejection, the VIN and VREF inputs each have their own
ground. VREF is referred to the local analog system ground
8 6 VREF (AGND), and VIN is referred to the analog ground sense pin
CN
1.0µF AD586 (AGND SENSE) which allows a remote ground sense for the
10µF 0.1µF AD677 input signal.
4
AGND The AD677 analog inputs (VIN, VREF and AGND SENSE) ex-
hibit dynamic characteristics. When a conversion cycle begins,
each analog input is connected to an internal, discharged 50 pF
Figure 6.
capacitor which then charges to the voltage present at the corre-
Figure 6 shows a voltage reference circuit featuring the 5 V out- sponding pin. The capacitor is disconnected when SAMPLE is
put AD586. The AD586 is a low cost reference which utilizes a taken LOW, and the stored charge is used in the subsequent
buried Zener architecture to provide low noise and drift. Over conversion. In order to limit the demands placed on the external
the 0°C to +70°C range, the AD586M grade exhibits less than source by this high initial charging current, an internal buffer
1.0 mV output change from its initial value at +25°C. A noise amplifier is employed between the input and this capacitance for
reduction capacitor, CN, reduces the broadband noise of the a few hundred nanoseconds. During this time the input pin ex-
AD586 output, thereby optimizing the overall performance of hibits typically 20 kΩ input resistance, 10 pF input capacitance
the AD677. It is recommended that a 10 µF to 47 µF high qual- and ± 40 µA bias current. Next, the input is switched directly to
ity tantalum capacitor and a 0.1 µF capacitor be tied between the now precharged capacitor and allowed to fully settle. During
the VREF input of the AD677 and ground to minimize the im- this time the input sees only a 50 pF capacitor. Once the sample
pedance on the reference. is taken, the input is internally floated so that the external input
Using the AD677 with ± 10 V input range (VREF = 10 V) typi- source sees a very high input resistance and a parasitic input
cally requires ± 15 V supplies to drive op amps and the voltage capacitance of typically only 2 pF. As a result, the only domi-
reference. If ± 12 V is not available in the system, regulators nant input characteristic which must be considered is the high
such as 78L12 and 79L12 can be used to provide power for the current steps which occur when the internal buffers are switched
AD677. This is also the recommended approach (for any input in and out.
range) when the ADC system is subjected to harsh environ- In most cases, these characteristics require the use of an external
ments such as where the power supplies are noisy and where op amp to drive the input of the AD677. Care should be taken
voltage spikes are present. Figure 7 shows an example of such a with op amp selection; even with modest loading conditions,
system based upon the 10 V AD587 reference, which provides a most available op amps do not meet the low distortion require-
300 µV LSB. Circuitry for additional protection against power ments necessary to match the performance capabilities of the
supply disturbances has been shown. A 100 µF capacitor at each AD677. Figure 8 represents a circuit, based upon the AD845,
which will provide excellent overall performance.
10Ω
AD587 For applications optimized more for low distortion and low
2 VIN VO 6 noise, the AD845 of Figure 8 may be replaced by the AD743.
10µF
0.1µF GND NR 8
4 1k Ω
1µF

±5V +12V 0.1µF

10Ω
+15V 78L12 INPUT 1k Ω AD677
2 7
100µF 0.01µF 10µF 0.1µF
499 Ω AD845 6 VIN
10Ω VCC
VREF 3
+5V VDD 4 0.1µF
10µF 0.1µF
100µF 0.1µF AD677 AGND

VEE VIN –12V

10Ω
AGND
–15V 79L12
SENSE
100µF 0.01µF 10µF 0.1µF

VIN Figure 8.
Figure 7.

REV. A –11–
AD677
AC PERFORMANCE FS is the sampling frequency, and Fa is the signal bandwidth of
AC parameters, which include S/(N+D), THD, etc., reflect the interest. For audio bandwidth applications, the AD677 is ca-
AD677’s effect on the spectral content of the analog input sig- pable of operating at a 2 × oversample rate (96 kSPS), which
nal. Figures 11 through 18 provide information on the AD677’s typically produces an improvement in S/(N+D) of 3 dB com-
ac performance under a variety of conditions. pared with operating at the Nyquist conversion rate of 48 kSPS.
Oversampling has another advantage as well; the demands on
A perfect n-bit ADC with no errors will yield a theoretical quan-
the antialias filter are lessened. In summary, system perfor-
tization noise of q/√12, where q is the weight of the LSB. This
mance is optimized by running the AD677 at or near its maxi-
relationship leads to the well-known equation for theoretical
mum sampling rate of 100 kHz and digitally filtering the
full-scale rms sine wave signal-to-noise plus distortion level of
resulting spectrum to eliminate undesired frequencies.
S/(N + D) = 6.02 n + 1.76 dB, here n is the bit resolution. An
actual ADC, however, will yield a measured S/(N + D) less than
DC PERFORMANCE
the theoretical value. Solving this equation for n using the mea-
The self-calibration scheme used in the AD677 compensates for
sured S/(N + D) value yields the equation for effective number
bit weight errors that may exist in the capacitor array. This mis-
of bits (ENOB):
[S / ( N + D )]
match in capacitor values is adjusted (using the calibration coef-
ACTUAL – 1.76 dB ficients) during conversion and provides for excellent dc
ENOB = linearity performance. Figure 19 illustrates the DNL plot of a
6.02
typical AD677 at +25°C. A histogram test is a statistical method
As a general rule, averaging the results from several conversions for deriving an A/D converter’s differential nonlinearity. A ramp
reduces the effects of noise, and therefore improves such param- input is sampled by the ADC and a large number of conversions
eters as S/(N+D). AD677 performance may be optimized by are taken and stored. Theoretically the codes would all be the
operating the device at its maximum sample rate of 100 kSPS same size and, therefore, have an equal number of occurrences.
and digitally filtering the resulting bit stream to the desired sig- A code with an average number of occurrences would have a
nal bandwidth. This succeeds in distributing noise over a wider DNL of “0”. A code with more or less than average will have a
frequency range, thus reducing the noise density in the fre- DNL of greater than or less than zero LSB. A DNL of –1 LSB
quency band of interest. This subject is discussed in the follow- indicates missing code (zero occurrences).
ing section.
Figure 20 illustrates the code width distribution of the DNL
OVERSAMPLING AND NOISE FILTERING plots of Figure 19.
The Nyquist rate for a converter is defined as one-half its sam-
pling rate. This is established by the Nyquist theorem, which DC CODE UNCERTAINTY
requires that a signal be sampled at a rate corresponding to at Ideally, a fixed dc input should result in the same output code
least twice its highest frequency component of interest in order for repetitive conversions. However, as a consequence of un-
to preserve the informational content. Oversampling is a conver- avoidable circuit noise within the wideband circuits in the ADC,
sion technique in which the sampling frequency is more than there is range of output codes which may occur for a given input
twice the frequency bandwidth of interest. In audio applications, voltage. If you apply a dc signal to the AD677 and record
the AD677 can operate at a 2 × FS oversampling rate, where 10,000 conversions, the result will be a distribution of codes as
FS = 48 kHz. shown in Figure 9 (using a 10 V reference). If you fit a Gaussian
probability distribution to the histogram, the standard deviation

AAA
In quantized systems, the informational content of the analog is approximately equivalent to the rms input noise of ADC.
input is represented in the frequency spectrum from dc to the

AAA
Nyquist rate of the converter. Within this same spectrum are
8000
higher frequency noise and signal components. Antialias, or low
pass, filters are used at the input to the ADC to reduce these

AAA
7000 7649
noise and signal components so that their aliased components
do not corrupt the baseband spectrum. However, wideband 6000

AAA
NUMBER OF CODE HITS

noise contributed by the AD677 will not be reduced by the

antialias filter. The AD677 quantization noise is evenly distrib- 5000

AAA
uted from dc to the Nyquist rate, and this fact can be used to
4000
minimize its overall affect.

AAAAAA
The AD677 quantization noise effects can be reduced by over- 3000
sampling—sampling at a rate higher than that defined by the

AAAAAAAAAAAA
2000
Nyquist theorem. This spreads the noise energy over a band-
width wider than the frequency band of interest. By judicious
1000 1267
selection of a digital decimation filter, noise frequencies outside 3
1081
the bandwidth of interest may be eliminated. 0
–2 –1 0 1
The process of analog to digital conversion inherently produces
DEVIATION FROM CORRECT CODE – LSBs
noise, known as quantization noise. The magnitude of this noise
is a function of the resolution of the converter, and manifests it- Figure 9. Distribution of Codes from 10,000 Conversions
self as a limit to the theoretical signal-to-noise ratio achievable. Relative to the Correct Code
This limit is described by S/(N + D) = (6.02n + 1.76 + 10 log
FS/2FA) dB, where n is the resolution of the converter in bits,

–12– REV. A
 AD677
The standard deviation of this distribution is approximately 105
0.5 LSBs. If less uncertainty is desired, averaging multiple con- 100
versions will narrow this distribution by the inverse of the square 90
root of the number of samples; i.e., the average of 4 conversions
would have a standard deviation of 0.25 LSBs. 80

70 THD
DSP INTERFACE

dB
60
Figure 10 illustrates the use of the Analog Devices ADSP-2101
50 S/(N+D)
digital signal processor with the AD677. The ADSP-2101 FO
(flag out) pin of Serial Port 1 (SPORT 1) is connected to the 40
SAMPLE line and is used to control acquisition of data. The 30
ADSP-2101 timer is used to provide precise timing of the FO
20
pin.
10
–80 –70 –60 –50 –40 –30 –20 –10 0
ADSP-2101 AD677 INPUT LEVEL – dB
FO SAMPLE
Figure 12. S/(N+D) and THD vs. Input Amplitude,
SCLK0 CLK
fS = 100 kHz
DR0 SDATA
SERIAL RFS0 BUSY 0
PORT 0
DT0
–20

AMPLITUDE – dB
TFS0
–40
–60
Figure 10. ADSP-2101 Interface –80
–100
The SCLK pin of the ADSP-2101 SPORT0 provides the CLK
–120
input for the AD677. The clock should be programmed to be
–140
approximately 2 MHz to comply with AD677 specifications. To 0 5 10 15 20 25 30 35 40 45 50
minimize digital feedthrough, the clock should be disabled (by FREQUENCY – kHz
setting Bit 14 in SPORT0 control register to 0) during data ac- Figure 13. 4096 Point FFT at 100 kSPS, fIN = 1 kHz,
quisition. Since the clock floats when disabled, a pulldown resis- VREF = 5 V
tor of 12 kΩ–15 kΩ should be connected to SCLK to ensure it
will be LOW at the falling edge of SAMPLE. To maximize the 0
conversion rate, the serial clock should be enabled immediately –20
after SAMPLE is brought LOW (hold mode).
AMPLITUDE – dB

–40
The AD677 BUSY signal is connected to RF0 to notify –60
SPORT0 when a new data word is coming. SPORT0 should be –80
configured in normal, external, noninverting framing mode and –100
can be programmed to generate an interrupt after the last data –120
bit is received. To maximize the conversion rate, SAMPLE –140
should be brought HIGH immediately after the last data bit is 0 5 10 15 20 25 30 35 40 45 48
FREQUENCY – kHz
received.
Figure 14. 4096 Point FFT at 100 kSPS, fIN = 1 kHz,

AA
106 VREF = 10 V

102
THD

AA
98

AA
dB

94

S/(N+D)
90

86

82
2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.0
VREF – Volts

Figure 11. S/(N+D) and THD vs. VREF, fS = 100 kHz (Calibra-
tion is not guaranteed below +5 VREF)

REV. A –13–
AD677
106
+5V THD, 5V
90 104

102 THD, 10V

80
+12V 100
70
–12V 98
S/(N+D) – dB

60 96

dB
S/(N+D), 10V
94
50
92
40
90 S/(N+D), 5V
30
88

20 86
0 100 1k 10k 100k 1M –40 –20 0 20 40 60 80
RIPPLE FREQUENCY – Hz TEMPERATURE – Degree °C

Figure 15. AC Power Supply Rejection (fIN = 1.06 kHz) Figure 18. AC Performance Using Minimum Clock Period
fSAMPLE = 96 kSPS, VRIPPLE = 0.13 V p-p vs. Temperature (tCLK = 480 ns), 5 V and 10 V Reference

0 1.0
0.8
–30 0.6
AMPLITUDE – dB
AMPLITUDE – dB

0.4
–50
0.2
–70 0.0
–90 –0.2
–0.4
–110
–0.6
–130 –0.8
–150 –1.0
0 5 10 15 20 25 30 35 40 45 48 0 5 10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY – kHz FREQUENCY – kHz

Figure 16. IMD Plot for fIN = 1008 Hz (fa), 1055 Hz (fb) at Figure 19. DNL Plot at VREF = 10 V, TA = +25°C, fS =
96 kSPS 100 kSPS

AA
AA
106 32000
30671
THD, 5V
NUMBER OF CODES WITH EACH DNL

104 26000

AA
102
22000

AAA
AA AA
100
18000
98

AAAAA
14645 14113
dB

96 THD, 10V 14000

A AA
AA
94 S/(N+D), 10V 12000
92

AAAA A
AAAA
AAAAAA
8000
90 2993
S/(N+D), 5V
4000

AAAAAAAAAAAAAAA
88 2500

2 152 392 60 6
86 0
450 470 490 510 530 550 570 590 –.35 –.25 –.15 –.05 0 .05 .15 .25 .35 .40
CLK PERIOD – ns DNL – LSBs

Figure 17. AC Performance vs. Clock Period, TA = +85°C Figure 20. DNL Error Distribution (Taken from Figure 19)
(5 V and 10 V Reference)

–14– REV. A
 AD677
OUTLINE DIMENSIONS
Dimensions shown in inchcs and (mm)

D-16
16-Lead Side Brazed Ceramic DIP Package

0.005 (0.13) MIN 0.080 (2.03) MAX

16 9

0.310 (7.87)
PIN 1
0.220 (5.59)

1 8

0.840 (21.34) MAX 0.060 (1.52)

0.015 (0.38)
0.200
(5.08)
MAX
0.150
0.015 (0.38)
0.200 (5.08) (3.81)
0.008 (0.20)
0.125 (3.18) MIN

0.320 (8.13)
SEATING 0.023 (0.58) 0.110 (2.79) 0.070 (1.78) 0.290 (7.37)
PLANE 0.014 (0.36) 0.090 (2.29) 0.030 (0.76)

N-16
16-Lead Plastic DIP

16 9
0.280 (7.11)
PIN 1 0.240 (6.10)
1 8

0.840 (21.33) 0.325 (8.25)

0.745 (18.93) 0.060 (1.52) 0.300 (7.62)
0.210 0.015 (0.38) 0.195 (4.95)
(5.33) 0.115 (2.93)
MAX
0.150
0.200 (5.05) (3.81) 0.015 (0.381)
MIN 0.008 (0.204)
0.125 (3.18)

0.022 (0.558) 0.100 (2.54) 0.070 (1.77) SEATING

0.014 (0.356) BSC 0.045 (1.15) PLANE

R-28
28-Lead Wide Body SOIC (SOIC-28)

0.7125 (18.10)
0.6969 (17.70)

28 15
0.2992 (7.60)
0.2914 (7.40)
PIN 1
0.4193 (10.65)
0.3937 (10.00)
1 14

0.0500 (1.27) 0.1043 (2.65)

0.0291 (0.74)
BSC 0.0926 (2.35) X 45°
0.0098 (0.25)
0°- 8°

0.0192 (0.49) 0.0500 (1.27)

0.0118 (0.30) 0.0125 (0.32)
0.0138 (0.35) 0.0157 (0.40)
0.0040 (0.10) 0.0091 (0.23)

REV. A –15–
–16–
PRINTED IN U.S.A. C1786–18–4/93