Vlsi Vsat Program: Coreel University Program Team
Vlsi Vsat Program: Coreel University Program Team
Contents
Introduction : Need for Hardware Description Languages Modeling of combinational logic circuits Modeling of sequential logic circuits Simple Test Bench & Functional Simulation
2 of X
Confidential
Specifications
Graphical Simulation Synthesizer
PAR
Physical Verification Physical Verification
Post-PAR Verification
Simulation
3 of X
4 of X
VERILOG HDL
Basic Unit A module Module Describes the functionality of the design States the input and output ports Example: A Computer Functionality: Perform user defined computations I/O Ports: Keyboard, Mouse, Monitor, Printer
5 of X
Example module HalfAdder (A, B, Sum Carry); input A, B; output Sum, Carry; assign Sum = A ^ B; //^ denotes XOR assign Carry = A & B; // & denotes AND endmodule
6 of X
Conventions Comments
// Single line comment /* Another single line comment */ /* Begins multi-line (block) comment All text within is ignored Line below ends multi-line comment */
Number
decimal, hex, octal, binary unsized decimal form size base form include underlines, +,-
String
" Enclose between quotes on a single line"
7 of X
Conventions (cont.)
Identifier
A ... Z a ... z 0 ... 9 Underscore
Strings are limited to 1024 chars First char of identifier must not be a digit Keywords Operators Verilog is case sensitive
8 of X
Description Styles
Structural: Logic is described in terms of Verilog gate primitives Example: not n1(sel_n, sel); and a1(sel_b, b, sel_b); and a2(sel_a, a, sel); or o1(out, sel_b, sel_a);
b sel
n1 sel_n a1 sel_b
a
a2 sel_a
o1
out
9 of X
Description Styles
Dataflow: Specify output signals in terms of input signals Example: assign out = (sel & a) | (~sel & b);
b
sel_b sel_n
sel
out
sel_a
10 of X
10
Description Styles
Behavioral: Algorithmically specify the behavior of the design
Example: if (select == 0) begin out = b; end else if (select == 1) begin out = a; end
a b
Black Box
2x1 MUX
out
sel
11 of X
11
12 of X
12
Dataflow Modeling
Uses continuous assignment statement
Format: assign [ delay ] net = expression; Example: assign sum = a ^ b;
Delay: Time duration between assignment from RHS to LHS All continuous assignment statements execute concurrently Order of the statement does not impact the design
13 of X
13
Timescale
`timescale 1ns/100ps
1 Time unit = 1 ns Time precision is 100ps (0.1 ns) 10.512ns is interpreted as 10.5ns
14 of X 14
15 of X
15
Dataflow Modeling
16 of X
16
Behavioral Modeling
Example:
module mux_2x1(a, b, sel, out); input a, a, sel; output out; always @(a or b or sel) begin if (sel == 1) out = a; else out = b; end endmodule
Sensitivity List
17 of X
17
Behavioral Modeling (cont.) always statement : Sequential Block Sequential Block: All statements within the block are executed sequentially When is it executed?
Occurrence of an event in the sensitivity list Event: Change in the logical value
18 of X
18
Inter-Assignment Delay
Example:
Intra-Assignment Delay
Example:
19 of X
19
Procedural Constructs
initial Statement : Executes only once always Statement : Executes in a loop Example:
initial begin Sum = 0; Carry = 0; end always @(A or B) begin Sum = A ^ B; Carry = A & B; end
20 of X
20
Event Control
Event Control Edge Triggered Event Control Level Triggered Event Control Edge Triggered Event Control @ (posedge CLK) //Positive Edge of CLK Curr_State = Next_state;
Loop Statements
Loop Statements Repeat While For Repeat Loop Example:
repeat (Count) sum = sum + 5;
If condition is a x or z it is treated as 0
22 of X
22
If condition is a x or z it is treated as 0
For Loop
Example:
for (Count = 0; Count < 10; Count = Count + 1) begin sum = sum + 5; end
23 of X
23
Conditional Statements
if Statement Format:
if (condition) procedural_statement else if (condition) procedural_statement else
procedural_statement Example:
if (Clk) Q = 0; else Q = D;
24 of X
24
Example 2: case (3b101 << 2) 3b100: A = B + C; 4b0100: A = B C; 5b10100: A = B / C; //This statement is executed endcase
25 of X
25
casez z is considered as a dont care casex both x and z are considered as dont cares Example: casez (X) 2b1z: A = B + C; 2b11: A = B / C; endcase
26 of X
26
Data Types Net Types: Physical Connection between structural elements Register Type: Represents an abstract storage element. Default Values
Net Types : z Register Type : x
Net Types: wire, tri, wor, trior, wand, triand, supply0, supply1 Register Types : reg, integer, time, real, realtime
27 of X
27
Data Types
28 of X
28
Behavioral Modeling
Can use only reg data type (within initial and always constructs) Cannot use wire data type
29 of X
29
30 of X
Confidential
31 of X
Confidential
// "Constant Pattern" // Start Time = 0 ns, End Time = 1 us, Period = 0 ns initial begin dir = 1'b0 ; #0 dir = 1'b1 ; # 500 dir = 1'b0 ; # 500 ; // dumped values till 1 us end initial #2000 $stop; endmodule
32 of X
Confidential
Exercise Design a Mux 8:1 using Verilog according to the following structure and verify the functionality using suitable test bench
33 of X
Appendix
34 of X
Confidential
Memories
An array of registers
reg [ msb : lsb ] memory1 [ upper : lower ];
Example
reg [ 0 : 3 ] mem [ 0 : 63 ]; // An array of 64 4-bit registers reg mem [ 0 : 4 ]; // An array of 5 1-bit registers
35 of X
35
Compiler Directives
37 of X
37
System Tasks
Display tasks
$display : Displays the entire list at the time when statement is encountered $monitor : Whenever there is a change in any argument, displays the entire list at end of time step
Time
$time: gives the simulation
38 of X
38
Connection by Position
parent_mod
39 of X
39
Connection by Name
parent_mod
40 of X
40
If an input port of an instantiated module is empty, the port is set to a value of z (high impedance).
module child_mod(In1, In2, Out1, Out2) input In1; input In2; output Out1; output Out2; //behavior relating In1 and In2 to Out1 endmodule module parent_mod(.) child_mod mod(A, ,Y1, Y2); //Empty Input endmodule
If an output port of an instantiated module is left empty, the port is considered to be unused.
module parent_mod(.) child_mod mod(A, B, Y1, ); //Empty Output endmodule
41 of X 41
Test Bench
`timescale 1ns/100ps module Top; reg PA, PB; wire PSum, PCarry; HalfAdder G1(PA, PB, PSum, PCarry); initial begin: LABEL reg [2:0] i; for (i=0; i<4; i=i+1) begin {PA, PB} = i; #5 $display (PA=%b PB=%b PSum=%b PCarry=%b, PA, PB, PSum, PCarry); end // for end // initial endmodule
Test Bench
Apply Inputs
Design Module
Observe Outputs
42 of X
42
43 of X
43
Caution:
Initial value of Clock (wire data type) = z ~z = x and ~x = x
44 of X
44
Caution: Clock is of data type wire, cannot be used in an initial statement Solution:
reg Clock; initial begin Clock = 0; end always begin #10 Clock = ~ Clock; end
45 of X
45
46 of X
Confidential