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7 [B.Tech]
SIXTH SEMESTER
Microprocessors & Micro Controllers
(ETEE-310)
PRRRQe
AKASH BOOKS
NEW DELHI
FIRST TERM EXAMINATION [FEB. 2016]
SIXTH SEMESTER [B.TECH]
MICROPROCESSOR AND |
MICROCONTROLLER [ETEE-310]
Time : 1% hrs. | M.M. : 30
Note: Attempt Q. No. 1 which is compulsory and any two more questions from remaining.
Q.1. Attempt any five.
HLT BS |
Q.1. (c) How much time is taken by the microprocesser 8085 to execut
conditional CALL. Instruction of 8085 microprocessor if condition i is not true?
Assume Microprocessor is running at 2MHZ? \
Ans. CALL instruction— '9/ 18 T states
- If condition is not true 9 T states is used earaten. 18 will be used ©
Given frequency=2MHZ |
Q.1. (d) State the function of TEST and LOCK signals of the mane
Seen
microprocessor.
Ans.1 (d) Refer Q.9. (c) of End Term Exam 2016.(Page No. 48- 2016)
Q.1 1. (e) Explain the LOOP instruction of microporcessor 8086 with suitable
examples.
jump~
SS
es0 ter ; Micr; oprocessor and Microcontroller
Sixth Sem
9-2016
! [.P. University\(B.Tech)-AB Publisher 2016-3
else Q.2.(c) Write and explain a software delay routine for 8085.
~ (4)
no jump, continue Ans. To know how many T-States an instruction requires, and keeping in mind
that
a T-State is one clock cycle long, we can calculate the time using the followin
Example: g formula:
Delay = No. of T-States / Frequency
include ‘omu8086.ine’
Example: If the speed of your microprocessor is 2 MHz then for a “MVI’” instruction
#make_COM# uses 7 T-States. Therefore the instruction would require 3.5 u Seconds to complete.
ORG 100h Now we can use a loop to produce a certain amount of time delay in a program.
MOV CX, 5 See an example of a delay loop: .
labell: MVIC, FFH 7 T-States
PRINTN ‘loop!’ | a
LOOP: DCRC 4 T-States
LOOP labell a |
| JNZ LOOP ' 10 T-States
RET
gi cal an d Ph ys ic al .a dd re ss es ? I low th e phys ic al addresses. Here see the first instruction initializes the loop counter and is executed only once
Q.1. (f What are Lo a ‘requiring only 7 T-States.
are generated? BX , SI or DI. It ts ceed
d in the 16 bi t IP, BP , SP ,
Ans. Logical address is containe
The following two instructions which is inside a loop that requires 14 T-States to
a execute and is repeated 255 times until C becomes 0.
known as the offset address or the effective address.
The base segment address is contained in one of the 16 bit contents of the| segment | We need to keep in mind though that in the last rotation of the loop, the JINZ
| | | s a instruction will not jump to the address and so it requires only 7 T-States rather than
registers CS, DS, ES, SS.
the 10. | :
The physical address or the real address is formed by combining the offset and
base segment addresses. This address is 20 bit and is primarily used for the accessing of ¢ Therefore, we must deduct 3 T-States from the total delay to get an accurate
ae delay calculation. | :
the memory.
~~ uy
94h ; Si
with i -
i, {Ore
© es
Num1 db 05h
Short ,jump range(— 127 <d <4 ~ ars | ) | 2
128) Word1 dw 1234h
Long jump range(-32767<4<439768)
As
2016 Sixth Semester, Microprocessor and Microcontro}}
er
Char db ‘X;
statement.
i c e s D B 5 D U P ( ? ) : A n a rray of 5 bytes I.P. University-(B.Tech)-AB Publisher
Pr 2016-5
ss.
which is an odd addre ae
ter to 0(00AH ie IORC, IOWC are I/O read command and I/O write command signals respectively
EVEN: increment location coun .
ae
en Address These signals enable an IO interface to read or write the data from
gee
or to the addressed
MyData DW 50 DUP(0): Array of 50 words will gt : port. The MRDC,
; ar MWTC are memory read command and memory write command
{ro Man e
r
DS-segment ENDS: r ven addregg signals respectively and may be used as memory read and write signals. All thes
a
e
DB Defined Byte: DB declares a va command signals instruct the memory to accept or send data from or to the bus. For
riable of type byt. . 7
memor y for, the variable of type byte. both of these write command signals, the advanced signals namely AIOWC and AMWTC
Te ee end Teserves ono locationtion init
Exam le: num1 DB 15h, Char] db \ in ) y
are available. They also serve the same purpose, but-are activated one clock cycle
5i earlier than the IOWC and MWTC signals, respectively.
numbers db 100 dup(0); Reserve 7 i | ae.
ei :
an array of 50 words of memory eS :
bytes with 00. Q:3. (c) Design a microprocesser 8086 system having two 4K x 8 EPROM
Aer andi and four 8K x 8 RAM. Avoid any foldback address. : (4)
Array is named as numbers.
Ans. A system requires 16kb EPROM and 16kb RAM. Also
DUP stands for duplicate 2 numbers of 8255, one number of 8279, one number of 8251 and one number of 8254.
the system has
° The I/O devices in the system should be mapped by standard I/O mapping. Hence
diagrams. The address/data
and address) separate decoders can be used to generate chip select signals for memory IC and
minimum mode. The only difference lies in mode. ALE is asserted in T1, just like peripheral IC’s. |
the status signals used and the cvanaail
:
. Lhe fig. shows the same for the write operation, — ¢ For 16kb EPROM, we can provide 2 numbers of 2764(8k x 8) EPROM.
1, 4 T, t, | ag 4 e For 16kb RAM we can Srowde 2 numbers of 6264-(8k x 8) RAM.
SB eee ¢ The 8kb memories require 13 address lines. Hence the address lines AO - Al2 are
oC | a J ra fiz t=, | SCR eaae 2s a used for selecting the memory locations.- .
hee Oe aere One pus Y de Li TE a % _ ©The unused address lines A13, Al4 and A15 are used as input to decoder 74LS138
ALE sb gs Pd x 2 ; : (3-to-8-decoder) of memory IC. The logic low enables of this decoder are tied to IO/
-
M(low) of 8085, so that this decoder is enabled for memory read/write operation. The
other enable pins of decoder are tied to appropriate logic levels permanently. The 4-
| S,-S, | Active | | —
outputs of the decoder are used to'select memory IC’s and the remaining 4 are kept for
ADD/STATUS__X_X BHE_X_Sr= 53 future expansion. - |
— | Ded ¢ The EPROM is mapped in the beginning of memory space from 0000H to 3FFF.
X Data outys——a
ADDIDATA —_)—KArs—Aa x
¢ The RAM is mapped at the end of memory space from C000 to FFFFH.
AD,s5 raat AD
¢ There are five peripheral IC’s to be interfaced to the system. The chip-select
AMWC
AIOWC signals for these IC’s are given through another 3-to-8 decoder 74LS138 (I/O
The input to this decoder is All, A12 and Al3
decoder).
.
this decoder is enabled for I/O read/write operation
I.P. University-(B.Tech)-AB Publisher
2016-7
MOV BX,[2000H] ; take lower 16-bit of NUM2
in BX
ADD AX,BX ; AX
= AX + BX
In the maximum mode, the 8086 is operated by sLrapping the MN/MX* pin to
ground. In this mode, the processor derives the status signals S2*, S1* and SO*. Another
chip called bus controller derives the control signals using this status information. In
the maximum mode, there may be more than one microprocessor in the system
configuration. The other components in the system are the same as in the minimum
mode system. The general system organization is as shown in the Fig.
The basic functions of the bus controller chip IC8288, is to derive control signals
Fig. Memory and I/O Port Interfacing with 8085 like RD* and WR* (for memory and I/O devices), DEN*, DT/R*, ALE, etc. using the
Q.4. (a) Write a program for 8086 microprocessor to add number of 16 byte — information made available by the processor on the status lines. The bus controller
chip
by the CPU.
each? 7 | (4) a. has input lines S2*, S1* and SO* and CLK. These inputs to 8288 are driven
DEN*, DT/k*, MWTC*, AMWC*, IORC*, IOWC* and
Ans. MOV AX,5000H ; Initialize DATASEGMENT It derives the outputs ALE,
The AEN*, IOB and CEN pins are special ly useful for multip rocessor systems.
~~ ATOWC*.
MOV DS,AX ; to 5000H | AEN* and IOB are generally grounded. CEN pin is usually
tied to +5V.
i Al AO Selects
I
| @ | 0 0 Counter 0
aaa | as q 0 0 Counter 1
a : 1. 0 Counter 2 |
So ag . 1 Co 1 _ Control Word Register
4 HORC ; ¢ Q.1. (b) What do you mean by Read Back Command in 8254.
ae
ey Ans. READ-BACK COMMAND. This command allows the user to check the count
3 value, programmed Mode, and current states of the OUT pin and Null Count flag of the
-_ selected counter(s). |
4 Read-Back Command Format
& : | Reference
PON ) register. In this secti i ‘tsof me : 7 PhA mark
this register and provide some examples of how
it is slieed: we epee eno a
PSW (program status word) register .
|
eee
a beget ee Although the PSW register is 8 bits wide, only 6 bits of it are
ge a unused bits
used by the _
are user-definable flags. l‘our of the flags are called | ;
Eee oe ae aaa that they indicate some conditions that result after an 7
ae | ecuted. These four are CY (carry), AC (auxiliary carry), P (pari
me
y), P (parity), and
overflow).
ogee oe PSW.4 are designated as RSO and RSI, respectively, andare __
See stig e ban! registers. They are explained in the next section. The PSW.5 |
- bits are general-purpose status flag bits and can be used bythe programme
r
for any purpose. In other words, they are user definable.
Permanent
CY |AC|Fo0/RS1|Rsolov |-|P : * A magnet
_
-
OOH
used a s s i
|
P
,
55
im
e 82
a c
ee ee to stepper motor. Th 7
os it
n o mg n
UP3:
i nn
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ee
it h
will oaech a
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ot e:
p
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a
in
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th e wi
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coils so each of
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be int
put y
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to be sa te ct unnd dvin gaa motor
need s OUTPUT SEQUENCE
echa 4 JMP AGAIN ; REPEATE
ion to ite eee Output the sequence in sacr
th e de si re d di rect INT 03H
en to aes +
)
sembly Language Progerram t o rotate Stepper Motor in Clockwis
e direction =~ : END START
m to ro ta te Stepper Mo to r in An ti cl oc kw is e di re ction
MODEL SMALL Assembly La ng ua ge Pr og ra
4
ee 100 p MODEL SMALL
ss s F STACK 100
ORTA EQU FFCOH ; PORTAADDRESS |. ‘DATRTAA EQU PORTA ADDRESS
RTB ADDRESS
PORTB EQU FFC2H ; PORT S PO FFCOH
PORTB ADDRESS
C ADDRESS PORTB EQU FFC2H
PORTC EQU FFC4H ; PO =
RT ADDRESS
CWR EQU FF C6 H ; C O N T R O L PO
=a. PORTCEQBQ U F O U PNT e
RO L eP : A D D R E S S
U FFC6H ; CO
PHASEC EQU 03H | SE RI ES TO RO TA TE MO TO R
PHASEA EQU 09H ; SRQUENCE IN
-_ ss. EQU 03H
E s
>PHASEaB sa 06H ; SEQUENCE IN SERIES TO ROTATE MOTOR
EQU 0C H ; IN C L O C K W I S E DI RE CT IO N
HASED
PHASEA EQU 09H
14—2016 Sixth Semester, Micr
oprocessor an d M
icrocon troljey
PHASED EQU 0CH: INANT ICLOCKWISE p :
PHASEB EQU 06H EDI RECTION
I.P. University-(B.Tech)—-AB Publisher 2016-15
-CODE
Assume that an analog input is present at I/P, of the ADC and a clock input of
suitable frequency is available for ADC.
¢ Solution: The analog input I/P, is used and therefore address pins A,B,C should
MOV DX,CTL be 0, 1, 0 respectively to select I/P,. The OE and ALE pins are already kept at +5V to
OUT DX, AL select the ADC and enable the outputs: Port C upper acts as the input port to receive the
EOC signal while port C lower acts as the output port to send SOC to the ADC.
AGAIN:
¢ PortA acts as a 8-bit input data port to receive the digital data output from the
MOV AL,PHASEC ADC. The 8255 control word is written as follows:
MOV DX,PORTC
D D, D; D, Dz; D, VY,
OUT DX. AL | a £20 is i 8 O20
¢ The required ALP is as follows:
MOV AL, 98h -initialise 8255 as
MOV CX,0FFFFH me it SV =
UP3: a St FP Nee |, Clock up
LOOP UP3 ©
JMP AGAIN: ; REPEATE OUTPUT
SEQUEN CE
ie
(525) Pay Pag | =O al
INT 03H = ee rs De.
END START Lae
Laces
only a compatible with 8259. The main difference between the two is that the Ee
the data bus during the next one or two successive INTA- pulses.
can be used with Intel 8086/8088 processor. It also induces ad diti
onal feat
8259 A architecture of 8051. 6)
as level triggered mode, buffered mode and automatic end of i nter
ures Su ch. Q.4. (a) With a neat sketch, discuss the internal
rupt mode. is an 8-bi t mic roc ont rol ler. The major components -
ae ‘ne The 805 1 mic roc ont rol ler
Func tional Description: The 8259 A has eight interrupt req s. |
uest in puts, TR2 of 8051 microcontroller and their function
IRO. The
receives
8259 A uses its INT output to interrupt the 8085A via INTR
interrupt acknowledge pulses from the at its iiput. Vec
pin. The 82594 Intel 8051 Microarchitecture
tor address used by
the 8085 A to transfer control to the service subroutine of the int
err upting device, js
provided by the 8259 A on the data bus. The 8259A is a progra
m mable device that
must be initialized by command words sent.
t
Sie -
; INTA INT ’ r-
T
>
| |
E
Rise ee hea t
RD—>] Read/ N
WR—+ <— IRO
wrile = |-— A In-service Priority Interrupt |<-IR1
AD—>/| logic L register |<=>|resolver|<== request |:
(ISR} register |:
t>——>—_——_?. B . (IRR) |:
U <— IR7
Ss
CASO <—} Cascade
CAS1 <—| bufferf/ |< Interrupt mask register (IMR)
CAS2 <—| comparator
:
SP/EN————_t _ PSEN#
The descriptions of various blocks are, Data bus buffer: This 3- state, bidirectional. _ALE/PROG#
EAH#/VPP
8-bit buffer is used to interface the 8259A to the system data bus. Control words RST
and
status information are transferred through the data bus buffer. Read/Write & contro] |
logic: The function of this block is to accept OUTPUT commands from the CPU. It. i.
contains the initialization command word (ICW) register and operation command
word (OCW) register which store the various control formats for device operation. E
This function block also allows the status of 8159A to be transferred to the data bus. ,
_ Interrupt request register (IRR): IRR stores all the interrupt inputs that are requesting
service. Basically, it keeps track of which interrupt inputs are asking for service. If an
interrupt input is unmasked, and has an interrupt signal on it, then the corresponding
bit in the IRR will be set. Interrupt mask register (IMR): The IMR is used to disabl 7.
(Mask) or enable (Unmask) individual interrupt inputs. Each bit in this register”
18-2016 Sixth Semester, Micri oprocessor and Micr
ocontroller
An 8051 microcontr
oller has the follow
1. ALU (Arithmetic ing 12 major components:
and Logie Unit) [.P. University-(B.Tech)+AB Publisher 2016-19
2-PC (Program Co
unter) |
Internal operations can be synchronized using clock circuits which produce clock
. Registers es. With each clock pulse, a particular function will be accomplished and hence
tm Ww
. Timers and counte hronization is achieved. There are two pins XTAL1 and XTAL2 which form an
rs , lator circuit which connect to a resonant network in the microcontroller. The circuit
. Internal RAM and
ROM has 4 additional pins .
naa
answer in 41H. Q.1. (a) Explain [9/7 ALE pin of 8085 Microprocessor.
MOV A,RO Ans. IO/M': Consider we have an address to be processed. But how do the processors
SUBB A.R2 aaa know whether the address is for memory or I/O functions. For this purpose a status
3
: ‘ “4 signal called IO/M’ is used. This distinguishes whether the address is for memory or IO.
MOV 41H.A ;Move the answ er to the low- When this pin goes high, the address is for an I/O device. While the pin goes low, the
SUBB16_16- b | ae address is assigned for the memory.
Step 1 of the process ye of he result
MOV A,R1 ’
eet
ALEou
hia
(O): Address Latch Enable
CLR C | ALE is provided by the processor to latch the address into the 8282/8283 address
ov
— late h. It is an active high pulse during T1 of any bus cycle. ALE signal is never floated.
SUBB A,R3 ;Subtract the second
low-byte from the ac Q.1. (b) What are flag registers? Explain auxliaty carry and parity flag of
MOV 40H,A Move the answ cumulato r | ____ 8085 microprocessor.
er to the low-byte of th
e result a an Ans. Flag Registers: It consists of 5 flip flop which changes its status according to
;Step 2 of the process
MOV A,RO ‘the result stored in’an accumulator. It is also known as status registers. It is connected
;Move the high-byte into th to the ALU.
e accumulator :
SUBB A,R2 ;Subtract the second high
-byte from the accumulat _-_—C-- There are five flip-flops in the flag register are as follows:
MOV 41H,A e
;Move the answer to the low- 1. Sign(S) 2. Zero(z) 3. Auxiliary carry(AC)
byte of the result ,
i
;Return - answer now resides in = s4«. Parrity(P) 5. Carry(C) ee
R2, and R3.
RET ae - The bit position of the flip flop in flag register is:
: a ; | ; D, | Dg | Ds | Da | Ds | D2 | Di | Po
-_ ei ah Gaia R PAC pa be (ex (EY
- |
)
-.. Allofthe three flip flop set and reset according to the stored result in the accumulator.
! q 1. Auxiliary carry(AC)-If any carry goes from D3 to D4 in the output then it is set
otherwise it is reset.
a tarry in its final
2. Carry(C)-If the result stored in an accumulator generates
j output then it is set otherwise it is reset.
(c) Exp lai n how phy sic al add res s is gen era ted in 8086 microprocessor?
Bi Q.1.
are four 16-b it seg men t regi ster s that allo w the 8086 CPU to access
‘Ans. There
ory in an unu sua l way . Rat her th an con cat ena tin g the segment
| one megabyte of mem ed
ces sor s who se add res s space ex ceeded
| reg | ister with the a ddress regi ster , as in mos t pro
ore adding it
er siz e, the 808 6 shi fts the 16- bit se gm en t onl y fou r bits left bef
a heir regist a 20-bit external (or
set (1 6x se gm en t + off set ), the ref ore pro duc ing
| to the 16-bit off pair. As a result, each
~ ae
add res s fro m the 32- bit seg men t:o ffs et
sRa
~ effective or physical) pairs.
add res s can be ref err ed to by 2"* = 409 6 dif ferent segment:offset
external
000 0 Se gm en t, 16 bits, shifted 4 bits left
~~
: 9110 100 0 10 00 011 1
0100 1010 1001 Offset, 16 bits
0011
; . ° ms D, D aND 7 are:
A ety 2 D, fe Ans. The functions performed by the Bus interface unit
| X X B, ¢ The BIU is responsible for the external bus operations.
B B as I/O of data for
1 B, ¢ It performs fetching, reading, writing for memory 4s well
| |
peripheral devices.
on of the instruction
lways 0 for B ¢ The BIU also performs address generation and the populati
| OR SR mod
ode Don't Care 7
queue.
zero flag after execution
Port C bit select Q.1. (g) What will be the contents of carry flag and
8 255 Contro} Register register C contains 27H.
format fo : of instruction CMP C if register Acontains 70H and
8255 BSR mode | r BSR Mode of Accumulator with the
Ans. CMP C; this instruction will compare the conient
VE = raction of A-C =A
: D 7 bit is always 0 for content of C register by performing 2’s complement subt
* Bits D,,D | BSR mode. | As given A= 70H and C= 27H
H5 and D, are don
© Bits D 3» Vo and D, are used to
't car e bits,
eS seen - A>C; so that no CF and ZF will be generated
of Port:oe (
2 used to set/reset the3 selected pinpin se
select the CF=0 & ZF=0 |
e Bitit. Dy is
)
_ Q.1. (h) Write operating modes of 8253.
Selection of Port C pin is determin The D3, D2, and D1 bits of the Control Word set the
ed as follows: Ans. Operation Modes:
; for modes 2 and 3, the D3 bit is
operating mode of the timer. There are 6 modes in total
B3 B2 Bi | Bit/pin of port Cc selae a ignored, so the mis sin g mod es 6 and 7 are alia ses for mod es 2 and 3. Notice that, for
E mus t be set to HIG H to enable counting. For mode 5, the
0 0 modes 0, 2, 3 and 4, GAT
star ts the coun t. For deta ils on each mod e, see the reference links.
5
- rising edge of GAT E
0
os
0 Mode 0 (000): Interrupt on Terminal Count
0. 1 Mode 0 is used for the generation of accurate time
m the init
delay under software control.
ial COU NT value loaded into
In
it,
0 1 ‘this mode, the cou nte r will star t cou nti ng
down to 0. Counting rate is equal to the input cloc
fro
k frequency.
1 0 Mode 1 (001): Programmable One Shot as
d as Mon ost abl e Mul tiv ibr ator. GATE input is used
1 In this mod e 825 3 can be use
1 1 trigger input.
pul
q
a low
:
e co un te r wil l the n ge ne ra te
counter reaches zero. Th
4 v
er tha t the ou tp ut
PortGy
im
) — aft
Pgo
& ode Port str obe
SF
Alwa ys 1 for
1
ortA l
un ti ng pr oc es s is triggered by the
th e co
VO mode This mode is similar to mode 4,
Ho we ve r,
GATE input.
fo r 1/ 0. mode
— g955 Contro |Wo rd
—_
ip eee
{Print ans/
ee tent is not zero then go to step ce _ nals ed
t in to
:
th
’
e me mo ry .
t o re t h e s q uar e roo
(9) S
n at e t he p rog r am. .
(10) Term i
26-2016 Sixth Semester, Microprocessor and Microc
ontroller
Q.2. (b) Write a program to generate Fibonacci 1.P. University—(B.Tech)-AB Publisher 2016-27
series.
Ans. Refer Q.2. (a) First Term 2016.
Q.3. (a) Draw and explain hardware Interrupt | Vector address
interrupt structure 8085 microp
:
RST 7.5 003Cy
Ans. Interrupt Structure in 8085. RST 6.5 0034,,
* Interrupt is signals send by an external RST 5.5 002C,
devi ce to the processo
;
j. eeare :
2 tA RST Vector location
: ’ -——dAnd) 003CH
75 CLR Q} [Mask
RST 7.5 interrupt recon tse fan] 3
ears RST L-
-0038h
land) 0034h
6.9 Mask i
er, And : 0030h
.
4 > RST and) 002Ch
<=
SOD|SDE MSE |M7.5|M6.5 M5.5 oo |
Mask 0028h
:
Senal output dataqH! 0024h
© —>s-__
4
{TRAP
.
= Available
0020h
1 = mixed
lf, SDE = 1, bit D7<— _————> RST 65 mask -&
Don't
| pi Soe ff /Y 001
is send to SOD line Care ———> RST 7.5 mask | as
Reset OR—p Interrupt Get RST 0010h
8h
if SDE = 0, bit D, is Any oor enable FF Code o008h
ignored
Sica > Mask set enable© 9 Sls] NTR |= nierunt — -Fanad
If, MSE = 0, Do. D,
and D, are ignored if. — | 3
HW 0000h -
MSE. 1, mask is set. _Q.3. (6) Explain the difference between 8253 and 8254 IC. 5
——> Reset RST 7.5 (5)
ffR75= 1:RST 7. : 3/54 will count out the delay and interrup t tthe
he CPU
CP when it has completed
is not allowed.
its coke ae easy to see that the software overhead is minimum and that multiple
lfR 7.5=0: RST 7- . bo
isallowed. delays can be easily be maintained by assignment of priceaty levels.
~~~
Fig. Format of 8-bit data to be loaded e The 8253/54 includes three identical 16 bit counters that can op
in accumulator in accumulator
before ex ecuting sim i nstruction independently. -
e 16-bit count is loaded in its register and, on command, it begins to decreme
il it reaches 0. | ae
* When RIM instruction is execute “ae
dan 8-bit data is loaded in accumulator, whi
ch 4 ae the end of the count, it generates a pulse that can be used to interrup
can be interpreted as shown in fig. |
CPU. | ae: 7
in binary or BCD. |
j r in
unter can count eithe | oo,
| '
is decrementing
SID | 17.5 | 16.5 : ag aaa
eIna . a count can be read by the CPU while the counter
15.5 IE |M7.5|M6.5|M 5.5
-
j
.
oO ( )
ce
cater cd
: q
sim
? RST 6.5 .
status of RST 7.5 | » oe
‘| = 5.
2;
i re N “MOS technology. 2. Uses H-MOS an
Interrupt Pending
; cf : : a
/
. - O +s Read-Back co ae
pena +—— Interrupt 1 = interrupts areenab- | d not available.| 3.
.
e S are desi i 1Rchit bi: “TS, Ser, the code segment (CS) registers, the data segment (DS) registers, and the
16-bit databus and 20-bit address bus. wie e
ee pinary words. It has . segment (SS) registers. These segment registers are used to hold the upper 16
if the starting address for each of the segments. The part of a segment starting
iss stored in a segment register is often called the segment base.
in
, Code Segment (CS): The CS register is used for addressing a memory location
ode Segment of the memory, where the executable program is stored.
are
_ |, Data Segment (DS): The DS contains most data used by program. Data
ter that
sed in the Data Segment by an offset address or the content of other regis
the offset address. -
k Seg men t (SS): SS defi ned a sect ion of mem ory to stor e addresses and data
}. Stac
- tasubprogram executes.
BNO Ee ee Seg men t (ES) : ES is addi tion al data seg men t that is used by some of the
1 Ser | a3 Extra
?2 | ‘% to hold the extra destination data.
|
gee
. |
1
tream :
3
Queue 8
LS eee ee i ee _ |Code
1
! Data
1
Stack
~ date er eel eek eee one. i o> ee es Sew Sew eae Yeas Samp um sem pee iomn Yau tons oe
j
l EU _| Extra
J .
I ‘ >: Ee , -
j
— - segment registers
j
!
j;
i Ari ithmatic
I
logic unit
i
!
I
j
i
i
of
i Md
, | . +
~
_
a
Sixth Semester, Micr
oprocessor and Mic
rocontroller
control signals that required perf 4
orming the o ion,
-
automatically by CP
U after m
divided into two catego
ries:
1. Conditional Flags Vn 0 store 16-bit data. The valid register
Conditional f] _ 8L, BH and BL, CH and CL and DH pairs are AH and
ag8 represent brresu
esnit of
lt of last arithmetic or logical] _ BX, CX, and Dx respectively, an d DL. These register pairs is referred
to the AX
* Carry Flag (CF
: 61cal instructions— a 1. AX Regist : er ‘
: For 16-bit WK 5
perations, AX is called the accumulato
dy stores operands for arithmetic operat r register that
ions.
from lower nibble (i.e. Do — D3 2. BX Register: This register is
: ALU generates a a ca mainly used as a base register. It ho
given by D3 bit to D4 is AF aca ise r
Ca rr at
y/ba MoaSe loc Locati
ation o fa memory ry re region wiith lds the starting
i a data segment.
*
teaoe ee R thin
by the processor to perform Binary e AF wee 1S Set i.e, Can _ 3. CX Register:
to aoe tee | pee w2e Used 7 halsto It is defined a8 a counter. It is primarily
used in loop instruction to
re loop counter.
4. DX Register: DX register is used to
contain I/O port address for I/O instruction.
Stack Pointer Register
}
mode. —
We ee WR GATE,
a 7 8253/54 [;— OUT,
In 8085, only one processor is used. In 8086, more than one processor is iw
Additional external processor can Ayn '
alsoh Agauee
employed. | a
In this microprocessor type, only 64 In this microprocessor type, 1MB memo As—— cs
KB memory is used. Ag
is used. — Ay
Q.5. (6) Explain the interfacing of 8254 wit
h 8086 with the help ofa
diagram. Fig. 4. Interfacing of 8253/54 with 8-bit address
, .
4 \% ]
a faite ha fd :
Ans. To generate a square wave of 1KHz fr equency We know that, 8253/54 has two address os e
on OUT 1 pin 0f8253/54. Asal ‘byte of demultiplexed data bus IBA.
CLK1 frequency is 1MHz and address for con trol reg ,
ister = OBH, counter 1 = 09Ha aci ed fo hos dac e line s of 825 3/5 4. The 825 3/54 IC decodes A,
counter 2 = OAH. Bek cal OE cad tae nade
to sel ect one of its por ts or con tro l reg ist er.
a : pee oo )
Sol.: To get square wave mode 3 is selected count should be can be use d to gen era te chi p sel ect sig nal . Fig . sho ws the
a address lines (A,-A4 )
1MHz
of 8253/54 with 8086. _
1KHz eee _. Address Map:
Address lines Address
Control word: } |- ports/Control
| 3 t 7p -
* Stop bit length (asynchronous . mode) | { ‘ —> 0 0 1 1
4 j . | Gbits | 7 bits | 8 bits
5bits
* Character length ~ | : |
| ae Pari
* Baud rate factor (asynchronous mode) | 4 s ~ 4 ak. 1
a
| x.)
e Internal/external synchronization (synchronous mode)
: :
a a rBce 2 : ;
. Odd Even
2
©
<7
a Disable | parity |Disable | parity
Number of synchronous characters (Synchronous mode)
The bit configurat ion of 4 .
1s shown in Figures. In the case 9 ZS ' | she ahs Synchronous mode
Synchronous mode, it is ie adetee |1
© one-or two byte syne characters. If es
sym xe . —> 0
characters were wri eae = oe
constitutes partaf itten eis: be set because the writing of sync. charaalil | : Internal External
iy i. synchronization | synchronization
= 3
L De | Ds D, esi
D. D D D 3
aa Number of synchronous charactors
S,| s, | Ep] PEN Ean B, a |
0 1 ;)
: fail
a ?
a !
sao Baud rate facotor
|
ia 2 charactor |1 charactor
= of }— Sef Oz 7 |
os ? 0 . Olena 4 a Bit Configuration of Mode Instruction (Synchronous)
syne | 1x 16x] 64~ 4 (2) Command
an d is use d for set tin g the ope rat ion of the 825 1. It is possible ‘to write a
2 e Charactor length 4 -- Comm and sync. characters.
an d whe nev er nec ess ary afte r wri tin g a mod e ins tru cti on
4 comm
oe as eaapeat 2 e 4 |
>| 0 0 1 ; |_ Items to be set by command are as follows: —
S bits| 6 bits} 7 bits]. 8 bits 4 -e Transmit Enable/Disable
e Receive Enable/Disable is
Parity check
= : | * DTR, RTS Output of data.
di sp la y ca n be se t as ar ig ht en
i display. The
7 ~
Ve ie multiplexed display.
MPU INBTERFACE SECTION
This section has 8 bidire
es for in te rf ac in g in
ct
cl
io
ud
na
in
l
g
lin
buf
es.
fer
DB
ad
,
dr
-
es
DB . 1
s lines Ap.
in te rr up t request line(IRQ).
a
motor speed
Scan
ga in s,
contr | "|
and we gi ta ll y co nt ro ll ed
Display le
areas like di
The DAC find applications in vo lt me te rs , pa ne l me te rs , etc. D/A
counter _ Return mm ab le ga in am plifiers, digital
cont ro l, pr og ra
si de s th os e wh er e th ey are used with a
ications be
converter have many appl er for ex am pl e a 14 -o r1 6- bi t D/A converter
sk audio play
Ta | 4 microcomputer. In a compact di di sk by a la se r to an an al og audio signal.
Out A,-A,, out B,-B, BD SL-SL,
us ed to co nv er t th e bi na ry da ta read off the nv ert stored
CNTUSTB is ai n a D/ A co nv er te r to co
RL-RL. in te gr ated circuits cont
8279 Block Diagram RG S ha Most sp ee ch sy nt he si ze r
da ta wo rd s in to an al og au dio signals.
binary
KEYBOARD SECTION ‘Characteristics l input. It
Sa ‘
r on e LS B ch an ge in di gi ta
ti on : It is a ch an ge in analog output fo
This section has 8 lines. . RLRL, - RL... Plus 2 aadit
: 0
The keys are automatically debounced and Ebon
additional li |
aa oboe an twomodes:
and CNTL/STB. 1. Re
is given by
so lu
(1 /2 n )* Vr ef . If n = 8 (i. e. 8- bit DAC)
1/256*5V = 39.06mV
>>two key lockout mode or DA C to se tt le fo r a fu ll sc al e code
li ng ti me : I tis th e ti me re quired for the
2 Sett
>>N-key rollover. |
change.
alog converter
pressed simultaneously only first keyi
| tieIns tw e id lockout mode if 2 keys are 08 00 8- bi t Di gi ta l to An
DAC
Features: ct ur ed by Na ti on al se miconductor.
In N key rollover mode, simultaneous k eys are recongnized and stored in inte nalt 80 0 is a mo no li th ic 8- bit DAC manufa
(i) DACO
buffer: around 100ms °
es , it can also be set et up p so so that no key recongnized until only one key is remai red (it ) It ha s se tt li ng ti me
i.e . fr om 4. 5V to +1 8V . Us ua ll y
on a ra ng e of po we r su pp ly voltage
(iii) It can operat e ke pt at a m i n i m u m of -12V.
This has a FIFO RAM. V+ is 5V or +1 2V . The V— pin can be
the su pp ly
; ti on of th e D A C is 39.06mV
The status logic kee ps track
:
request) signal when FIFO is ee ape
m
ee
provides IRQ(interruptl (iv) Resolu
25k
| v 14 WW SV
DISPLAY SECTION at hey oP
= B,-Bs +s
This section has 8 output lines divided into 2 groups of 4,A,—A, and Do-D7 PA-PAg
T re ap 7 3g B o- By. =
hese lines can be used in: both ways 8 lines or 2 sets of 4 line —W— 15 =§
Vo
s
eee eoep os
TOR, 4 8255
Se ay can be blanked usius ing
The displ; ea li
BD line. The section has 16 x 8 disp] ay NAM
~-
om, | | ~12Ve—
r e e 3 Tapers Se oe
This section has scan counter and 4 scan lines. SL 0.1 4 4
decoded 1usi
using a 4 9 — SL,. These 4 scan lines canbe
— 16 decoder to generate 16 lines for scanning =
:
42-2016 Sixth Semester, Microprocessor and Microcontrolle
r
ALP to generate Square wave
LP. University—(B.Tech)-AB Publisher 2016—43
0000:4000 MOV CL,FF
are available
* Internal Data Memory: Up to 256 bytes of internal data memory
O0nn:4002 DEC CL
0000:4004 JNZ 4002 ia depending on the 8051 derivative. Locations available to the user occupy addressing
is divided in several
| _ space from 0 to 7Fh, ise. first 128 registers and this part of RAM
0000:4006 RET and indirectly
blocks. The first 128 bytes of internal data: memory are both directly
0000:4007 MOV AL, 80
) addressable. The upper 128 bytes of data memory (from 0 x 80 to 0 x FF) can be,addressed
0000:4009 OUT 67, AL | + only indirectly.
0000:400B MOV AL: 012 | r t Since internal data memory is used for CALL stack also and there is only 256 bytes
is crucial for fast
ee a splited over few different memory areas fine utilizing of this memory
0000:400D OUT 63. AL ;
_ and compact code. See types efficiency also.
0000:400F MOV AL. 00 which means that each
Memory block in the range of 20h to °Fh is bit-addres sable,
a a : this
are 16 such registers,
0000:4011 OUT6 ,
3 | | bit being there has its own ‘address from 0 to 7Fh..Since there
0 :
000:4013 CALL 4000
1, AL block contains in total of 128 bits with separate addresses ( Bit 0 of byte 20h has the bit
MOV AL. FF | address 0, and bit 7 of byte 2Fh has the bit address 7Fh).
0000:4016
| | a 3 | | Three memory type specifiers can be used to refer to the internal data memory:
0000:4018 OUT 61, AL
0000:401A CALL 4000 ee ee |
tr ne ee seats sae ae
pe pee tee ea gen G :
ae aa
inde aaeentn
| |
Sree
JMP 400F
an
0000:401D
ee
Q.7. (b) Explain. the interfacing of 8254 wiihieiee <.
| aae : addressin rect addressinging
— a
indi = ng !|
|
n ‘ | ~ Bark O Foohex |OOHT
with the help of neat di
Bark 3 1F; a !
1 |
eeeOo. (2 Q.5
} (6) of End Term 2016. <
addressablefe
| 16 bitregisters P Le, S | :
functions aan and ee RS1 bits memory organizt ion in the € 8 8051 and also write the aan_ Ce ee r |
in the PSW of 8051 Ww ;
. we
ew . tin
Ans 8051 Memory Organization Th
2 1 ~ RAM memory {
Address FFFF hex apse ys se e
aoem naar TS Tee ee paoeeemr
am
numbers are stored in RAM locations 50H onwards.
| Q.8. (6) Ten hexadecimal largest number should be5)
Eo) Be Seesa program to find the largest number - .
in se set. The
EA pin =0
eS Write
5 | Additional rom saved in 60H. ere
to find largest number among given block of numbers using
| Ans. A program
(oak nee is ; 5 |
max.
‘microcontroller ~ |
Address FFFF hex so
MOV DPTR,#5000H:
= |
: | | “CER 6 >
: Address 4000 hex MOV R2,#09H e
BN 1a
c :
|
im +f t er MOVXA,@DPTR
| Seonn nmomo
ee Address 3FFF hex | MOV 60H.A |
Embedded ROM | UP: INC DPTR-
ee MOVXA,@DPTR
Werccentralles CJNE A,60H,DN
-Address 0000 hex-» | ee
Se ce = ———__—/ ¢ ee 51
ne See aS SS SJMP NEXT
aw - LIL IL ILI}
wren
=
A ao a so es 5 ——
. ar. <a a - a a
. ‘ Le? is
~ 1
peeks 2 BIS eal. Se)
.
} — ee rs eee Ag - os
24) eg
y
3 Pi) 71 7 i
F Pity * 4
an
a
Pod eAcae SoU IAN ie Soe a
MSO ee ree aid As
a tats | oh)
MO V 60H,A : controlle,
“rO k
a Publisher 2016—45
; i | LP. University-(B.Tech)—-AB
IN XT: DJINZ R2 Up
ica tes tha t ope ran d is a dat a. If ‘# is not present
6BH ind
) f > ¥ given above ‘#’ symbol before
; as a address.
M ee DPTR ae ‘hag Z then the hexadecimal number considered
OV A,60H
| | a Direct addressing mode:
MOVx @DPTR A the add res s of the data (source data )
g mod e in whi ch
= ae This is type of addressin
3 d.. i.e. it is giv en dir ect ly in the for m of numerical data.
RET __ Fisgiven as operan
f Block of numb ae e.g. MO V B,2 0H; The ins tru cti on abo ve mov es val ue at add ress 20H memory location
se f :
r om location 5000-5ers ; 1Sj stored at locat
s of SFR.
block eos ¥ to register B. Here 20H is addres
Register R2j Iss eae oe °000H, oa
al Bye Numbers gto.) ; ference between direct addressing and immediate addressing mode is, we
f The dif
etched during first te 4S a counter for 10 ike immediate mode.
> 8 don’t use Ww in direct addressing mode, unl
j xecutio number S, It is set to 09
First number
is stor as tw ® number a‘rel Register addressing mode:
pre
Second Number is ee In Accumulator and This is typ e of add res sin g mod e in whi ch we use the reg ist er nam e directlyas source data.
en fetched and st Served in location 60H
exe cut ion of this ins tru cti on con ten t of register R5 is get
e.g MOV A, R5 After
ater) copied to location accumulator.
a Register direct addressing mode:
data is given by value at regist er
In this mod e of add res sin g add res s of sou rce
ars
ire ctl y tha t’s why we cal lit asa ind ire ct register addressing mode.
| ind
Her e in this ins tru c tio n reg ist er R1 hol ds the address, suppose
e.g. MOVA, @R1
er exe cut ion of abo ve ins tru cti on val ue at location 20H is
| value at R1 is 20H’ then aft
Her e sym bol ‘@’ ind ica tes add res s. In thi s type addressing
transferred to to accumulator.
mode w e can use only register RO
and R1 to provide indirect address.
—
:
the
*
In
: ‘ .. yi aX ALY
.
the
data
ae gh 7 Res ae ‘ oii a a .
ediate
‘,
imm
moves .
‘nd icate
instruction
i ano” >
~S. as ian
“4a
; on een
i o
%
Sees 2 aete
ee
Ye a
se
46-2016 Sixth Semester, Microprocessor and Microcontroller
4
I.P. University-(B.Tech)-AB Publisher 2016-4
5 TFO | Timer 0 Overflow flag. Set when timer rolls from aj] l’s tone | Bit Addressable)
Cleared when processor vectors to execute interrupt sora TMOD: Timer/Counter Mode Control Register (Not
routine located at program address 000Bh. ®1
| . a aoe Te mo) gate | crt 11 Mo
4 TROI Timer 0 run control bit. Set to 1 by program to enable timer jp
k count; cleared to 0 by program to halt timer. at Timer 1 Timer 0
3 IE1 1 External interrupt 1 Edge flag. Set to 1 when a high-to-low
| edge, edo.
signal is received on port 3.3 (ENE4), Cleared when procegadl ;
Gate When TRx (in TCON) is set and Gate = 1, timer/ counter ; will: ia Se i si
rae |e
vectors to interrupt service routine at program address 0013h - | high (handware control). When Gate = 0, timer/counter x, will run only while
Not related to timer operations.
= control) (i
2 IT1 ] a
External inter .
rupt 1 signal type control bit. Set to 1 by programot C/T Timer or Counter selector. Cleared for timer operation (input from interna
system clock). Set for counter operation (input from Tx input pin),
to! enable external interrupt
: 1 to be triggered by a falling edge |
signal. Set to 0 by program to enable a low-leve
. M1..-~- Mode selector bit (note 1).
interrupt 1 to generate an interrupt. signal
1
on external ; MO. Mode selector bit note 1).
ae
1 M1 — Timer/counter o perating mode select The latch is necessary for output devices to return the result otherwise the result will
select mode. bit 1. Set/cleared by shes
25 |
disappear.
0 M0W— Timer/counter operating mode select bit 0. Set/cleared by progr Q.1.(6) The memory address of the last location ofa 1K byte memory/chip is
a (2)
select mode. | given as FBFFH. Specify the starting address.
Q.9.(c) Explai
at
4 b Ans. As given last location of [Kbyte = FBFFH
he piain the following 8086 instruction
7.
TEST:; Logical
7B co mpare 2 instructi
j ‘
a
t>
w
_
|
fa
Address Out
4
A
:
Hs
MO ~< Low-I/O READ, HIGH=MEMORY READ
~
><
Padi
hid
Ea
i
Serial Output Da
Meus se
RD sac eter Tat
os
Pei = emma
ta
#-TRLDV —} pune
£\,
DUR in ae eee
trie
Serial Data Ena
i ealiih $ Biinlde
LT
> 0 = Available
Crk
if Send to SOD Don't
Stas,
if SDE = 0, pit ne Care Fig. (a) Input (read operation)
SAT
ignored,
=
_ nas Ss These are explained in steps.
=
Mia? t ~
=
@O
@
Ss
a
®
@
’ MSE = 0, D6 D7 Se
1, When processor is ready to initiate the bus cycle, it applies a pulse to ALE
t
& D, are ignored if =
Bros.= 2
set
_| during T1. Before the falling edge of ALE, the address, BHE , M/IO, DEN and DT/R
»ResetRST7.5
R 7.5 =RST7, 4 | - must be stable i.e. DEN = high and DT/R =0 for input or DT/R = 1 for output.
is not allowed 2. At the trailing edge of ALE, ICs 74LS373 or 8282 latches the address.
IfR 7.5= 0; RST 7. 3. During T2 the address signals are disabled and S,-S, ale available on AD,,/S,-
MVIA, C8H; Content of SIM=C is allowed,
8H a AD,,/S, and BHE /S,. Also DEN is lowered to enable transceiver.
SIM
HLT 4. Incase of input operation, Rp is activated during T, and AD, toAD,, goin high
| impedance preparing for input.
Q.1.(f) How Type 2 dedicated interrupt is generated. What is its we ci 5. If memory or I/O interface can perform the transfer immediately; there are no
location?
| _ wait states and data is output on the bus during T;.
Ans. Type 2: NMI (Non Mask-able Interrupt) (INT2)
6. After the data is accepted by the processor, Rp is raised high at the beginning ez
¢ This is the highest priority hardware interrupt and is non mask-able. The input of Ti: *
is edge triggered but is synchronized with the CPU clock and mus be active
t for two ; 7. Upon detecting this transition during T,, the memory or I/O device will disable
clock cycles to generate recognition. ) ; its data signals.
¢ The interrupt signal may be removed prior to entry to the service routine. a data on the
-8. For an output operation, processor applies WR = and then the
¢ Since the input must make a LOW to HIGH transition to generatane interrupt, data bus during T,.
spurious transition on the input should be suppressed.
e If the input is normally HIGH, the NMI low tim
| e cant qiarenica Sigua aoa 9. In); WR is raised high and data si gnals are disabled.
is oe . i oe
10. For either input or output operation, DEN
\
CPU clock times. in th e In te rr up t Ve ctar Ta ble ( VT) ord ing to the c
transfer
next e at this i tobe nectiv3 e
2 x 4 = 00008H er. Als o M/I 00 i is set acccor di
e Its ISR address is stored at s loca| tit on
transceiv he |
fa il ur es fo r ex am pl e pov , bus cycle in 8086 is four c
for catastroph ic filled by
I in te rr up t inp ut is 1s us ed the gap between the successive cycles is
pits
ll y NM
r
ca
:
e Basi
Sa,
ea
Hee 3
Sa ee
ti me ou t of sy st em watc hdog timer.
se failure, minimum mode memory re" ideal state clock cycles.
uickly during transfer, wait
di ag ra m for 8086 d
a a -@:3. (@) Draw the timing When the memory or I/O device isandnotT, able to respond q READY input of the 8086.
by disabling the
mo de 1s s h o wn} : states (Tw) are inserted between Ts
i n i m u m
diagram for read operation 1 n
am m The bus activity during wait state 1s s
ame as during Ts.
eet
'
S
ae se Cotten: ixth Semester, Microp ro
c :
co e for MOv is “es
0010
binary cod
© for the MOV Cg, > | [BX]
cessor and Microc
7 ee
Ans,
~15. Tech. |~ 2017-5
Convertir
hstructions to ene Uage
— MOD = 11 aoe
Effective Address Calculatit
|
R/M W=0 Wei
de
=
MOD aa
POODE .
AL a. a =t0
; 000 =<
B(BX)+(S1)+D
= 000 = (BX)+(6D) (BX)+(51) +D,
SH oT oa
| a
001
CL
=
CX | on (
(BX)+(DI) a ae
3 _ xan
= DL .
* An instructic
can be coded ed w ; Be sre ne | 010
Hl ae as 010 (BP+(s1
°B ion
conta;
1 ¢ 6 bytes
=p with | +(SD+D (BP iG
yte 1 three kinds of O11 B ; +(SD+ Dig
Opokas « sare AH gp (BP + (DI) (BP)
(DI) +D, (BP)+(1)+ D i
: intormati ; 100
BP
100 (SD) (SI) +D 3 (ST)
eld (6 bit
s) Specifies th
© operation such
10n;
101 CH 101 (D en a
Bex Register D} irection Bit
1t (D bit) ch as add subtr fact | ST fie a
(DI) + D,
een
Q.3. (a) Given that: BX = 637D, SI = 2A9B, Displacement = C237. SI = 567 8 H; DI = AB EF H;
ae= = 12: 34 } H: ’ BX == 3456H; CX = 10 H;
Determine the effective addr : ess (if a pplicable) resulting from these
in st ru ct io n MO VS B
S B 1 ed
is executat
registers and the addressing mode: (3) 4 : SS=9097H. If now the
poses i
1” the me mo ry . . Als Also indicate wha
(1) Immediate (2) Direct = 2 st e
at ee eearly what happens
cl
by he Sear s
e le ft in th e ab ov e registers.
(3) Register using BX (4) Based Indexed sactem bed ible
da ta ar
.
me D fl ag is se t | |
Ans. (i) No effective address is used © Assu S:SI into ES: DI
-
of byte . D
(i1)Direct effective address is given in the instruction itself 3 | qi
Ans. MOVSB : copies contents
= 0 ; Fo rw ar d pr oc essing (L 0
(111)No effective address is used Direct io n Fl ag
| | ‘ ( R to L)
DF = 1; Backward processing C8H
(iv)BX+SI = 8E18H
d r e s s of s o u r c e D S : SI =Sis 959
Physical Ad ation BS : DI = 7256FH
Q.3.(b) Write an ALP to produce a delay of 1 second. Consider the 8085 | e d fr om 959C8H to
10 bytes of data are m o v
clocked at 5 MHz. Physical Address ate nvaer
; | (3) He r e D F = 1 & C X = 1 0 , That m e a n s
Ans. In 8085 single register cannot be used to generate 1 sec time delay, So wen
to use time delay using a loop within a loop technique:
eed —
“a
: ‘1256Fy : system having
a
_ Given tame delay= 1 second and every time DF = 1. ocessor 8086 based microcort Jevice. The 10
Qh) Designs ee ory map should not
oKram, | input See Ths memmem
Frequency of 8085= 5MHz | 4 chips of 4k RAM. ace memory mapped 10, ory map of a lete
Time period of 8085= 0.2usec devices are invertace aa asem. the comp
a have any fold back 4
ALP to generate 1 sec delay
microcomputer system.
ee a a
% . de her POA Bas: s age
Ans.
Four chips of 4K RAM = 16 K RAM _ END TERM
Two chips of 2K RAM = 4 ne EXAMINATION [MAY-JUNE. 2017]
| SIXTH SEMESTER (B.TECH.]
16K RAM address lines : 24x 2! =A. -A
4K RAM address lines : 2? x 210 ak e . — ll
. MICROPROCESSOR AND
:
MICROCONTROLLER
Table Memory Map 7 [ETEE-3 10]
See = _ = _ - . Ay A) An Ajy Aw Ate Any Ape Bos Ay Agy by Ay A, Ti:me 3 Hrs.
FC000 . iacce URS M.M. : 75
q
eee lee al T- fi Note: Q. No. ‘1 is compulsory. Attempt any five Questions from remai
1 l l 0) 0) 0) 0) 0) 0 () 0) 0 0) 0) 0) 0) 0 | questions from each
ning. Select one
unit,
16 K RAM a
FBFFF aap a Poe ey 1-7 Q.1. (a) Draw and explain timing diagram of memory
FB000 read machine cycle of
bore e Be O00 eee 0 0 9 | 8085- | (2.5)
| | Ans. Read Cycle : The high order address (A,, <>A,) and low order address (AD, ©
| , a AD,) are asserted on 1st low going transition of the clock pulse. The timing diagram for
= of 10/M read are shown in Fig. The A,, A, remains valid in T,, T,, and T, i.e. duration of
2 ae cle,, but AD, 7 <= AD, 0 remains valid only in T,.1 Since it has to remain valid for
the bus cycle
= Odd | the whole bus cycle, it must be saved for its use in the T, and T,,.
16Kx 8 "
.
| 4-1, BHT, PE T3 Et 1 4-T Et Tt CT
Poo Os ae CLK
CS, + cs, =Ai2 Ais Arg
lOMae |O/M = 0,S,=1.S,=0
cS, = CS, { ee
CS, , a F S4;S0
ake = Odd - .
Cs, +c =O 14 16K x 8
oe PC L=Ai, = Ag Xe Unspecified
a : As
F
D,-D,.
CS,
ae 4K x8
: | | —J D,-D,5 3 I
Q.4.(c) Consider the Instruction Fi - Memory read timing diagram
ee teh e ing of T, of each bus cycle and is negated towards the
: 2010H JUMP p; oF ALE is asserted at the beginnin
What 1sis the
th value of Disp , das the clock pulse to latch the address
= to go meto the memory (2) | endofT,. ALE is active during T, only and is used as the clo FT. Itends at the end of
Ans. 2010H locati 0 a‘| AD
: H JMP 2005H
ry location 2005 H. (AD, AD,) during i T.. The RD is ase asserted nearchethememo
begirynninorg I/OOF port
45. to assert data. RD
| | T,.As soon as the RD becomes active, it forces emory to terminate the data.
rr
a| & inact
becomes inact ive towar ds the end of T,,3 caus the in
port g
orm
: orv :
location 7000H into regis ter B by
of Q.1.(b) Transfer 8 bit data of memory | (2.5)
2 _ using three methods.
ie Ans, (i)LXI H, 7000H
| j , | | - (ii)LDA 7000H
i 3 ie : on MOV B, A
(iii)LHLD 7000H
MOV B, M
10-2017 Sixth Semester, Microprocessor and Microcontroller I.P. University-[B.Tech.|-AB Publisher 2017-11
nte r poi nts to loc ati on 00 00 H. In wh ic h memo, |
Q.1.(c) In 8085, the stack poi oe
used? (2. Q.1.(e) The contents of DS is 32A5H. The amount of data that is to be
location will be stack contents be stored if the stack is is 12K byte. Wher e in memory, will this segment be located?
; data
in segm ent
Ans. So in order to answer this question, we need to really understand how the Ans. Data segment
PUSH instruction actually works in 8085. Consider the following situation: DS : BX/SI/DI gives the physical address.
Register B has contents 0xAA Q.1.(f) Draw and explain Interrupt Vector Table of 8086.
interrupt
Register C has contents 0xBB Ans. Interrupt Poini t table/Vector Table: : When an ininterrupt : occurs, the
a FAR Ste
SP = 0000 eR are called in the same manner as that used for calling
a 086, two 16-bit data words are required to specify the memory location, i.e.,
Now, Let us assume the instruction encountered is PUSH. The PUSH instruction As in S so two 16-bit data words are used to specify the location of the eens ee
first decreases the stack pointer SP addres
ano ‘ One word is used to load the CS register and points to the starting
B -> OxAA eede segment containi ining ng the service routine. ) .
C -> OxBB t word s for all thes e inte rrup t ae o ee Pet icetions
i ae ee offse
ble or interrupt point table. In 8086, the firs t .
SP -> FFFF
interrupt seo to 0OO3FFH are set aside for this interrup pointer table. ’
and then stores the higher order register, decrements again and then stores the starting with hea
the 256 type s of inte rrup ts are classified as Sons
lower order registers as well. As seen from figure, ;
~1ots and available interrupts her are the reserved interrupts. Eady
B -> OxAA reserved pees by the intel for the furt processor. hie on Be ieee
C -> 0xBB their ISR addr esse s in these oe :: r
eae. “ee for load ing
FFFF -> 0xAA 255 are avai labl e to the user to store their ISR addresses.
ee 0 ae
FFFE -> 0xBB
SP -> FFFE
Q.1.(d) Explain assembler directives: EVEN, PROC, END. . (2.5) |
Ans. EVEN - This EVEN directive instructs the assembler to increment the location \
of the counter to the next even address if it is not already in the even address. If the word |
is at even address 8086 can read a memory in 1 bus cycle. If the word starts at an odd | .
address, the 8086 will take 2 bus cycles to get the data. A series of words can be read
much more quickly if they are at even address. When EVEN is used the location counter|
will simply incremented to next address and NOP instruction is inserted in that ehii! 4
incremented location.
:
a
s :
Example: x a7
DATA1 SEGMENT ; Location counter will point to 0009 after assembler reads”
ynext statement SALES DB 9 DUP(?) ;declare an array of 9 bytes oak Reserved
_ EVEN ; increment location counter
to 000AH | : ;
interrupts
(27)
RECORD DW 100 DUP( 0 ) ;Array of 100 words will start ;from an even address for_
quicker read ) ~-
DATAI1 ENDS
PROC - The PROC directive is used to identi fy the start of a procedure. The term
near or far is used to specify the type of the procedure.
Example: 4 |
SMART PROC FAR; This identifies that the start of a procedure named as SMART
and instructs the assembler that the procedure is far .
j :
ie
SMART ENDP This PROC is used with ENDP to indicate the break of the procedure, & .
END - END directive is placed after the last statement of a program to tell the 4
assembler that this is the end of the program module. The assembler will ignore | oo)
rs
any statement after an END directive. Carriage return is required after the END gg
*
©
wah
directive. : |
eel ete:
ih
he
= ee
Ba
LP. University-(B.Tech.]|-AB Publisher 2017-13
er , Mi cr op ro ce ss or and Microcontroller
Sixth Semest
12-2017 (2.5)
(25 Q.1.(h) With the help of a waveform, explain 8253 in mode 3.
e an d ex plai n B S R mo de of 8255.
Q.1.(g) Writ ch li ne of po 6 Ans. Mode 3 (X11): square wave generator
mode is appl ic ab le to port C only. Ea
Ans. The Bit Set/ibe Reset (BSR)itab ly the con trol wor d regi ster . BSR mode This mode is similar to mode 2. However, the duration of the high
and low clock
loading
(PC, - PC.) can be set/reset by suitably of BSR mod e does not affe ct the oper a and pulses of the output will be different from mode 2.
VO mode are independent and selection Lion of
Suppose n is the number loaded into the counter (the COUNT
message), the output
other ports in I/O mode. for n/2 coun ts, and low for n/2 coun ts. Thus , the peri od will be n counts, and
will be high
.
if n is odd, the extra half-cycle is spent with OUT high
Mode 3: Square Wave Generator
x - By B, By SIR
0 X X
= MU UU UU Ue
UU UU U
y t Setiwatl
_
ae, Gi kee
CLK
LeECY¥
“ otha
_ GAmode | | |
Auxiliary Carry flag
le,
purpose
ee
th e us er for ge ne ra l
Available to
é
Ste
Teo PSW.5
Register Bank selector bit 1.
atid
RS1 PpSw.4_
»&
Owlhedt
Always 1 for
Y
OV PpSW.2 a
‘a
A
M i op ro ce ss or an d Mi cr oc on troller
14-2017 Sixth Semester, * Mi cr [.P. University—[B.Tech.|-AB Publisher 2017-15
Register Bank Address
RS1 RSO Q.2. (b) What is an addressing mode? Explain various addressing modes of
OOH - 07H 8085 with examples. (6.5)
0
08H - OFH Ans. Addressing Modes in 8085
1
10H - 17H These are the instructions used to transfer the data from one register to another
2 register, from the memory to the register, and from the register to the memory without
3 18H - 1FH
, 1 any alteration in the content. Addressing modes in 8085 is classified into 5 groups—
Immediate addressing mode
Bits of the PSW Register
g aft er exe cution of ae In this mode, the 8/16-bit data is specified in the instruction itself as one of its
Q.1. (j) Sho w sta tus of CY, AC and P fla
5) operand. For example: MVI A, 20F: means 20F is copied into register A.
instruction: Register addressing mode
MOV A; #88H In this mode, the data is copied from one register to another. For example:MOV A,
ADDA, # 93H B: means data in register B is copied to register A.
Ans. MOV A, #88H Direct addressing mode
ADD A, #93H In this mode, the data is directly copied from the given address to the register. For
Both are the format of instruction used by 8051 microcontroller example: LDA 5000H: means the data at address 5000H is copied to register A.
Status of CY=0 Register Indirect addressing mode
AC=0 In this mode, the data is transferred from one register to another by using the
address pointed by the register. For example: MOV M, B: means data is transferred
P=]
from the memory address. pointed by the register to the M(memory pointer).
UNIT-I
Implicit addressing mode
Q.2.(a) Explain following pins of 8085. (6)
This mode doesn’t require any operand; the data is specified by the opcode itself. For
ALE, IO/ M, READY, HOLD example: CMA.
Q.3.(a) Write an assembly language program to sum the following series:
Ans. ALE: Address Latch Enable:
WZ iccceccsecescccassscsssscenmsorta: +F, (5)
In the previous article we saw how ALE helps in demultiplexing the lower order
Store the result at memory location 4000H assuming that the series start
address and data bus. This signal goes high during the first clock cycle and enables the
from memory location 3500H.
lower order address bits. The lower order address bus is added to memory or any ~
external latch.
Ans. Statement: Calculate the sum of series of numbers. The length of the series
is in memory location 3500H and the series begins from memory location 3501H.
READY:
Consider the sum to be 16 bit number. Store the sum at memory locations 4000H
READY is used by the microprocessor to check whether a peripheral is ready to ~ and 4001H.
accept or transfer data. A peripheral may be a LCD display or analog to digital converter
3500H = 0FH
or any other. These peripherals are connected to microprocessor using the READY pin. —
If READY is high then the periphery is ready for data transfer. If not the microprocessor — 3501H = 01H
waits until READY goes high. 3502H = 02H
HOLD: 3503H = 03H
This indicates if any other device is requesting the use of address and data bus. 3504H = 04H...
Consider two peripheral devices. One is the LCD and the other Analog to Digital Result = 14+2+3+4+5...4F= H
converter. Suppose if analog to digital converter is using the address anddatabusand —
4000H = Lower byte
_if LCD requests the use of address and data bus by giving HOLD signal, then the d f
microprocessor transfers the control to the LCD as soon as the current cycle is over. _ 4001H = Higher byte
After the LCD process is over, the contro] is transferred back to analog and digital Source program:
converter. LDA 3500H
1O/ 1 ’: MOV C,A : Initialize counter
Consider we have an address to be processed. But how do the processors know LXIH,3501H _ : Initialize pointer
whether the address is for memory or I/O functions? For this purpose a status signal SUBA : Sum low =0
called IO/M ’ is used. This distinguishes whether the address j s for memory or IO, When MOV B,A Sum high = 0
this pin goes high, the address is for an I/O device. While the pin goes low, the address BACK: ADD M - Sum = sum + data
is assigned for the memory. JNC SKIP
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P INR B - Add carry to MSB of SUM
SKIP: INX H : Increment pointer .
Start ISR
DCRC
JNZ BACK
: Decrement counter
; Check if counter 0 repeat
— | sae eee
Request device
STA 4000H : Store lower byte go get Ready
MOVA, B 7
STA 4001H : Store higher byte | 1 Execute data : transfer
Fetch next instructio
and execute ce
HLT : Terminate program execution
Yes :
Enable interrupt | .
Sum =0
Pointer = 2201H- System
Count = (2200H)
Call ISR associated
>} with this interrupt Return to main
program
Sum = Sum + (Pointer) Fig.(a) : Main program execution sequence (b): ISR execution sequence
-
ae
a
sere
a _
18-2017 Sixth Semester, Microprocessor and
Microconty l] 3
e The RST 6.5, RST 5.5 and INTR are level sensitive interrupts H
interrupts the interrupting signal should remain high, until it js Fevopnined: for thes
UNIT-II ye : - Itis used to test . and debug the hardware and software
of an exte
Q.4.(a) Draw and explain chart of program execution as the prototype ofa microprocessor based instrument.
Part of the atiinieat in a ier
assembler. Explain various program development tools used j follow; is a multiwire cable which connects the host system
n it. 8 by an to the system being developed :
Ans. Assembly Language Program Development Tools (6.5)
1. Editor | EDITOR
- An editor is a program which allows you to create a file cont PROGRAM
aining the ass
language statements for your program. embly
[we asm
Example: PC-Write, Wordstar.
- As you type in your program, the editor stores the AS CII codes for the letters i .
numbers in successive RAM locations. - d i
ASSEMBLER
PROGRAM
- When you have typed in all your program, you then save the file on the tag ig 2
This file is @ lied source file and the extension is .asm, ” My file. Ist
_My file obj. | Other obj file
2. Assembler
=e - An assembler programnis is used
U to translate the a ssembly |] LINKER
instructions to corresponding binary codes. When you run ONics ae for PROGRAM
the anemia
source file of your program from the disk whe
re you have saved it after sa
- On the first pass through the source program, the ngeee | |e abs :
| . +S
.
displacement of named data items, the
offset of labels, etc. arid sucete ae
a symbol table. ation Heein OH
PROGRAM
- On the second pass through the source pr
grove Onay
ogram, the assembler
code -forTheeachasseinstmbruct ion and inser ts the offsets, etc. that it calculated durin g the first pass, f
ler generates 2 files on the floppy disk
called object file (.0b/), or hard disk. The first fileis
Myfile. hex
- The second file gs generated ‘ Q.4.(b) Explain the difference between 8085 and 8086 microprocessor. (6)
pivene xtenei n (is) ed by assemb ApS
ler is called the assembler list file and is. | z Ans. 8085 microprocessor vs 8086 microprocessor describes difference between
8085 and 8086 microprocessor types.
8085 microprocessor 8086 microprocessor
It is 8 bit microprocessor It is 16 bit microprocessor
It has 16 bit address line It has 20 bit address line
about the linked files (exe). | It has 16 bit data bus
LR a It has 8 bit data bus
4. Locator 7 | [ae
Clock speed of 8085 microprocessor is Clock speed of 8086 microprocessor vary
-A locator is a program a : a 3 MHz between 5, 8 and 10 MHz for different
object code are to be aaa ae ee ete address of where the segmentsts f versions. _
-A locator pro 7] ; 7 7 egis It has 5 flags. It has 9 flags.
(DOS). EXE2BIN converts EXE2BIN comes with the IBM PC Disk Operating System — It does not support pipelining. It supports pipelining.
5. Debugger a .exe file to a .bin file which has physical addresses. eb BoE It operates on clock cycle with 50% It operates on clock cycle with 33% duty
- A debugge | te 8 ans ca duty cycle. cycle.
system oe aoe os to ed your object code program into 8086 microprocessor supports memory
- 8085 microprocessor does not
gger allo ws oudi esho ot or deb ug it ory loca tionirae
s— support memory segmentation. — segmentation.
- The debu
after your program runs you to look at the cont ents of regi ster s and mem
; of transistors
It has less number of transistors It has more number
compare to 8085 microprocessor. It is
_ noer
thea arn.ws you to change the contents of registers and memory locations andre-run
-It allo ol i compare to 8086 microprocessor. |
It is about 6500 in size. about 29000 in size.
- Some debuggers allow you to sto eek ih a It is accumulator based processor. It is general purpose register based
check or alter after ea
as
P €xecution after each instruction so that you can oe processor.
ch register contents. ‘
‘
; deriy 3
like RD* and WR* (for memory
and I/O devices), DEN* DIR
information made available b y the process ; ‘A
; UR » “o
etc.te
Cc, Sign
ysi al :
has input lines S2*, S1* and S0* S0* andPp CLK. orTh on the status lines. The bus contr USING the| Address Aig'9 hec 1s Ay“17 e ye. ay
It derives the cutouts Ale GEN “nese inputs to 8288 are driy Oller chip FFFFFH {4 eee “12 Air Aig Ago Ang Aoy Ang A,
AIOWC*. The AEN*. IOB an and CEN pinnaefee ne MWC ; IORG#| othe CRY Be a gf pg 1
AEN* and IOB are generally eroee sea ae specially useful for multiproccase om and| FE000H LE e ket ae jones .
gr ed. CEN pin is usually tied to +5y SOr systems | FDFFFH it Pepe age es bs OO OS OO OE 8-8 go gg. G
aH | es eae tts
—+| Reset o,, stTAa FCOOOH«=—stiséd:(C(iédd -
__IN hosel ia be Ee Ore 6° e- 6-6 O06 6 0 6 1
:
Generator
——_» RDY fencen ed Sp MRC
Reset Clk RDY —> S; 8288 f—-> MWIC —~1
—>s, Bus | » bac Tae
ueRe e—s
| - —»| “Controller
ALE eae 4——
Reset Clk RDY DE |
, S» 1 (eee Saai ea a
, J CS ° | ee
S, ; CS, RAM Aue
“> —p} Logic — CSe ROM. 22a
8086 BHE ROM — S Oe S
ie ee -—— CS;
°: OF ’
aR So lO.
~A :
|
|
O pr 2
a KK 1P/st8, Latches — Os 3
16/9 3—
Aid/Sg | 2 0r3.Qi |!
74373 |1 | = ‘
d Os 5
a et
MN / MX 4 & Data Or Pp?
X! buffers”
4. : 74245 |
~ DIR E
4 Yl CSo
RAM
| RO wa aT).
he: 1S
MRDC Mwre °
= Total 8K bytes fof EPROM need 13 address lines A,-A,, (since 2'° = 8k). Address
—
m5 lines A,,—A,, are used for decoding to generate the chip sel ect. The BHE signal goes low
when a transfer is at odd address or higher byte of data is to be accessed. Let us assume
for
that the latched address, BHE and demultiplexed data lines are readily available
interfacing fig. shows the interfacing diagram for teh memory system.
mem ory syst em in this exam ple cont ains in total four 4K x 8 memory chips.
The
parallel to obtain 16 bit
The two 4K x 8 chips of RAM and ROM are arranged in
data bus wi dt h.
If Ay is 0, ie. the add res ses is even and is in RAM , then the lower RAM,
cati ng 8—bi t tran sfer at an even a ddr ess . If A) is 1 i.e. the address is
chip is selected indi
29 201 7
Sixth Semester, Microprocesso
r and Microcont
ro ] ler
odd and is in RAM. The BHE goes low the uppel! [.P University{B.
RAM chip is Selec Tech
that the 8-bit transfer is at an odd address. If .]-AB Publisher
the selected addr “o¢: Further indica 2017-23
respective ROM chips are seledcted. If at a time A, and BHE nee are in ROM, OUT Port C, AL
or ROM chips are selected; i.e. the data
MOV AL, Oth ; pulse to the ADC
|
transfer is of 16 bit : The se ae th OUT
takes place as shown in table. e RAM | Port C, AL
lection of7 Chips h ere MOV AL, 00h
Table. Memory chip selection
OUT | Port C, AL
Decoder UP I/P -5 A, A, Ap Selection geIT: IN
WA AL, Port C ;Check for EOC by
Address/ BHR RO As A) BHE comment
:Ww ces transfer
; reading port C upper and
: on D, > De 0 0 0 Even end’ega “Fae
| oe , a srotating through carry.
pis transfer on D, > D, 0 0 1 Oniy oe ae ae ; mrs ete
in RAM lf EOC, read digital equivalent
;i n AL
bt transfer on D, > D,,, | 0 1 0 Ohieas PPE: In RAM .
= transfer on D, > D,, 1 0 0 ivenaca al €ss in RAM
Se ee on D) > D, 4 0 1 Ongae
Se
i in ROM cs
Vref+ SS
yte transfer on D.> De 1 1 0 Only odd dae SV =
a
|
SS in ROM +SV Vec «Clock up
<D 5,
fsivnaQ.6t . D raw and d explain block dia aeof 825 PA;-PAgK = 4 0,-0,
required to initialize 8251 in gr am 1 in detail. §
asynchronous mode for foll 1
. °
ow: be ie A | rc, E00 BRC eo Pie
(i) 5 bit character length a ios : A, ~ el oe 0808 =
(ii) Event Parity (12.5) LOE GND
(iii) Internal Sync de
tection
(iv) Single syne charac =
.
ter.
- 2
IORD
= Ss
- stop Timer 0
y 1
corresponding bit will be set in thei in service register. Each CLR TRO
y
by
—
0 is started
<4, a
‘Timer
ee
, e passing of ea ch cl oc k,
1. Timer 0 counts up with th th e st at es of FF F3 , FFF4, FFFS,
ts up, it goes th ro ug h
oscillator. As the timer coun
-_-_
on ti l it re ac he s FF FFH. One
DO-D7<=>] Data bus | ve ou
, FF FS 8, FF F9 , FF FA , FF FB, and so un
buffer | FFF6, FFF7 th e JN B instruction
| :Wi : Control lo = in g th e ti me r flag (TFO = 1). At th at po in t,
; ? ae more clock roll s it to 0, ra is
falls through. e D E L A Y su br ou ti ne ends,
by th e ‘n st ru ct io n “ C LR TRO’. Th
ae write /
Read : es t inves
2. Timer 0 is stop ped
ated.
and the process 18 repe s and
—
, pees Prionity Interrupt
oon IRO
<-IRI TL an d T H re gi st er
a <=> |resolver|<==|request e pr oc es s, we m u s t reload the
th
Notice that to repeat
|:
3 R) register |:
:: cole
(RR) start the timer again.
| <= IR7 ‘
———
Siemens and Intel are no more manufacturing ductors about the allocation of these 128 bytes of RAM and examine their usage as stack and
ee
MCU. The list of thess ox ue es along
pani register.
——
with their websites is given at the end.
RAM Memory Space Allocation in 8051
_
it; for some people this might be unnece Py
ene
to spend too many dollars for r beginners | : ; | The 128 bytes of RAM inside the 8051 are assigned the address 00 to 7FH. They
same System when you can make it with a si ngle Making the __ can be accessed directly as memory locations and are divided into three different groups
dollar?. So, price conside rat |
important. You can consult your local mar ket ion is very Ls -as follows —
for this purpose, but in
¢ 32 bytes from 00H to 1FH locations are set aside for register banks and the
stack.
read/write
e 16 bytes from 20H to 2FH locations are set aside for bit-addressable
memory.
write storage; it is
° 80 bytes from 30H to 7FH locations are used for read and
Cre -
7FH
cm Scratch pad RAM
Bit-Addressable RAM
Register Bank 3
=| Register Bank 2
—— (Stack) Register Bank 1
Register Bank 0
* Light sensing & controll
ing devices A
Temperature Sensing
‘
and controlli ng devi
ces
\ -
wo w
6
0OxB8
wWwwwwmww
The second bank of registers RO—-R7 starts at RAM location | ae CJNE R1,#data,reladdr
08 and go 0xB9
' 2:
OFH. The third bank of RO-R7 starts at memory location 10H
and Seeee 7 = tions o CJNE R2,#data,reladdr 0xBA
17H. Finally, RAM locations 18H to 1FH are set aside for the
fourt h bank ° ofoca
ROe-R7”
A
CJNE R3,#data,reladdr 0xBB
Default Register Bank
CJNE R4,#data,reladdr OxBC
If RAM locations 00-1F are set aside for the four re
Oe
ister CJNE R5,#data,reladdr
bank of RO-R7 do we have access to when the 8051 is Seno a he ich Tegister 0xBD
register bank 0; that is, RAM locations from 0 to 7 are accessed ith th CJNE R6,#data,reladdr OxBE
Oa
© answer jg
R7 when programming the 8051. Because it is much
easier to refer thes RAM rot CJNE R7,#data,reladdr OxBF a | C
by names such as RO to R7, rather than by their mem or
y locations, eae locationg . Description: CJNE compares the value of operand1 and operand? and branches to
How to Switch Register Banks the indicated relative address if operand and operand2 are not equal. If the two
operands are equal program flow continues with the instruction following the CJNE
instruction. l
desired register bank, since they can be accessed by the bit addicts 3 oe
HBG ss | eee cn soweewers
ae h CLR. For example, “SETB PSW.3” will set PSW.3 = 1 and select tie - a ee Q. Gi) CPLA
ae te ee
Ans sw oe all the bits in the Accumulator will be reversed. This can be thought of as “Accumulator
Ee ae oe _ Logical Exclusive OR 255” or as “955-Accumulator.” If the operand refers toa bit of an
Operation: | SWAP ; : - output Port, the value that will be complemented is based on the last value written to
a Swap Accumulator - “Nibbles that bit, not the last vate read from it.
yntax: SWAP A = Q. (iv) ANL destination, source .
-
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80+2017 Sixth Semester, Microprocessor and Microcontro]ley
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FIRST TERM EXAMINATION [FEB. 2018]
_.__
ra SIXTH SEMESTER [B.TECH]
_ MICROPROCESSOR AND MICROCONTROLLER
[ETEE-310]
Time: 1%hrs. M.M. : 30
+ Note: Q.No.1 which is compulsory. Attempt any two questions from the rest.
Q.1. (a) Write the instructions to move value 5FH in memory location 3000H
using indirect addressing mode in 8085 microprocessor. (2)
Ans. LXI H, 3000H
MVI A, 5FH
MOV M,A
HLT | : |
Q. 1. (b) Explain the concept of segmented memory in 8086? | (2)
Ans. Memory Segmentation in 8086 Microprocessor .
| Segmentation is the process in which the main memory of the computer is divided
_ | into different segments and each segment has its own base address. It is basically used
_ | to enhance the speed of execution of the computer system, so that processor is able to
| fetch and execute the data from the memory easily and fast.
- The Bus Interface Unit (BIU) contains four 16 bit special purpose registers
_} (mentioned below) called as Segment Registers. |
i \ Code segment register (CS): is used for addressing memory location in the code
- | segment of the memory, where the executable program is stored.
: Data segment register (DS): points to the data segment of the memory where
+= | the data is stored. | es
a Extra Segment Register (ES): also refers to a segment in the memory which is
en
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LF
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T, Tt Ts T, qT; oe he. Ts <n name of the logical segment should be used for a specified segment. The 8086 works
directly with only 4 physical segments: a Code segment, a data segment, a stack segment,
and an extra segment. |
Example: ASUME CS: CODE; This tells the assembler that the logical segment
named CODE contains the instruction statements for the program and should be treated
as a code segment.
Junspeciiep 20H memdyHigh-order
address |. q
ASUME DS: DATA; This tells the assembler ti.at for any instruction which refers
Low-Order Low-Order to a data in the data segment, data will found in the logical segment DATA.
EQU Directive: The EQU directive is used to give name to some value or symbol.
‘ OOH ==( SEH Opcoda-+--<-<== ' --+439Hidata oi
AD Kach time the assembler finds the given names in the program, it will replace the name
____ | Memory addres Memory address ; with the value or a symbol. The value can be in the range 0 through 65535 and it can be
another Equate declared anywhere above or below.
The following operators can also be used to declare an Equate:
THIS BYTE
M
Y Status 1D/M =0. [S,& S, ‘Opcode lO/M = S,|& S,= Status line THIS WORD
‘ Th Aes
S. “= $Slatus Tine fetch THIS DWORD
A variable-declared with a DB, DW, or DD directive — has an address and has space
reserved at that address for it in the .COM file. But an Equate does not have an address
1 D
or space reserved for it in the .COM file.
Example:
Here is description of what happens in the system bus until the instruction MVI A-— Byte EQU THIS BYTE
32H is executed (again I will explain a generic microprocessor rather than 8085): | DB 10
= The Program Counter loads the memory address 2000H into the address bi A_ word EQU THIS WORD
during T1 of the Op. Code machine cycle. . 3 = _ DW 1000 |
* The address decoding system locates and identifies the memory location A_ dword EQU THIS DWORD
20008
* At T2, the Timing and Control unit produces the MEMR-signal (Read) which las DD 4294967295
during T2 and T3. During this window of time the memory places the Opcode 3EH fror g Buffer Size EQU 1024
location 2000H into the data bus. | ae Buffer DB 1024 DUP (0)
* The operating system places the Opcode in the Iastruction Register then into tht
Buffed_ ptr EQU $ ; actually points to the next byte after the 1024th byte in buffer. .
Instruction Decoder. When the Instruction Decoder decodes the Opcode it feeds thy
decode d signal into the Timing and Control Unit. The fetch operation is completedit Q. 3. (a) Explain all the addressing modes of 8086 with suitable example. (5)
73 Ans. Addressing modes: The method by which address of source of data is given
* The Program Counter is incremented to 2001H. alongwith instruction is called as addressing mode of source. -
¢ During T4, the Timing and Control unit finds out that a second byte which contains 1. Immediate addressing mode (IAM): If 8/16 bit data required for executing the
| instruction
is given alongwith the instruction, then it is called immediate addressing mode.
the data needs to be read (i.e. address 2001H).
* The second machine cycle is Memory Read cycle. - Example: 1.MOVAL, 75H
. 2. MOV BX, 7506 H; 7506 H > BH BL
* At the T1 of the 2nd machine evc] aitthe :
address 2001
Sta A Ans tine yele the Program Counter loads 2. Direct addressing mode (DAM): If 8/16 bit data is present in memory and 16
bit E.A. of this memory location is given alongwith the instruction, then it is called direct
* The address decoding system locates and identifies the memory location 2001H. ; addressing mode instructions.
* At T2 the Timing and contro] oa ° ‘
and T3. During this window of tim unit produces MF'MR signal which lasts during T
it
Example: MOV AL, [9106H]
the MPU. ie the data 32H is placed into the data bus then int : 3. Register direct addressing mode (RDAM): If 8/16 bit data required for
* During the rest of T3, the executing the instruction, is present in register and the name of register is given
data 32H is stored into the accumulator.
Q. 2. (b) Explain: DB alongwith the instruction, then it is called RDAM instruction.
»ASSUME and EQU assembler directives with examples:
Ans. DB-The DB
a
dir ective
sa (5)
Example: MOV CX, BX
4. Register indirect addressing mode (RIAM): If the data is present in memory
is used to declare a BYTE -2-BYTE variable
“is made up of 8 bits. -A BYTE and the E.A. is present in a register, then it is called RIAM instruction.
Declaration examples: KA=(BXJASU/ADI) ~
Bytel DB 10h | | Example: MOV CX, BX
Byte2 DB 255 ; OF Fh, the max. possible for a BYTE 5. Register relative addressing mode (RRAM): Data is present in memory
CRLF DB 0Dh, 0Ah, 24h; Carriage Return, terminator BYTE ocation and the EA = [BX){BPV[SI/[DI + 8/6 bit displacement.
Example: MOV CX, 97H [BP]
y ae i sy >‘ and peel wy eke ae
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ie 5 -
5 es AS
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9
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4 hg ie — - - ? 4 Pas) x
f ’ Fy ’ wae: see Bs 24 SEL SSS te
- a 5
*
*
1s
to backup memory.
at ee
F at ad
¢ The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor
*If there is any interrupt it accept the interrupt and send the INTA (acti ene
Me eae
receives HOLD and TRAP at the same time then HOLD is recognized first and then
nl
Hf /
TRAP is recognized). | |
* The vectored address of particular interrupt is stored in program counter. —_— ¢ There are two ways to clear TRAP interrupt.
¢ The processor executes an interrupt service routine (ISR) addressed
in program ae 1. By resetting microprocessor (External signal)
counter. . Ax | | Oe
~
—
OP CO DE on th e da ta bu rrupt
ra te d b y the 8085 to transfer the addi tion 4
dg e ma ch in e cy cl es ar e ge ne
acknowle bytes TRAP Edge and level 1 No 0024H
into the microprocessor. RST 7.5 Edge gQnd Yes 003CH
808 5 sav e the ad dr es s of next ins tructi on ta 4
4. On receiving the instruction, the RST 6.5 Level grd Yes 0034H
stack and execute received instruction. |
RST 5.5 Level Ath Yes 002CH
SIM and RIM for interrupts:
i
| INTR Level 5th Yes -
© The 8085 provide additional masking facility for RST 7.5, RST 6.5 and Reps
Ny
,
e The format of the 8-bit data is shown below.
*
Se * ee
eS ask
And | f 0030H
Be Bs 6De PDs sDypD5. 47D; Do
—
RST diana 002CH
4 ee Pakee
SOD/SDE}] X |R7:5|MSE|M7.5|M6.5|M5.5
a2 frase 0028H
0024H
= Available —
Serial output data<— | —® RST 5.5 mask pol > TRAP
1 = mixed
Serial data enable \_____» R EK 0020H
if, SDE=1, bitD———_ Don't Se Rese? oy To ude Getet RST 0018H
is send to SOD line care ®RST 7-5mask 5it Pabe INTR
Any recognised
interrupt
hierdie
enable FF fea) 00 a
0010H
9008H
if SDE = 0, bit D, is —> Mask set enable~
ignored If, MSE = 0, Do. D, ans 0000H
and D, are ignored if. — .
Q. 4. (a) Write an assembly language program to gener ate Fibonacci series
MSE. 1, mask Js set.
upto first ten terms using 8085 instructions. (5)
>» Reset RST 7.5
FR7.5=1:RSTZ Ans. MVI D, COUNT ; Initialize counter
is not allowed. MVIB, 00 ; Initialize variable to store previous number
lfR 7.5 = 0: RST 7. MVI C, 01 ; Initialize variable to store current number
is allowed. MOV A, B; [Add two numbers] — |
Fig. Format of 8-bit data to be loaded in accumulator in accumulator
BACK: ADD C ; [Add two numbers]
_ before executing sim instruction MOV B, C ; Current number is now previous number
: The status of pending interrupts can be read from accumulator after executia
al MOV C, A; Save result as a new current number
RIM instruction: DER D; Decrement count
* When RIM instruction is executed an 8-bit data is loaded in acc
umulator, which _JNZ BACK ; if count 0 go to BACK
can be interpreted as shown in fig. HLT ; Stop.-
Q. 4. (b) Write an assembly language program to find square of a 16-bit
Ds D, D; D, D, Do number stored at location 2000H of data segment. Also store the result
at location
3000H. (5)
SID 17.5 16.5 15.5 lE M7.5 M6.5 M 5.5
Ans. LXI H, 2200H : Initialize lookup table pointer
~
_LXI D, 2000H : Initialize source memory pointer |
|. Mask status off
Serial Input Data <—
TPeRSTSS LXI B, 3000H : Initialize destination memory pointer
= Unmarked
Interrupt pending
_» Mask status of MOV A, M : Get the square
RST 7.5 j
STAX B : Store the result at destination mem ory location
Dit
6. ‘The interrupt requests are individually mask-able. RET Returns from subroutine 1 4
7. The operating modes and masks may be dynamically changed by the software RETI Returns from interrupt subroutine 1 4
at any time during execution of programs. AJMP addr1il Absolute jump 2 3
8. Itaccepts requests from the peripherals, determines priority of incoming
i request :# LJMP addr16 Long jump | 3
checks whether the incoming request has a higher priority value than the level SJMP rel Short jump (from —128 to +127 2 3
currently being serviced and issues an interrupt signal to the microprocessOm locations relative to the following
9. It provides 8 bit vector number as an interrupt information. instruction) 3
10. It does not require clock signal. JC rel Jump if carry flag is set. - 2 3
11. It can be used in polled as well as interrupt modes. Short jump.
JNC rel Jump if carry flag is not set. a. 3
12. The starting address of vector number is programmable.
3 Short jump.
13. It can be used in buffered mode. JB bit,rel Jump if direct bit is set. 3 : 4
Q. 1. () Compare the merits and demerits of asynchronous communication 3 7 Short jump.
with sychronous communication. | , a JBC bit,rel Jump if direct bit is set and clears 3 4
Ans. Asynchronous Communication | | | bit. Short jump. —
Advantages: JMP @A+DPTR Jump indirect relative to the 1 2
| DPTR | Bre
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micreprecesoer? Expisin alt Proeramniable roginteny an C,-carry flag: If an arithmetic operation results in a carry, the C 41s set, otherwise
it is reset.
Ans. Block diagram of 8085 micro Es | i DD 0. Db Bb BD, D,
SZ EXACT XEP Tx cy
>
X-don't cares.
Timing & Control Unit: This unit synchronizes all the microprocessor operations
Ke with the clock and generates the control signals necessary for communication between
the microprocessor and peripherals. The control signals are similar to a syne pulse in an
, ;
‘ae
mae he
oscilloscope. RD and WR pulses.
- _Instruction Register and Decoder: These are the part of ALU. When an instruction
is fetched from memory, it is loaded in the instruction register. The decoder decodes the
t
Register array: B, C, D, E, H, E are the general purpose register. W and Z are the
te I
_. temporary register. | a
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.
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: Ans. The AD oAD 7 lines . Schematic diagram to latch low order address bus.
hy 2Ass
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Sixth Semester, Micro
processor And Microcon
troller
Q. 2. (c) What are the diff
: ere nt vectored j : ‘ a oe University-{B.Tech]-Akash Books 2018-15
| No condition needed if it is a plain jum
Ans. Refer to Q. 3. (b) of First Term Examination 2018 (4.5) =| check some status flags to do this jumping P instruction otherwise sometimes it can
action in memory.
Q. 3. (a) Write a pro us a Jump Instruction
numbers 3AH and ain aad to dhapiny thi uuagaces
Ge eae NC aS Sea eam ITE ero
Ans. MVI A, 3AH; Move immediate 3AH into a pile vm oe ae ) The program sequence is transferred to the memory
ADI 48H; Add immediate accumulator with 48H | es gibt —— oe a oo ena
OUT 01H; Store the result of accumulator at output port
01H . 3 ;‘le ae sas caus PE CTs mmian eageemes
HLT; Stop a | | 4 : =
7 | | 2. JC: - (conditional jump
Q. 3. (b) Explain how many times the following loop will be sseeuten: (5) 4q or a 16-bit PPO if Si Cteure ees oe
LXI B, 0007H a} Kg: - JC ABC Gump to the level abe if C=1) 3
LOOP : DCX B eos | 3 s 3. JNC:- (conditional jump) The program sequence is transferred to a particular
MOVA,B | ; Oe 4 level or a 16-bit address if C=0 (or carry is 0)
ORAC ta | a Eg: JNC ABC (jump to the level abe if C=0)
_JNZ LOOP | ; 3 = = : 4. JP: - (conditional jump) The program sequence is transferred to a particular level
Ans. 7 times | — or a 16-bit address if S=0 (or sign is 0)
Lx1IB.0007H tao | sees , : | 4 Eg: - JP ABC (jump to the level abe if S=0)
Loop: DCX B ae pose aries | eis : | 4 a 5. JM: - (conditional jump) The program sequence is transferred to a particular level
MOV A,B — Sood | eee s a Ne = ora 16-bit address if S=1 (or sign is 1)
| 7 | = ane 2385 ale Eg: - JM ABC (jump to the level abc if S=1)
PEAS 5 | a | NS i ee oe i 4 6. JZ:- (conditional jump) The program sequence is transferred to a particular level
_JNZ LOOP - o | eu es Se , ae or a 16-bit address if Z=1 (or zero flag is 0)
‘ _ Load Immediate register pair BC with 0007H | | - Eg: - JZABC Gump to the level abe if Z=1) |
| | | a = oF 3 7, JNZ: - (conditional jump) The program sequence is transferred to a particular
at DCX B - reduces the contents of BC pair Ae | ae a level or a 16-bit address if Z=0 (or zero flag is 0) ©
Z = | P20 C206. 3. cae cae - Eg: - JNZ ABC (jump-to the level abe if Z=0)
ious - MOVA, B= : se a . A-=-00 | BE ao nerare 3 é aa 8 JPE: : (conditional jump) The program sequence is transferred to a particular
7
Be - Bhit 16 bit 7 es : | = Jas pate 2s . $53 | a ~. - level or a 16-bit address if P=1 (or parity flag is 1)
=
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Q. 4. (a) What is the main difference between minimum and maximum mode
ER oeTe RN =
(2.5) = Ans. Case 1: Minimum mode configuration of 8086: If pin number 33 of 8086 is
Ree ar Nee 2
1p
re fens
5
ae eet ot
jump is encountered, the processors loada new address from where it 8086 will have the function as shown in the parenthesis, next to these pins.
,Rha
’
wr
J
16-2018 Sixth Semester, Microprocessor And Microcontroller
I.P. University-(B.Tech]}-Akash Books 2018-17
“on Nad output is enabled. When DEN = 1, the transceiver output floats in tristate. So, DEN
A x |
is used to enable the transceiver. This output is active low during each memory and I/O
31+ ROGT, / oN access. |
30 {+ Rar,zt| ~ (HLDA) | we" THE MINIMUM 7. HOLD and HLDA: Both HOLD (pin 31) and HOLD acknowledge (HLDA)i.e.,
29+ LOCK| (WR pin 30 are used for DMA (Direct Memory Access). We have already discussed DMA earlier.
8086 7K epee Case 2: Maximum Mode Configuration of 8086: If pin number 33 of 8086 is
CPU +S, | : (Mid)
connected to logic 0 then the processor operates in the maximum modes. The
27-+- S, 1 (OTM) configuration is quite complex and is used for the multiprocessor systems. Herein, pins
| eS, | EN 24 to 31 have functions described outside the dotted line in Fig. 1. Like now pins 26,27
25 as, \ (ALE) _ and 28 works as Sy,5; and S, respectively. These are control bus signals.
24- as, \(INTA)
INTA)
|/
\ f To achieve maximum mode for use with external coprocessor, the MN/ MX pin must
Vio
be connected to ground. Let us see the pins of this mode now
_ Please note here that pins 24 through 31 have dual functions depanding on the mode
1. S,,S, and S, : Status bits show the function of the current bus cycle. Such.
of operation. signals are normally decoded by 8086 bus controller. Let us see ina tabular
form, their functions.
In minimum mode, for example, pin
29 acts as write. (WR)- This pin will go low
Functions
OC Of,W|
when 8086 wants to carry out a operation on memory or ports. Also note that the minimum
OoOrRrF
OCrF OC]
mode of operation is suitable for a single processor systems. Interrupt acknowledge
SHOR
OOO oO
Let us now study the signals which correspond only to minimum mode shown in I/O read
dotted lines above. I/O write
Halt
1. M/IO (Memory/IO ): In minimum mode, pin number 28 acts as Memory/OQ.
Opcode Fetch
a
ee
output line. The status of this pin indicates whether memory is being accessed or VO - Memory Read
port is being accessed by CPU. | Memory Write
HE
rr
If M/IO = 1 then CPU is accessing memory.
Be
Passive
: else if MIO =0 then CPU is accessing I/O devices.
3 2 Write WR: It is an output an number 29. If processor wants to perform a write '. 5
“ag A
2- RO/GTI and RO/GTO :The request/grant pins request DMA during maximum
mode operation. Both these lines are bidirectional and are needed to request and grant
oy
a
= operation on memeory and I/O devices then the WR pin gives low. a DMA operation.
OS | 3. INTA (Interrupt Acknowledge): It is an active low signal which is sent tit e 3. LOCK: The lock output is used to lock peripherals off the system. This pin is
fc, ae interrupting device to tell it that its interrupt requiest has been accepted. ~ a activated by using the clock prefix on any instruction.
5 ae 4. ALE (Address Latch Enable): It is an active high output line (Pin no. 24). If 4 4. QSI and QSO: The queue status bits show the states of the internal instruction
e 2 = ALE « 1, it indicates that address is present on the multiplexed address/data bus. This queue. These pins are provided to access numeric math co-processor (8087). The operation
strobe (ST B) inp uts of the ext ern al lat che s to strobe in ; a
ALE signal is connected to the of the queue status bits is in truth-table below:
: a= or latch this address into them. Qs, Qs, Function
a |= ae 5.DT/R (Data Transmit/Receive): 1 output pin of 8086 in minimum peas that 0 0 Queue is idle (NOP)
0 \ae First byte is opcodes
the direction of flow of data on the data line.
~
a2 fs _ decides
2 0 Queue is empty
: _«‘IfDT/ R = 1 then data flows out from CPU. 1 1 Subsequent byte of opcode
an a * °
microprocessor? (4)
-
6. DEN (Data Enable): It is : an output pin number 26 in the minimum mode DEN
» nh , q
A ‘ ‘
Aa
4
-e Itis possible to enhance the memory size of code data or stack ge BMents7
hey, Theoe LEA, LDS, 2 and LESI Anstructions — The LEA, LDS, LES instructions
; provide
64 KB by allotting more than one segment for each area. ; =a ‘ ie el ay ira eater ae addresses by loading either a 16-bit offset address
| ee - er or a register together with a segment address i
_ Physical | DSorES e.g. LEA SI, [(DI+BX+5H]} aero
- EFFEF
addressH _ Memory <= Hlghent nadie a3 a
xe Following g is the € table showi
table showing 7 of data transfer instructions:
the list :
7FFFFH - | =~ OPCODE | OPERAND EXPLANATION EXAMPLE
Extra a Mot me he MOV AX, [SI]
| , | | =2 ese rioht | | 2 oe a PUSH D pushes D to the stack PUSH DX
our segment registers : an 3
in BIU ea «. a S POP D pops the stack to D POP AS
Es} 7 1010.10 SFFFF H + Top ot saa me 6| PUSHA none put all the registers into the stack _ PUSHA
eed ag 025-010 2] | Stack ee ie POPA none gets words from the stack to all registers | POPA
SS 41.5 102] 0-1-0 3} | Segment a a XCHG D,S exchanges contents
of D and S XCHG [2050], AX
DS} 2 }|0]0 ]0 SS 50000 H <— Bottom of stack segment g IN D,S copies a byte or word from S to D IN AX, DX
wa 2800, <— Bottom of Data segment — PUSHF none copies the flag register at the topofthe | PUSHF
ae . Ce | stack
3 POPF none copies a word at the top of the stack POPF
te | to the flag register
DS =Q.1000
4. (c) The icontents of diff erent registers
. in 8086 are |
given by CS = a
F000H, Here D stands for ‘nati
destination and S stands for source.
Find a ee saa andES=3000H ee . 5 a D and S can either be register, data or memory address. ee
on - . address of the different segments in the memory. 7) Q. 5. (b) Write an 8086 assembly language program to find the factorial of
FO00H re BIVEN the question contents of different _ the given byte of data using a recursive algorithm. 7 (6.5)
, DS register = 1000H, SS reo; “rent registers in 8086 are CS register = .
Me Riis -eiaas ee re register = 2000H & ES r egister = 3000H “Ans. Program —
be ae:
in the memory, so both will - registers ee
be aeis used to store the base address; of different segments ADDRESS | MNEMONICS COMMENTS
CS memory et mina | Saree Bh 0400 MOV CX, [0500] ! CX <- [0500]
[Jer . = ’ D a : :
3 _ =2000H, & ES memory segment = on Segment = 1000H, SS memory segment | 0404 MON-AE; 0001 | Ae <= 0001
ae : Q. 5. (a) Explain the di ae ao 2 : Sg / eens i ~ 0407 MOV DX, 0000 DX <- 0000
examples for each. aifs ransfer instructions in 8086 giving | 040A = MULCK 3 DEAR S AK CE
0
me
0
POG 0 ers ae ey
ee
te? =
2
ACK p
ot:
e
eRe
= 1 xX
igtae er
2
wl grace
For example, if port B and upper port C have to be initialized as sue ports and
eth Ut
Se 2. The printer is informed of the eso ofa byte of data to be printed by activating
2. Mode selection bits, D,, D;, Dg are all 0 for mode 0 operation.
STROBE input signal. - 3. Port B and upper port C should operate as Input ports, hence, D,
= D, = 1.
‘8, Whenever the printer receives the dati it informs the sander by activating a 4, Port Aand lower port C should operate as Output ports, hence,
D, ==D)= =0.
t=2
- output signal called ACK (acknowledge). 4
red oper atio n, the cont rol wor d regi ster will have to be loaded
~ Hen ce, for the desi
Input/Output mode: This mode is selected when D, pit of the Control Word Registé at) with "10001010"== 8A (hex).
is 1. There are three I/O modes: \ ; xa 5
Mode 0 - simple YO .
1. Mode 0- Simple /O FPA EY Sa In this mode, the ports can be used for simple I/O operations
without handshaking
| CE pS, - ves of port C can be=
a ‘Mod1e- Strobed I/O a - Port A, port B pro vid e sim ple I/O ope ra tion . The two hal
See Ni can be use d as individual
“3 Mode 2 - Strobed Bidivortional ue. Gener as an add iti ona l 8-bi t port , or the y
e ies be used such that
the two hal ves of por t C are ind epe nde n t, the y may
Control Word format as an inp ut por t whi le the oth er hal f is ini tia lized as an output
one halfis initialized
port.
22-2018 Sixth Semester, Microprocessor
And Microcontro]]
er
The input/output features in mo
de 0 are as follows:
1. Output ports are latched. I.P. University-[B.Tech|-Akash Books
2018-23
2. Input ports are buffered, not la 1. Two ports t.e. portA and B can be used as 8-bit i/o ports.
tched.
3. Ports do not have handshake or 2. Each port uses three lines of port c as handshake signal and remaining two signals
interrupt capability.
4. With 4 ports, 16 different comb can be used as V/o ports.
inations of I/O are
Possible. 3. Interrupt logic is.supported.
:
Latched’ : means the bits are i aa
4. Input and Output data are latched.
Input Handshaking signals
1. IBF (input Buffer Full) - It is.an output indicating that the input latch contains
information.
2. STB (Strobed Input) - The strobe input loads data into the port latch, which holds
the information until it is input to the microprocessor via the IN instruction.
3. INTR (Interrupt request) - It is an output that requests an interrupt. The INTR
pin becomes a logic 1 when the STB input returns to a logic 1, and is cleared when the
indeterminate. data are input from the port by the microprocessor.
4, INTE (Interrupt enable) - It is neither an input nor an output; it is an internal bit
Mode 0-input mode
| programmed via the port PC4(port A) or PC2(port B) bit position.
- Output Handshaking signals
1. OBF (Output Buffer Full) - It is an output that goes low whenever data are
output(OUT) to the port A or port B latch. This signal is set to a logic 1 whenever the
. desired port using A, an ACK pulse returns from the external device.
d A, lines
2. ACK (Acknowledge)-It causes the OBF pin to return to a logic 1 level. The ACK
The signal is a response from an external device, indicating that it has received the data
device via theCPU then issues an RD si
System data bus. . a from the 82C55A port.
Mode 0-output mode | a 3. INTR (Interrupt request) - It is a signal that often interrupts the microprocessor
when the external device receives the data via the signal. this pin is qualified by the
| In the output mode, the CP
U sends data to 8255 via sy
stem data b us and then
|
internal INTE(interrupt enable) bit.
the external peripheral port
s receive ae Ag | 4. INTE (Interrupt enable) - It is neither an input nor an output; it is an internal bit
programmed to enable or disable the INTR pin. The INTE A bit is programmed using
a rl
a J
Pp by making CS low. It then selects the desired the PC6 bit and INTE B is programmed using the PC2 bit.
eal
cS
AD 7523
a
5 NC
B, 6
MODEL SMALL
Interfacing.Analo: g to Digital pe
Converters . Data e STACK 100
e DATA |
; Co nt ro l po rt ad dr es s for 8255
CONTROL EQU OFFC6H
O F F C O H; Po rt Aa dd re ss for 8255
PORTA EQU
; Po rt B ad dr es s fo r 8255
PORTB EQU OFFC2 H
C 4 H ; Po rt Cc ga de ce e fof r 8255
PORTC EQU OFF
e CODE Pe
a
| : |
START:
‘I ni ti al iz e D a t a s e g m ent
MOV AX, @DATA;
MOV DS,AX
ee ae
3
s ; <a
Fi
ig. | , “a4
;
H In it ia li ze al l p a y as output
MOV AL,80
7
oe: ip ;. mr pin diagram of AD7523 is shown in fig the supply range is fro OUT DX,AL ;Ports
BL an al og eq ui va le nt to 5V
gynue may be any where between -10V to + 10V. The maximum analo me +OV to +16 MOV BL, FFE} ‘Take are
in
aiks | : & yeaa volt
926-2018 Sixth Semester, Microprocessor And Microcontroller
iS
MOV BL,FFH ; To generate same wave this procedure is repeated is used to reset the microprocessor.
f
-
é
e
CS Chip Select: When this pinpin 1s; set to low, it allows read/wri
a.
JMP RAMP
=>
= ‘
read/write operations, else
=
this pin should be set to high.
ti ra
>
iS
INT 03H |
‘
rete
i -.
5
qn,
=e
A,: This pin indicates the transfer of command/status information. When it is low
«
-
a it indicates the transfer of data.
S
Q. 7.(b) Draw the functional pin diagram of keyboard and displav cani..u__ 4%
spl
play
ay at
controller RD, WR: This Read/Write pin enables the data buffer to send/receive data over the
:
(8279).
5 | (4.5) data bus. | )
Ans. 8279 pro grammable keyb oard /dis
interfaces a keyboard with the CPU. The keyboard
play cont roll er is desi gned by Intel that. IRQ: This interrupt output line goes high when there is data in the FIFO sensor
first scans the keyboard and ide fe
7| : RAM. The interrupt line goes low with each FIFO RAM read operation. However, if the
if any key has been
: pressed. It then sends thei eir relative response of the el Ae
FIFO RAM further contains any key-code entry to be read by the CPU, this pin again
the CPU and vice-a-versa. - : ee ney e
goes high to generate an interrupt to the CPU.
8279 — Pin Description
a 'q
Vg: Voc: Lhese are the ground and power supply lines of the microprocessor.
The following figure shows the pin digesta of 8279 in 2+ ial
A
Ae
. Ht »
SL, — SL,: These are the scan lines used to scan the keyboard matrix and display
the digits. These lines can be programmed as encoded or decoded, using the mode control
,
/ an ,
—
: t
~
A
Ss
Aare a B
we 5
register.
RL, — RL: These are the Return Lines which are connected to one terminal of keys,
while the other terminal of the keys is connected to the decoded scan lines. These lines
are set to 0 when any key is pressed.
in
SHIFT: The Shift input line status is stored along with every key code in FIFO
it is pulled up
the scanned keyboard mode. Till it is pulled low with a key closure,
| |
internally to keep it high
TB - CON TRO L/S TRO BED I/P Mode : In the keyb oard mode , this line is
CNTL/S
as a contr ol inpu t and stored in FIFO on a key closure. The line is a strobe line that
used
has an internal pull up.
enters the data into FIFO RAM, in the strobed input mode. It
The line is pulled down with a key closure.
for blan k disp lay. It is used to blan k the disp lay duri ng digit switching.
BD: It stan ds
- OUTB ,: Thes e are the outp ut ports for two 16x4 or
OUTA, — OUTA, and OUTB,
lay refresh regis ters. The data from thes e lines is synchronized
one 16x8 internal disp
the keyboard.
with the scan lines to scan the display and
:- Ther e are two mode s of oper atio n on 8279 — Input
Operational Modes of 8279
Mode and Output Mode.
| , %
Input Mode | e
gi ve n by th e ke yb oa rd an d thi s mo de is further
This mode deals with the input
classified into 3 modes.
28-2018 Sixth Semester, Microprocessor And Microcontrolle
r
iP, University-
* Scanned Keyboard Mode- In this mode, the key {B.T ech]-Akash
matrix ¢ an be j inter Books
either encoded or decoded scans, In the encoded scan, an 8x8 key faceed ug 3 2018-29
Xtal
scan, a 4x8 keyboard can be interfaced. The code of key Oscillator
pre
CONTROL status is stored into the FIFO RAM. ned with =
* Scanned Sensor Matrix—In this mode, a se
d Xtal 49 To Peripherals Timer
nsor array can b e interf —» interrupt
processor using aced Wi |
either encoder or decoder scans. In the encoder vy
Serial
sca . port
or with decoder scan 4x8 sensor matrix can be int PD
erfaced. IL To
Strobed Input — In this mode, when the co | : CPU
ntrol linej S set to 0, t
return lines is stored in the FIFO he data nt <|
byte by byte.
Output Mode
8051 Power Control Logic
This mode deals with display-
8051 has two power saving mode,
into two output modes.
¢ Power Down Mode
Display Scan- This mode allo e Idle Mode :
ws 8/16 character
organized as dual 4-bit/sing Difference Between Power Down & Idle Mode
le 8-bit display units.
* Display Entry — This mode As shown in above figure of 8051 power control logic, two control bits axe there, IDL
allow
the right side/left side. and PD, which are used for Idle and Power down mode respectively.
|
In Power Down mode, the oscillator clock provided to system is OFF i.e. CPU and
peripherals clock remains inactive in this mode.
In Idle Mode, only the clock provided to CPU gets deactivated ,whereas peripherals
clock will remain active in this mode.
Hence power saved in power down mode i is more than in idle mode.
Below table shows power supply current required to 8051 family controllers in
Normal (Active), Idle and Power down mode.
Operating
| . Oscillator
Ans. 8051 Assembly Current required in
2 S complement program 8051 Controllers | Frequency] Current required | Current
ORG 0000H | Fosc.. in Normal mode | required in Idle mode| Power Down mode
crocontroller in
e
‘ z
( Se
7 = aes Idle mode. CPU clock turned off whereas internal peripheral Si = | Interrupt Number Interrupt Description Address
such as timer, serial port, interrupts works normally. I Pheral module —
Interrupt and H/W reset can c; : cae aay oe
eee saat: | ; te 1 _ Timer/Counter0 o00B8h
0 = Disable Idle mode. es 2 External INT 1 0013h
|
Q. 99. (b) Write the format of the 8051 processor status word (PSW) 4 001Bh
: :
Ans. 8051 FLAG BITS AND THE PS | 2 ‘
| Lhe
— see
‘RE SET’ all the int errupt s get dis abl ed, and the refore, ali aan es
Upon if anyone or all are activated,
i errupts, , if
OVOLIS
ster. In this: section we discuss variou©s bits of _
| nust be enabled by a software. In all. these five int
re. All these interrupts
Best interrupt flags as shown in the figure.
‘hi ~ a 7 nding
OE : 7
of how itheis altered. jue ecahe a in some special function register that 1s Interrupt Enabled
_ used to change the bank registers Tc ne esi HSI, respectively,ire and are‘Ss INT1 1 it interrupt
| and PSW.1 bits are general-purpose status flag bits and
E
oC ies section. The PSW.5
ale .
tA
,
Foley
for any purpose. In other words, they are user definable © usec! by the programmer Trim 3
| _ [ey [Ac [Fo |Rsi[RS0 [Ov |-|p 3
CY -~—s PSW.7 Carry flag. =
re oo a PSW.6 Auxiliary Carry flag Low Priority
tar ie: FO. te PS5W.5 Available to the user for general ae
aces
ee ver, oa 1 PSW.4 Register Bank selector bit1, re |
_
ee ~RSO
ea PSW.3_ Register
) Bank
: selector bit 0 0.
ector bit Sapa upt structure of 8051
tae mi microc onkrolie®:
:
fe. PEW. User-definable bit. sane a (T™ ' ‘pit addressable register in which EA must fe p©articular
‘Interrupt Enable bles na
. disabling the intermuP™ Thea ¢corresponding bit in this register e
Bea Parityateflag.
PSW.0 _ indic Set/cleared by hardware each ing, a for enabling inte rrup ts.
an odd/eyen number of 1 bits in the nue men eyele to,
ator, umul a argon
7 4
Ave
’ &) .
; ; _ > af
™ » | pee
re tae ce \
‘ pin
32-2018 Sixth Semester, Microprocessor And Microcontroller
interrupt like timer, external and serial inputs. In the below IE register, bit COrreg itp - :
to 1 activates the interrupt and 0 disables the interrupt.
Dy | Ds | Ds | Ds | Ds | De | Di | D |
SAleZ ee PAC Bp E Fe CY
All of the three flip flop set and reset according to the stored result in the accumulator.
1. Auxilliary carry (AC)- If any carry goes from D3 to D4 in the output then it is set
otherwise itis reset. | Be
in its final
2. Carry (C) - If the result stored in an accumulator generates a carry
output then it is set otherwise it is reset. |
. If lower order
3. Parity Flag (PF): This flag is used to in dicate the parity of result
and for odd
8-bits of the result contains even number of I's, the Parity Flag is set to one
number of 1’s, the Parity Flag is reset /.e. zero.
is set to one; if the resu It of ar it hm et ic or logical operation is
4. Zero Flag (ZF): It . eee
zero else it is reset. |
for mat the sign of number 1s indicated by
5. Sign Flag (SF) : In sign mag nit ude
one.
MSB bit. If the result of operation is negative, sign flag is set to
ee
rocessor, an d id en ti fi es
ots
lo ca te s
e. The address decoding system
2001H. :
ME MR sig nal whi ch lasts during T2
unit produc es
Q.an 2. (a) Drraaw and explain th e At T2 the Timing and control ced int o the data bus then into
e timingadiagram of MV e the dat a 32H is pla
IB 05H and T3. During this window of tim
the MPU. ea.
= “ (Opcod
, e fetch) the data 32H is sto red int o the accumulator.
| 24
| a (Memo tr e During the rest of TS, dat a is tr an sf erred into
2 T; Ty the RIM ins tru cti on 69 H
T;
aT. — q; ~ Q.2. (b) If after executing fer ent sig nal s. (2)
mulato r, the n ind ica te, the status of dif
the accu
Ans.
RIM Instruction >
elses bees!
0, 9, D, Dd, D, 9%
2D, 2,
Mask status of 3
RST $3.5 Bx
‘ |
Mask status of (2 =
crsal Input Data 2¢
RST 65
,
Interrupt. pending > Mask status of }* 4
Kpenae sy —o
Peerrupt 1s not ponding
status of RST? 5
Interrupts are enab
Interrupt pending
ini byte © Opcode ig jst byte | —_Base Register > Contains Matrix column
bytelocne * sh Operand ig 2nd if 3rd ;
| Number (Variable)
erally 8-bit byt Ralls 423 ee |
Eo: MOY AR ae p Ta demenetorat
ADD w data)
| 3
Le (generally 16-< Index Register + Contains Matrix Row
TESS Ordaigyaame = Number (Variable) =
Eg: AD
: I 881 oe | Se |
Eq: Te rr Regardless of 2
SUI FcH : a using SI or DI
eee | . When Base Register is BX
Q.3. (a) Explain B
Mi
. ased, Ind
“roprocessor with Su a
ae PA == DS: He. BX + (SI. or Dl) + Diaie splaceme
} nt
itab® le ¢ €xed, Ba -
Sed-Indexeg addressing : -
Ans. Base Resi ples modes of 80 ;
Avg ”
Following figure shows the interna] block di
agram of 8036 microproce
The 8086 CPU is divided into two inde penden ssor
t functional parts, the bu
anit or BIU, and the execution unit or BY. s interface
=. CSE
a CSO 5
ye” e—RD SHE —
. oe
rd i”
fe
< : .
Byte
4
4‘
+s
~ Queue
.
biel
ll
hi
PSP 2 ee oe es on
:
4
\
4
eins
fl4
eS
wr:
:
f=
Fy
—
i voy
rpom r wr rrr
‘+
4%.
rrr
:
rw ew wwe er ee eK
4
Domes
*
a
Pi
agw
-
=
a EU
”
?
oot Toe
pat)
“a
ae
awert
z
VT
Bs
ee j. , re ; ; -
SE ICO Ee EEE
z ; s
ST
:
OE PE +
We we we we we ge oo :
_ 8086 Internal
Block Diagram ~~~~>~~-~---
7 ~ a, A ofC
- a
(at Reais
END TERM EXAMINATION [May
LP. University-[B.
Tech} _Akash Books
3 It has built in baud r 2019-9
CONTROLLERS [ETEE-310) e
e
Internal or external character synchronization
Automatic sync insertion
Time : 3 hrs. e Baud rate from DC to 64 Kbhaud
Note: Aiiempi five questions in all incl
ee uding Q.No. 1 which is eo mpul MM, ; 15 5. It allows full duplex transmission and reception.
from. each unit. Assume missing data if any. soy, §
%. Select o 1 Question 6. It provides double buffering of data both in the transmission section and in the
Q.1. (a) Is there some mini
mum pulse width re qu receiver section
case of 8085 microprocess ired for the INTR sia al in
ors? Explain with reason
. 7. It provides error detection logic, which detects parity, overrun and framing errors.
(3) |
~~
8. It has Modern Control Logic, which supports basic data set control signals.
9. It provides separate clock inputs for receiver and transmitter sections, thus
: providing an option of fixing different baud rates for the transmitter and receiver
oper
u8at
58 . ed at 3 MHz : clock f
requency, then the INTR puls section.
|
e must remain sta tes. If 8085 tS
high for at least 10. It is compatible with an extended range of Intel microprocessors.
Q.1. (b) Explain how man
y umes the following | 11. It is fabricated in 28 pin DIP package and its all.inputs and outputs are TTL
LXI B, 0008H § !00p will be executed (3)
LOOP: DCX B- compatible. Se ae ee
. emperature-.
p a
JNZ LOOP 12. It is available in standard as well as extende
Ans. 7 times | Q.1. (f) What are the
.
different i
operating des
modes of 8255 Programma i)
Q.1. (©) Write a pro al Peripheral Interface?
microprocessor Gram to generate a delay of 1 milli-second in 8086| Ans.
a5 ae to a 1.(c), End Term Examination 2018
. (Page No. 9-2018) Fa ( "
; xplain the usefulness of TE
< ST ae aan 8255 PPI MODES OF OPERATION
microprocessor | LOCK ’ instructions in 8086 | CONTRO WORD OF 82554
Ans. LOCK : Its an active low
| | ee : Di Do
D? D6 Ds no
rc O/1-
{BSR MODE |
: |For Port C :
Q.1. (e) Write the ‘mportant features of82ading ed
:
internal!| lly
51 IC ce the clock |NoEffect | Mod :
Ans . Features of 8251 Microcon
trolley
SART) (3)
On VO Mode Simple - vo
PA}——PAG-PA7 | PA |-—>pa
y --> PC4-PC7
wr M
aN
GROUP B \
825SA :
PCL | ~~ *PCO-PC3 8255 PORT C tower: PC 4g PCy
Les
: PCL 77 . * foe Inout
iguration provides a
means fi 5
GROUP A
and Port B PORT< (Upper! PC 5 «PC 5
“handshaking” signals use the lines on Port C to senerate or accept th ese T for input
0 for Output
ntmA
aca LiPBIO:7) OL
re 99 for Meda 6
* ST Rehiodet
= isséd;«t
G tor BSR Mode
< a Pc2 |" OBF(B)[AL]
a L
Pco [~~ INTR
C6, leo
ces oe
O/P-
PCr ["" ACK(B)[AL)
aPco | ~*INTR (B): :
7
a
mode CWR Dy
| a roup of
_ Ans. Logical period ctions: The ~ Ee AND, OR, XOR, a NOT , Rotate, Clear
bit-by-bit basis.
ae
ogical oper
instructions, which perform '0e™*" alie™ on Byt es of data on
"med
ce
ehte ish>
r nfsabis
* RLC + SWAP
POR
P
ee
ry}
=
-—S
«RRC |
elite
.
Sao
on
_
ay .
ay | y
x
’ , = * fi
€(Direc
re€ct (Dire
)t)c)ANDAND#Dat
A a| rege
ndiréct ; Ks
-—
hardwired
|
- ’
control unit because the micrcinstructions are to
+) is j
| | be fet
Ans. Let us taSUPP
; a
OS®
re t o b e a d
a s
j
2064H. These d
an
14- 2019 Si|xth Semester, Microp
rocessors and
Program Code: [.P. University-[B.Tech|—-Akash Books
LXI D, 2060H 2019-15
XCHG F DB ODh, 0Ah, 24h ;Carriage Return, terminator BYTE
MVI C, 04H CRL _ The DW directive is used to declare a WORD type variable -A WORD
MOVA,M DW |
‘ s 1 6 bits or (2 BYTE).
UP: socupie
a t i o n e x a m ples:
INX D peclar
XCHG
ADDM - Word2 DW 65535; OF FFFh, (the max. possibile for a WORD)
DER C e
3 DD - The DD directive is used to declare a DWORD -—A DWORD double word is
BYTE. |
nade up of 32 bits =2 Word’s or 4
Declaration examples:
Dword1 DW 12345678h
Dword2 DW 4294967295 ;OFFFFFFFFh.
ate wi |
Ans Refer Q 3 (b) First Te th the help of examples nterrupts in 4. STRUCT and ENDS directives to define a structure template for grouping data
rm Examination 2018. (Page N items.
a ed
: | 0. 4 (1) The STRUCT directive tells the assembler that a user defined uninitializ
(a) Explain thec regist ee ng oo oe data structure follows. The uninitialized data structure consists of a combination of the
ae© in- 8086 micropro £ister addressi m 1 a
three supported data types. DB, DW, and DD. The labels serve as zero-based offsets
With the help ihe. de and immediate addr Spe
Ans. The Way of s ae
essing into the structure. The first element's offset for any structure is 0. Astructure element
“ay . Pecilying xample,
addresgj
It also ee This specifies that a.” be Operated by. ans. a is referenced with the base “+” operator before the element's name.
€S whether the © Sven data is n Instruction is knee é A Structure ends by using the ENDS directive meaning END of Structure.
Types of
Regist er
addressin
ad
g a es: © OPerand . isregister or register e
or “imediat data
pair or an a direes
re 8s, Syntax:
STRUCT
are registers dressing mode ~ In th Ss a Structure_element_name element_data_type?
Ex ample: 'S type of3 addr ssing mode bo tan 6ws
l. MOV AX, BX - operands
Re
= XOR AX, DX
ENDS —
Immediate es (OR). oe.
mode on - | “: . ‘ek
or 16 bit, data Destinati on type of dre Ssin se STRUGs224 |
_data_type?
Structure_element_name element
Example: | Perand can never = Ode the Source =
3. MOV AX 2090 MMediate data | and is a8 bit
~ MOV CL, 0A oe
_ 8. ADDAL, 45 ; ENDS — |
oo 0000 DECLARATION: —
a
a
ae sa th e pr ogram, it wul
.
gi ve n na
.
me s 1p
the assembler finds the
; ,
w+.
ene
ae,
p
ou Ss no
16-2019 sixth Semester, Microprocessors and
Microcont ll
Tollerg
the name with the value or a symbol. The valu
e can be in the
it can be another Equate declared anywhere above or range throy -
Thecogi
follee
owi operators can also be used to declareoe
an Equate: on 6559
I.P. University-[B.Tech]|_Akash Books 2019-17
e and f oFFSET: It is an operator which tells
the assembler to determine the offset
THIS WORD eer ) is cement of a named data item from the start of the segment which contains it.
THIS DWORD oe | | | or disP 7 to load the offset of a variable into a register so that variable can be
accessed
A variable — declared with: a DB, DW, or DD directiy Iris use
qith one © f the addressed modes.; Example: when the assembler read MOV BX.OFFSET
space reserved at that address forj
address. or space reserved tin the .COM file. But © ~ has an addr
| for it‘ee in the RICES, 1it willwil dete
determine the offset of the prices.
:
-COM file. an Equate €Ss a a, | ROUP : It can be used to tell
does Not hay CT Ae the : directive into one logicathe assembler to group the logical segments
l group. This allows the contents of all
Example: | i nae ents to be accessed from the same group. Example: SMALL-SYSTEM GROUP he
A~ByteEQUTHISBYTR | en | segCODE, DATA, STAC
ey 19° Sh - = ACK- SEG
K-SE G.
<a ae THIS WORD
| | CO g.4. (c) How many bytes of storage do the following
EPROM = memory |
oo
eC. tain? (i) 2716 (ii) 2764 | 3 ts)
A_dword EQU T . aie Ans. 2708 (1K *8) =1024 bytes
DD 4294967295 aa
er Size EQU 1024 |
2716 (2K*8)=2048 byte
See 2732 (4K*8)=4096 bytes
aa DB1024DUP()
uffed_ptr EQU $ - ac —— 2764 (8K*8)=8192 bytes
Se » actual] cae 16k*8)=16384 bytes |
nara, 27128 (161 )
are] someE*e™ : assem
other Ibis used
b] to tell the aer *yte after the; 1024th byasgaseen
am 04. idee
. the microprocessors? (2)
OPERAND|
k
3
Plle: the code Segment ; 2 fogical segment. Itis
(9) PROC: (PROCE te the name
n 1S used to indicate to the asse | OPCOD callsretur
mble CALL address a a subro utiness and
n addre saves
on the stack “CALL
CALL 2050
Afte the aathe Procedur. e. )Itis Used to ide nti ly the startoe of a Proce
si Seas
dure. It follo
a returns from the subroutine to
RET =. {°8 one the main program e RET
ple:
ast Pie: SMAR|
oa 4 a =.
;| transfers the con trol o SOA
JUMP | = aacrrne aceeution to the specified address JUMP 2050
INS
JA | address
address | pif
— CFO
ager and ZP=0
om
AA 2050 uh
MOV [(SIJ, ALI; Store AL content into memory
LOOP L1; Loop to L1 until counter becomes 0
JNBE | address jump if CF=0 and ZF=0 — JNBE 2050 | HLT; Terminate program
‘JAE 2050 | Flow Diagram
JAE address jump if CP=0
JNB address jump if CF=0 JNB 2050 |
JBE address jump if CF = 1or ZF=1 JBE 2050 | ;
JNA | address jump if CF = 1 or ZF = 1 JNA 2050 |
JE address jump if ZF = 1 3 JE 2050 | a eT
JG address jump if ZF = 0 andSF =O IG 20507 i. SS eo ferieh prs algo es a oh a
AL= Pla oe
ties Pal Mente Memory
LOOPZ | address | loop while ZF = 1 and CX =0 — LOOPZ 2050 ; )
LOOPNE) address loop while ZF = 0 and CX =0 LOOPNE 2050 fs
LOOPNZ! address loop while ZF = 0 and CX = 0 LOOPNZ 2050) i
(A=
es 2
; <a
ic}
=
agmea
.
teh
~
se
e
ee a E
~)
aa fi
2. <19.e
b
ly or indirectly.
ZF is zero flag ig
OF is overflow flag
PF is parity flag
SF is sign flag
CX is the register
Q.5. (b) Write| an 8086 assembl i bonacc
| ; : language Program to generate the ma
series using a recursive anceh
Ans. To : | PGE a ay emcee
AL = AL + elemento
34
at first. Then “a ae
2 at first 8 the limit from location offset 500. The limit is decre 7 OP '-- T=
5a Vite
fi
Py2 be
Ut De: eee W
Ft ae
‘ taril iNet!
; TT iY p
Bee
Pome2\ | VR Se
eee
ath a :
TNE!
so} i a
: ; Load “41
—
MOV SI, 500H: Ping ith OOH
: » Foint to offset
500
MOV (SI),AL; S
tore first numbe
r oot memory
20-2019 Sixth Semester, Microprocessors and Microcontrolleng
. “™ ‘. . * e M
Poll Comman . IR
though it functions halen i olled moda, |
a wee The poll tor by masking INTs
a2 ae _ using software exe 1 in OCW3. The aoead of
roe e 8259A treats the ad of the requests 3 9A ig
es A a a is set an interrupt acknow\aial
253/54 areas follows a In the above figure, there are three counters, a data bus buffer, Read/Write control
Cena Be logic, and a control register. Each counter has two input signals - CLOCK & GATE, and
_ | one output signal - OUT.
‘a Data Bus Buffer: It is a tri-state, bi-directional, 8-bit buffer, which is used to
| interface the 8253/54 to the system data bus. It has three basic functions.
a .© Programming the modes of 8253/54.
if - ° Loading the count registers.
|a ¢ Reading the count values. .
eZ Read/Write Logic: It includes 5 signals, i.e. RD, WR, CS, and the address lines A,
__| &A,. In the peripheral I/O mode, the RD and WR signals are connected to IOR and IOW,
MEMW.
a = respectively. In the memorymapped I/O mode, these are connected to MEMR and
| - Address lines A,& A, of the CPU are connected to lines Ay and A, of the 8253/54,
counters are selected
and CS is tied to a decoded address. The control word register and
according to the signals on lines Ay & A,.
a y | 0 0 Counter 0
4 0 1 . Counter 1
: ef 0 Counter 2
1
ie 1 ST pic
xX . | x a No Selection -
a
ars | be ti
Control Word Register: This register is accessed when lines Ay & , are ee :
a e | oe : i
ME
Ree : | cm ag | Sgt: oe.
ue «ti —
a command‘+o word, which specifies the counterto be used, » itits mode, and
Deemeh in;
| aan an ueed 2 eee table shows the result for various control
re ad or wr it e op er at io n. Following
Seed either a
“puts, ?
>9
LP University-[B. Tech]-Akash
Books 2019-27
4, Communication: Cell Phones, Tele
phone Sets, Answering Machines etc
5. Office Equipment: Fax, Printers ete.
|
6. Multimedia Application: Mp3 Player
, PDAs etc.
7. Automobile: Speedometer, Auto-break
ing system etc.
Pee Mes How many 16-bit timers does an 8051 microcontroller
have? Also
explain the different operating modes for
the timers of 8051 microcontroller. (5)
| Ans. Timer: 8051 has two timers Timer0 (TO
) and Timer! (T1), both are 16-bit
wide. They can be used either as timers or as counters.
Both timers fe 16 bits wide
Since 8051 has 8-bit architecture, each of these is accessed
by two separate 8-bit fogistera
as shown in the figure below. These registers are used to
load timer-count. ;
THO |
TLO
805] has Timer Mode Register and Timer Control Register for selecting a mode of
operation and controlling purpose.
Let’s see these registers,
TMOD register: TMOD is an 8-bit register used to set timer mode of timer0 and
timerl.
Timer 1 Timer 0
Gk 6 5 : 4 3 2 1 0
Its lower 4 bits are used for Timer0 and upper 4 bits are used for Timer]
Bit 7,3 - GATE:
1 = Enable Timer/Counter only when the INTO/INT! pin is high and TRO/TR1
»is set. |
0 = Enable Timer/Counter when TRO/TR1 is set.
Bit 6,2 - C/T(Counter/Timer): Timer or Counter select bit
1 = Use as Counter
| |
0 = Use as Timer
& 1:0 - M1 :M 0: Ti me r/ Co un te r mode select bit
Bit 5:4
Ti me r/ Co un te r mo de sel ect bit as per below table
These are |
8. Medic ical Instruments: ECG Machine, Accu-Check ete } | de | Operation
) at ; 0 (18-bit timer mode) 13-bit timer/counter, 8-bit of THx
& 5-bit of
| | el o ;? ae
TLx =
28-2019 Sixth Semeste r Microprocessors and Microcontrollers |
oks -| 2019-29
| University-[B.Tech]-Akash Bo
?
LP.
16-bit timer/counter, THx cascaded with Th
0 1 1 (16-bit timer mode)
: ee
2 os(8-bit auto reload mode)| 8-bit timerr/coun ter (auto reload mod 8), T
-bit time imer Mode 3: :
O an d THO act as two =
; - heave reload with value held by THx each time te | Sp li ts in to tw o 8- bi t co un te r/ timers. TL
Mee 0 re sp ec tively.
overflow | tt in g the TFO an d TF 1
Split 16-bit timerx into two 8-bit time, i: timers with overflows se
Mt timer mode) in mode 3 ):
- Timer 1 (when timer 0 is
Sena: THx and TLx like two 8-bit timer ms
* Counter stopped if in mode 3 9
. . : >
| |
|
;
Timer Modes: Timers have their operation modes which are selected in TMop * Can be used in mode 6, 1, or
register using M0 & M1 bit combinations. (INT1) and ext ern al inp ut (T1), but no fla g or interrupt.
* Has gate
|
Timer Modes Timer Mode 0 (13-bit Timer): ° May be used as a baud rate generator.
- Timer high-byte (THx) is cascaded with the 5 least-significant bits of the timer
low-byte (TLx) to form a 13-bit timer, where x = Qorl. Timer
- Upper 8-bits of TLx are not used. clock
- Overflow occurs on the 1 FFFH-to-0000H and sets the timer overflow flag. |
- MSB is THx bit 7, and LSB is TLx bit 0. | Timer TFO Interrupt
- MOV TMOD, #00H; setting both timers to mode 0 clock ]5 Overflow flag
MAES Bee
bea” | Leer
_~ Clock is applied to the combined high and low-byte
2h
»
timer registers. ee G oy
: Overflow occurs on the FFFFH-to-0000H and sets the timer overflow flag. Se can be used Tor (oy RegisterA will hold Quotient, and register andB will21H,holdAfterRemainder.
dividing
- MSB is THx bit 7, and LSB is TLx bit 0. eee ar ee two number0EH and 03H at location 20H
= eg ;
: LSB toggles at clock frequency/2! will be stored at location 30H and 31H.
and MSB at clock frequency/216 the caput
| Address Value
i “
Timer
20H | 0EH
ate
clock Interrupt
03H
4
21H ;
f :
1
: a Pa ‘Overflow
a _ Timer Mode 2 (Auto-Reload): | )
30H 00H
Bx ee aS: 4. | Me 31H | 00H
| Al = oe (TLx) operates as an 8-bit timer while the timer high -byte (THx)
| es ee
og
we
> *
30-2019 Sixth Semester, Microprocessors and Microcontrollers ].P. University-[B.Tech|~Akash Books 2019-31
on
INC R1; Increase Ri to point to the next locati ++ 0 — EXO: Enable External0 Interrupt Bit
MOV @R1, B; Store Remainder to 31H F 1 = Enable External0 interrupt
HALT: SJMP HALT ;Stop the program 0= Disable External0 interrupt
8051 provides DI VAB instruction. By using this instruction, the division can be
done. In some other microprocessors like 8085, there was no DIV instruction, In that Interrupt priority
| ned by using interrupt priority register (IP)
rrupt can be assig
ity to the intest
microprocessor, we need to use repetitive Subtraction operations to get the result of the prior!
division. prio rity after Reset:
{Interrupt
When the denominator is00H, the overflow flag OV will be 1. otherwise it is
Interrupt source Intr. bit/ flag
the division.
0 for Priority
External Interrupt 0 INTO
Output 1
Timer Interrupt 0 TFO-
Address Value 9
aa
3 External Interrupt 1
ais
20H 4 Timer Interrupt 1
OEH ( }
5 Serial interrupt eS reset are shown. As per 8051 interrupt
0V* hed with
upts priorities upon 1 anocontrolleris finishe
_In the ae Tie ‘dared are not served Sea are microcontroller queues
priorities, ‘ori
lowe see
es. a case when two or more interrupts
higher priority on
a c c o r d i n g to p r i o r ity.
them
: Explain the interrupt enable regi
Q.9. (a)
ster and interrupt priority control joritpy a regis‘5 teralso -ority lev/e els
possible to: change the priority jority
register in case of 8051 microcontr IP Register: Interrupt Ra
oller, | iori ister ;
bi ‘+ in the Interrupt price
|
pe clearing the corresponding
of theinterne
interrupts Dy §
t h e fi gure. . Thi11s S
s h o w n 1D
(IP) register as ty interrupt bu -annot be int err upt ed. I f these ininterrupt
t
the high-pr ority 1
ex ec ut es 10 pr ed ef in e d manner and
mi la rl y, th e hi gh -p ri jor
or ityity in ma ter™ ™ o ller
register, bit corresponding in te rr up t. Si , e m i c ro tr
c o n
ogra m m e d th
the interrupt. - priorities are not pr T 1 , T F 1 , a n d SI.
to interrup
IE register: Interrupt Enable | r is I N T O , T F O , I N : ri or it y s
Register its orde gi ster to o o : P
IE register is used to enable in te rr upPpt priority re
3
/disable interrupt sources. 8051 has 1n x0 IP
PX1 PTO P 5
7 6 win S : :
6 5 7 : PTi
4 3 2 . pS
1 0
EA — — ES ET1
—
EX4 ETO
—
EXO
Bit 7 - EA: Enable All Bit bits.
-/ IE
? i 5- Reserved te a
1 = Enable al] interrupts
. ees ae
| erafee Serial Interrup‘oritt y to s
0 = Disable all interrupts
Bit 6,5 - Reserved bits low priority to ser-oritialy Bi oe
_ Bit 4- ES: Enable Serial Inte ten pe
me r! In t Prio
terrupty nty Ee
rrupt Bit i
Bit 3 es pT 1: Ti
oan high priori to Timer
| 1 = Enable serial interrupt
0 = Disable seria] interrupt . . Bit “
Interr pt 1 Priority
Interrupt Bit . External e r r upt.
peasy 1 = Enable Timer1 interrupt «Bit 2- PX p r i o r i t y t o Extern a l 1 i n t
h
1 = Assign hig
0 = Disable Timer1 interrupt
ore. Bit 2 ~ EX1: Enable External
hae ee
] Interrupt Bit
jae 1 = Enable External] interrupt
_-- -., 0 = Disable Extern
a
al! interrupt
i iy i Bit 1 - ETO: Enable Timer0 Interrupt
Bit
1 = Enable Timer0 interrupt -ority to External0 interrupt
0 = Disable Timer( interrupt - to External0 interrupt:
s an d Mi cr oc on tr o ll er s
Sixth Se me st er , Mi cr op ro ce ss or
32-2019 pores dio “dais
addressing: mo 7
w e e te r indirect
Q.9. (b) Differentiate be t r o c o n tr ol le r (b y g i v i n g s u i t a b l e
d d r e s s i n g m o d e u s e dBy byB O
80S E
51 : m i c
: mmediate a (5.5)
examples of both).
Ad dr es si ng mo de s of 80 51 )
Ans.
mo de : In th is ty pe , th e op er and ae in Noe
1. Immediate ad dr es si ng
e op co de . In si mp le wa y, it me an s da ta is pr ov id ed 1n instruc on
instruction along with th
| ee |
itself.
V A, #0 5H -> Wh er e MO V st an ds for mo ve , # re pr es en ts im me di ate data.
Ex: MO
05h is the data. It means the immediate date 05h provided in instruction is moved into
A register.
2.Register addressing mode: Here the operand in contained in the specific register
of microcontroller. The user must provide the name of register from where the operand/
data need to be fetched. The permitted registers are A, R7-RO of each register bank. Ex: .
MOY A,RO-> content of RO register is copied into Accumulator. ai.
3. Direct addressing mode: In this mode the direct address of memory location is
provided in instruction to fetch the operand. Only internal RAM and SFR’s address can. 7
4
be used in this type of instruction. |
Ex: MOV A, 30H => Content of RAM address 30H is copied into Accumulator.
4. Register Indirect addressing mode: Here the address of memory location is
indirectly provided by a register. The“@’ sign indicates that the register holds the add
ress
of memory location i.e. fetch the content of m emory location whose address is
provided, :
in register. | | :
Ex: MOV A,@RO => Copy the content of memory location whose addr
ess is givenin -
RO register.
9°. Indexed Addressing mode: