INDEX

SR. TITLE PAGE TEACHER

NO NO SIGNATURE
1 LOGIC GATES 2-6

2 ADDER 6-9

3 SUBTRACTOR 9-11

4 DECODER 12-15

6 ENCODER 15-19

7 MULTIPLEXER 19-22

8 DEMULTIPLEXER 22-25

9 FLIP FLOP 25-31

10 REGISTERS 31-32

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Logic Gates
o The logic gates are the main structural part of a digital system.

o Logic Gates are a block of hardware that produces signals of binary 1 or 0

when input logic requirements are satisfied.

o Each gate has a distinct graphic symbol, and its operation can be described
by means of algebraic expressions.

o The seven basic logic gates includes: AND, OR, XOR, NOT, NAND, NOR, and
XNOR.

o The relationship between the input-output binary variables for each gate
can be represented in tabular form by a truth table.

o Each gate has one or two binary input variables designated by A and B and
one binary output variable designated by x.

The various logical gates are:

1. AND

2. OR

3. NOT

4. NAND

5. NOR

6. XOR

7. XNOR

AND Gate

The AND gate produces the AND logic function, that is, the output is 1 if input A
and input B are both equal to 1; otherwise the output is 0.
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The algebraic symbol of the AND function is the same as
the multiplication symbol of ordinary arithmetic.

We can either use a dot between the variables or concatenate the variables
without an operation symbol between them. AND gates may have more than two
inputs, and by definition, the output is 1 if and only if all inputs are 1.

OR Gate

The OR gate produces the inclusive-OR function; that is, the output is 1 if input A
or input B or both inputs are 1; otherwise, the output is 0.

The algebraic symbol of the OR function is +, similar to arithmetic addition.

OR gates may have more than two inputs, and by definition, the output is 1 if any
input is 1.

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Inverter(NOT) Gate

The inverter circuit inverts the logic sense of a binary signal. It produces the NOT,
or complement, function.

The algebraic symbol used for the logic complement is either a prime or a bar
over the variable symbol.

NAND Gate

The NAND function is the complement of the AND function, as indicated by the
graphic symbol, which consists of an AND graphic symbol followed by a small
circle.

The designation NAND is derived from the abbreviation of NOT-AND.

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NOR Gate

The NOR gate is the complement of the OR gate and uses an OR graphic symbol
followed by a small circle.

Exclusive-OR Gate

The exclusive-OR gate has a graphic symbol similar to the OR gate except for the
additional curved line on the input side.

The output of the gate is 1 if any input is 1 but excludes the combination when
both inputs are 1. It is similar to an odd function; that is, its output is 1 if an odd
number of inputs are 1.

Exclusive-NOR Gate

The exclusive-NOR is the complement of the exclusive-OR, as indicated by the

small circle in the graphic symbol.

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The output of this gate is 1 only if both the inputs are equal to 1 or both inputs
are equal to 0.

Adder- A combinational circuit that performs the addition of bits is called an

Adder. Each computer has an adder located in its CPU(ALU) that is responsible for
the process of addition. There are two types of Adder. They are also used in other
parts of the processor, where they are used to calculate addresses, table indices,
increment and decrement operators, and similar operations.

 Half Adder

 Full Adder

Half Adder:

A combinational circuit that performs the addition of two bits is called a Half
Adder. It receives two inputs and produces two outputs Sum and Carry. The block
diagram for a half adder is as follows.

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Designing of Half Adder:

Designing of Half Adder involves the following steps.

1. Problem: addition of two bits.

2. The number of available inputs are two.

3. The input and output variables are assigned letter symbols. Let’s represent
the inputs by A AND B, and the outputs SUM and Carry by S and C
respectively.

4. Truth Table

 Simplified Boolean function.

The Sum and Carry are in simplified form and further it cannot be simplified.

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Full Adder:

A combinational circuit that performs the addition of three bits is called a Full
Adder. It receives
eives three inputs and produces two outputs Sum and Carry. The
Block diagram for the Full Adder is shown below.

Designing of Full Adder:

The designing of Full Adder involves the following steps.

 Problem: Addition of three Bits.

 The number of available in

inputs are three.

 The input and output variables are assigned letter symbols. Let we
represent the inputs by A, B, and C; and the outputs by S and C i.e. S for
Sum and C for Carry.

 Truth Table

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Subtractor:
A combinational circuit that performs the subtractions of bits is called a
Subtractor. There are two types of Subtractors.

1. Half Subtractor

2. Full Subtractor

1. Half Subtractor:

A combinational circuit that performs the subtraction of two bits is called Half
Subtractor.
tractor. It receives two inputs and produces two outputs Difference and
Borrow. The block diagram of the Half Subtractor is given as

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Half Subtractor Block diagram:

Designing of a Half Subtractor:

The designing of the half Subtractor involves the follo

following steps.

 Problem: Subtraction of two bits

 The number of available inputs 2.

 The input and output variables are assigned letter symbols. Let we
represent the inputs by A and B, and the outputs Difference and Borrow by
D and B.

 Half Subtractor Truth Table

Table:

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Full Subtractor:

A combinational circuit that performs the subtraction of three bits is called a Full
Subtractor. It receives three inputs and produces two outputs Difference and
Borrow. The Block Diagram of the Full Subtractor is as follows.

Full Subtractor
btractor Block Diagram:

The designing of the Full Subtractor involves the following steps.

 Problem: Subtraction of three bits

 The number of available inputs are 3.

 The input and output variables are assigned letter symbols. Let we
represent the inputs by A, B, and C; and the outputs Difference and Borrow
by D and B.

 Full Subtractor Truth Table:

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Decoder
The combinational circuit that change the binary information into 2 N output lines
is known as Decoders. The binary information is passed in the form of N input
lines. The output lines define the 2 N-bit
bit code for the binary information. In simple
words, the Decoder performs the reverse operation of the Encoder.. At a time,
only one input line is activated for simplicity. The produced 2 N-bit
bit output code is
equivalent
valent to the binary information.

There are various types of decoders which are as follows:

2 to 4 line decoder:

In the 2 to 4 line decoder, there is a total of three inputs, i.e., A 0, and A1 and E and
four outputs, i.e., Y0, Y1, Y2, and Y3. For each combination
bination of inputs, when the
enable 'E' is set to 1, one of these four outputs will be 1. The block diagram and
the truth table of the 2 to 4 line decoder are given below.

Block Diagram:

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Truth Table:

The logical expression of the term Y0, Y0, Y2, and Y3 is as follows:

Play Videox

Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'

Logical circuit of the above expressions is given below:

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3 to 8 line decoder:

The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8 line

decoder, there is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and
three outputs, i.e., A0, A1, and A2. This circuit has an enable input 'E'. Just like 2 to
4 line decoder, when enable 'E' is set to 1, one of these four outputs will be 1. The
block diagram and the truth table of the 3 to 8 line encoder are given below.

Block Diagram:

Truth Table:

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The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:

Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2

Logical circuit of the above expressions is given below:

Encoders
The combinational circuits that change the binary information into N output lines
are known as Encoders.. The binary information is passed in the form of 2N input
lines. The output lines define the N
N-bit
bit code for the binary information. In simple

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words, the Encoder performs the reverse operation of the Decoder. At a time,
only one input line is activated for simplicity. The produced N-bit output code is
equivalent to the binary information.

There are various types of encoders which are as follows:

4 to 2 line Encoder:

In 4 to 2 line encoder, there are total of four inputs, i.e., Y 0, Y1, Y2, and Y3, and two
outputs, i.e., A0 and A1. In 4-input lines, one input-line is set to true at a time to
get the respective binary code in the output side. Below are the block diagram
and the truth table of the 4 to 2 line encoder.

Block Diagram:

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Truth Table:

The logical expression of the term A0 and A1 is as follows:

A1=Y3+Y2
A0=Y3+Y1

Logical circuit of the above expressions is given below:

8 to 3 line Encoder:

The 8 to 3 line Encoder is also known as Octal to Binary Encoder.. In 8 to 3 line

encoder, there is a total of eight inputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and
three outputs, i.e., A0, A1, and A2. In 8-input lines, one input-line line is set to true at a

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time to get the respective binary code in the output side. Below are the block
diagram and the truth table of the 8 to 3 line encoder.

Block Diagram:

Truth Table:

The logical expression of the term A0, A1, and A2 are as follows:

A2=Y4+Y5+Y6+Y7
A1=Y2+Y3+Y6+Y7
A0=Y7+Y5+Y3+Y1

Logical circuit of the above expressions is given below:

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Multiplexer
A multiplexer is a combinational circuit that has 2n input lines and a single output
line. Simply, the multiplexer is a multi-input and single-output combinational
circuit. The binary information is received from the input lines and directed to the
output line. On the basis of the values of the selection lines, one of these data
inputs will be connected to the output.

Unlike encoder and decoder, there are n selection lines and 2 n input lines. So,
there is a total of 2N possible combinations of inputs. A multiplexer is also treated
as Mux.

There are various types of the multiplexer which are as follows:

2×1 Multiplexer:

In 2×1 multiplexer, there are only two inputs, i.e., A0 and A1, 1 selection line, i.e.,
S0 and single outputs, i.e., Y. On the basis of the combination of inputs which are
present at the selection line S0, one of these 2 inputs will be connected to the
output. The block diagram and the truth table of the 2×1 multiplexer are given
below.
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Block Diagram:

Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.A0+S0.A1

Logical
gical circuit of the above expression is given below:

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4×1 Multiplexer:

In the 4×1 multiplexer, there is a total of four inputs, i.e., A 0, A1, A2, and A3, 2
selection lines, i.e., S0 and S1 and single output, i.e., Y. On the basis of the
puts that are present at the selection lines S 0 and S1, one of
combination of inputs
these 4 inputs are connected to the output. The block diagram and the truth table
of the 4×11 multiplexer are given below.

Block Diagram:

Truth Table:

The logical expression of the term Y is as follows:

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Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

Logical circuit of the above expression is given below:

De-multiplexer
multiplexer is a combinational circuit that has only 1 input line and 2 N output
A De-multiplexer
lines. Simply, the multiplexer is a single-input and multi-output
output combinational
circuit. The information is received from the single input lines and directed to the
output line. On the basis of the values of the selection lines, the input will be
connected to one of these outputs. De De-multiplexer
exer is opposite to the multiplexer.

Unlike encoder and decoder, there are n selection lines and 2 n outputs. So, there
is a total of 2n possible combinations of inputs. De
De-multiplexer
multiplexer is also treated
as De-mux.

There are various types of De

De-multiplexer which are as follows:

1×2 De-multiplexer:

In the 1 to 2 De-multiplexer,
multiplexer, there are only two outputs, i.e., Y 0, and Y1, 1
selection lines, i.e., S0, and single input, i.e., A. On the basis of the selection value,

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the input will be connected to one of the output
outputs.
s. The block diagram and the
truth table of the 1×22 multiplexer are given below.

Block Diagram:

Truth Table:

The logical expression of the term Y is as follows:

Y0=S0'.A
Y1=S0.A

Logical circuit of the above expressions is given below:

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1×4 De-multiplexer:

In 1 to 4 De-multiplexer,
multiplexer, there are total of four outputs, i.e., Y 0, Y1, Y2, and Y3, 2
selection lines, i.e., S0 and S1 and single input, i.e., A. On the basis of the
combination of inputs which are present at the selection lines S 0 and S1, the input
be connected to one of the outputs. The block diagram and the truth table of the
1×44 multiplexer are given below.

Block Diagram:

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Truth Table:

The logical expression of the term Y is as follows:

Y0=S1' S0' A
y1=S1' S0 A
y2=S1 S0' A
y3=S1 S0 A

Logical circuit of the above expressions is given below:

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flip-flop
A flip-flop is a sequential digital electronic circuit having two stable states that can
be used to store one bit of binary data. Flip-flops are the fundamental building
blocks of all memory devices.

Types of Flip–Flops

 S-R flip-flop

 J-K flip-flop

 D flip-flop

 T flip-flop

S-R Flip-flop

 This is the simplest flip-flop circuit. It has a set input (S) and a reset input
(R). When in this circuit when S is set as active, the output Q would be high
and the Q’ will be low. If R is set to active then the output Q is low and the
Q’ is high. Once the outputs are established, the results of the circuit are
maintained until S or R get changed, or the power is turned off.

 Truth table of S-R flip-flop

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S R Q State

0 0 0 No Change

0 1 0 Reset

1 0 1 Set

1 1 X

 Characteristics Table of S-R flip-flop

S R Q(t) Q(t+1)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 X

1 1 1 X

 Characteristics equation of S-R flip-flop

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Q(t+1)=S+R‘Q(t)Q(t+1)=S+R‘Q(t)

J-K Flip-flop

 Because of the invalid state corresponding to S=R=1 in the SR flip-flop,

there is a need of another flip-flop. The JK flip-flop operates with only
positive or negative clock transitions. The operation of the JK flip-flop is
similar to the SR flip-flop. When the input J and K are different then the
output Q takes the value of J at the next clock edge. When J and K both are
low then NO change occurs at the output. If both J and K are high, then at
the clock edge, the output will toggle from one state to the other.

 Truth table of JK flip-flop

J K Q State

0 0 0 No Change

0 1 0 Reset

1 0 1 Set

1 1 Toggles Toggle

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  Characteristics table of JK flip-flop

J K Q(t) Q(t+1)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

 Characteristics equation of JK flip-flop

Q(t+1)=jkQ(t)‘+K‘Q(t)Q(t+1)=jkQ(t)‘+K‘Q(t)

D Flip-flop

 In a D flip-flop, the output can only be changed at positive or negative clock

transitions, and when the inputs changed at other times, the output will
remain unaffected. The D flip-flops are generally used for shift-registers and
counters. The change in output state of D flip-flop depends upon the active
transition of clock. The output (Q) is same as input and changes only at
active transition of clock

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  Truth table of D flip-flop

D Q

0 0

1 1

 Characteristics equation of D flip-flop

Q(t+1)=DQ(t+1)=D

T Flip-flop

 A T flip-flop (Toggle Flip-flop) is a simplified version of JK flip-flop. The T flop

is obtained by connecting the J and K inputs together. The flip-flop has one
input terminal and clock input. These flip-flops are said to be T flip-flops
because of their ability to toggle the input state. Toggle flip-flops are mostly
used in counters.

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  Truth Table of T flip-flop

T Q(t) Q(t+1)

0 0 0

0 1 1

1 0 1

1 1 0

 Characteristics equation of T flip-flop

Q(t+1)=T′Q(t)+TQ(t)′=T⊕Q(t)

Registers
A Register is a collection of flip flops. A flip flop is used to store single bit digital
data. For storing a large number of bits, the storage capacity is increased by
grouping more than one flip flops. If we want to store an n-bit word, we have to
use an n-bit register containing n number of flip flops.

The register is used to perform different types of operations. For performing the
operations, the CPU use these registers. The faded inputs to the system will store
into the registers. The result returned by the system will store in the registers.
There are the following operations which are performed by the registers:

Fetch:

It is used

o To take the instructions given by the users.

o To fetch the instruction stored into the main memory.

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Decode:

The decode operation is used

sed to interpret the instructions. In decode, the
operation performed on the instructions is identified by the CPU

. In simple words, the decode operation is used to decode the instructions.

instructions

Execute:

The execution operation is used to store the result produced by the CPU

into the memory. After storing this result, it is displayed on the user screen.

Types of Registers

There are various types of registers which are as follows:

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