Awr 1243
Awr 1243
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AWR1243
SWRS188D – MAY 2017 – REVISED DECEMBER 2021 www.ti.com
Antenna RX1
Structure RX2 SPI/I2C
RX3
RX4 External Interface to
mmWave Sensor MCU External
CSI2 (4 Lane Data + 1 Clock lane) Peripherals
TX1
Reset
TX2
TX3 Error
MCU Clock
3 Description
The AWR1243 device is an integrated single-chip FMCW transceiver capable of operation in the 76- to 81-GHz
band. The device enables unprecedented levels of integration in an extremely small form factor. AWR1243 is an
ideal solution for low power, self-monitored, ultra-accurate radar systems in the automotive space.
The AWR1243 device is a self-contained FMCW transceiver single-chip solution that simplifies the
implementation of Automotive Radar sensors in the band of 76 to 81 GHz. It is built on TI’s low-power 45-nm
RFCMOS process, which enables a monolithic implementation of a 3TX, 4RX system with built-in PLL and ADC
converters. Simple programming model changes can enable a wide variety of sensor implementation (Short,
Mid, Long) with the possibility of dynamic reconfiguration for implementing a multimode sensor. Additionally,
the device is provided as a complete platform solution including TI reference designs, software drivers, sample
configurations, API guides, and user documentation.
Device Information
PART NUMBER(2) PACKAGE(1) BODY SIZE TRAY / TAPE AND REEL
AWR1243FBIGABLQ1 Tray
FCBGA (161) 10.4 mm × 10.4 mm
AWR1243FBIGABLRQ1 Tape and Reel
(1) For more information, see Section 13, Mechanical, Packaging, and Orderable Information.
(2) For more information, see Section 12.1, Device Nomenclature.
LNA IF ADC
LNA IF ADC
Digital Front-end
(Decimation filter
chain)
LNA IF ADC
LNA IF ADC
RF Control / BIST
Table of Contents
1 Features............................................................................1 9.1 Overview................................................................... 33
2 Applications..................................................................... 2 9.2 Functional Block Diagram......................................... 33
3 Description.......................................................................2 9.3 Subsystems.............................................................. 34
4 Functional Block Diagram.............................................. 3 9.4 Other Subsystems.................................................... 37
5 Revision History.............................................................. 5 10 Monitoring and Diagnostics....................................... 39
6 Device Comparison......................................................... 6 10.1 Monitoring and Diagnostic Mechanisms................. 39
6.1 Related Products........................................................ 7 11 Applications, Implementation, and Layout............... 42
7 Terminal Configuration and Functions..........................8 11.1 Application Information............................................42
7.1 Pin Diagram................................................................ 8 11.2 Short-, Medium-, and Long-Range Radar ..............42
7.2 Signal Descriptions................................................... 12 11.3 Reference Schematic..............................................43
8 Specifications................................................................ 16 12 Device and Documentation Support..........................44
8.1 Absolute Maximum Ratings...................................... 16 12.1 Device Nomenclature..............................................44
8.2 ESD Ratings............................................................. 16 12.2 Tools and Software................................................. 45
8.3 Power-On Hours (POH)............................................ 17 12.3 Documentation Support.......................................... 45
8.4 Recommended Operating Conditions.......................17 12.4 Support Resources................................................. 45
8.5 Power Supply Specifications.....................................18 12.5 Trademarks............................................................. 46
8.6 Power Consumption Summary................................. 19 12.6 Electrostatic Discharge Caution..............................46
8.7 RF Specification........................................................20 12.7 Glossary..................................................................46
8.8 Thermal Resistance Characteristics for FCBGA 13 Mechanical, Packaging, and Orderable
Package [ABL0161].....................................................21 Information.................................................................... 47
8.9 Timing and Switching Characteristics....................... 21 13.1 Packaging Information............................................ 47
9 Detailed Description......................................................33 13.2 Tray Information for ................................................47
5 Revision History
Changes from May 1, 2020 to December 8, 2021 (from Revision C (May 2020) to Revision D
(December 2021)) Page
• Global: Updated to reflect Functional Safety-Compliance and relevant certification collateral...........................1
• Global: Replaced "A2D" with "ADC"; Changed Masters Subsystem and Masters R4F to Main Subsystem and
Main R4F; Shift to more inclusive langauge made in terms of Master/Slave terminology..................................1
• (Features) : Mentioned the specific operating temperature range for the mmWave Sensor.............................. 1
• (Applications) :Revised the figure and updated application links........................................................................2
• (Device Information): Removed a pre-production orderable part number (XA1243FPBGABL) from the table
and its assosiated features. ............................................................................................................................... 2
• Updated/Changed Functional Block Diagram to remove XA1243FPBGABL OPN specific features................. 3
• (Device Comparison) : Removed a row on Functionaly-Safety compliance and instead added a table-note for
this and LVDS Interface; modified the existing table-note on simultaneous TX operation; Additional
information on Device security added.................................................................................................................6
• (Device Comparison) : Updated/Changed RF Specification Receiver from "Max real sampling rate (Msps)" to
"Max real/complex 2x sampling rate (Msps)"; and "Max complex sampling rate (Msps)" to "Max complex 1x
sampling rate (Msps)"......................................................................................................................................... 6
• (Signal Descriptions): Removed XA1243FPBGABL OPN specific pin functions; updated descriptions for
CLKP and CLKM pins for Reference Oscillator................................................................................................ 12
• (Absolute Maximum Ratings): Added entries for externally supplied power on the RF inputs (TX and RX) and
a table-note for the signal level applied on TX..................................................................................................16
• (Power Supply Specifications): Updated/Changed footnote in Table 8-1 ........................................................ 18
• (Maximum Current Rating at Power Terminals): Updated footnotes section to add estimation assumption for
VIOIN rail.......................................................................................................................................................... 19
• (Average Power Consumption at Power Terminals): Removed 3TX, 4RX power numbers since only 2TX are
operational simultaneously in the device.......................................................................................................... 19
• (RF Specification): Updated/Changed RF Specification Receiver from "A2D sampling rate (complex)" to "ADC
sampling rate (complex 1x)"; and "A2D sampling rate (real)" to "ADC sampling rate (real/complex 2x)"........ 20
• (RF Specification): Updated/Changed the table to remove XA1243FPBGABL specific features.....................20
• (Synchronized Frame Triggering): Updated the maximum pulse width to 4ns................................................. 22
• (Clock Specifications): Updated/Changed Table 8-6 to reflect correct device operating temperature range... 24
• (Table. External Clock Mode Specifications): Revised frequency tolerance specs from +/-50 to +/-100 ppm..24
• (Switching Characteristics for Output Timing versus Load Capacitance): Updated/Modified the table to
remove Slew Rate = 1 condition; removed a footnote...................................................................................... 30
• Figure 9-1: Updated the figure to remove XA1243FPBGABL OPN specific features. .....................................33
• (Monitoring and Diagnostic Mechanisms): Added a new section..................................................................... 39
• (Reference Schematics) : Added weblinks to AWR1243 EVM documentation collateral ................................ 43
• (Device Nomenclature):Updated/changed Device Nomenclature ................................................................... 44
6 Device Comparison
FUNCTION AWR1243(1) AWR1443 AWR1642 AWR1843
Number of receivers 4 4 4 4
Number of transmitters 3 3 2 3
On-chip memory — 576KB 1.5MB 2MB
Max I/F (Intermediate Frequency) (MHz) 15 5 5 10
Max real/complex 2x sampling rate (Msps) 37.5 12.5 12.5 25
Max complex 1x sampling rate (Msps) 18.75 6.25 6.25 12.5
Device Security(2) — — Yes Yes
Processor
MCU (R4F) — Yes Yes Yes
DSP (C674x) — — Yes Yes
Peripherals
Serial Peripheral Interface (SPI) ports 1 1 2 2
Quad Serial Peripheral Interface (QSPI) — Yes Yes Yes
Inter-Integrated Circuit (I2C) interface — 1 1 1
Controller Area Network (DCAN) interface — Yes Yes Yes
CAN-FD — — Yes Yes
Trace — — Yes Yes
PWM — — Yes Yes
Hardware In Loop (HIL/DMM) — — Yes Yes
GPADC — Yes Yes Yes
LVDS/Debug(3) Yes Yes Yes Yes
CSI2 Yes — — —
Hardware accelerator — Yes — Yes
1-V bypass mode Yes Yes Yes Yes
Cascade (20-GHz sync) — — — —
JTAG — Yes Yes Yes
Number of Tx that can be simultaneously used 2 2 2 3(4)
Per chirp configurable Tx phase shifter — — — Yes
PRODUCT PREVIEW (PP),
Product
ADVANCE INFORMATION (AI), PD PD PD PD
status(5)
or PRODUCTION DATA (PD)
(1) Developed for Functional Safety applications, the device supports hardware integrity upto ASIL-B. Refer to the related documentation
for more details.
(2) Device security features including Secure Boot and Customer Programmable Keys are available in select devices for only select part
variants as indicated by the Device Type identifier in Section 3, Device Information table.
(3) The LVDS interface is not a production interface and is only used for debug.
(4) 3 Tx Simultaneous operation is supported only in AWR1843 with 1V LDO bypass and PA LDO disable mode. In this mode 1V supply
needs to be fed on the VOUT PA pin. Rest of the other devices only support simultaneous operation of 2 Transmitters.
(5) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
E VSSA VSSA VSSA VSS VSS VSS VSS VSS VSSA CLKP VSSA
VIN
J VSSA VSSA VSSA VSS VSS VSS VSS TDO CSI2_CLKM CSI2_CLKP
_13RF1
CSI2 CSI2
K RX2 VSSA VIN_18BB VSS VSS VSS VSS VSS VIOIN_18
_TXM[2] _TXP[2]
CSI2 CSI2
L VSSA VSSA VSSA VSS VSS VSS VSS TMS
_TXM[3] _TXP[3]
HS_M HS_P
M RX1 VSSA TCK
_Debug1 _Debug1
P Analog Test 1 Analog Test 2 Analog Test 3 Reserved MISO_1 SPI_HOST_INTR_1NERROR_IN QSPI_CS QSPI[1] QSPI[3] Sync_out NRESET PMIC_CLK_OUT VNWA VDDIN
R VSSA Analog Test 4 Reserved Reserved Reserved VDDIN SPI_CS_1 MOSI_1 SPI_CLK_1 QSPI_CLK QSPI[0] QSPI[2] VIOIN VIN_SRAM VSS
Not to scale
1 2 3 4 5 6 7 8
FM_CW
B VOUT_PA VSSA TX1 VSSA TX2 VSSA TX3
_SYNCIN1
VIN
C VSSA VSSA VSSA VSSA VSSA VSSA VSSA
_13RF2
FM_CW VIN
D
_SYNCOUT _13RF2
VIN
G VSSA VSSA VSSA VSS VSS VSS
_13RF1
Not to scale
1 2
3 4
VIOIN FM_CW
D
_18DIFF _SYNCIN2
CSI2 CSI2
G VSS Reserved
_TXM[0] _TXP[0]
Not to scale
1 2
3 4
VIN
H RX3 VSSA VSS
_13RF1
VIN
J VSSA VSSA VSSA VSS VSS VSS
_13RF1
M RX1 VSSA
P Analog Test 1 Analog Test 2 Analog Test 3 Reserved MISO_1 SPI_HOST_INTR_1NERROR_IN QSPI_CS
Not to scale
1 2
3 4
9 10 11 12 13 14 15
CSI2 CSI2
H VSS VSS TDI
_TXM[1] _TXP[1]
CSI2 CSI2
K VSS VSS VSS VIOIN_18
_TXM[2] _TXP[2]
CSI2 CSI2
L VSS TMS
_TXM[3] _TXP[3]
HS_M HS_P
M TCK
_Debug1 _Debug1
Not to scale
1 2
3 4
Note
All IO pins of the device (except NERROR IN, NERROR_OUT, and WARM_RESET) are non-failsafe;
hence, care needs to be taken that they are not driven externally without the VIO supply being present
to the device.
CSI2_CLKP J15 O — Differential clock Out (for CSI and LVDS debug
CSI2_CLKM J14 O — interface)
CSI2_TXP[1] H15 O — Differential data Out – Lane 1 (for CSI and LVDS
CSI2_TXM[1] H14 O — debug interface)
CSI2_TXP[2] K15 O — Differential data Out – Lane 2 (for CSI and LVDS
CSI2 TX
CSI2_TXM[2] K14 O — debug interface)
CSI2_TXP[3] L15 O — Differential data Out – Lane 3 (for CSI and LVDS
CSI2_TXM[3] L14 O — debug interface)
HS_DEBUG1_P M15 O —
Differential debug port 1 (for LVDS debug interface)
HS_DEBUG1_M M14 O —
HS_DEBUG2_P N15 O —
Differential debug port 2 (for LVDS debug interface)
HS_DEBUG2_M N14 O —
FM_CW_CLKOUT B15
O — Reserved Signal. Not applicable in AWR1243.
Reserved FM_CW_SYNCOUT D1
Space FM_CW_SYNCIN1 B1
I — Reserved Signal. Not applicable in AWR1243.
FM_CW_SYNCIN2 D15
Reference clock output from clocking subsystem
Reference clock OSC_CLKOUT A14 O — after cleanup PLL. Can be used by peripheral chip
in multichip cascading
Low-frequency frame synchronization signal output.
SYNC_OUT P11 O Pull Down Can be used by peripheral chip in multichip
System cascading
synchronization Low-frequency frame synchronization signal input.
SYNC_IN N10 I Pull Down This signal could also be used as a hardware trigger
for frame start
(1) Status of PULL structures associated with the IO after device POWER UP.
(2) For the AWR1243 WARM_RESET can be used as an output only pin for status indication.
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
PARAMETERS(1) (2) MIN MAX UNIT
VDDIN 1.2 V digital power supply –0.5 1.4 V
VIN_SRAM 1.2 V power rail for internal SRAM –0.5 1.4 V
VNWA 1.2 V power rail for SRAM array back bias –0.5 1.4 V
I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this
VIOIN –0.5 3.8 V
supply.
VIOIN_18 1.8 V supply for CMOS IO –0.5 2 V
VIN_18CLK 1.8 V supply for clock module –0.5 2 V
VIOIN_18DIFF 1.8 V supply for CSI2 port –0.5 2 V
VIN_13RF1 1.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could
–0.5 1.45 V
VIN_13RF2 be shorted on the board.
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) This value is for an externally applied signal level on the TX. Additionally, a reflection coefficient up to Gamma = 1 can be applied on
the TX output.
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard
terms and conditions for TI semiconductor products.
(2) The specified POH are applicable with max Tx output power settings using the default firmware gain tables. The specified POH would
not be applicable, if the Tx gain table is overwritten using an API.
VIN_13RF1
(1-V Internal LDO
bypass mode)
0.95 1 1.05 V
VIN_13RF2
(1-V Internal LDO
bypass mode)
VIN18BB 1.8-V Analog baseband power supply 1.71 1.8 1.9 V
VIN_18VCO 1.8V RF VCO supply 1.71 1.8 1.9 V
Voltage Input High (1.8 V mode) 1.17
VIH V
Voltage Input High (3.3 V mode) 2.25
Voltage Input Low (1.8 V mode) 0.3*VIOIN
VIL V
Voltage Input Low (3.3 V mode) 0.62
VOH High-level output threshold (IOH = 6 mA) VIOIN – 450 mV
VOL Low-level output threshold (IOL = 6 mA) 450 mV
VIL (1.8V Mode) 0.2
(1) The device only supports simultanoeus operation of 2 transmitters. In the 1-V LDO bypass mode, 1V supply needs to be fed on the
VOUT PA pin.
The 1.3-V (1.0 V) and 1.8-V power supply ripple specifications mentioned in Table 8-2 are defined to meet
a target spur level of –105 dBc (RF Pin = –15 dBm) at the RX. The spur and ripple levels have a dB-to-dB
relationship, for example, a 1-dB increase in supply ripple leads to a ~1 dB increase in spur level. Values quoted
are rms levels for a sinusoidal input applied at the specified frequency.
Table 8-2. Ripple Specifications
RF RAIL VCO/IF RAIL
FREQUENCY (kHz) 1.0 V (INTERNAL LDO BYPASS)
1.3 V (µVRMS) 1.8 V (µVRMS)
(µVRMS)
137.5 7 648 83
275 5 76 21
550 3 22 11
1100 2 4 6
2200 11 82 13
4400 13 93 19
6600 22 117 29
(1) The specified current values are at typical supply voltage level.
(2) The exact VIOIN current depends on the peripherals used and their frequency of operation.
8.7 RF Specification
over recommended operating conditions and with run time calibrations enabled (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
76 to 77 GHz (VCO1) 14
Noise figure dB
77 to 81 GHz (VCO2) 15
1-dB compression point (Out Of Band)(1) –8 dBm
Maximum gain 48 dB
Gain range 24 dB
Gain step size 2 dB
Image Rejection Ratio (IMRR) 30 dB
IF bandwidth(2) 15 MHz
ADC sampling rate (real/complex 2x) 37.5 Msps
ADC sampling rate (complex 1x) 18.75 Msps
Receiver
ADC resolution 12 Bits
Return loss (S11) <–10 dB
Gain mismatch variation (over temperature) ±0.5 dB
Phase mismatch variation (over temperature) ±3 °
RX gain = 30dB
In-band IIP2 IF = 1.5, 2 MHz at 16 dBm
–12 dBFS
RX gain = 24dB
Out-of-band IIP2 IF = 10 kHz at -10dBm, 24 dBm
1.9 MHz at -30 dBm
Idle Channel Spurs –90 dBFS
Output power 12 dBm
Transmitter
Amplitude noise –145 dBc/Hz
Frequency range 76 81 GHz
(1) 1-dB Compression Point (Out Of Band) is measured by feed a Continuous wave Tone (10 kHz) well below the lowest HPF cut-off
frequency.
(2) The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set
of available HPF corners is summarized as follows:
Available HPF Corner Frequencies (kHz)
HPF1 HPF2
175, 235, 350, 700 350, 700, 1400, 2800
Figure 8-1 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain
programmed.
18 -18
NF (dB)
In-band P1DB (dBm)
16 -24
NF (dB)
12 -36
10 -42
8 -48
30 32 34 36 38 40 42 44 46 48
RX Gain (dB)
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) °C/W = degrees Celsius per watt.
(3) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(4) Air flow = 1 m/s
SOP
Setup DC power SOP
Time Stable before MSS nRESET DC
DC Hold time to QSPI
BOOT ASSERT Power
Power nRESET nRESET READ
START tPGDEL notOK
OK release
VDDIN,
VIN_SRAM
VNWA
VIOIN_18
VIN18_CLK
VIOIN_18DIFF
VIN18_BB
VIN_13RF1
VIN_13RF2
VIOIN
SOP[2.1.0]
VBGAP
OUTPUT
CLKP, CLKM
Using Crystal
MCUCLK
OUTPUT (1)
Tactive_frame
SYNC_IN
(Hardware
Trigger)
Radar
Frames
Tpulse
Tlag
Frame-1 Frame-2
Cf1
CLKP
Cp 40 MHz
CLKM
Cf2
Note
The load capacitors, Cf1 and Cf2 in Figure 8-4, should be chosen such that Equation 1 is satisfied.
CL in the equation is the load specified by the crystal manufacturer. All discrete components used
to implement the oscillator circuit should be placed as close as possible to the associated oscillator
CLKP and CLKM pins.Note that Cf1 and Cf2 include the parasitic capacitances due to PCB routing.
C f2
C L = C f1 ´ +CP
C f1 + C f 2 (1)
In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only; CLKM
is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally. Table 8-7
lists the electrical characteristics of the external clock signal.
8.9.4.1.2 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input,
and SPISOMI = output)
8.9.4.1.3 SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input,
and SPISOMI = output)
LVDS_TXP/M
LVDS_FRCLKP/M
Data bitwidth
LVDS_CLKP/M
Trise
LVDS_CLK
1100 ps
(1) The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.
CSI2_CLK(P/M)
0.5UI + Tskew
CSI2_TX(P/M)
1 UI
Clock
Lane
Data Lane
Dp/Dn
VOL TREOT
Capture
TD-TERM-EN THS-SKIP
1st Data Bit LP-11
LP-11 LP-01 LP-00 TEOT
THS-SETTLE
THS-TRAIL THS-EXIT
VIH(min)
VIL(max)
VIH(min)
VIL(max)
THS-SKIP
THS-SETTLE
A. The HS to LP transition of the CLK does not actually take place since the CLK is always ON in HS mode.
Figure 8-11. Switching the Clock Lane Between Clock Transmission and Low-Power Mode
9 Detailed Description
9.1 Overview
The AWR1243 device is a single-chip highly integrated 77-GHz transceiver and front end that includes three
transmit and four receive chains. The device can be used in long-range automotive radar applications such
as automatic emergency braking and automatic adaptive cruise control. The AWR1243 has extremely small
form factor and provides ultra-high resolution with very low power consumption. This device, when used with
the TDA3X or TD2X, offers higher levels of performance and flexibility through a programmable digital signal
processor (DSP); thus addressing the standard short-, mid-, and long-range automotive radar applications.
9.2 Functional Block Diagram
LNA IF ADC
LNA IF ADC
Digital Front-end
(Decimation filter
chain)
LNA IF ADC
LNA IF ADC
RF Control / BIST
9.3 Subsystems
9.3.1 RF and Analog Subsystem
The RF and analog subsystem includes the RF and analog circuitry – namely, the synthesizer, PA, LNA, mixer,
IF, and ADC. This subsystem also includes the crystal oscillator and temperature sensors. The three transmit
channels can be operated simultaneously for transmit beamforming purpose as required; whereas the four
receive channels can all be operated simultaneously.
Please note that AWR1243 device supports simultaneous operation of 2 transmitters only.
Lock Detect
RX LO
x4
MULT
TX LO
Timing SYNC_OUT
Engine
SYNC_IN
RFSYNTH
Lock Detect
Clean-Up
PLL
SoC Clock
XO /
CLK Detect
Slicer
FM_CW_SYNCIN1*
FM_CW_SYNCIN2*
OSC_CLKOUT
FM_CW_SYNCOUT
FM_CW_CLKOUT
40 MHz
* These pins are 20GHz LO input pins. Connect LO to one pin while grounding the
other pin.
PCB 6 bits
Chip
12dBm
û- LO
@ 50 Ÿ
0/180°
(from Timing Engine)
Self Test
Self Test
DAC
Loopback
Path
Package
DSM
Chip
Image Rejection
PCB
I/Q Correction
Decimation
ADC Buffer
I RSSI
50 W
LO
GSG
Q
DSM
DAC
Ramp/Chirp 1 2 3 N
Data Ready
F L H L L H L L H L L H L F
S S S E S S E S S E S S E E
Short
Packet
Short Long Short
ST SP ET LPS Packet Packet Packet
Chirp 1 data
.5μs-.8μs Data rate/Lane should be such that "Chirp + Interchirp" period
should be able to accommodate the data transfer
Copyright © 2017, Texas Instruments Incorporated
Frame Start – CSi2 VSYNC Start Short PacketLine Start – CSI2 HSYNC Start Short PacketLine End – CSI2 HSYNC End Short
PacketFrame End – CSi2 VSYNC End Short Packet
The data payload is constructed with the following three types of information:
• Chirp profile information
• The actual chirp number
• ADC data corresponding to chirps of all four channels
– Interleaved fashion
• Chirp quality data (configurable)
The payload is then split across the four physical data lanes and transmitted to the receiving D-PHY. The data
packet packing format is shown in Figure 9-6
First
11 5 1 0 11 0
CH Chirp Channel
NU Profile Number Chirp Num
11 5 1 0 11 0
CH Chirp Channel
NU Profile Number Chirp Num
11 5 1 0 11 0
CH Chirp Channel
NU Profile Number Chirp Num
11 5 1 0 11 0
CH Chirp Channel
NU Profile Number Chirp Num
11 0 11 0
Last
Figure 9-6. Data Packet Packing Format for 12-Bit Complex Configuration
(1) Monitoring is done by the TI's code running on BIST R4F. There are two modes in which it could be configured to report the
temperature sensed via API by customer application.
a. Report the temperature sensed after every N frames
b. Report the condition once the temperature crosses programmed threshold.
It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4Fvia Mailbox.
(2) Monitoring is done by the TI's code running on BIST R4F.
There are two modes in which it could be configured to report the detected output power via API by customer application.
a. Report the power detected after every N frames
b. Report the condition once the output power degrades by more than configured threshold from the configured.
It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4F.
Note
Refer to the Device Safety Manual or other relevant collaterals for more details on applicability of all
diagnostics mechanisms. For certification details, refer to the device product folder.
Antenna RX1
Structure RX2 SPI
RX3 External
RX4 MCU Automotive
AWR1243
(For Example Interface PHY
CSI2 (4 Lane Data + 1 Clock lane)
TDA3x)
TX1
Reset
TX2
TX3 Error
MCU Clock
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package
type (for example, ABL0161 ALB0161), the temperature range (for example, blank is the default commercial
temperature range). Figure 12-1 provides a legend for reading the complete device name for any AWR1243
device.
For orderable part numbers of AWR1243 devices in the ABL0161 package types, see the Package Option
Addendum of this document , the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the AWR1243 Device Errata .
AWR 1 2 43 B I G ABL Q1
Qualification
Q1 = AEC-Q100
Prefix Blank = no special Qual
XA = Pre-Production
AWR = Production Tray or Tape & Reel
Generation R = Big Reel
± GHz Blank = Tray
Variant Package
2 = FE ABL = BGA
4 = FE + FFT + MCU
6 = FE + MCU + DSP
8 = FE + FFT + MCU + DSP Security
Num RX/TX Channels G = General
RX = 1,2,3,4 S = Secure
TX = 1,2,3 D = Development Secure
Models
AWR1243 BSDL model Boundary scan database of testable input and output pins for IEEE 1149.1 of the
specific device.
AWR1x43 IBIS model IO buffer information model for the IO buffers of the device. For simulation on a
circuit board, see IBIS Open Forum.
AWR1243 checklist for A set of steps in spreadsheet form to select system functions and pinmux options.
schematic review, layout Specific EVM schematic and layout notes to apply to customer engineering. A
review, bringup/wakeup bringup checklist is suggested for customers.
12.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
The current documentation that describes the DSP, related peripherals, and other technical collateral follows.
Errata
AWR1243 device errata Describes known advisories, limitations, and cautions on silicon and provides
workarounds.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 1-Jun-2023
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
AWR1243FBIGABLQ1 ACTIVE FCCSP ABL 161 176 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 AWR1243 Samples
IG
964FC
AWR1243FBIGABLRQ1 ACTIVE FCCSP ABL 161 1000 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 AWR1243 Samples
IG
964FC
ABL G1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 1-Jun-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
TRAY
Pack Materials-Page 1
GENERIC PACKAGE VIEW
ABL 161 FCBGA - 1.17 mm max height
10.4 x 10.4, 0.65 mm pitch PLASTIC BALL GRID ARRAY
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225978/A
www.ti.com
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