Digital Electronics 1

Digital Electronics
(Theory)
GATE & ESE
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Contents
Chapter 1 Number Systems 07 - 26
Chapter 2 Boolean Algebra and Logic Gates 27 - 67
Chapter 3 Combinational Logic Circuits 69 - 109
Chapter 4 Sequential Logic Circuit 111 - 148
Chapter 5 Data Converters 149 - 159
Chapter 6 IC Logic Families 161 - 185
Chapter 7 Semiconductor Memories 187 - 193
Chapter 8 Microprocessors 195 - 264
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4
Syllabus EE
Combinational and sequential logic circuits, multiplexer, demultiplexer, schmitt trigger,
sample and hold circuits, A/D and D/A converters, 8085 microprocessor: architecture,
programming and interfacing.
Syllabus ECE
• Number systems; binary integers and floating point numbers
• Combinatorial circuits: Boolean algebra, minimization of functions using Boolean
identities and Karnaugh map, logic gates and their static CMOS implementations,
arithmetic circuits, code converters, multiplexers, decoders and PLAs
• Sequential circuits: latches and flip-flops, counters, shift-registers and finite state
machine, propagation delay, setup and hold time, critical path delay
• Data converters: sample and hold circuits, ADCs and DACs
• Semiconductor memories: ROM, SRAM, DRAM
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6
Number Systems
Chapter 1 – Number Systems

Objectives
Upon completion of this chapter you will be able to:
• Convert a number from one number system to its equivalent in another number
system
• Represent the decimal number in binary codes like BCD, Excess-3 and gray code.
• Perform arithmetic operation on binary numbers and BCD numbers
Introduction
In science, technology and business and many other fields of endeavor we constantly
deal with quantities. These quantities are measured, manipulated and recorded using
physical systems. There are basically two systems to represent numerical value of a
quantity which are analog and digital. In analog representation a quantity is measured
by voltage, Current or meter movement which is proportional to the quantity under
measurement. Some examples of analog representation are auto speedometer, mercury
thermometer etc.
In digital representation, quantities are not represented by proportional values but
rather by symbols or digits. Some examples of digital representation are 10 decimal
digits, 26 alphabets, 52 playing cards etc. The most frequently used number systems in
the applications of digital computers are binary number system, octal number system,
decimal number system and hexadecimal number system.
Advantages of Digital Representation Over Analog Representation

The chief reasons to shift to digital technology are:
(1) Digital systems are easier to design
(2) Information storage is easy
(3) Accuracy and precision are greater
(4) Operations can be programmed
(5) Digital circuits are less affected by noise
(6) Digital systems use switching circuits having only two positions, ON and OFF.
Hence they are easier to design
(7) Digital processing depends on the principle of Boolean algebra which is a simple
mathematical process
(8) Error correction and detection as well as data comparison is possible in digital
systems
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Number Systems
Introduction to Number Systems
Definition and Importance

Number system is the basis for counting various items. On hearing the word ‘number’, all
of us immediately think of a familiar decimal number system with its 10 digits: 0, 1, 2, 3,
4, 5, 6, 7, 8 and 9.
Few Important Points to Define a Number System

To define any number system, we have to specify the following aspects:
(i) Base of the number systems such as 2, 8, 10 or 16
(ii) The base decides the total number of digits available in the number system. For
example, if base is 2, we have 2-digits (0 and 1), if base is 10, we have 10-digits
(0 to 9) and so on. Therefore, the total number of digits available in the number
system is equal to the base of the number system
(iii) First digit in the number system is always zero (0) and the last digit in the number
system is always base −1. As an example, in the decimal system, the last digit is 9,
i.e., (10 − 1 = 9)
Base or Radix (R) of a Number System

The base or radix of a number system is defined as the number of different symbols
(digits or characters) used in that number system. It is denoted by r.
The radix of binary number system = 2 i.e., it uses two different symbols 0 and 1 to write
the number sequence.
The radix of octal number system = 8 i.e., it uses eight different symbols 0, 1, 2, 3, 4, 5, 6
and 7 to write number sequences.
The radix of the decimal number system = 10 i.e., it uses ten different symbols 0, 1, 2, 3,
4, 5, 6, 7, 8 and 9 to write number sequences.
The radix of hexadecimal number system = 16 i.e., it uses sixteen different symbols 0, 1,
2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E and F to write the number sequence.
The radix of ternary number system = 3 i.e., it uses three different symbols 0, 1 and 2 to
write the number sequence.
To distinguish one number system from the other, the radix of the number system is
used as a suffix to that number.
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Number Systems
Various Numbering Systems
S.NO. Name of the number system Base/Radix
1 Binary 2
2 Octal 8
3 Decimal 10
4 Hexadecimal 16
5 Ternary 3
Example: 102 binary number; 108 octal number; 1010 decimal number; 1016 hexadecimal
number
Positional Number Systems

(1) Base or radix is equal to the number of digits in the system
(2) The largest value of digit is one (1) less than the radix
(3) Each digit is multiplied by the base raised to the appropriate power depending
upon the digit position
The maximum value of digit in any number system is given by (r – 1).
Example: Maximum value of digit in decimal number system = (10 – 1) = 9.

• The number system, in which the weight of each digit depends on its relative
position within the number, is called positional number system
• Any positional number system can be expressed as sum of products of place value
and the digit value
• Binary, Octal, Decimal and Hexadecimal number systems are called positional
number systems
Example: 75610 = 7 × 102 + 5 × 101 + 6 × 100

156.248 = 1 × 82 + 5 × 81 + 6 × 80 + 2 × 8−1 + 4 × 8-2
• The place values or weights of different digits in a mixed decimal number are as
follows:
105 104 103 102 101 100 ∙ 10−1 10−2 10−3 10-4
Decimal point
• The place values or weights of different digits in a mixed binary number are as
follows:
24 23 22 21 20 ∙ 2−1 2−2 2−3 2−4
Binary point
The place values or weights of different digits in a mixed octal number are as
follows:
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Number Systems
84 83 82 81 80 ∙ 8−1 8−2 8−3 8−4

Octal point
• The place values or weights of different digits in a mixed hexadecimal number are as
follows:
164 163 162 161 160 ∙ 16−1 16−2 16−3 16−4
Hexadecimal point
Decimal to Radix-r Conversion
(a) Integer Number

Divide the given decimal number repeatedly by ‘r’ and collect the remainders. This
must continue until the integer quotient becomes zero. The remainders are then
written in reverse order to get the binary output.
Solved Examples
Problem:
Convert the following decimal number 3710 into binary equivalent.
Solution: r = 2
Quotient Remainder
37/2 18 + 1
18/2 9+0
9/2 4 + 1
4/2 2+0
2/2 1+0
½ 0 + 1

1 0 0 1 0 1 ∴ 3710 = 1001012
(b) Fractional Number

First, the fractional number is multiplied by ‘r’ to give an integer and a fraction.
The new fraction is multiplied by ‘r’ to give a new integer and a new fraction. This
process is continued until the fraction becomes 0 or until the number of digits has
sufficient accuracy.
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Number Systems
Solved Examples
Problem:
Convert the following decimal number 0.687510 into binary equivalent.
Solution: r = 2
0.6875 × 2 = 1.3750 1
0.3750 × 2 = 0.7500 0
Go from top
to Bottom
0.7500 × 2 = 1.5000 1
0.5000 × 2 = 1.0000 1
∴ (0.6875)10 = 0.10112
Problem:
Convert the following decimal number (37.6875)10 to its binary equivalent.
Solution: r = 2
(37.6875)10 = x2
3710 = 1001012 0.687510 = 0.1011
Hence (37.6875)10 = 100101.10112
Note:
(A) Convert the integral part of decimal to binary equivalent
(1) Divide the decimal number by 2 and store remainders in an array
(2) Divide the quotient by 2
(3) Repeat step 2 until we get the quotient equal to zero
(4) Equivalent binary number would be the reverse of all remainders of step 1
(B) Convert the fractional part of decimal to binary equivalent

(1) Multiply the fractional decimal number by 2
(2) Integral part of the resultant decimal number will be the first digit of the fraction
binary number
(3) Repeat step 1 using only the fractional part of the decimal number and then step 2
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Number Systems
Problem:
Convert the following decimal number 15310 to its octal equivalent.
Solution: r = 8
Integer Quotient Remainder
153/8 = 19 +1
Go from
19/8 =2 +3 bottom
to top
2/8 =0 +2
∴ 15310 = 2318.
Problem:
Convert the following decimal number (0.513)10 to its octal equivalent.
Solution: r = 8
0.513 × 8 = 4.104 4
0.104 × 8 = 0.832 0
0.832 × 8 = 6.656 6 Go from top
0.656 × 8 = 5.248 5 to Bottom
0.248 × 8 = 1.984 1
0.984 × 8 = 7.872 etc. 7
(0.513)10 = (0.406517…)8
Problem:
Convert the following decimal number 25310 to its hexadecimal equivalent.
Solution: r = 16
253/16 = 15 + (13 = D)
15/16 = 0 + (15 = F) 4 25310 = FD16.
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Number Systems
Radix-r to Decimal Conversion

Multiply each digit of the radix-r number by its positional weight and take the sum to
obtain the decimal equivalent.
Solved Examples
Problem:
Convert the binary number 1011012 to its decimal equivalent.
Solution: 101101 = 25 × 1 + 0 × 24 + 1 × 23 + 0 × 21 + 1 × 20 = 32 + 8 + 4 + 1 = 45
(101101)2 = 4510
Problem:
Convert the octal number 2578 to its decimal equivalent.
Solution: 2578 = 2 × 82 + 5 × 81 + 7 × 80 = 128 + 40 + 7 = 17510.
Problem:
Convert the hexadecimal number 1AF.23 to decimal.
Solution: 1AF.2316 = 1 × 162 + 10 × 161 + 15 × 160 + 2 × 16-1 + 3 × 16−2 = (431.13678…)10
Numbers with Different Bases
Decimal (Base = 10) Binary (Base = 2) Octal (Base = 8) Hexadecimal (Base = 16)
00 0000 00 0
01 0001 01 1
02 0010 02 2
03 0011 03 3
04 0100 04 4
05 0101 05 5
06 0110 06 6
07 0111 07 7
08 1000 10 8
09 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
15 1111 17 F
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Number Systems
Solved Examples
Problem:
Convert the following hexadecimal number (2C6B.F2)16 into its binary equivalent.
Solution: 2 -> 0010

C -> 1100
6 -> 0110
B -> 1011
F -> 1111
2 -> 0010
(2C6B.F2)16 = (0010110001101011.11110010)2
Problem:
Convert the following hexadecimal number (3A.E5)16 into its octal equivalent.
Solution: (3A.E5)16 = (0011 1010.1110 0101)2 = (111 010.111 001 010)2 = (72.712)8
Why Octal or Hexadecimal?

Hex and Octal are used as shorthand ways of representing strings of bits. In computers,
strings of 64-bits are very common and may not always represent a numerical value. Like
in microprocessors they may represent an address or an Op-Code. So it is always easier
and less error prone to represent such strings in octal or hexadecimal form.
Summary of Conversion
• When converting from radix-r to decimal use the method of taking the weighted sum
of each digit position
• When converting from decimal to radix-r, use the method of repeatedly dividing by
‘r’ and collecting remainders
• When converting from binary to octal (or hex), group the bits in a group of 3 (or 4)
bits and represent each such combination by equivalent octal or hexadecimal value
• When converting from octal (or hex) to binary, represent each digit by a group of
3(or 4) bits
• When converting octal to hex (or vice versa), first convert to binary and then convert
to desired number system
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Number Systems
Binary Codes
BCD (Binary Coded Decimal): In this each digit of the decimal number is represented by
its four bit binary equivalent. It is also called natural BCD or 8421 code. It is a weighted
code.
10 out of 16 combinations of 4 bits are used in BCD code and 6 combinations are left
unused. Don’t care values or unused states in BCD code are 1010, 1011, 1100, 1101, 1110,
and 1111.
Excess-3 Code: This is an un-weighted binary code used for decimal digits. Its code
assignment is obtained from the corresponding value of BCD after the addition of 3.
Don’t care values or unused states in excess-3 code are 0000, 0001, 0010, 1101, 1110, 1111.
Gray Code: It is a very useful code called “minimum change codes” in which only one bit
in the code group changes when going from one step to the next.
It is an unweighted code which means different bit positions do not have any specific
weights assigned to them. There are no unused states in this code.
• Binary to Gray Code Conversion

MSB in the gray code is the same as the corresponding digit in binary number. Starting
from left to right add each pair of adjacent binary digits to get the next gray code digit
(Any carry if generated must be discarded).
• Gray Code to Binary Conversion

MSB in the binary is the same as that in the gray code. Then each binary digit is added
in the generated gray digit in the next adjacent position (Any carry if generated must
be discarded).
Solved Examples
Problem:
Convert the following decimal number (943)10 into its BCD equivalent.
Solution:
9 -> 1001
4 -> 1000
3 -> 0011
(943)10 -> (100110000011)
Problem:
Convert the following decimal number (137)10 into its binary and BCD equivalent.
Solution:
(137)10 -> (10001001)2
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Number Systems
(137)10 -> (000100110111)BCD

Here, BCD number requires 12 bits whereas binary equivalent requires 8 bits.
Problem:
Convert the following decimal number (48)10 into its equivalent excess-3 code.
Solution: BCD equivalent of (48)10 = (01001000)2

Excess-3 Code = BCD Code + 3 = (01001011)
Problem:
Convert the following binary number (10011)2 into its equivalent gray code.
Solution:
1 0 0 1 1
1 1 0 1 0
(10011)2 == 🡺 (11010)Gray
Problem:
Convert the following gray code (11010)Gray into its binary equivalent.
Solution:
1 1 0 1 0
1 0 0 1 1
(11010)Gray 🡺 (10011)2
Representation of Various Decimal Numbers in Binary Codes
Decimal Binary Gray BCD Excess-3
0 0000 0000 0000 0011
1 0001 0001 0001 0100
2 0010 0011 0010 0101
3 0011 0010 0011 0110
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Number Systems
4 0100 0110 0100 0111
5 0101 0111 0101 1000
6 0110 0101 0110 1001
7 0111 0100 0111 1010
8 1000 1100 1000 1011
9 1001 1101 1001 1100
10 1010 1111
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000
Complements
Complements are used in digital computers to simplify the subtraction operation and
logical manipulation. Two types of complements are defined:
• Radix complement: also called as r’s complement
• Diminished radix complement: also called as (r − 1)’s complement
Given a number ‘N’ in base ‘r’ having ‘n’ digits:
• (r − 1)’s complement is defined as (rn − 1) − N
• r’s complement is defined as rn − N
• So, r’s complement can be derived from (r-1)’s complement by adding 1
• 1’s complement of a number can be directly obtained by complementing all the

bits in the number N. 2’s complement can then be obtained by adding 1 to the 1’s
complement
Solved Examples
Problem:
Find 9’s complement of the decimal number (54700)10.
Solution: N = 54700, n = 5, r = 10
9’s complement = (105 − 1) − 54700 = 99999 − 54700 = 45299
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Number Systems
Problem:
Find 1’s complement of the binary number (10110110)2.
Solution: Complement all the bits i.e. replace all 0’s by 1’s and vice versa.
1’s complement of (10110110)2 = (01001001)2
Problem:
Find 2’s complement of the binary number (10110011)2.
Solution: 1’s complement of (10110011)2 = (01001100)2

2’s complement = 1’s complement + (00000001)2 = (01001101)2
Signed and Unsigned Magnitude Representation

Positive numbers (including zero) can be represented as Unsigned Numbers but we need
a notation for negative numbers. So, the MSB of any binary number is kept reserved for
sign notation in signed number representation. The convention is to make sign bit ‘0’ for
positive numbers and ‘1’ for negative numbers.
In sign magnitude representation, the range of n-bits is –(2n−−1 − 1) to (2n−−1 − 1)
In 1’s complement representation, positive numbers are represented similarly to positive
numbers in sign magnitude, but for representing negative numbers, we first write
positive numbers and then take 1’s complement of that number.
In 2’s complement representation, positive numbers are represented similarly to positive
numbers in sign magnitude, but for representing negative numbers, we first write
positive numbers and then take 2’s complement of that number.
Range of 1’s complement Signed magnitude number is –(2n-1 − 1) to (2n-1 − 1)
Range of 2’s complement Signed magnitude number is –2n−−1 to (2n−−1 − 1)
Solved Examples
Problem:
What is the range of signed decimal numbers that can be represented by 6-bit 1’s
complement number?
Solution: Range = −(2n−−1 − 1) to (2n−−1 − 1)
In this case, n = 6
Hence, range = −31 to 31
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Number Systems
Representation in Sign Magnitude Form
Signed 2’s Signed 1’s Signed Magnitude

Decimal
Complement Form Complement Form Form
+7 0111 0111 0111
+6 0110 0110 0110
+5 0101 0101 0101
+4 0100 0100 0100
+3 0011 0011 0011
+2 0010 0010 0010
+1 0001 0001 0001
+0 0000 0000 0000
-0 ------ 1111 1000
-1 1111 1110 1001
-2 1110 1101 1010
-3 1101 1100 1011
-4 1100 1011 1100
-5 1011 1010 1101
-6 1010 1001 1110
-7 1001 1000 1111
-8 1000 ----- -----
Notes: Negative Zero is not represented in 2’s Complement form.
Binary Arithmetic
Binary Arithmetic refers to arithmetic operation on binary numbers like addition,
subtraction and multiplication. Subtraction can be treated as addition of negative
numbers so that addition and subtraction can be looked upon as binary addition of two
numbers.
Rules
(1) When both numbers have same sign (i.e., addition) then we add only magnitudes
and use the sign as MSB,
(2) When both numbers have different sign (i.e., subtraction) then we can perform
addition in two ways:
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Number Systems
(1) 1’s Complement Addition

One number is kept as it is and the other number is complemented and then only
magnitudes are added.
If carry is generated then it is added to LSB of the result and sign of the result is the
same as sign of the un-complemented number.
If carry is not generated then 1’s complement of the result is taken and the sign of
result is the same as that of complemented number.
(2) 2’s Complement Addition
In this addition carry is discarded, so sign bit is considered as it is in the result. If
MSB is ‘1’ it indicates that the result is negative and 2’s complement of the result
must be taken.
Solved Examples
Problem:
Find the result of binary addition of (3)10 and (4)10.
Solution:
+3 => 0 0 1 1

+4 => 0 1 0 0
+7 => 0 1 1 1
Since MSB is 0, the result is positive.
Problem:
−4)10.
Find the result of binary addition of (3)10 and (−
Solution: 1’s complement of 4 (100) => (011)
+3 => 0 1 1
-4 => 0 1 1
Always take care of balancing of numbers; it means both

number have equal number of digits or not.
+ 1 1 0
Since, no carry is generated; we need to take 1’s complement of result.

1’s complement of result = (001)2 = 110
Sign of the result is the same as that of the complemented number that is negative so
the result is −110.
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Number Systems
Problem:
−4)10 using 2’s complement addition.
Perform binary addition of (3)10 and (−
Solution: Taking 2’s complement of 4 (0100) => (1100)
+3 => 0 0 1 1
-4 => 1 1 0 0
Always take care of balancing of numbers; it means both
number have equal number of digits or not
1 1 1 1
Since, the MSB is 1 the result is negative and we need to take 2’s complement of the
result.
2’s complement of result = (001)2 = 110
So, the result is −110.
BCD Addition
(1) Add the BCD numbers as regular true binary numbers
(2) If the sum is 9(1001) or less, the result is a valid BCD Number
(3) If the sum is greater than 9 or there is a carry out of MSB, the result is an invalid
BCD number
(4) If the result is invalid then 6(0110) is added to the result to make it valid and carry
out of BCD digit is added to the next more significant BCD digit
Solved Examples
Problem:
Perform BCD addition of the following numbers (87)10 and (99)10.
Solution
87 = 1 0 0 0 0 1 1 1
99 = 1 0 0 1 1 0 0 1
1 0 0 0 0
Carry
So, this BCD number is invalid as per Step-3 so 6 (0110) must be added.
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Number Systems
87 = 1 0 0 0 0 1 1 1
99 = 1 0 0 1 1 0 0 1
1 0 0 0 0
+ 0 1 1 0
1 0 1 1 0
Adding next digits with carry generated
87 = 1 0 0 0 0 1 1 1
99 = 1 0 0 1 1 0 0 1
1 0 0 1 0 0 1 1 0
Carry
So, this BCD digit is also invalid due to carry generated and thus we add 6 (0110) to the
result.
The result thus obtained is (1 1000 0110) = (0001 1000 0110) = (186)10
Floating–Point Number
Basics Concepts
All the numbering systems which have been discussed so far fall in the category of
base r fixed point numbers. Fixed point number means that the fractional number (i.e.,
decimal point) once finalized will remain fixed. The functional point is fixed within each n
bit number word. For example, if the system is 8 bit, and we decided that the fractional
point is after 5th bit then binary format will be as given below.
Floating Point
B4 B3 B2 B1 B0 . B−1 B−2 B−3
Here, it will be interesting to note that ones, the number of bits is finalized for a
particular system, we cannot change it abruptly. Hence, for above format, minimum
number we can represent is (0)2 i.e.,
B4 B3 B2 B1 B0. B−1 B−2 B−3 = (00000.000)2 Minimum number that we can present is
B4 B3 B2 B1 B0. B−1 B−2 B−3 = (11111.111)2 i.e., (31.875)10
22
Number Systems
Remedy
The remedy to this problem is the switch over to the scientific notation. In scientific
notation, the number is in the form of N = M × 10E, where M and E are fixed point
numbers called mantissa and exponent respectively.
E is an integer that specifies the number of zeros to be appended to M, to obtain floating
point number N. Here, we may ask one question why the version of scientific number
(notation) is called FLOATING POINT. To understand this, we shall take a simple example.
Let us consider the number (1000.234)10
This number can be represented as under:
1000234 × 10−3
1000234 × 10−2
1000234 × 10−1
1000234 × 10−0
1000234 × 101
10.00234 × 102
1.000234 × 103
0.1000234 × 104
In representation of (1000.234)10, we must have observed that the decimal point is
not fixed as such it can FLOAT from number to number depending upon power of 10.
Normally, in scientific notation, we represent numbers as M × BE. Therefore, depending
upon our requirement, we set E and in M will allow decimal points to float. Therefore, it
is called a floating-point numbering system. In N = ±M × BE,
B = base of floating point number system. We have taken base 10 for the decimal system.
But, for binary number, it will be 2, B = 2
0 1 9 10 31
S Exponent E Mantissa (significand)
Sign 8 bit signed exponent 23 bit M(only magnitude)

bit
23
Number Systems
Question:
Consider the following floating point number representation
31 24 23 0
Exponent Mantissa
The exponent is in 2's complement representation and mantissa is in the sign magnitude
of the normalized number in this representation.
Solution:
Given floating point number representation is
31 24 23 0
Exponent Mantissa
Exponent are in 2's complement representation and its 7-bit long.

Mantissa are in sign magnitude from and its is 23-bit long.
Minimum value of magnitude of mantissa is.
0.100 0000 0000 0000 0000 0000

(1 followed by 22-zero's)
It represent the number in floating point normalization is,
Number of 1's after Number of 1's after

−
⇒ decimal piont decimal piont
2 −1 ×2
⇒ (21 − 1) × 2−1
⇒ 0.5
Maximum value of magnitude of mantissa is,
0.111 1111 1111 1111 1111 1111

(1 followed by 22 1's)
It represent the number in following point normalization is,
Number of 1's after Number of 1's after

−
⇒ decimal piont decimal piont
2 −1 ×2
24
Number Systems
⇒ (223 − 1) × 2−23
⇒ (1 − 2−23)
Thus the range of magnitude of the normalized number is 0.5 to (1 − 2− 23).
Question:
The following is a scheme for floating point number representaion using 16 bits.
Bit position
15 14 9 8 0
S e m
Sign Exponent Mentissa
Let S, e, m be the number represented in binary in the sign, exponent and mentissa field
respectively. Then the floating point number represented is,
(−1)s (1 + m × 2−g) ee − 31, is the exponent ≠ 111111
0 Otherwise
What is the maximum difference between two successive real number representable in
this system?
Solution:
Given floating point number representation using 16-bit is show below
Bit position
15 14 9 8 0
S e m
Sign bit Exponent Mantissa
First Method
According to question, definition of floating point number is,
(−1)s (1 + m × 2−g) 2e − 31, if the exponent

≠ 111111 ≠ 63
0 Otherwise
25
Number Systems
Maximum value of exponent (e) can be 111110 = 62

i.e., e = 62
So floating point number representation is
(−1)s (1 + m × 2−g) 2+ 31, if e ≠ 63

0 Otherwise
Let us assume to real successive number W1 and N2 mantissa (m − 1) and (m) respectively
So, N1 can be represented in given floating point representation as,
N1 = (−1)s [1 + (m − 1) × 2−g) × 2+ 31
and N2 can be represented in given floating point representation as
N2 = (−1)s [1 + m × 2−g) × 2+ 31
Now taking difference between N2 and N1 as
N2 − N1 = (−1)s × 2−g × 2+ 31
N2 − N1 = (−1)s × 2+ 31
Omitted sign bit [i.e., (−1)s]
So, N2 − N1 = 222
Thus maximum difference between two successive real number represented under given
system is 222.
Second Method
Maximum value of exponent (e) can be 111110 = 62
i.e., e = 62
So floating point representation is
(−1)s (1 + m × 2−g) 2+ 31, if e ≠ 63

0 Otherwise
Now we can chessing two successive real number N1 having decimal value of mantissa is
zero and N2 having decimal value of mantissa is 1, then,
N1 = (−1)s (1 + 0 × 2−g) × 2+31
N2 = (−1)s (1 + 1 × 2−g) × 2+31
So, N2 − N1 = 222 [((−1)s → Omitted]
26
Boolean Algebra and Logic Gates
Chapter 2
Objectives
• Simplify logic expressions using Boolean theorems
• Represent logic expressions in SOP and POS forms
• Implement logic expressions using basic logic gates
• Implementing dual and complement of logic expressions
• Form the logic expressions from switching circuits and venn diagrams
Introduction
In the digital age, the cost of digital circuits used to implement the logic becomes a
crucial factor. Hence finding simpler, cheaper but equivalent realization of logic can
result in huge benefits in reducing overall cost of the design.
Advantages of Minimization
• Number of logic gates required to implement the logic is reduced so it leads to a
simpler and cheaper logic
• Speed of circuit increases due to the fact that signal now traverses through a lot
less logic gates so the propagation delay encountered is less
• Power dissipation is also reduced due to a lesser number of logic gates
• Fan in (no. of input) is reduced due to simpler logic
Logic Reduction Techniques

There are some standard logic reduction techniques and each one is used under
different circumstances which are mentioned below:
Boolean Algebra
• When no. of variable are less (1, 2, 3)
• It is preferred when output is 0 or 1
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Boolean Laws
In this section we will discuss the following Boolean laws:
• Commutative law
• Associative law
• Distributive law
• AND law
• OR law
• INVERSION law
K–Map
• When no. of variables are 2, 3, 4, 5 (up-to 5 variable)
• Output is 0, 1 or x (don’t care)
Tabulation Method
• It is used when numbers of variables are more
Boolean Algebra
Boolean constants and variables are allowed to have only two possible values 0 and 1.
The Boolean 0 and 1 do not represent actual numbers but rather the state of a voltage
variable or what is called as its Logic Level. Boolean algebra is a means of expressing a
relationship between inputs and output of a logic circuit.
Logic 0 Logic 1
False True
Off On
Low High
No Yes
Open Switch Closed Switch
Various significance of logic 0 and 1
Truth Table
A Truth Table is a means to show how the output logic of the circuit depends on the
input logic level for various combinations of the inputs.
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INPUTS OUTPUT
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
A
? Y
B
The figure above shows a logic circuit with two inputs A and B and one output Y. The
truth table shown on the right depicts the logic level of the output for each possible
combination of the input. This is the most basic way of representing the functionality of
a logic circuit.
Boolean Algebra Operations
• NOT (A or A')
0 = 1 A=A
1=0
• AND (.)
0.0 = 0 A.A = A
0.1 = 0 A.1 = A
1.0 = 0 A.0 = 0
1.1 = 1 A.A = 0
• OR (+)
0 + 0 = 0 A+A=A
0 + 1 = 1 A+1=1
1 + 0 = 1 A+0=A
1 + 1 = 1 A+A=1
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Solved Examples
Problem:
Simplify AB + AB
Solution: A(B + B) = A ( B + B = 1)
Problem:
Find the min. no. of NAND gate required to implement this function: AB + ABC + AB C
(a) 0 (b) 1 (c) 2 (d) 3
Solution:
AB + ABC + AB C = AB + AB(C + C)( C + C = 1)
AB + ABC + AB C = AB + AB = A(B + B) = A
No NAND gate required
A A
i/p o/p
Boolean Algebra Theorems
(1) Transposition Theorem

(A + B)(A + C) = A + BC
Similarly: (x + y) (x + z) = x + yz
(2) Distribution Theorem

A + BC = (A + B)(A + C)
A + AB = A + B
(3) Demorgan’s Theorem
ABC = A + B + C
A+B+C=A.B.C
(4) Consensus Theorem

AB + AC + BC = AB + AC
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Shortcut Method
(a) Three variable
(b) Each variable comes twice
(c) One variable is complemented
Solved Examples
Simplify the following logic expressions:
(a) AB + AB C + AB CD
Solution:
AB C + AB(1 + CD )(1 + λ = 1)
= AB C + AB = A(B + BC) ( B + BB = B + C)
= A(B + C) = AB + AC
(b) (A + B) (A + C)
Solution:
A.A + A.C + AB + BC = A + A(C + B) + BC = A(1 + B + C) + BC = A + BC
(c) (A + B + C)(A + B + C)(A + B + C)
Solution:
take A + B = X
= (X + C)(A + B + C)(X + C) = (X + CC)(A + B + C) (By Distribution Theorem)
= X(A + B + C) = (A + B)(A + B +C) = A + B(B + C) = A + BB + BC = A + BC
(d) (A + B)(A + B) (A + B) (A + B)
Solution:
(A + B)(A + B) (A + B) (A + B) = (A + BB)(A + BB) = (A)(A) = 0 (Distribution Theorem)
(e) A + AB
Solution:
(A + A)(A + B) = 1(A + B) = A + B (Distribution Theorem)
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(f) A + AB
Solution:
(A + A)(A + B) = 1(A + B) = A + B (Distribution Theorem)
(g) AB + A B + AB
Solution:
A(B + B) + A B = A + A B = (A + A)(A + B) = A + B(Distribution Theorem)
(h) AB + AB + AB
Solution:
B(A + A) + AB = B + AB = (B + A)(B + B) = A + B (Distribution Theorem)
(i) ABC + ABC + ABC
Solution:
ABC + ABC + ABC + ABC ( A + A = A)
= AB(C + C) + (C + A)BC = AB + BC = B(A + C)
(j) AB + AC + (BC) → Redundant Term
Solution:
AB + AC + BC(A + A) = AB + AC + BCA + ABC = AB(1 + C) + AC(1 + B) = AB + AC
(k) AB + BC + AC
Solution:
BC + AC(The term which is complemented is taken)
(l) AB + BC + AC
Solution:
AB + BC
(m) (A + B)(A + C)(B + C)
Solution:
(A + B)(A + C) ( (B + C) is redundant term)
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(n) (A + B)(B + C)(A + C)
Solution: (A + B)(B + C) (Consensus Theorem)
(o) A B + AC + B C
Solution:
In this case all the variables are complemented only one is un-complemented then.
= A B + AC(∴ The term which is un-complemented is taken)
(p) A B + BC + A C
Solution: BC + A C (Consensus Theorem)
(q) (A + B)(B + C)(A + C)
Solution: (B + C)(A + C) (Consensus Theorem)
(r) Let f(A,B) = A + B then the value of f[f(x + y, y), z] is
Solution:

f[f(x + y, y), z] = f[x + y + y, z] = f[x. y + y, z] = x. y + y + z = x y. y + Z
Minterms, Maxterms & Properties
Minterm
It is a standard product term i.e., a product term which contains all variables of a given
function either in normal form or compliment form. The variables are so arranged that
the product should be 1.
Maxterm
It is a standard sum term i.e., a sum term which contains all the variables of the function
either in normal or compliment form. The variables are so arranged that the sum should
be 0.
F(A, B, C) = min terms F(A, B, C) = max terms
A B C = m0 (0, 0, 0) A + B + C = M7(1, 1, 1)
A B C = m1 (0, 0, 1) A + B + C = M6(1, 1, 0)
A B C = m7 (1, 1, 1) A + B + C = M0(0, 0, 0)
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Properties
(1) n – variable function → {2n min terms & 2n max terms}
(2) Mj = mj & mj = Mj
= m =
M ; M m
(3) iD
2n − 1 − i (
iD
) ( )
2n − 1 − i ; D = indicates dual
2n − 1 2n − 1
(4) ∑ mi = 1 ; ∏ Mj = 0
i=0 j=0
Forms of Boolean Function

(1) Sum of product (SOP) form = DNF (Disjunctive Normal Form)
(2) Canonical SOP form = DCF (Disjunctive Canonical Form)
(3) Product of sum (POS) form = CNF (Conjunctive Normal Form)
(4) Canonical POS form = CCF (Conjunctive Canonical Form)
SOP (Sum of Product Form)

It consists of two or more AND terms ORed together. The AND terms contain Boolean
variables in normal or complemented form.
Solved Examples
Problem:
For the given truth table, minimum SOP expression.
A B Y
0 0 1
0 1 0
1 0 1
1 1 0
Solution:
In SOP form only 1 taken.
= A B + AB = B(A + A) = B
Y can written as: Y (A, B) = Σ m(0, 2)
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Problem:
Simplified the expression for Y (A, B) = Σ m(0, 2, 3)
Solution: logical expression in SOP form:

Y = A B + A B + AB = B(A + A) + AB = B + AB = (B + A) (B + B) = A + B = A + B
In canonical form, each term must have all variables.
Y = A B + A B + AB Is canonical form whereas Y = A + B is minimal form
Problem:
In canonical SOP form, no. of minterm presenting the logical expression: A + AC is___.
Solution:
A + BC = A(B + B)(C + C) + BC(A + A) = (AB +AB)(C + C) + ABC + ABC
: A + BC = ABC + ABC + ABC + ABC + ABC + A BC = ABC + ABC + ABC + ABC + A BC
i.e., 5 terms.
POS Form (Product of Sum)

It consists of two or more OR terms ANDed together. The OR terms contain Boolean
variables in normal or complemented form.
Summary of Boolean Algebra Laws
(1) A⋅0 = 0
(2) A⋅1 = A
(3) A⋅A = 0
(4) A + A = 1
(5) A + A = A
(6) A⋅A = A
(7) A + 0 = A
(8) A + 1 = 1
(9) A + BC = (A + B) (A + C)
(10) A + AB = (A + A) (A + B) = A + B
(11) A + AB = A + B
(12) A + A B = A + B
(13) A + A B = A + B
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Solved Examples
Problem:
For a given truth table minimize POS expression.
A B Y
0 0 1
0 1 0
1 0 1
1 1 0
Solution: We take only that value at which o/p is ‘0’

Y = (A + B) (A + B) = B + A A = B
• Y can be written in POS form as: Y(A,B) = ΠM(1, 3) = B
Y ( A,B )
And for SOP:= ∑
= m ( 0,2 ) B Y(A,B) = ∑m(0, 2) = B
i.e., ∑m(0, 2) = ΠM(1, 3)

if F(A, B, C) = ∑m(0, 1, 4, 7)
There are 3 variable then 8 combination then max term are 2, 3, 5, 6
F(A, B, C) = ∑m(0, 1, 4, 7) = ΠM(2, 3, 5, 6)
n
Notes: With n variable maximum possible logical expression are 22
2
Example: for n = 2, logical expression = 22 = 16
Logic Gates
Logic Gates are the most fundamental digital circuits that can be constructed from
diodes, transistors and resistors connected in such a way that the circuit output is the
result of a basic logic operation performed on the inputs. It is a device which accepts
two or more inputs and produces a single output. The function of each logic gate can be
represented by a Boolean expression.
Logic Gates can be Broadly Classified as Shown Below
Logic Gates
Basic Gates Universal Gates Others

(NOT, AND, OP) (NAND, NOR) (EXOR, EXNOR)
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NOT Gate
Figure shown below shows the symbol for a NOT gate which is more commonly referred
to as inverter. This circuit always has a single input and the output logic level is opposite
to the input.
Truth Table
Input A Output Y
0 1
1 0
A A=Y
A A=Y
Equivalent Circuit
A Y
0 1
1 0
Important Point about the NOT Gate

• The NOT gate is also known as an “inverter” because its output is the inverted
version or “complement” of its input. This is shown in the truth table of NOT gate.
• The bubble (o) in the symbol of NOT gate indicates the inversion operation.
Solved Examples
Problem: Circuit shown in the figure represents:
(a) Buffer
(b) Astable MV
(c) Bi-stable MV
(d) Square wave generator
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Solution: If there is no feedback then it is buffer, in buffer if we apply 0 then get 0.

Input =“1” then output= “1”.
Buffer means whatever the input i.e. the output
• But there is feedback and the output is stable. If we give 1 as input, output is also 1
and if it gives 0 then output is 0 then two stable states. Hence it is bi-stable multi-
vibrator.
Problem:
Circuit shown is
tpd tpd tpd
Solution: tpd = propagation delay.
3tpd
3tpd
This waveform has:

‘0’ for = 3tpd
1 for = 3tpd
It is called
(1) Square wave generator
(2) As o/p is not stable sometime 1 and sometime 0 Hence it is also called astable
multivibrator
(3) Clock generator
(4) Ring oscillator
Total time period (T) = 6Tpd
Then, T = 2Ntpd, where N = no. of inverters in feedback.
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Problem:
In a circuit shown in figure the proportion delay of each not gate is 100p sec. then
frequency of generator square wave.
(a) 10 GHz
(b) 1 GHz
(c) 100 MHz
(d) 10 MHz
Solution:
T = 2Ntpd = 2 × 5 × 100p sec = 1000p sec
1 1
f= = = 109 Hz = 1GHz
T 1000 × 10-12 sec
Problem:
The circuit shown in the fig. the proportion delay of each NOT gate is 2nsec. Then the
time period of the generated square wave is.
(a) 6 ns
(b) 14 ns
(c) 12 ns
(d) 18 ns
X
Y
Solution:
Astable multivibrator, square wave generator.
T = 2Ntpd = 2 × 3 × 2nsec = 12nsec
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6nSec
X 6nSec
6nSec
Y
6nSec
tpd for NOT gata
Thus the time period at x and y is the same.
Notes:
(1) When even number of inverters (NOT gates) are connected in feedback, then it acts
as bistable multivibrator
(2) When odd number of inverters (NOT gates) are connected in feedback, then it
acts as astable multivibrator or square wave generator or ring oscillator or clock
generator
1
• Output frequency of ring oscillator f0 = = fclock
2nt pd
Where, n = Number of inverter used in feedback loop and it must be odd in

number
tpd = Propagation delay of each flip-flop
AND Gate
The output of AND gate is AND product of the inputs. In other words, the output of an
AND gate is high only if all the logic inputs are high and otherwise the output is low.
The output is high(Y = 1) if and only if all the inputs to the AND gate are high (1). The
output is low (0), if any one or more inputs are low (0). AND gate can have two or more
inputs and only one output.
Y = AB
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Truth Table
Inputs Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
• AND gate follows both commutative law and associative law.

• Commutative Law: AB = BA
A B
AB =
B A
• Associative Law: ABC = (AB)C = A(BC)
A A AB
B ABC = B
C ABC
C C
Disable & Enable

• Thus o/p remains in ‘0’ due to control input disable. The AND gate is not in a
working condition.
A
0
0
Control(Disable)
• AND gate is in working state output is changing in enabled state.
A
A
1
Control(Enable)
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• In the TTL logic family, if any input is open, and floats then it will act as ‘1’.
• In the ECL logic family, floating input will act as logic ‘0’.
B Y
(open floating input)
Unused Inputs
(1) A Vcc
A
B
B
B
1
• In multi pin (input) AND gate unused input can be connected to logic 1 or “pull up”.
• Unused input can be connected to logic ‘0’ or “pull down”.
(2) A A.B.B = AB A
A.A.B = AB
B B
• Unused input can be connected to one of the used I/P.
(3) A
B Y=AB (only for TTL)
• If it is TTL logic family, then unused input can be open or floated. (unconnected)
Note:
• Because of unnecessary input attached to B, fan in will be down. (Fan-in is the
maximum number of inputs that a digital logic gate can accept).
B Y=AB
• Best way to connect unused pins (I/P) in AND gate is connecting to logic ‘1’.
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B Y=AB
OR Gate (Inclusive OR)

OR gate has two or more inputs and the output is equal to OR combination of the inputs.
It operates in such a way that output is high when either or both inputs are high and else
output is low.
A+B
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
So that Truth Table is,
Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
• OR gate follows both commutative and associative law.

(i) Commutative law: A + B = B + A
A B
A+B A+B
B A
(ii) Associative law: A + B + C = (A + B) + C = A + (B + C)
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A A A+B
B B A+B+C
C A+B+C
C
Enable and Disable

• Output is changing as input is changing or we say the gate is enabled.
A
Y=A
Control
0
• Output is fixed or not changing, the gate is said to be disabled.
A
Y=1
Control
Unused I/P’s
(1) In OR gate, unused I/P is connected to logic. ‘0’ “pull down”.
(2) Connect to be one of the used I/P.
(3) If it is ECI then unused I/P can be open or floated.
• In OR gate, Best way of connecting the unused I/P is to connect to logic ‘0’.
A Y=A+B
44
Solved Examples
Problem:
In the circuit shown in fig. in TTL, AND, OR, INVERTER circuit for the given input, output
is:
(1) 0
(2) 1
(3) AB
(4) AB
A AB
Y
floated 1 + AB = 1 0
1
1
I/P
1
Solution: In TTL, all inputs are float then it is logic ‘1’. Hence option (a) is correct.
Problem:
For ECL AND, OR, INVERTER circuit for the given input, output is :
(1) 0
(2) 1
(3) AB
(4) AB
A AB
Y
float AB AB
0
0 0
Solution: If all inputs are floating in ECL then it is ‘0’ and output Y = AB
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NAND Gate
It behaves like an AND gate followed by an inverter. The output of this gate is low if both
inputs are high and otherwise high.
A AB = A + B
A
A+B
B
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
So that Truth Table
Inputs Output
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
Enable and Disable
A A
1 A
0 1
46
• NAND gate follows commutative law but does not follow associative law.
A A AB
B ABC = B
C (AB)C = AB + C
C
• There are only two gates that do not follow associative law i.e. universal gate NAND
or NOR gate.
• Unused input in NAND gate can be connected similar to unused input in AND gate.
B Y
NOR Gate (Bubbled AND)

This is another universal gate. It behaves like an OR gate followed by an inverter. The
output of this logic gate is high when both the inputs are low and otherwise low.
The word NOR can be split as NOT- OR which means that a NOR operation can be
implemented with the combination of an OR gate and a NOT gate, i.e. inverter. Thus a
NOR gate is equivalent to an OR gate.
A A
A+B=A.B
Y = A.B
B B
So that, Truth Table is,
Inputs Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
47
Enable and Disable
A A
A 0
0 enable 1 disable
• NOR gate follows commutative law but not follows associative law.

i.e. A + B = B + A and A + B + C = A + BC
• Unused I/P in NOR gate can be connected similar to OR gate (i.e. connected to logic
low)
EX-OR or XOR
• Exclusive OR gate. The output of this logic gate is high when the number of 1’s at the
input is odd and low when the number of 1’s at the input is even.
• For two inputs of XOR gate, this condition translates to output being low when both
inputs are equal and high when both inputs are different.
Y=A⊕B
B
So the Truth Table is
Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
• SOP expression = AB + AB
• POS expression = (A + B) (A + B)
A A
A A
0 Buffer 1 inverter
48
• It is also called a controlled inverter.
Note:
A⊕A= 0
A⊕A=1
A⊕0 =A
A⊕1 =A
If A ⊕ B = C then
A⊕C = B
B ⊕C =A
A⊕B ⊕C = 0
B, if n is add
B ⊕ B ⊕ B ⊕ ...........n
0, if n is even
Solved Examples
Problem:
The circuit shown in fig. contains cascading of 20 EXOR gate. If x is the Input then output
is
(a) 0
(b) 1
(c) x
(d) x
x
Y
Solution: Output of even EXOR gate is same as input, So Y = X

• Internal diagram of EXOR gate
AB + BA
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• EXOR gate follow both commutative and associative law

• EXOR gate is available with two inputs only
Truth Table of 3 Input XOR Gate
A B B Y = (A ⊕ B ⊕ C)
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
A
A
B
B Y =
Y
C
C
• The o/p of EXOR gate is 1. When no. of 1’s at the input is odd.
EX-NOR or XNOR
• Exclusive NOR gate. The output of this logic gate is high when the number of 1’s at
the input is even and low when number of 1’s at the input is odd.
• For two input XNOR gates, this condition translates to output being high when both
inputs are equal and low when both inputs are different.
• The word EX-NOR is a short form of exclusive-NOR. Exclusive-NOR means. NOT-
exclusive OR, so EX-NOR gate is equivalent to an EX-OR gate followed by a NOT gate.
AʘB
50
So that Truth Table as,
Inputs Output
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
• SOP expression = A B + AB
• POS expression = (A + B)(A + B)
• Therefore it is called a coincidence logic circuit and also called an equivalent
detector.
Enable and Disable
A
A A
A
0 Control (inverter) 1 Control (Buffer)
Note:
AΘA=1
AΘA=0
AΘ0=A
AΘ1=A
= 1, if n is add
• B Θ B Θ B Θ ...........n
= 0, if n is even
• EXOR and EXNOR is not always complement, it is complement only when the
number of inputs is even and if the number of inputs is odd then EXOR and EXNOR
are the same.
i.e., A ⊕ B ⊕ C = A ⊕ B ⊕ C ⇒ same
and A ⊕ B ⊕ C ⊕ D = A ⊕ B ⊕ C ⊕ D ⇒ complement
Note: Ex-OR & Ex-NOR Logic gates are also called as special purpose gates.
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Question:
Why are NAND & NOR referred to as universal gates?
Solution:
All Boolean functions can be easily realized using the NAND & NOR gate itself hence they
are called as universal gates.
Solved Examples
Problem:
Find expression of A Θ B Θ C
Solution:

A Θ B Θ C = (A B + AB) Θ C = (A B + AB)C + (A B + AB)C
Since,
(A B + AB) = (A Θ B ) = A Θ B = AB + AB = (AB + AB) C + (A B + AB)C
Problem:
Minimize
A B B Y
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
Solution: For EXOR = o/p is 1 when odd number of 1’s at input

In this case, y = A ⊕ B ⊕ C = A Θ B Θ C
• EXOR and EXNOR are never always complemented; it is complemented only when
even variables occur.
• EXNOR gate is an even number of 1’s detector when the number of inputs are even.
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• EXNOR gate is an odd number of 1’s detector when the number of inputs are odd.
• Under 3-input only the expression of Ex-OR and Ex-NOR are equal.
Solved Examples
Problem:
Prove A ⊕ A = A Θ B
Solution: Put x = A, y = B
x ⊕ y = XY + XY = AB = A Θ B
Problem:
Simplify A ⊕ B ⊕ AB
Solution:

(AB + AB) ⊕ AB = (AB + AB)AB + (AB + AB)AB = AB(A + B) + AB(A + B) + (AB. AB)AB
(AB + AB) ⊕ AB = AB + AB + [(A + B) (A + B)]AB = AB + AB + AB = A (B + B) + AB = A + AB
(AB + AB) ⊕ AB = (A + A)(A + B) = A + B
Problem:
Find Y
A
B
Solution:
A A⊕B
B =A⊕B
Y= 1
A
=A⊕B
B A⊕B
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Symbols
NAND Bubbled or
NOR Bubbled AND
AND
OR
Note: Always keep in mind that,

(1) Bubbled OR works as NAND
(2) Bubbled AND works as NOR
(3) Bubbled NAND works as OR
(4) Bubbled NOR works as AND
NAND as Universal Gate

(i) NOT
A
1
A
gate required
(ii) AND
A AB
2
B AB gates required
(iii) OR
A A
3
AB=A+B=A+B gates required
54
(iv) EXOR
A A.AB
4
Y = A ⊕ B = AB + AB gates required
A AB
B
B B.AB
(v) EXNOR
A
5
EXOR gates required
B 1 Gate
4 Gate
(vi) NOR
A
4
OR gates required
B 1 Gate
3 Gate
NOR as Universal Gate
(i) NOT
A
1 gate required
A
(ii) AND
A A

3
AB gates required
A B
55
(iii) OR
A A+B
2
A+B gates required
B
(iv) EXNOR
A
A+A+B=AB

A 4 gates required
A⊕B
B
A+B
B B+A+B=BA
(v) EXOR
A
EXOR 5 gates required
B 1 Gate
4 Gate
(vi) NAND
A
4 gates required
AND
B 1 Gate
3 Gate
Summary of Universal Gates
Number of NAND gates Number of NOR gate

Logic
required required
NOT 1 1
AND 2 3
OR 3 2
XOR 4 5
XNOR 5 4
56
Solved Examples
Problem:
To implement xyz the minimum number of two input NAND gate required are?
Solution:
➀
X
Y XYZ
Z ➁
➁
Total no. of NAND gate = 2 + 2 + 1 = 5
Problem:
To implement XY + WZ, the minimum number of 2 input NAND gates required.
Solution:
X 1
2
Y
XY+WZ
W
4
Z 3
1st inverter cancelled 2nd and 3rd cancelled 4th

Now the total no. of NAND gate is = 2 + Bubbled OR (= NAND) = 2 + 1 = 3
3 NAND gate required.
Note:
Two level AND - OR = Two level NAND-NAND
57
• AND − OR = NAND − NAND

• To implement SOP form, only NAND gates are required.
• To implement POS form, only NOR gates are required.
Solved Examples
Problem:
If (A + B)(C + D) then the minimum number of NOR gates required are?
Solution:
A A
B B
=
C C
(A+)(C+D)
D D
Twolevel OR - AND Twolevel NOR - NOR
Three NOR gates are required.

• OR − AND = NOR − NOR
Problem:
The given logic gate circuit is shown below, what is the logical expression of Z?
Solution: The given logic gate circuit is shown below,
58
Shifting bubbles towards last NAND gate and rearrange the circuit,
X
X
Y
Z
X
Y
Y
Now, above circuit becomes
X
X
XY
Y
Y
Z
X
X
XY
Y Bubbled NAND
replace by OR gate
So, above circuit becomes,
X
X
XY
Y
Z = XY + XY
X
X
XY
Y
Y
So that, Z = XY + XY
Z=X⊕Y
Hence, the output of circuit Z shows EX-OR Logic gate.
Dual Form
+ve logic −ve logic
+ve logic means higher voltage −ve logic means higher voltage
corresponds to logic '1'. corresponds to logic '0'.
logic '0' → 0v logic '0' = +5v
logic '1' → +5v logic '1' = 0v
59
Solved Examples
Problem:
logic 0 → −5v and logic 1 → 0v. Find the logic sign?
Solution:
Higher value of voltage (0v) is for logic 1. Then +ve logic.
Problem:
ECL; logic 0 → −1.7v and Logic 1 → −0.8v
Solution:
−0.8v is larger value than −1.7v then it is +ve logic.
Positive and Negative Logic Gates

−ve logic AND
+ve logic AND −
A B Y A B Y

0 0 0 1 1 1
0 1 0 1 0 1
1 0 0 0 1 1
1 1 1 0 0 0
+ve logic OR –ve logic OR
A B Y A B Y

0 0 0 1 1 1
0 1 1 1 0 0
1 0 1 0 1 0
1 1 1 0 0 0
• For −ve logic OR gate, convert 1 to 0 and 0 to 1.

• We can say that +ve logic AND gate is equal to −ve logic OR gate and −ve logic AND
gate is equal to +ve logic OR gate.
• Dual expression is used to convert +ve logic into −ve logic or −ve logic to +ve logic.
• Dual is nothing but −ve logic
AB Dual A + B
60
-ve logic
• AND  → OR
Dual
-ve logic
• OR  → AND
Dual
ANd ↔ OR
. ↔+
Dual
1 ↔ +
Keep variable assist
Solved Examples
Problem:
Find Dual ABC + ABC + ABC
Solution: Dual: (A + B + C) (A + B + C) (A + B + C)
If we find again dual then, ABC + ABC + ABC
Important Points
• For any logical expression, if two times dual is used it results in the same
expression.
• Self Dual:
AB + BC + AC
Dual: = (A + B)(B + C)(A + C) = (B + AC)(A + C) = BA + BC + AC + AC
= AB + BC + AC (Again same expression)
• In some of the logical expressions, not all its dual gives the same expression.
• In self Dual expression, if one time dual is used it results in the same expression.
2 n−1
• If there are n variables then total no. of self dual expression is 2
2 n−1
(i) For n = 1--> 2 = 21 => Then 2 Self dual expressions
A → self dual → A
Total self dual expressions are 2
A → self dual → A
1
(ii) For n = 2, = 22 = 4 Then 4 Self dual expressions.
A → A, B → B and A → A, B → B
61
Complement
If Y = ABC + ABC + ABC
Complement is Y = (A + B + C) (A + B + C) (A + B + C)
AND ↔ OR
. ↔+
Complement
1 ↔ 0
Complement of each variable.
Venn Diagram
For two variable (A, B)
A B
10 01
AB AB
AB
00
AB
11
Solved Examples
Problem:
For a given Venn diagram, minimize the SOP expression for shaded region.
A B
Solution:
Y = A B + AB + AB = B(A + A) + AB = B + AB = (B + A)(B + B) = A + B
62
Problem:
SOP expression for shaded region.
A B
Solution:
Y = AB + AB + AB = A(B + B) + AB = (A + A)(A + B) = A + B
Problem:
SOP expression
A B
Solution:
AB + AB + AB + A B = B(A + A) + B(A + A) = B + B = 1
For 3 variables:
ABC
A
B
ABC
ABC
ABC C
63
Current Energy Scenario in India
SOP form for shaded portion.

= ABC + ABC + ABC + ABC + ABC + ABC → extra added
= BC(A + A) + AB (C + C) + AC(B + B) = AB + BC + CA
Problem:
The Boolean Expression for the shaded region in given Venn diagram is shown below,
Solution:
Given Venn diagram is shown below,
A B
Thus, the expression only for shaded region,

Y = AB + AB → EX-OR in SOP form
Y = (A + B) (A + B) → EX-OR in POS form
Switching Circuit
For Series
Truth Table Y
+
A Y A
0 0 Bulb.
V
1 1
-
For Parallel:
Truth Table
A Y Y
0 1
Bulb.
1 0 V A
64
• In place of the bulb there is a resistor then the answer remains the same but some
drop.
Truth Table
VCC
A Y

0 1
1 0
Y
• In place of switch if there is a transistor
Truth Table
A Y VCC

0 1
1 0
Y
• For A = 1 transistor to become a short circuit.
For Two Switches A and B
AND
A B Y
0 0 0 Y = AB
A B
0 1 0
1 0 0 V
1 1 1

65
NAND
Y = AB
A B Y
0 0 1
A
0 1 1 V
1 0 1
B
1 1 0
OR
A B Y
A
0 0 0 Y=A+B

0 1 1
V B
1 0 1
1 1 1
NOR
Y=A+B
A B Y
0 0 1

0 1 0 V A B
1 0 0
1 1 0
Solved examples
Problem:
Find the expression of y.
Y
A
C
V
D
Solution: Y = A.(B + C).D = (AB + AC)D = ABD + ACD
66
Problem:
A logic circuit has 3 input A, B, C and o/p is Y. o/p Y is -1. For the following combination.
(i) B and C are true = BC
(ii) A and C are false = A.B
(iii) A, B and C are true = ABC
(iv) A, B and C are false = A B C
Then minimize the o/p for Y.
Solution:
Output:
Y = 1. (Take minterm = SOP form)
Y = BC + AC + ABC + ABC = BC(1 + A) + A B(1 +B) = BC + A C
If o/p Y = 0, then take max term (POS form)
Problem:
A logic circuit have 3 input A, B, C and output is F = 1. When majority no. of I/p’s are logic 1.
Minimize expression F.
Solution:
A B B Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
F = ABC + ABC + ABC + ABC = ABC + ABC + ABC + ABC + ABC + ABC
= BC(A + A) + AC (B + B) + AB (C + C) = AB + BC + CA
67
68
Combinational Logic Circuits
Chapter 3
Objective
• Simplify Boolean expressions using K-map
• Design basic combinational logic circuits
• Implement Boolean expressions using basic combinational circuits as building
blocks
• Analyze combinational circuits for any timing hazards
Introduction
In the last chapter we simplified Boolean expressions and designed logic circuits as a
combination of logic gates. Those circuits are called combinational logic circuits as the
output of those circuits depends on the combination of logic levels of inputs. These
circuits do not have any memory characteristic. In this chapter we will discuss more
about such circuits and present a simple method for logic simplification which is K-map
(Karnaugh Map).
B
A
0 1
0 1 X
1 X 1
K-Map
• It is used when output can be 0, 1 and x (don’t care).
• K – map is graphical representation.
• Each square in a K-map represents one minterm or maxterm.
• In K – map gray code representation is used
• Gray code representation
• K-map is ideally is suitable for designing the combinational logic circuits using either
a SOP method or a POS method.
69
00
10 01
11
Each successive term is changed by only one bit.
For Two Variables

• A and B are the inputs or variables
• 0 and 1 are the value of A or B
• Inside the 4 boxes we have to enter the value of Y i.e., output
LSB
MSB B
A
00 0 01 1
0
10 2 11 3
1
For Three Variables

• A three variable K-map consists of 8 boxes
• The position of variables A,B.C are interchangeable
LSB
MSB BC
A
0 00 0 01 1 11 3 10 2
00 4 01 5 11 7 10 6
1
70
For Four Variables

• A 4 variable K-map consists of 16 boxes
LSB
MSB CD 00 01 11 10
AB
00 0 1 3 2
01 4 5 7 6
11 12 13 15 14
10 8 9 11 10
Procedure to Simplify Boolean Expression using K-Map

(i) Octets (group of 8 adjacent squares)
(ii) Quads (group of 4 adjacent squares)
(iii) Pairs (group of 2 adjacent squares)Priority decreases
(iv) Single term
(v) Remove redundant (a term whose all minterms are part of other groups)
Solved Examples
Minimize:
Problem: f(A, B) = ∑m(0, 2, 3) B

A 0 1
Solution: 0 1
f(A, B) = A + B (+ is put due to SOP form)
1 X 1
Problem: f(A, B) = ∑m(0, 1, 2, 3)

B
A 1
0
Solution: f (A, B) =1
0 1 1
In K – map if all are one means the function is 1.
1 1 1
71
Problem: f(A, B) = ∑m(1, 3) + ∑d(2) B

A 1
0
Solution: f (A, B) = B (No need of any gate)
0 1 1
X 1
1
Problem: f(A, B) = ∑m(0, 3) + ∑d(2, 1)

B
A 1
0
Solution: f (A, B) = 1
In SOP form if all are 1’s means o/p is 1. 0 1 X
1 X 1
Problem: f(A, B, C) = ∑m(1, 3, 5, 7) BC

00 01 11 10
A
Solution: f(A, B, C) = C 0 1 1
1 1 1
Problem: f(A, B, C) = ∑m(0, 1, 3, 6)

BC
00 01 11 10
Solution: f(A, B, C) = A B + AC + ABC A
0 1 1 1
1 1
Problem: f(A, B, C) = ∑m(1, 3, 6, 7) BC

00 01 11 10
A
0 1 1
Solution: If we take BC then it is redundant
term and it must be removed. 1 1 1
f(A, B, C) = AC + AB
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Problem: f(A, B, C) = ∑m(0, 1, 5, 6, 7) BC

00 01 11 10
A
Solution:
0 1 1
f(A, B, C) = A B + BC + AB
two solution 1 1 1 1
= A B + AB + AC
K–map provides minimal expression but not necessarily unique i.e., two solutions also
possible.
Problem: BC
00 01 11 10
f(A, B, C) = ∑m(0, 1, 2, 5, 7) + ∑d(3, 6) A
0 1 1 X 1
Solution: f(A, B, C) = A + C 1 1 1 1
Problem:
BC
00 01 11 10
f(A, B, C) = ∑m(0, 1, 2, 6, 7) + ∑d(3, 6, 5) A
0 1 1 X
Solution: f(A, B, C) = B + A X
1 X 1 1
Problem:
CD
00 01 11 10
f(A, B, C, D) = ∑m(0, 1, 3, 5, 7, 8, 9, 11, 13, 15) AB
00 1 1 1
Solution: 01 1 1
f(A, B, C) = D + BC
11 1 1
10 1 1 1
Problem: CD
AB 00 01 11 10
f(A, B, C, D) = ∑m(0, 2, 8, 10, 14) + ∑d(5, 15)
00 1 1
Solution: f(A, B, C, D) = B D + ACD 01 X
11 X 1
10 1 1
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Problem: f(A, B) = ΠM(0, 2, 3) B

A 0B 1B
Solution: f(A, B) = BA 0
0 A
1 A 0 0
Problem: f(A, B) = ΠM(0, 2, 3) + Πd(1) B

A 0B 1B
Solution: f(A, B) = A
0 A X
1 A 0 0
Problem: f(A, B, C) = ΠM(0, 1, 3, 5, 7) B+C

B+C B+C B+C B+C
A
Solution: f(A, B, C) = C (A + B) 0 0 0
0 A
1 A 0 0
Problem: f(A, B, C) = ΠM(0, 2, 4, 6)

B+C
A
Solution: f(A, B, C) = C 0 0 1 3 0 2
0
1 0 4 5 7 0 6
Problem: The minimized form of given expression using K-map,

Y = A + AB →
Solution: Y = A + AB → Two variables function

Now, above function can be converted in canonical form,
Y = A(B + B) + AB
Y = AB + AB + AB
(11) (10) (01)
Now, fill the K-map and simplified above function,
B
A B B B
A 1
A 1 1
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Minimized function from K-map,

Y=A+B
Problem: For the k – map minimize POS expression is

B+C
Solution:
A B+C B+C B+C B+C
f(A, B, C) = (B + C)(B + C)
0 A 0 X X 1
1 A 0 1 0 X
• The two functions are the same if the position of 1’s and 0’s are the same in k–map
and if the 1’s place 0 are placed and at 0’s place 1’s are placed then the function is
complement to each other.
Implicant, Prime Implicant and Essential Prime Implicant
Implicant
It is the set of all adjacent min terms
Example: Pair, quad, octants
Prime Implicant
It is an implicant which is not a subset of another implicant.
Essential PI (EPI)
It is a prime implicant which contains at least one min terms which is not covered by
other prime implicants.
In the figure shown below various implicants can be formed by grouping the minterms in
different order and their classification is as mentioned below:
(1) PI, Non EPI
2 1
(2) PI, EPI
(3) PI, EPI 1
3
(4) PI, EPI 1 1 1
(5) PI, EPI 1 1 1
1
5
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Classification of Digital Circuits
Digital Circuit
Combination Circuit Sequential Circuit
Preset output is only depend on present input

present input Present output depends on
previous output
No feedback
Feedback
No memory
Memory
Example: Half Adder, Full Adder, Example: Flip Flop, Register, Counter
Multiplexer, Decoder
Procedure to Design Combinational Circuits

• Identify input and output.
• Construct a truth table.
• Write logical expressions in SOP or POS form.
• Minimize logical expression, if possible.
• Implement logic circuits using Logic gates.
Half Adder (HA)

Half adder performs basic arithmetic operation of addition of two bits. Half adder is a
combinational logic circuit with two inputs and two outputs. It is the basic building block
for addition of two “single” bit members. This circuit has two outputs namely “carry” and
“sum”.
Input Outputs
A SUM
HA
B CARRY
Block diagram
76
Truth Table
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Logical Expression
SUM = AB + AB = A ⊕ B and CARRY = AB
Implementation
A
SUM
B
CARRY
Important Points
• Logical expression for SUM = A ⊕ B, CARRY = AB
• Min. no. of NAND Gate: 5
• Min no. of NOR Gate: 5
• No. of MUX: 3
• No. of DECODER: 1 2 × 4 Decoder and 1 OR Gate.
Half Adder Implementation using NAND Gate
AB
A A ⊕ B = SUM
B
AB = CARRY
=> Number of gates required = 5
77
Half Adder Implementation using NOR Gate
A A+B A B + A B = A ⊕ B = SUM
1
B
A.B
AB = CARRY
=> Number of gates required = 5
Half Subtractor
Half subtractor performs the basic arithmetic operation of subtraction of two bits.
Half subtractor is a combinational circuit with two inputs and two outputs (difference
and borrow).
It produces the difference between the two binary bits at the input and also produces an
output (borrow) to indicate if a1 has been borrowed.
In the subtraction (A-B), A is called a minuend bit and B is called a subtrahend bit.
A Difference
HA
B Borrow
Truth Table
A B Diff Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Logical Expression
Difference = AB + AB and Borrow B = AB
Implementation
A
Difference
B
Borrow
78
Half Adder and Half Subtractor
A
X=A⊕B
B
Control
Y = AB HA
= AB HS
• If control = 0, then A ⊕ 0 = A, Y = AB and circuit is HA.

• If control = 1, then A ⊕ 1 = A, Y = AB and the circuit is HS.
Important Points
• Number of NAND gate required = 5
• Number of NOR gate required = 5
• Number of MUX required = 3 (2 x 1 MUX)
• Number of Decoder required = 1 (2 × 4) Decoder and 1 OR gate.
Half Subtractor using NAND Gate
A
AB A ⊕ B Difference
B
B
AB Borrow
Number of NAND gate required = 5
Half Subtractor using NOR Gate
A
(A + A + B)
AB Borrow
A
A+B
B
A ⊕ B Difference
Number of NOR gate required = 5
79
Full Adder
A Full adder is a combinational circuit that forms the arithmetic sum of three bits.
It can add two one-bit numbers A and B, and carry Cin. The full adder is the three input
and two output combinational circuit.
A SUM
B FULL ADDER
C CARRY
Truth Table
A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Logical Expression
SUM = A BC + ABC +ABC + ABC = A ⊕ B ⊕ C = ∑m(1, 2, 4, 7)
CARRY = ABC + ABC + ABC + ABC = AB + BC + AC = ∑m(3, 5, 6, 7)
In full adder if each logic gate has a proportion delay of tpd, then to provide sum or carry
output, it requires to a 2tpd delay.
A B C
tpd
tpd
SUM = 2 tpd
tpd
tpd
tpd
CARRY = 2 tpd
tpd
Now, CARRY = ABC + ABC + ABC + ABC = AB(C + C) + C(AB + AB) = AB +C(A ⊕ B)
80
Implementation
A A⊕B
B AB
A ⊕ B ⊕ C = SUM
C
C
CARRY
= AB + C (A ⊕ B)
Using Half Adders
A
HA SUM
B
HA
C
CARRY
Important Points
• Logical expression for SUM = A ⊕ B ⊕ C, CARRY = AB + BC +AC
• Number of Half Adder and OR gate required = 2HA, 1 – OR
• Minimum number of NAND gate required = 9
• Minimum number of NOR gate required = 9
• Number of MUX required = 3 (4 × 1) MUX
• Number of DECODER required = (3 × 8) Decoder and 2 OR gate.
Implementation of Full Adder using NAND Gate
A AB A⊕B
B
(A ⊕ B)C
sum
C
carry
81
Implementation of Full Adder using NOR Gate

Since, A ⊕ B ⊕ C = A Θ B Θ C, the circuit is the same, only NAND is replaced by NOR.
A A+B
(A ⊕ B)
B
C + (A ⊕ B) SUM
C
C
CARRY
Types of Adders
• There are three types of adders
(1) Serial adder (We design as sequential circuit)
(2) Parallel adder
(3) Carry Look Ahead adder
• In serial adder only one full adder (FA) is used to add a group of bits.
• It is the slowest adder.
Parallel Adder
4 Bit Adder
• 3 full adders and 1 half adder required or 4 full adders are required.
• Parallel adder is used to add groups of bits.
• To add two N bit number it requires (N − 1) full adder and half adder or N full adder
or (2N − 1) half adder and (N − 1) OR gates required.
Implementation of Parallel Adder
A3 B3 A2 B2 A1 B1 A0 B0
C0
FA FA FA FA
C4 S3 C3 S2 C2 S1 C1 S0
82
A 3 A 2 A 1 A0 

1 1 0 1

1 0 1
1
S3S2S1S0 C4
B3 B2 B1 B0   
Sum Carry
• Parallel adder is also called ripple carry adder.

• There is propagation delay from input carry to output carry, hence it is also known
as ripple carry adder.
• In parallel adder each full adder will provide 2 logic gate delays. In n bit parallel
adder provide total delay of Tdelay = 2ntpd
Carry Look Ahead Adder

• Disadvantage of parallel adder is it has carry propagation delay.
• As the number of bits increases, speed of operation is reduced.
• To avoid this Carry Look Ahead Adder is used.
Ai
Pi
Bi
Gi Pi
Ci SUM (S)
Ci
CARRY (Cin)
Pi = Propagation, Gi = Generation term.
Pi = Ai ⊕ Bi, Gi = AiBi, Si = Pi ⊕ Ci, Ci+1 = PiCi + Gi
Four Bit Carry Look Ahead adder
Input A3A2A1A0, B3B2B1B0
Then P0 = A0 ⊕ B0, P1 = A1 ⊕ B1, P2 = A2 ⊕ B2, P3 = A3 ⊕ B3
G0 = A0B0 S0 = P0 ⊕ C0, G1 = A1B1 S1 = P1 ⊕ C1
G2 = A2B2 S2 = P2 ⊕ C2, G3 = A3B3 S3 = P3 ⊕ C3
Ci + 1 = PiCi + Gi Carry Look Ahead generator expression.
C1 = P0C0 + G0
C2 = P1C1 + G1 = P1(P0C0 + G0) = P1P0C0 + P1G0 + G1
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C3 = P2C2 + G2 = P2P1P0C0 + P2P1G0 + P2G1 + G2
C4 = P3C3 + G3 = P3P2P1P0C0 + P3P2P1G0 +P3P2G1 +P3G2 + G3
n ( n + 1) 4 × 5
Total number of AND gate inside = 1 + 2 + 3 + 4 = = = 10
2 2
Number of OR Gate = n
Total propagation delay = 2tpd
This is faster than parallel adder.
Full Subtractor
It performs the arithmetic subtraction of three bits.
The full subtractor is a combinational circuit with three inputs A, B and C and two
outputs D and Bo.
A is the minuend, B is the subtractor, C is the Borrow produced by the previous stage, D
is the difference output and Bo is the borrow output.
A Difference
B FS
C Borrow
Truth Table
A B C Diff(A − B − C) BORROW
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Logic Expression
Difference = A ⊕ B ⊕ C = ∑m(1, 2, 4, 7)
Borrow = AB + AC + BC = ∑m(1, 2, 4, 7)
84
Implementation
A B C
Difference
Borrow
Full subtractor can be implemented with 2 – half subtractor and 1 OR gate.
Important Points
• Number of NAND gate required = 9
• Number of NOR gate required = 9
• Logical expression for difference = A ⊕ B ⊕ C
• Logical expression for borrow = AB + AC + BC or AB + C(A  B)
• Number of MUX required = 3 (4 × 1) MUX
• Number of decoders required = 1 (3 × 8) decoder and 2 OR gate.
Comparator
A comparator is a combinational circuit which compares two bits and produces three
outputs based on the relative values of the bits.
A A>B=X
A=B=Y
COMPARATOR
B
A<B=Z
Truth Table
A B X Y Z
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
x y z
= AB = A Θ B = AB
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Logic Expression
X = AB, Y = A Θ B = AB + AB, Z = AB
Implementation
A B
Note: For equality condition A Θ B holds

If A3A2A1A0 are equal to B3B2B1B0
Then the equality condition is (A3 Θ B3) (A2 Θ B2) (A1 Θ B1) (A0 Θ B0)
Then the circuit is
A0
B0
A1
B1
1
A2
B2
A3
B3
Summary:
For “n-Bit” Comparator:
(1) Total number of combination = 22n
(2) Number of combination which shows equal expression i.e., A = B is 2n
(3) Number of combination which shows, greater expression i.e. A>B or lower
22n - 2n
expression i.e., A < B is
2
(n = number of bits)
86
Problem:
The output Y of a 2-bit comparator is logic-1 whenever the 2-bit input A is greater than
the 2-bit input B. The number of combinations for which the output is logic-1.
Solution: Let 2-bit input A = A1A0
2-bit input B = B1B0
When A > B → Y Logic-1.
So according to above condition truth table as,
A1 A0 B1 B0 Y=A>B Min-terms
0 0 0 0 0 m0
0 0 0 1 0 m1
0 0 1 0 0 m2
0 0 1 1 0 m3
0 1 0 0 1 m4
0 1 0 1 0 m5
0 1 1 0 0 m6
0 1 1 1 0 m7
1 0 0 0 1 m8
1 0 0 1 1 m9
1 0 1 0 0 m10
1 0 1 1 0 m11
1 1 0 0 1 m12
1 1 0 1 1 m13
1 1 1 0 1 m14
1 1 1 1 0 m15
87
Now, the truth table for (A > B) is shown below,
A1 A0 B1 B0 Y Min-terms
m4
0 1 0 0 1
m8
1 0 0 0 1
m9
1 0 0 1 1
m10
1 1 0 0 1
m11
1 1 0 1 1
m12
1 1 1 0 1
Thus, the number of combinations for which the output is logic “1” = 6.
Another Approach
Direct formula based approach,
Given comparator is 2-bit → n = 2
Total number of entry in truth table of 2-bit comparator → 22n = 24 = 16
22n − 2n 16 − 4
Number of combination in truth table for which A > B → = =6
2 2
Multiplexer
• Multiple inputs and one output.
• Depending on control or select input, one of the inputs is transferred to the output
line.
• In most of the electronic system, the digital data is available from more than one
source. It is necessary to route this data over a single line.
• A multiplexer is a digital circuit which selects one of the n data inputs and routes
(connects) it to the output. The selection of one of the n inputs is done with the
help of the select inputs.
88
I0
Data
I1 4:1
I/ Y
P I2
MUX O/
I3 P
S1 S0
Control
• It is also called a data selector or many to one circuit or universal logic circuit or
parallel to serial circuit.
m = 2n or n = log2m
Where m = no. of data inputs
n = no. of select inputs (control inputs)
2:1 MUX
It has two inputs and 1 select line.
I0 I0
2:1
Y
MUX Y
I1
I1
S0
Symbol of MUX
I0
Y
I1
S0
89
Truth Table
A B
0 I0
1 I1
Logical Expression
Y = SI0 = SI1
Implementation
I0
I1
4: 1 MUX
It has 4 inputs and 2 select lines.
I0
I1 4:1
Y
I2
MUX
I3
S1 S0
Truth Table
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
90
Logical Expression
Y = S1S0I0 + S1S0I1 + S1S0I2 + S1S0I3
Implementation of higher order MUX with lower order MUX
Implement 4 : 1 MUX using 2 : 1 MUX
I0
2:1
I1
S0
2:1
Y
I2
2:1 S1
I3
S0
In 4 : 1 MUX, number of 2 : 1 MUX required = 3
Implement 8 : 1 MUX using 2 : 1 MUX
I0
2:1
I1
S0
2:1
I2
2:1 S1
I3
2:1 Y
S0
I4
S1
2:1
I5
S0
2:1
I6
2:1 S1
I7
S0
91
32 + 16 + 8 + 4 + 2 + 1
• 64 × 1  → 63 (2 × 1) MUX
• 128 + 64 + 32 + 16 + 8 + 4 + 2 + 1
256 × 1 → 255 (2 × 1) MUX
• Therefore for 2n : 1 MUX the number of 2 : 1. MUX required is 2n − 1.
16 × 1 MUX from 4 × 1 MUX
16 4
Number of MUX = + = 4+ 1=5
4 4
I0
I1
4:1
I2
I3
S1 S0
I4
I5
4:1
I6
I7
S1 S0 4:1 Y
I8 O/
I9 P
4:1 S3 S2
I10
I11
S1 S0
I12
I11
4:1
I12
I13
S1 S0
16 + 4 + 1
• 64 × 1 MUX  → 21 (4 × 1) MUX
• 64 × 1 MUX ←→ 9 (8 : 1) MUX

64 8
+
8 8
92
MUX as Universal Gate
2 : 1 MUX
NOT Gate
1 I0
Y
0 I1
Y = S0I0 + S0I1 = A × 1 + 0 × A = A
• 1 (2:1) MUX is required to implement NOT gate
AND Gate
O I0
Y
B I1
Y = A * 0 + AB = AB
1 (2 : 1) MUX is required to implement AND gate.
OR Gate
B I0
Y
1 I1
S=A
Y = AB + A × 1 = A + B
1 (2 : 1) MUX is required to implement an OR gate.
93
NAND Gate
1 I0
B I1
Y = A × 1 + BA = A + B =AB
For B:
1 I0
B
0 I1
2 (2 : 1) MUX required for NAND gate.
NOR Gate
B I0
0 I1
Y = AB + A * 0 = A + B
2 (2:1) MUX required for NOR gate as 1 MUX is required for B
94
EXOR Gate
B I0
I1
B
Y = AB + AB
2 (2 : 1) MUX required for EXOR gate as 1 MUX is required for B
EXNOR Gate
B I0
B I1
A
Y = A B + AB
2 (2 : 1) MUX required for EXNOR gate as 1 MUX is required for B
Note
• For EXOR number of 2 × 1 MUX required = 2
• For AND gate number of 2 × 1 MUX required = 1
• For half adder number of 2 × 1 MUX required = 3
• For half subtractor number of 2 × 1 MUX required = 3
95
4 : 1 MUX
Any two variable functions are implemented with 4 : 1 MUX.
AND Gate
0
0
4:1 Y
0
1 A B
S1 S0
OR Gate
1
4:1 Y
1
1 A B
S1 S0
EXOR Gate
1
4:1 Y
1
0 A B
S1 S0
EXNOR Gate
1
0
4:1 Y
0
1 A B
S1 S0
96
Solved Examples
Determine minimized output logical expressions
Problem:
I0
C
I1
Y
I2
C
I3
A B
Solution:
Y = ABC + ABC + ABC + ABC = A C(B + B) + AC(B + B) = A C + AC = A Θ C
Problem:
C I0
1 I1 4x1
Y
0 I2 MUX
C I3
A B
Solution:
Y = ABC + AB + AB * 0 + ABC = A BC + AB + ABC = AC + BC
BC
A
BC BC BC BC
A 1 1 1
A 1
Implement following Logical Expressions using Multiplexer
97
Problem:
f(A, B, C) = ∑m(0, 1, 4, 6, 7)
Solution:
A B C
0 0 0 → C B A
1 I0
0 0 1 → C B A 0 I1
0 1 0 → C B A 4:1
C I2
0 1 1 → C B A
1 I3 S1 S0
1 0 0 → C B A
1 0 1 → C B A
A B
1 1 0 → C B A
1 1 1 → C B A
AB AB AB AB
I0 I1 I2 I3
C 0 2 4 6
C 1 3 5 7
1 – 4 : 1 MUX and 1 – NOT gate required.
Problem:
Implement logical expression f(A, B, C) = ∑m(1, 2, 3, 5, 6, 7) with
(i) AB as select line
(ii) AC as select line
(iii) BC
Solution:
(i)
AB AB AB AB
I0 I1 I2 I3
C 0 2 4 6
C 1 3 5 7
98
1
4:1 Y
C
A B
1 – 4 : 1 MUX Required
(ii)
AC AC AC AC
I0 I1 I2 I3
B 0 1 4 5
B 2 3 6 7
B 1 B 1
1
4:1 Y
B
1
A C
(iii) BC Control:
BC BC BC BC
I0 I1 I2 I3
A 0 1 2 3
A 4 5 6 7
0 1 1 1
0
1
4:1 Y
1
1
B C
99
Problem:
Given 4 × 1 multiplexer is shown below; determine the expression of output Q.
1 D3
1 D2 4 x 1
Q
1 D MUX
1
C D0 S1 S
0
A C
Solution:
Given that-
1 D3
1 D2 4x1
Q
D1 MUX
1
C D0 S1 S
0
A B
Inputs are: D0 = C and D1 = D2 = D3 = 1.

Selection lines are: S1 = A, S0 = B.
Output Q of the circuit is shown below,
Q = S1 S0D0 + S1 S0D1 + S1 S0D2 + S1 S0D3
Q = A B C + AB.1 + AB.1 + AB.1
Q = A B C + AB + AB + AB
(1) (2, 3) (4, 5) (6, 7 )
We can convert Q in SOP min-terms,

Q = ∑m(1, 2, 3, 4, 5, 6, 7)
Apply K-map in SOP form,
AB C
C 01 11 10 B
00
00 1 1 1 A
1 1 1 1
01
100
So, minimized function Q,

Q=A+B+C
Important Points
Any two variable function is implemented

• Using one 4 : 1 MUX 
Some of three variable are implemented
All two variable functions are implemented

• Using one 4 × 1 MUX and one NOT 
All three variable functions are implemented
Any three variable function is implemented

• Using one 8 : 1 MUX 
Sum of four variable functions are implemented
All three variable functions are implemented

• Using one 8 × 1 MUX and one NOT 
All four variable functions are implemented
Advantages of Multiplexers
(1) It reduces the number of wires, required to be used.
(2) A multiplexer reduces the circuit complexity and cost.
(3) We can implement many combinational circuits using MUX.
(4) It simplifies the logic design.
(5) It does not need the k maps for simplification.
DEMUX (Demultiplexer)
• Single input and multiple outputs.
• A demultiplexer performs the reverse operation of a multiplexer i.e., it receives one
input and distributes it over several CC.
Y0
1x4 Y1
I I 1:4 O/
P
DEMUX Y2
Y3
S1
S0
S1 S0
select
• DEMUX is a combinational circuit which has one input and multiple outputs and
depending on select Input, data input is transferred to any of the outputs.
• Also known as 1 to many circuit or data distributor.
101
Y0
I 1:2 Y0
Y1
Y1
Truth Table
S Y1 Y0
0 0 1
1 1 0
Logical Expression
Y0 = SI and Y0 = SI
Implementation
Y0
1
Y1
S S
1 : 4 DEMUX
I S1 S0
Y0= S1 S0I
4x1 Y1= S1 S0I Y0

I
MUX Y2= S1 S0I
Y1
Y3= S1 S0I
Y2
S1 S0 Y3
102
Implementation of Higher of DEMUX from Lower Order DEMUX
3
• 1 × 4 DEMUX ←→ 1 × 2 DEMUX
Y0
7
• 1 × 8 DEMUX ←
→ 1 × 2 DEMUX 1x2
Y1
5
• 1 × 16 DEMUX ←→ 1 × 4 DEMUX I 1x2
21 Y2
• 1 × 64 DEMUX ← → 1 × 4 DEMUX
1x2
9 Y3
• 1 × 64 DEMUX ←
→ 1 × 8 DEMUX
17
• 1 × 256 DEMUX ← → 1 × 16 DEMUX
Decoder
• Decoder is a combinational circuit which has multiple inputs and multiple outputs.
• It is used to convert binary data to other code (binary octal)
Example:
Binary to octal (3 x 8)
BCD to decimal (4 x 10)
Binary to hexadecimal
BCD to seven segments
• 2 to 4 decoders is the minimum possible decoder.
2 × 4 Decoder
E A B
Y0
(MSB)
A Y0
2x4 Y1
Decoder Y2 Y1
B
Y3
Y2
E
Y3
103
Truth Table
E A B y3 y2 y1 y0
0 × × 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
Logical Expression:
Y0 = A B E, Y1 = ABE, Y1 = ABE, Y3 = ABE
• Decoder and DEMUX internal circuit remains same.
Solved Examples
Problem:
Implement half adder using 2 x 4 decoder.
Solution:
AB
(MSB)
A AB
2×4 SUM= A B + A B
AB
B DECODER AB
Carry = A B
E=1
We implement HA using 1 – 2 × 4 decoder and 1 OR gate and some for HS.
BORROW = A B
(MSB)
A AB
2×4 DIFF = A B + A B
AB
B DECODER
AB
AB
E=1
104
Binary to Octal DECODER

• Also called as 3 × 8 Decoder
ABC
Y0
ABC
Y1
MSB ABC
A Y2
3×8 ABC
B Y3
DECODER ABC
Y4
C
ABC
Y5
ABC
Y6
ABC Y7
E=1
Solved Examples
Problem
Implement using 3 x 8 decoder make FA.
Solution:
SUM = ∑m(1, 2, 4, 7) = A BC + ABC + AB C + ABC
CARRY = ∑m(3, 5, 6, 7) = AB + BC + CA
0
1
2
MSB
3
A SUM
3×8
B
DECODER
4
C 5
CARRY
6
7
105
Implementation of Higher Order Decoder using Lower Order Decoder
4 × 16 ← 5
→2×4
1 × 16 ←→ 1 × 4
5
16 × 1 ←
5
→ 4 × 1 (Since 2 × 4 decoder means 1 × 4 DEMUX using 2 select lines)
C Y0 Y0
MSB
2×4 B
D 3×8
C
MSB D
C C Y7
2×4 2×4 A
D D
Y8
C B
C 3×8
2×4
D
D
Y15
C
2×4
D
Encoder
• Encoder is the combinational circuit which has multiple inputs and multiple outputs.
• Encoder is used to convert other code to binary.
Example: Octal to binary, decimal to BCD, hexadecimal to binary.
Octal to Binary Encoder
I0
I1
I2
8×3 Y0
I3
OCTAL to Y1
I4 BINARY
Y2
I5
I6
I7
106
• In normal encoder one of the input lines is high and corresponding binary code is
available at the output.
• But this may create a problem when more than one input line is high. So we design
Priority Encoder.
• In priority encoder more than one input is high but binary output corresponds to the
highest priority input.
Truth Table
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
Logical Expression
Y0 = I1 + I3 + I5 + I7
Y1 = I2 + I3 + I6 + I7
Y2 = I4 + I5 + I6 + I7
I0 I1
I3
I1 Y0
I5
I7
I2
I2
I3 I3
I6 Y1
I4
I7
I5 I4
I5
I6 Y2
I6
I7 I7
107
Hazards
Hazards are unwanted switching transients that may appear at the output of a circuit
due to different paths exhibiting different propagation delays. Hazards occur in
combinational circuits where they may cause a temporary false value at the output.
Hazard
Static Dynamic Essential
Occur in two Occur in multilevel Occurs in Asynchronous

level circuit circuit Sequential circuit
Occur in Combinational circuit Avoid by adding redundant term
Occur in Combinational circuit
Static '1' Hazard Static '0' Hazard
And-OR circuit OR-AND circuit

In SOP form In POS form
• To avoid static and dynamic hazard redundant terms are added in a combinational
circuit.
• Essential hazard cannot be avoided but feels essentials.
• For the given circuit determine o/p wave form when.
Case 1: No propagation delay
0
1
A
1
X
0
Static '0'
0 0
Y
108
Case 2: If there is propagation delay of 1ns in NOT gate and no delay in AND gate.
0
1
A
1 1ns
X
1 0
1
Static '0' Hazard
0 0
Y
1ns
Case 3: If there is propagation delay of 1ns in NOT gate and 2ns in AND gate
0
1
A
1ns
1
X
0
Y'
2nsec
Similarly, if the output is expected to be static at “Logic 1” but it exhibits a small glitch of
“Logic 0” then it is called as Static-1 Hazard.
109
110
Sequential Logic Circuits
Chapter 4
Objective
• Implement basic building blocks of sequential circuits that are flip flops.
• Design basic sequential circuits like registers and counters.
• Implement simple state machines.
Introduction
A sequential circuit is characterized by inputs, outputs and internal states. in
synchronous sequential circuits, change of internal states occurs in response to
synchronized clock pulses. Asynchronous sequential circuits do not use clock pulses
and internal states change whenever inputs change. In sequential circuits, output is a
function of inputs and previous values of outputs so memory elements are employed to
store the past values of outputs.
In the case of a sequential circuit, the timing parameter comes into effect. In fact, the
output of the sequential circuit depends upon the present time input, the previous
output and the sequential in which the inputs are applied.
The basic memory element is Flip Flop whose representation is shown below:
Q
Inputs
FF
Q
Flip-flop has two outputs which are designated as which are often complementary to
Q
each other. The state of flip flop refers to the state of Output Q as when Q = 1, the flip
flop is said to be in set state and when Q = 0, the flip flop is said to be in reset state.
The flip flop can switch between its two states and is also known by other names such
as “Latch” or “Bistable Multi-vibrator”.
The problem with using NOT gate for creating latch is that it has only one input so we
use NAND and NOR gates for implementing latches.
111
SR Latch using NAND Gate

It consists of two cross-coupled NAND gates that is the output of one NAND gate is fed
as input to the other NAND gate.
Working Operation of S-R Latch

Case 1: S = 0, R = 0 Race
Case 2: S = 0, R = 1 Reset
Case 3: S = 1, R = 0 Set
Case 4: S = 1, R = 1 No change
S Q
Q
R
Truth Table
S R Q
0 0 Invalid (Q = Q = 1)
0 1 1
1 0 0
1 1 Previous state (no change)
• In SR latch if both gates are enabled then output remains in the previous state and
if both are disabled then output remains in invalid state.
SR Latch using NOR Gate

It consists of two cross-coupled NOR gates that are the output of one NOR gate that is
fed as input to the other NOR gate.
S
Q
Q
R
112
Working Operation of S-R Latch
Case 1: S = 1, R = 0 The latch output does not change.
Case 2: S = 0, R = 1 Is called as the Reset condition
Case 3: S = 0, R = 0 Is called as the Set condition
Case 4: S = 1, R = 1 Is the prohibited state. The output is unpredictable. Therefore, this

condition must be avoided.
Truth Table
S R Q
0 0 Previous state
0 1 0
1 0 1
1 1 Invalid (Q = Q = 0)
• SR latch is used to eliminate switch bouncing by storing the logic state.

• Bouncing means vibration of switches when ON or OFF.
SR Flip Flop
In synchronous circuits, the exact time at which output can change state is determined
by a signal called as a clock. The clock signal is generally a rectangular or a square pulse.
The difference between latches and flip flops is the presence of a clock signal.
Clock
Q
R
113
SR Flip Flop using NAND Gate
Truth Table
Clock S R Qn + 1
1 x x Previous state(Qn) S R Qn + 1
1 0 1 Qn 0 0 Qn
1 0 1 0 → reset 0 1 0
1 1 0 1 → set 1 0 1
1 1 1 Invalid → unused 1 1 Invalid
S
Q
Clock
Q
R
SR Flip Flop using NOR Gate

• Truth table is the same as for the NAND gate SR FF.
Characteristic table
S R Qn Qn + 1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0 S R Qn + 1

1 0 0 1 0 0 Qn
1 0 1 1 0 1 0
1 1 0 x 1 0 1
1 1 1 x 1 1 Invalid
114
Logic expression
R Qn
S R Qn R Qn R Qn R Qn
S 1
S 1 1 X X
Qn + 1 = S + RQ and S.R = 0
• Since S = 1, R = 1 the output is invalid because S.R = 1 does not satisfy the above
condition.
• Excitation Table
Excitation table shows the possible values of input for each combination of present
and next state. It helps in deriving logic expressions for the inputs of Flip-Flops
depending on the value of desired output.
Qn Qn + 1 S R
0 0 0 x
0 1 1 0
1 0 0 1
1 1 x 0
• Disadvantage of SR FF is invalid state present when S=1 and R = 1.
• To avoid this JK FF used.
JK Flip Flop
S = JQ
R = KQ
S Q
J
Clock
K
R Q
115
Characteristic Table
Clock J k Qn + 1
0 x x Qn
1 0 0 Qn
1 0 1 0
1 1 0 1
1 1 1 Qn
Truth Table
J k Qn + 1
0 0 Qn Hold
0 1 0 Reset
1 0 1 Set
1 1 Qn Toggle
JK Flip-Flop using NAND Gate
J
Q
Clock
Q
K
JK Flip-Flop using NOR Gate
J Q
CLX
K Q
116
J K Qn Qn + 1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Logical Expression
KQn
J
K Qn K Qn K Qn K Qn
J 1
J 1 1 1
Qn + 1 = JQn + KQn
Excitation Table
Qn Qn + 1 J k
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
• Drawback in JK FF is race around condition which means when J and K are both 1
then output will keep on toggling and output value will be indeterminate.
117
Race Around Condition

This is a drawback of JK flip flop.
Q
J Q
J
Clock
K Q
K Q
If tpw = 10n sec(Pulse Width), tPFF = 1n sec (Propagation delay of flip flop) then:
10 nsec
Clock:-
O/P:-
Q
• In JK FF RAC occurs when J = K = 1 and tpd FF is less than that of tpd clock and therefore
the output changes several times in a single clock pulse.
Condition to Remove Race Around Condition

(i) tpdclock < tpdFF
(ii) Use of Master slave flip flop
(iii) Increase the propagation delay of JK flip flop
(iv) This is eliminated in the D-flip flop
Master Slave Flip Flop
J Q J Q
M S
K Q K Q
CLK
118
• Since input of slave is J = Q and K = Qn therefore it is always (1, 0) or (0, 1). But,
race around condition occurs only when the input is (1, 1). So, race conditions are
removed.
Clock
QM
QS
• In Master Slave FF, output changes only when slave output is changing.
• In Master Slave FF, Master and slave is edge triggered.
D–Flip Flop
D J Q D S Q
CLK CLK
K Q R Q
J=D S=D
K=D R=D
Truth Table
CLK D Qn + 1
0 x Qn D Qn + 1

1 0 0 0 0
1 1 1 1 1
D Qn Qn + 1
0 0 0
0 1 0
1 0 1
1 1 1
Qn + 1 = D = Therefore it is also called transparent latch.
119
Excitation Table
Qn Qn + 1 D
0 0 0
0 1 1
1 0 0
1 1 1
T Flip–Flop (Toggle)
T J Q
CLK J=K=T
K Q
Truth Table
CLK T Qn + 1
0 x Qn T Qn + 1

1 0 Qn 0 Qn
1 1 Qn 1 Qn
T Qn Qn + 1
0 0 0
0 1 1
1 0 1
1 1 0
Qn + 1 = TQn + TQn = T ⊕ Qn
120
Excitation Table
Qn Qn + 1 T
0 0 0
0 1 1
1 0 1
1 1 0
• All tables are subsets of JK FF therefore it is also called a universal flip flop.
Excitation Table Summary
Qn Qn + 1 S R J K D T
0 0 0 x 0 x 0 0
1 1 1 0 1 x 1 1
0 1 0 1 x 1 0 1
1 0 x 0 x 0 1 0
Qn + 1 =S + RQn ⇒ SR = Set Reset

Qn + 1 = JQn + KQn ⇒ JK = Name of person who give the IC
Qn + 1 = D ⇒ D = Delay Element.
Qn + 1 = T ⊕ Qn ⇒ T = Toggle.
Toggle Mode of JK Flip Flop
1 Q f/ Q 1 Q
J J f/ J f/
2 2 2
K Q K Q 1 K Q
J Q J Q f/ D Q
2 f/
f/ 2
2
K Q Q Q
1
S Q
f/
2
R Q
121
Types of Triggering
Trigger
Level Trigger Edge Trigger
+ve Edge Trigger -ve Edge Trigger
• In the level trigger circuit, the circuit is active based on whether the clock is “logic 1”
or “logic 0”.
• In the level trigger circuit, output may change many times in a single clock.
• in edge trigger circuit, circuit is active on the edge of the clock that is positive edge
(clock goes from “logic 0” to “logic 1”) or negative edge (clock goes from “logic 1” to
“logic 0”)
• In edge triggers, output may change only once on a single pulse.
Differention
Conversion of One FF to other FF
Procedure
• Required FF characteristics table.
• Available FF excitation table.
• Write a logical expression for excitation.
JK–Flip Flop to D–Flip Flop
D Qn Qn + 1 J K
0 0 0 0 x
0 1 0 x 1
1 0 1 1 x
1 1 1 x 0
122
Logical Expression for J and K
Qn Qn
D D
D X D X 1
J= K=
D 1 X D X
J=DK=Q
Implementation
D J Q Q
K Q Q
JK FF to SR FF
S R Qn Qn + 1 J K
0 0 0 0 0 x
0 0 1 1 x 0
0 1 0 0 0 x
0 1 1 0 x 1
1 0 0 1 1 x
1 0 1 1 x 0
1 1 0 x x x
1 1 1 x x x
Logic Expressions for J and K
R Qn R Qn
S R Qn R Qn R Qn R Qn S R Qn R Qn R Qn R Qn
S X S X 1 X
J= K=
S 1 X X X S X X X
J = S K=R
123
Implementation
S J Q
CLK
R K Q
JK FF to T FF
T Qn Qn + 1 J K
0 0 0 0 x
0 1 1 x 0
1 0 1 1 x
1 1 0 x 1
Logic Expressions for J and K
Qn Qn
T T Qn
Qn Qn Qn
T X T X
J= K=
T 1 X T X 1
J = T K=T
Implementation
T J Q
K Q
124
SR FF to JK FF
J R Qn Qn + 1 S R
0 0 0 0 0 x
0 0 1 1 x 0
0 1 0 0 0 x
0 1 1 0 0 1
1 0 0 1 1 0
1 0 1 1 x 0
1 1 0 1 1 0
1 1 1 0 0 1
Logical Expressions for S and R
K Qn K Qn
J K Qn K Qn K Qn K Qn J K Qn K Qn K Qn K Qn
J X J X 1 X
S= R=
J 1 X 1 J 1
S = JQn R = KQn
Implementation
S Q
J
Clock
K
R Q
125
SR FF to D FF
D Qn Qn + 1 S R
0 0 0 0 x
0 1 0 0 1
1 0 1 1 0
1 1 1 x 0
Logic Expression for S and R
Qn Qn
D D
D D X 1
D 1 X D
S=D R=D
Implementation
D
S Q
R Q
SR to T FF
T Qn Qn + 1 S R
0 0 0 0 x
0 1 1 x 0
1 0 1 1 0
1 1 0 0 1
126
Logic Expression for S and R
Qn Qn
T T
Qn Qn Qn Qn
T X T X
S:- R:-
T 1 T 1
S = TQn R = TQn
Implementation
S Q
T
R Q
D FF to SR FF
S R Qn Qn + 1 D
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 0 0
1 0 0 1 1
1 0 1 1 1
1 1 0 x x
1 1 1 x x
Logic Expression for D
R Qn
S 1
D=
S 1 1 X X
D = S + RQn
127
Implementation
S D Q
T FF to SR FF
S R Qn Qn + 1 T
0 0 0 0 0
0 0 1 1 0
0 1 0 0 0
0 1 1 0 1
1 0 0 1 1
1 0 1 1 0
1 1 0 x x
1 1 1 x x
Logic Expression for T
R Qn
S 1
T=
S 1 X X
T = RQ + SQ
Implementation
T Q Q
S
Q Q
128
Summary of Flip Flop Conversion
To
From
SR FF JK FF D FF T FF
SR FF --- S = JQ, R = KQ S = D, R = D S = TQ, R = TQ
JK FF J = S, K = R --- J = D, K = D J = T, K = T
D FF D = S + RQ D = JQ + KQ --- D=T⊕Q
T FF T = SQ + RQ T = JQ + KQ T=D⊕Q ---
Setup Time
The minimum time in which the input must be kept at a constant value prior to the
occurrence of the clock edge is called set-up time.
Hold Time
The minimum time in which the input must be kept constant after the occurrence of the
clock edge is called hold time.
Register
• Registers are used to store groups of more than one bit
• To store n–bits, n FFs are cascaded in register
• To increase the storage capacity in terms of number of bits, we have to use a group
of Flip-flop. Such a group of flip-flops is known as a register
• Register are of four types (Depending on nature of Input and Output)

(i) SISO (Serial In Serial Out)
(ii) SIPO (Serial In Parallel Out)
(iii) PISO (Parallel In Serial Out)
(iv) PIPO (Parallel In Parallel Out)
• Depending on application the register are of two types:

(i) Shift register
(ii) Storage register
129
SISO (Serial In Serial Out)
D3 Q3 D2 Q2 D1 Q1 D0 Q0
I/P O/P
Q3 Q2 Q1 Q0
CLK
Q3 Q2 Q1 Q0 CLK
0 0 0 0 0
1 0 0 0 1
1 1 0 0 2
0 1 1 0 3
1 0 1 1 4
• For serial in register the ‘n’ bit data storage requires ‘n’ clock pulse as each bit is
introduced at successive clock edges.
• SISO register is used to provide n clock pulse delay to Input data as can be seen
from the table that the input ‘1’ applied prior to first clock edge appears at output
after 4 clock cycles.
Delay = nTclk
• To provide n bit data serially out it requires (n − 1) clock pulse.
SIPO (Serial In Parallel Out)
Q3 Q2 Q1 Q0
Data I/P
Q3 Q2 Q1 Q0
CLK
P3 P2 P1 P0
DATA
CLK
130
• In the SIPO register, to provide ‘n’ bit data serially in, ‘n’ clock pulses are required
and for parallel output it requires 0 clock pulse.
• It is used as a serial to parallel converter.
• SIPO is used to convert temporal code to spatial code.
• Since serial data is slow and parallel data is fast so it is used as a slow to fast
converter.
Solved Examples
Problem:
The circuit shown in the figure is a 4 bit SIPO register which is initially loaded with 1010.
If three clock pulses are applied then the data if the system is:
CLK 1 0 1 0
(a) 1010
(b) 1101
(c) 1111
(d) 0000
Solution: (c)
After 1st Clock Pulse, Data = 1101
After 2nd Clock Pulse, Data = 1110
After 3rd Clock Pulse, Data = 1111
Problem:
Circuit shown in the figure is initially loaded 1011 if clock pulses applied continuously
after how many clock pulse data again become 1011.
1 0 1 1
131
(a) 4
(b) 7
(c) 11
(d) 15
Solution: (b)
Output of 3 variables XOR is 1 if the number of 1’s at th e input is odd.
CLK Q 3 Q 2 Q 1 Q0
1 0 1 0 1
2 0 0 1 0
3 1 0 0 1
4 1 1 0 0
5 1 1 1 0
6 0 1 1 1
7 1 0 1 1
PISO (Parallel In Serial Out)
I0 I0 I0
I1 I1 I1
D3 Q3 D2 Q2 D1 Q1 D0 Q0
Q3 Q2 Q1 Q0
Clock
Control
Control = 0 => Parallel In

Control = 1 => Serial Out
• In the PISO register to provide parallel input it requires 1 clock pulse and to provide
serial output (n - 1) clock pulses are required.
• PISO is also used to convert spatial code to temporal code.
132
PIPO (Parallel In Parallel Out)
I/P O/ I/P O/ I/P O/ I/P O/

1 P1 2 P2 1 P1 0 P0
D3 Q3 D2 Q2 D1 Q1 D0 Q0
Q3 Q2 Q1 Q0
CLK
• PIPO is used as a storage register.

• For Parallel Input it requires 1 clock pulse.
• For Parallel Output it requires 0 clock pulses.
Summary
Different registers take the following number of clock cycles for input and output.
Input Output
SISO n n−1
SIPO n 0
PISO 1 n−1
PISO 1 0
• Each shift left register operation provides multiplication by 2. In ‘n’ left shift
operation performed then data is multiplied by 2n.
• Each shift right operation performed then data is divided by 2. If ‘n’ right shift
operation performed then data is divided by 2n.
Counters
• Counters are basically used to count the number of clock pulses applied. It can also
be used for frequency division, time measurement, frequency measurement, range
measurement, pulse width measurement.
133
Pulse
16 x pulse width = Total width
Also used as a waveform generator.

• With n FF, max possible state in the counter is 2n.
• N ≤ 2n or n ≥ log2N Where N = Number of state, n = Number of FF
Type of Counters
Depending on the clock pulse input to the flip flop counters can be of two types:
(i) Asynchronous counters
(ii) Synchronous counters
Asynchronous Synchronous
(1) Different FFs are applied with

(1) All FF are applied to some clock
different clocks
(2) It is slower (2) It is faster

(3) Fixed count sequence i.e., up or
(3) Any count sequence is possible
down
(4) Decoding errors will be present (4) No decoding error will be present
(5) Ripple counter (5) Ring counter
• Number of stages used in the counter is also called the modulus of the counter.
i.e., if MOD 5 counter = 5 stage.
MOD n counter = n stage.
MOD N
f Counter f/N
Solved Examples
Problem:
A decade counter is applied with frequency of 10 MHz then output frequency is.
fin 10MHz
Solution: fout = = = 1MHz
10 10
134
Cascading of Counters
Let MOD M and MOD N are cascaded then it will act as MOD MN counter.
MOD N MOD M MOD MN

fin fout fin fout
Ripple Counter
• It is an asynchronous counter which means different FFs are fed with different
clocks.
• All the FFs are operated in toggle mode.
• Only one FF is applied with external clock and other FF’s clock is fed from previous
FF’s output (whether Q or Q).
• The FF applied with an external clock will act as LSB.
3 Bit Ripple Counter (Up Counter)
I J0 Q0 I J1 Q1 I J2 Q2
I K0 Q0 I K1 Q1 I K2 Q2
CLK Q0 Q1 Q2
LSB MSB
• The CKT shown in figure Q0 toggles for every clock pulse.

• Qn change when Qn − 1 change from 1 − 0. i.e., Q2 changes when Q1 changes from 1 − 0
because all FFs are negative edge triggered.
Truth Table
CLK Q3 Q2 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0
135
• It is also called MOD 8 ripple counter.
Timing Diagram
1 2 3 4 5 6 7 8 9
CLK
Q0
2T
Q1
4T
Q2
8T
• In n bit ripple counter propagation delay of each FF is tpd FF the time period of the
1 1
clock is. Tclock ≥ n tpd FF or fclock ≥ and fmax =
n tpd FF n tpd FF
3 Bit Ripple Counter (Down Counter)
1 T0 Q0 1 T1 Q0 1 T2 Q0
Q0 Q0 Q0
clock
LSB MSB
• For the circuit shown in figure Q0 toggles for every clock pulse.
• Q1 toggles when Q0 changes from 0 to 1.
• Q2 toggles when Q1 changes from 0 to 1.
136
Truth Table
Clock Q2 Q1 Q0
0 0 0 0
1 1 1 1
2 1 1 0
3 1 0 1
4 1 0 0
5 0 1 1
6 0 1 0
7 0 0 1
• This is called ripple counter because the input clock is the previous FF output.
• In ripple counter with n FFs maximum possible state is 2n.
f
• Frequency after n FFs in the Ripple counter is n . (i.e., for 3 − FF o/p is f/8)
2
Decoding Error
• If the O/P is (000) and clock is applied then 3tpd FFis delayed.
• Due to different delays encountered by different outputs, there are intermediate
states.
• Unwanted intermediate states are also called transient states.
• Decoding errors or transient state present in ripple counter due to propagation
delay.
• To avoid decoding error strobe signal is used.
1 T0 Q0 1 T1 Q0 1 T2 Q0
CLK
Q0 Q0 Q0
LSB MSB
137
• Strobe signal is zero for n tpd FF and after that if it is one for the next clock. Then
all the output is zero for the transient time therefore due to strobe signals we can
remove decoding errors.
Tclock ≥ ntpd FF + TS
Asynchronous Inputs
• Clear and present are known as asynchronous inputs because they do not depend
on the occurrence of the clock.
• S, R, J, K, D, T are synchronous inputs.
Clear: Clear is used to reset our FF or counter.
Preset: Preset is used to set our FF or counter.
D Q D D
CLK CLK CLK

Q
CLR CLR = 0, no effect CLR = 1, FF is zero

= 1, FF is zero = 0, no effect
Summary of Ripple Counter
Triggering Edge Clock Nature
Negative Q Up Counter
Positive Q Up Counter
Negative Q Down Counter
Positive Q Down Counter
138
Non Binary Ripple Counter
BCD Counter (Decade Counter)

• 4 flip flops used.
1 J0 Q0 1 J1 Q1 1 J2 Q2 1 J3 Q3
1 K0 Q0 1 K1 Q1 1 K2 Q2 1 K3 Q3
CLR CLR CLR CLR
Truth Table
CLK Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
Q3 Q2 Q1 Q0
8 1 0 0 0
1 0 1 0
9 1 0 0 1
0 0 0 0 0
Q3 Q3
Q2 Q2
CLR CLR
Q1 Q1
Q0 Q0
• If we used only Q3 and Q1, we also use this as a clear circuit.
139
Q3 Q3
CLR CLR
Q1 Q1
• All BCD counters are decade counters but the reverse is not true.
• Output frequency of BCD counter is f/10.
• Low for 8 clock and high for 2 clock in Q3. So, the duty cycle is 20%.
Synchronous Counters
Ring Counter
• The last FF output is connected to the first FF input.
D3 Q3 D2 Q2 D1 Q1 D0 Q0
Q3 Q2 Q1 Q0
CLK
• Only one FF output is high and the remaining FF output is low.

• In a 4 bit ring counter 4 states are there (i.e., for n FFs there are n states.)
Truth Table
CLK Q3 Q2 Q1 Q0
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 1 0 0 0
• In synchronous counter the triggering may be +ve edge or –ve edge, but the output
remains same.
140
Timing Diagram
1 2 3 4 5 6 7 8
CLK
Q3
Q2
Q1
Q0
f
• n bit = n state and fo =
n
360
• Phase shift between generated waveform is .
n
Application
• Used in stepper motor control.
• In analog to digital converter.
• Number of unused state in ring counter is 2n − n.
Ring Counter using JK FF
J3 Q3 J2 Q2 J1 Q1 J0 Q0
K3 Q3 K2 Q2 K1 Q1 K0 Q0
CLK
141
Self-Starting Ring Counter
D3 Q3 D2 Q2 D1 Q1 D0 Q0
Q3 Q2 Q1 Q0
CLK
• Advantage of a ring counter is the decoding is simple and no logic gates are required
for decoding.
• Last output cannot be connected to the input of the self-start ring counter.
Johnson Counter
• It has a symmetric output waveform.
• 8–stages are there for a 4 bit counter.
360
• Phase shift = = 90
4
• It is just like a SISO register.
D3 Q3 D2 Q2 D1 Q1 D0 Q0
Q3 Q2 Q1 Q0
CLK
0 0 0 0
Truth Table
CLK Q3 Q2 Q1 Q0
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
8 0 0 0 0
142
• Total number of used state = 8.

• Total number of unused state = 2n − 8 − 24 − 8 = 8 state.
• Also called twisted ring counter, Mobius counter or creeping counter or walking
counter or switch fall counter.
CLK Q3 Q2 Q1 Q0
0 0 0 0 0 → Q3 Q0
1 1 0 0 0 → Q3 Q2
2 1 1 0 0 → Q2 Q1
3 1 1 1 0 → Q1 Q0
4 1 1 1 1 → Q3 Q0
5 0 1 1 1 → Q3 Q2
6 0 0 1 1 → Q2 Q1
7 0 0 0 1 → Q1 Q0
8 0 0 0 0
• In Johnson counter to decode each state, one two input AND/NOR gate is used.
• Lock out may occur (when counter enters into unused state)
Note: In synchronous counter propagation delay of each counter is tpd FF then,


Tclock ≥ tpd FF 

1 
fclock ≤ In synchronous counter
tpd FF 
1 
fmax =
tpd FF 
Synchronous Series Carry Counter
1 T0 Q0 T1 Q1 T2 Q2 T3 Q3
Q0 Q1 Q2 Q3
LSB MSB
CLK
• Circuit shown in figure is synchronous series carry up counter.

• In this counter Q0 toggles for every clock pulse.
143
• Q1 toggles when Q0 = 1 and the clock is applied.

• Q2 toggles when Q1 = Q0 = 1 and the clock applied.
• Q3 will toggle when Q2 = Q1 = Q0 = 1 and the clock applied.
• This circuit may be used as down counter when Q is connected to T.
Truth Table
CLK Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
Tclock ≥ tpd FF + (n − 2)tpd AND
Synchronous Parallel Carry Counter
Q0 Q0
Q1
1 T0 Q0 T1 Q1 T2 Q2 T3 Q3
Q0 Q1 Q2 Q3
Clock
144
• Faster than a series carry counter
• Disadvantage is increased number of input pins of AND gate
• Tclock ≥ tpd FF + tpd AND
• Speed of various counters is in the order given below,
• Ripple counter < Synchronous serial carry < synchronous parallel carry counter for
faster logic
Synchronous Counter Design for any given Sequence
Solved Examples
Problem:
Design a synchronous counter for the count sequence 0 → 3 → 1 → 3 → 0 using positive
edge triggered D − FF.
00
10 11 State Diagram
01
Solution: Procedure
(i) Identity number of FFs and inputs and outputs.
(ii) Construct state table.
(iii) Logical expression for inputs.
(iv) Minimize.
(v) Implement the circuit.
Now, since the counter is two bits so we will use two FFs having the same clock
(synchronous).
(i)
D1 Q1 D0 Q0
Q1 Q0
145
(ii) State table
Preset State Next State

Q1 Q0 Q1+ Q0+ D1 D0
0 0 1 1 1 1
1 1 0 1 0 1
0 1 1 0 1 0
1 0 0 0 0 0
(iii) Logical expression

D1 = Q1Q0 + QQ0 = Q1(Q0 + Q0) = Q1
D1 = Q1Q0 + Q1Q0 = Q1 ⊕ Q0 = Q1 Θ Q0
(iv) Implementation
D1 Q1 D0 Q0
Q1 Q0
Problem:
Design using T – FF whose states are 0 – 3 – 1 – 2 – 0.
Solution:
(i)
T1 Q1 T0 Q0
Q1 Q0
MSB
LSB
CLK
146
(ii) State table
Q1 Q0 Q1+ Q0+ T1 T0
0 0 1 1 1 1
1 1 0 1 1 0
0 1 1 0 1 1
1 0 0 0 1 0
(iii) Logical expression

T1 = 1, T0 = Q1Q0 + Q1Q0 = Q1
(iv) Implementation
T1 Q1 T0 Q0
Q1 Q0
MSB
LSB
CLK
Problem:
The state of the output just before the arrival of the second clock pulse is if initial state
of Xand Y are 0.
1 J Q 1 J Q
CLK CLK X Y
Output
1 K 1 K
Solution:
Given counter is a 2-bit asynchronous/ripple counter because there is no common clock
between both flip-flops.
1 J Q 1 J Q
CLK CLK X Y
Output
1 K 1 K
147
As the positive o/p of FF 1 is connected as + ve pulse to next FF, this configuration

appears to be down counter.
So, we can say, the given circuit is a 2-bit asynchronous down counter.
Counting sequence of 2-bit down counter as follows,
Clock Q 1+ = Y Q 2+ = X
0 0 0
Output state just before

1 1 1
the second clock
2 1 0
3 0 1
4 0 0
Thus, the value of X and Y just before the arrival of second clock pulse is X = 1, Y = 1.
Performance Comparison of Counter and Register
Parameter of
Sr. No. Registers counters
comparison
1 Basic building block R-S, J-K flip flops T-flip flop.
2 Mode of operation Serial, parallel Serial Up or down.
Output will always follow a

Change in output Output need not
3 sequence either in the up-ward
state follow a sequence
or downward direction.
SISO,SIPO,PIPO and up counters, down counters

4 Types
PISO up\down counters
Direction of data
5 Bidirectional Bidirectional
transfer
Number of flip-flops
6 One One
per bit
Data storage,
Time and frequency
data shifting,
7 Few application measurement clock A to D
multiplication or
converter
division.
148
Data Converters
Chapter 5 – Data Converters

Objective
• Design different digital to analog converters
• Design and compare performances of different analog to digital converters
Introduction
In this digital age, all the processing is done in digital form but most real world signals
are analog in nature. So, we need an interface between analog and digital signals which
are called data converters. There are two basic types of data converters analog to digital
converter and digital to analog converter.
Va
ADC ADC V0
Digital to Analog Converter (DAC)
Important Terms
• Resolution/Step Size
It is the change in analog voltage corresponding to one LSB increment in the Input.
Vr
Resolution =
2 −1
n
Where Vr = Reference voltage corresponding to logic 1.

n = no. of bits.
• Analog Output Voltage
Vanalog = Resolution × Decimal equivalent of binary data
• VFS
Full scale voltage is the maximum analog output voltage of DAC.
V
=
V r × 2n −=1 Vr
FS n
2 − 1
149
Data Converters
Resolution 1
=
• % Resolution =
× 100 × 100
V 2n − 1
FS
• Error/Accuracy
Error acceptable in ADC’s or DAC’s is equal to resolution or step size.
Solved Examples
Problem
In a 4 bit DAC reference voltage is 5V, if binary data 1001 is applied then analog voltage is.
Solution:
r
V 5 1
= =
Resolution =
n−1
2 16 − 1 3
1
Vanalog = ×9=
3V
3
Digital to Analog Circuit

There are practically two types of DACs:
(1) Weighted resistor DAC
(2) R-2R Ladder type DAC
Weighted Resistor DAC (4 Bit)

b3 = MSB = more current
b0 = MSB = more current
Vr
I3 = * b3
R Vr
R1
V
I = r * b2 R
2 2R b3 I3
If
−
T
Vr b2 2R I2
I1 = * b1 T
4R b1 4R I1
T
Vr 8R
I0 = * b0 b0 I0 +
8R T
If = I3 + I2 + I1 + I0
• V0 = −If Rf
150
Data Converters
• LSB Resistance = (2n − 1) MSB resistance

• In weighted resistor DAC the accuracy is less due to use of different resistance. To
overcome this we use R − 2R ladder.
R – 2R Ladder
R-2R Ladder
Normal ladder Inverted ladder
Non inverting Inverting
3 Bit R – 2R Ladder (Non-Inverting)

• Adjacent to 2R is LSB.
Rf
R1
R R VX V0
+
2R 2R 2R 2R
LSB MSB
Vr
 Rf 
V= 1 + V
0
 Rl  x
n−1
Vr
Vx = Resolution * Decimal equivalent of binary data. = * ∑ 2 i bi
2n
i=0
n−1
∑ 2i b i
Desimal equivalent b2b1b0 = b2 22 + b1 21 + b0 20 =
i=0
151
Data Converters
n−1 
Vr i R 
V0 = × ∑ 2 b i * 1 + f 
2n
Ri 
i=0 
V0 = Resolution * Decimal * gain
3 Bit R – 2R Ladder (Inverting)
Rf
R R R R1
2R 2R 2R 2R V0
Vr
• V0 = Resolution * decimal * gain
n−1  −R 
Vr
• =
V0
2n
× ∑ 2ib i *  R + fR 
i=0  1 
n−1  1 
Vr
• =
If × ∑ 2ibi *  R + R 
2n i=0  1 
152
Data Converters
Inverter Ladder Type DAC Circuit

• Since A and A’ both are ground then (logical or virtual ground and ground) the
switch is at same potential then charging and discharging of switch problem
removed in previous circuit.
Vr
Rf
I
MSB
I3
I/2 b3
A' If
I/2 −
2R A
R
I2
I/4 b2 V0
A' +
I/4 2R
R
I1
b1
I/8 A'
I/8 2R
R I0
I/16 b0
A'
I/16 2R
LSB
2R
Vr
I =
R
I I I I
• I3 = × b3 , I2 =× b2 , I1 =× b1 , I0 = × b0
2 4 8 16
n − 1 
• I = I + I + I + I = I 8b + 4b + 2b + b  = Vr  1
f 0 1 2 3
16  3 2 1 0
2n 
∑ 2ibi  × R

i = 0 
n − 1 
Vr   −R 
• V0 =
n
∑ 2 bi   R f 
i
2  i = 0 


153
Data Converters
Solved Examples
Problem:
If a 12-bit (3-digit) DAC that uses the BCD input code has a full scale output of 9.99V,
then the value of Vout for an input code of 0111 1001 0101 is __________ V.
Solution:
9.99
Step size = = 10 mV
999
0111 1001 0101

7 9 5
Vout = 795 × 10 mV = 7.95V
Analog to Digital Converter

Important Terms
range
• Resolution =
2n − 1
VRange = Vmax − Vmin
1
• Resolution = × 100
2 −1
n
• Dynamic Range = (6n + 1.76) dB ≈ 6ndB
Analog to Digital Converter Circuits

Counter Type ADC Vref
V1 > V2 = V0 = Vref V1 +
V1 > V2 = V0 = −Vref
V0
V2 −
Vref
Va
+
− Counter
Digital o/p
CLK
DAC
154
Data Converters
• It is one bit quantizer.

• In counter type ADC a comparator is used in the Input stage to compare Input
analog voltage with reference voltage provided by DAC feedback
• A counter is used to count the number of clock pulses applied
• When analog voltage (Va) is greater than DAC voltage then output is 1. Then counter
counts and if analog voltage (Va) is less than reference voltage (DAC voltage) then
output is 0 and counter stops counting and it gives corresponding digital output.
• Maximum number of clock pulses required for ‘n’ bit conversion is 2n − 1
• Maximum conversion time = (2n − 1)TCLK . Conversion time depends on Input analog
voltage.
• Also called ramp type ADC.
Parallel Comparator Type ADC
2n − 1 comprator required



For n − bit 2n resistor required
 n
2 × n Priority encoder required

• Also called Flash ADC (fastest ADC)
3 Bit Parallel Comparator Type ADC
Vr Va
R −
7
+
R 7Vr −
8 + 6
6Vr Y0 PIPO
R − D2 Q0
8 5 8×
+ ×3 Y1
Priority D1 Q1
5Vr Y2
R − Encoder
D0 Q2
8
+ 4
4Vr
R −
8
+ 3
CLK
3Vr
R − 1 Clock required
8 2
+
2Vr
R −
8 1
+
R Vr 1 0
8
no clock
155
Data Converters
• 1 clock pulse is required

• Therefore it is the fastest ADC among all
• Maximum number of clock pulses required for ‘n’ bit conversion is which is inside
PIPO
Range of analog output

7V
Va > r 111
8
7Vr 6V
> Va > r 110
8 8
6Vr 5V
> Va > r 101
8 8
5Vr 4Vr
> Va > 100
8 8
4Vr 3V
> Va > r 011
8 8
3Vr 2V
> Va > r 010
8 8
2Vr V
> Va > r 001
8 8
Vr
> Va 000
8
SAR Type (Successive Appropriation Register)
SOC EOC
Va S−1 CLK
+ CONTROL SAR
− CKT
VT
DAC (IV)
SOC: Start of conversion.

EOC: End of Conversion.
• Ring counter is used to set the base
• Control circuit is used to reset when (Va < Vr)
• In SAR Type ADC, ring counters will be present to successively set the base
• Control circuit is used to reset, previously set bit when (Va < Vr)
• In SAR Type ADC, n clock pulse required for n bit conversion = nTclock
156
Data Converters
• SAR type, conversion time is independent of Analog Input Voltage

• SAR is mostly used in digital circuits to provide interface with microprocessors
Dual Slope Integrating Type ADC
C
R
−
−Va
S −
−Vr +
COUNTER
+
CLK
CONTROL
CKT
• Vr slope is always greater than Va slope
T1 (n) T2 (N)
V0
• In a dual slope, a counter is used to count the clock pulse

• Initially counter is reset to zero and switch is connected to Va (analog voltage)
where the integrator is integrating analog voltage
• Output of the integrator will become negative voltage, due to this comparator
output becomes 1 and counter counts clock pulses
• After 2n pulses again counter output becomes zero
• At this time t1 control circuit connect switch S to −VR. During −VR integration
up to T2 the time output of the integrator is negative. Due to this counter again
continue clock pulses at time T2 the output of the integrator becomes positive and
comparator output becomes 0 due to this counter will stop
• Let N is count when counter stops then,
Va Vr
VO =−
RC
× T1 +
RC
( t − T1 ) At time t = T2, V0 = 0
−Va Vr
∴
= 0
RC
. T1 +
RC
(T 2
− T1 ) ⇒ Va=
T1 Vr ( T2 − T1 )
157
Data Converters
Va .2n.TCLK = Vr (NTCLK )
Va 2n Vr
=N = or Va .N
Vr 2n
If Vr = 2n then Va = N
• This is the most accurate ADC among all
• All ripple and noise is separated or compressed by a capacitor. (Therefore this has
more accuracy due to the integrator)
• Maximum number of clock pulse = 2n + 2n − 1 ≈ 2n + 2n = 2n + 1
• Conversion Times for N bit ADCs
Type of ADC Conversion Time (Clock Cycles)
Counter Type 2N
Successive Approximation Type N
Dual Slope Integration Type 2 (N + 1)
Flash Type 1
Application
Mostly used in digital voltmeter.
Specification of A/D Converter

Input Voltage Range
For ADC generally input voltage range is 0 to 10 V or} 5 V or} 10 V, and so on depending on
the type of ADC.
Input Impedance:
It is generally in the range of 1 KΩ to 1 MΩ and input capacitance is few tens of PicoFarad.
Conversion Time
For a moderately fast ADC the conversion time is 50 μ sec and for a fast ADC the
conversion time is 50 n sec.
Format of ADC
An ADC can be unipolar, bipolar, or 1’s complement or 2’scomplement.
Accuracy
Accuracy of ADC depends upon the quantization error and error due to any external noise
and all other sources of error affect the accuracy of ADC.
158
Data Converters
Solved examples
Problem:
A 10 - bit successive approximation ADC has a resolution of 10 mV. Determine digital
output for analog input of 4.365 V.
Solution:
4.365
Digital output = = 436.510 ≈ 43610
10 mV
Problem:
For a dual slope type ADC, frequency of Clock is 1 MHz, Vreference = −10. Fixed time period T1
is 1 ms, RC time constant is set to 2 ms and Input voltage, Vi = 5V. Value of Ramp voltage
Vs is ___________________V
Solution:
t fix 1
Vs =
− Vin =
−5 =− 2.5V
RC 2
159
Data Converters
160
IC Logic Families
Chapter 6 – IC Logic Families

Objective
Upon completion of this chapter, you will be able to:
• Understand the terminologies associated with IC technology
• Design and compare the performance of logic gates using different logic families
Introduction
Digital logic has advanced rapidly from Small Scale Integration (SSI) with 12 gates per
chip to Very Large Scale Integration (VLSI) with tens of thousands of gates per chip. ICs
pack a lot more circuitry in a small package as compared to discrete components and
this results in smaller size of the circuit. ICs differ in the components that they use in
their circuitry like TTL family uses BJT and CMOS logic family uses MOSFET.
Classification of Logic Family
Classification of
logic families
Bipolar logic family Unipolar logic family
PMOS
Saturated Un-saturated
logic family logic family NMOS
RTL Schottky CMOS

TTL
DTL
ECL
DCTL
I2L
TTL
HTL
161
IC Logic Families
Characteristics of Logic Family
Propagation Delay (TPD)

• It is measured in n sec
tPHL + tPLH
tpd =
2
• tPHL is the propagation delay when output goes from HIGH to LOW and is the
propagation delay when output goes from LOW to HIGH.
A Y
tpd tpd
OFF-ON ON-OFF
• Propagation delay is always measured from 50% value of the input and output
waveforms.
• In Transistors, ON to OFF time is more compared to OFF to ON time due to
saturation or storage time.
In general tpdHL ≠ tpdLH.
If tpdHL = tpdLH the propagation delay can be either of the two tpdLH or tpdHL.
If tpdHL ≠ tpdLH, then propagation delay (tpd) = tpdHL if tpdHL > tpdLH = tpdLH
if tpdLH > tpdHL
Power Dissipation
Power dissipation by each logic gate Pdiss = VCC × mW
Where Vcc is the collector voltage or supply voltage and Iavg is the average supply current.
Figure of Merit (FOM)

• FOM = Pdiss × td joule
• I2L has the best FOM
• The desirable condition is the low value of FOM.
162
IC Logic Families
Fan Out
Fan-out also known as the loading factor of a logic gate is defined as the number of
loads that the output of a gate can drive.
• It is the maximum number of logic gates that can be driven by a logic gate
IOH
fan outH = IIH
IIH
IOH
IIL
IIH
IOL
IIL
IOL
fanoutL =
IIL
• Maximum fan out is min value of fanoutH, fanoutL

• TTL has max fans out
• IOH is the output current of a gate when output of gate is high and IOL is the
output current of gate in low state
• IIH is the output current of a gate when output of gate is high and IIL is the output
current of gate in low state
Fan In
Fan-in is defined as the number of independent inputs that the gate is designed to
handle without hampering its normal operation.
For Example:
A three input NAND gate has got a fan-in of 3.
A 13 input NAND gate has got a fan-in of 13.
Noise Margin
• It is the maximum noise voltage that can be added to the logic family which will
not affect the output
VIL ← 0 0 → VIL
VIH ← 0 0 → VOH
• VOH > VIH > VIL > VOL
• NMH = VOH − VIH and NML = VIL − VOL
• Overall noise margin = (NMH, NML)min
163
IC Logic Families
Solved Examples
Problem:
If VOH = 400 µA, IIH = 40 µA, IOL = −16 mA, IIL = 1.6 mA Find a fanout?
Solution:
400 16
fanoutH = = 10 fanoutL = = − 1.0
40 1.6
Maximum fan out (10, 10)min = 10
Construction of Gates
AND Gate
VCC
A B DA DB Y
0 0 ON ON 0
0 1 ON OFF 0
DA
1 0 OFF ON 0
A Y
1 1 OFF OFF 1
DB
B
OR Gate
A B DA DB Y DA
0 0 OFF OFF 0 A
0 1 OFF ON 1
DB V0 = A + B
1 0 ON OFF 1
B
1 1 ON ON 1
NOT
If A = 0, Tr is cutoff, Y = 1.
If A = 1, Tr is Sat., Y = 0. VCC VCC
Y Y
Y VCC
A A
164
IC Logic Families
NAND
VCC
A B Y VCC
0 0 1
0 1 1 Y
1 0 1
A T1
1 1 0 Y
A
B T2
B
NOR
A B Y VCC
0 0 1
VCC
0 1 0
Y
1 0 0

1 1 0 Y
T1 T2
A B A B
Solved Examples
Problem:
VCC
VCC V0
165
IC Logic Families
Solution:
V0 = AB + CD
Note:
• When the logic gate input is 0 (Transistor OFF) it will act as a current source
• When logic gate input is 1 (Transistor ON) it will act as a current sink
VCC
Source
O/1 OFF/ON
Sin k
• In the cutoff and saturation, region transistor will act as switch.
JE JC Region
RB RB cutoff
RB FB Reverse active
FB RB Active
FB FB Saturation
RTL (Register Transistor Logic) Family
VCC
A
B
Wired AND
AB . CD
C
A B
D
• Basic gate: NOR gate.

• tpd = 50 ns; FOM = 500 pJ
166
IC Logic Families
• NM = 0.2V
• Fan-out = 3
• Wired AND used
Disadvantage
• Lower speed of operation
• Low noise margin
• Lowest fan out
DCIL (Direct Coupled Transistor Logic) Family

• In the RTL logic family, if input resistance is removed then resultant is DCIL
• tpd = 40 nsec
VCC
A B T1 T2 Y
0 0 OFF OFF 1

0 1 OFF ON 0 VCC
1 0 ON OFF 0
1 1 ON OFF 0
T1 T2
A + B +
0.65 V— 0.7 V
—
Disadvantage
Current Hogging: In DCIL logic, if the switches used have different characteristics then
the transistor having lower VBESAT will be first ON and it will not allow other transistors to
turn ON, this phenomenon is known as current hogging.
Integrated Injection Logic I2L

VCC
when when B
A=0 A
A=1
167
IC Logic Families
• It is injecting current into base

• When A is high the current flows through the base of Transistor. i.e., Transistor must
be ON
• I2L covers less space. i.e., I2L has high density
• It is equivalent to NOT gate
VCC
R
= R
PNP
• There is no problem with current hogging.

• FOM = 0.1PJ − 0.7PJ
• Best FOM among all the logic families.
• tpd = 40 ns
• Fan out = 8.
SSI - 1 - 12 

MSI- B - 99  no. of gates used
• 
LSI - 100 - 1000 in this integration.
VISI- > 1000 
R = 2K R = 2K
DA D1 D2
A T1
DB
20K
B
168
IC Logic Families
• In I2L logic, due to integration of PNP and NPN transistor. It occupies less area
hence density is more in I2L logic. It is mostly used in MSI and LSI logic families
• Also called MTL (merged logic family) due to integration of transistors
DTL (Diode Transistor Logic) Family
AND Gate Followed by NOT Gate
A B T1 Y
0 0 OFF 1

0 1 OFF 1
R = 2K R = 2K
1 0 OFF 1
1 1 ON 0
DA D1 D2
A T1
DB
20K
B
• 20k resistors are used only for discharging the transition capacitance. The
capacitance which is discharge is transition capacitance CC .
• The circuit is called Basic DTL gate
• In this any one of the inputs is low or all the inputs are low, DA or DB will become
forward biased whereas D1 and D2 will become reverse biased due to Transistor T1 is
OFF and output is 1.
• When all the inputs are high then DA and DB become reverse biased and D1 and D2
will become forward biased and T1 is ON and output is low.
NAND Gate
• To increase fan out we introduce Transistor in place of diode
• It provides wired AND operation VCC
• 5K resistor used to lower the I1 current

• tpd = 30 ns 1.6K 2K
• Pdiss = 8 mw
2.1K
• FOM = 240 PJ
A T
• NM = 0.75 V
• Fan out = 3 5 KΩ
B I1
169
IC Logic Families
High Threshold Logic (HTL) Family

It is used in industry using motors, high voltage switching circuits to provide greater
noise margin. The power supply is increased from 5 to 15 V and resistances are increased
to make circuit in each branch equal.
• Zener diode is used in place of D2
• NM = 4 – 5V (Highest noise margin)
VCC = 15V
logic 0 = 2V 
•  Higher voltage swing
logic 1 = 12V 
3K 20K
• tpd = 90 ns
• Pdiss = 55 mw 12K Y
DA 6.9V
• FOM = 4950 PJ − 5000 PJ A
• Fan out = 8 DB 5K
• Basic gate = NAND gate B I1
Solved Examples
Problem:
Consider the DTL circuit shown in figure given below. The output Y of the given circuit is
VCC = 5V
1.6k Ω 2k Ω
Y
2k Ω Q1
A Q2
B D2
5k Ω
C
Solution:
When any of the inputs is low, Q1, D2 and Q2 are OFF and hence the output is HIGH and
when all inputs are HIGH, then Q1, D2 and Q2 conduct pulling the output logic LOW.
170
IC Logic Families
TTL (Transistor Transistor Logic) Family

T1 = Multi emitter transistor.
The circuit shown in fig. is standard TTL logic family. It basically has three stages.
(1) Multi-emitter I/P stage
(2) Phase splitter
(3) Totem pole or active pull up output stage
(Active = use for Transistor and Pull up = Transistor connect to VCC)
VCC
130
4K 1.6K
T4
D
A T1 T2 Y
B
T3
1K
Operation
• Any one of the inputs is low or all inputs are low, then the EB junction is Forward
Biased. (JE = FB) and collector base (JC = RE) is Reverse Biased. Transistor is in
active mode due to this transistor T2 and T3 are OFF (in cut-off region) whereas T4 is
in saturation. Hence, output is 1
• When all the inputs are high then JE (EB junction) of T1 is Reverse Biased. And JC (CB
junction) is Forward Biased. (The mode of operation is Reverse active). T2 and T3 are
in saturation and T4 is in cutoff. Hence output is zero
• VIH = 2V, VOH = 2.4V, VIL = 0.8, VOL = 0.4, tpd = 10 ns
• Pdiss = 10 mw
• Fanout = 10
• NM = 0.4V
• Diode D is used to cutoff Tr T4 when T3 is ON
Advantage of Totem Pole

• Lower power dissipation
• Higher speed of operation
• Higher fan out
171
IC Logic Families
Disadvantage of Totem Pole

• It is not used in wired logic
• To provide wired AND logic open collector configuration is used
• 130 Ω resistor used in collector in output stage to reduce ripple or noise generation
in the high frequency of operation
• In TTL if any input is open it behaves as logic 1
• Clamping diodes are connected in the input stage to protect the transistor during
high frequency of operation
• There are different type of TTL
(1) Standard TTL
(2) High speed TTL [IC name: 74HS00]
(3) Low speed TTL [IC name: 74LS00]
(4) Schottky TTL [IC name: 74S00]
High Speed TTL

• In standard TTL logic family if resistor value is reduced then tpd reduces and is
known as high speed logic family. tpd = 6 nsec
• Power dissipation increases.
Low Speed TTL

• In TTL logic family if resistor value is increased then power dissipation reduces and
resultant is known as low power logic family
Schottky TTL
• Schottky Diode is used between collector and base region then it removes storage
time and saturation delay. The family is known as Schottky TTL.
tpd = 6 nsec
SAT
active
T4
Cutoff
172
IC Logic Families
Advantages of Using Schottky Transistor in TTL

(1) Schottky diode is used to prevent transistor going into saturation
(2) Reduces the transistor switching time so that speed of operation increases
(3) Reduces the propagation delay from a few nano-seconds to approximately 1
nano-second
(4) Power delay product is not reduced due to low value of resistance used in TTL
(5) TTL with Schottky transistor is known as Schottky TTL
(6) IC numbers for Schottky TTL families are
• 74S00 → Schottky TTL
• 74LS00 → Low power Schottky TTL
• 74ALS00 → Advance low power Schottky TTL (it will never be driven into
saturation)
ECL (Emitter Coupled Logic) Family

• It never goes into the saturation region
• Work only in the cutoff and active region
• It is the fastest logic family due to work in the active and cutoff region. (Because it
is non-saturated)
300Ω A+B=Y 290Ω
A+B
Vrcj
A+B
A B = − 1.17V 1.5K
1.5K
Rc
−5.2V
• tpd = 1 nsec
• Fan out = 25
• It basically contains two stages.
(1) Differential amplifier input stage
(2) Common collector or emitter follower output stage
173
IC Logic Families
• Due to the use of differential amplifiers complementary outputs are available in the
ECL logic family. (NOR/OR) gate
• Due to use of a common collector stage in the output fan out is high
• ECL uses negative power supply. Due to this any spikes or negative voltage do not
affect operation
• tpd = 1 ns
• Pdiss = 55 mw
• FOM = 55 PJ
• Fan out = 25
logic 0 = − 1.7V 
• NM = 0.3 V  It is logic 1 mode only volatge supply is negative
logic 1 = − 0.85V 
• ECL provide wired and logic
(A + B) + (C + D)
C
• If any input is open then it is logic ‘0’
Solved Example: (These Questions Should be Added here as it is)

Problem:
In the circuit shown below Q1 has negligible collector to emitter saturation voltage and
the diode drops negligible voltage across it under forward bias. If Vcc is 5 volt, X and Y are
digital signals with 0 volt as logic-0 and Vcc as logic-1, then Boolean expression for Z?
Solution:
+Vcc
Given circuit is shown below,
R1
Z
R2
X Q1
Diode
174
IC Logic Families
Here, transistor (Q1) and diode (D) both can work as a switch and transistor (Q1) is
controlled by input (X) and diode (D) is controlled by input (Y).
Condition 1: When X = 0 and Y = 0.

Transistor Q1 is operated under cutoff mode, it means open circuited (OFF) and diode D
is in forward bias mode, it means short circuited (ON).
+Vcc
R1
Z = Vout = 0
(because of short circuit)
R2
S.C.
X=0
O.C
Y=0
Hence, X = 0 and Y = 0 → Z = 0.
Condition 2: When X = 0 and Y = 1.

Transistor Q1 is operated under cutoff mode, it means open circuited (OFF) and diode D
is in reverse bias mode, it means open circuited (OFF).
+Vcc
R1
Z = Vout = Vcc = 1
R2 (because of short circuit)

O.C.
X=0
O.C.
Y=1
Hence, X = 0 and Y = 1 → Z = 1.
175
IC Logic Families
Condition 3: When X = 1 and y = 0.

Transistor Q1 is operated under saturation mode, it means short circuited (ON) and diode
D is in forward bias mode, it means short circuited (ON).
+Vcc
R1
Z = Vout = 0

S.C.
X=1
S.C.
Y=0
Hence, X = 1 and Y = 0 → Z = 0
Condition 4: When X = 1 and Y = 1 .

Transistor Q1 is operated under saturation mode, it means short circuited (ON) and diode
D is in reverse bias mode, it means open circuited (OFF).
+Vcc
R1
Z = Vout = 0

S.C.
X=1
S.C.
Y=1
Hence, X = 1 and Y = 1 → Z = 0
176
IC Logic Families
Based on above four conditions we can form truth table as,
Input Transistor Diode Output

X Y Q D Z
0 0 OFF ON 0
0 1 OFF OFF 1
1 0 ON ON 0
1 1 ON OFF 0
K-map of function Z in SOP form is,
X
0 1
Y
0 0 0
1 1 0
XY
Thus, Z = XY
MOS (Metal Oxide Semiconductor)
D D
G G Substrate
S S
N–Channel MOS D
Logic ‘0’ = OFF
Logic ‘1’ = ON G
S
P–Channel MOS
D
Logic ‘0’ = ON
G
Logic ‘1’ = OFF S
177
IC Logic Families
Since FET is a voltage variable resistor hence in the MOS circuit in place of the resistor
we use MOSFET.
NMOS NOT Gate

VDD
A T2 Y
0 OFF 1 Vcc
1 ON 0 T1
A T2
A
NMOS NAND Gate
A B T2 T3 Y VDD
0 0 OFF OFF 1 VDD
0 1 OFF ON 1
1 0 ON OFF 1 T1
1 1 ON ON 0
Y Y
A T2
A
B Y
B T3
NMOS NOR Gate

tpd = 250 nsec VDD
VDD
tdiss = 1 mw
FOM = 250 PJ
Y
Fan out = 5
NM = 1.5V A B
A B
178
IC Logic Families
PMOS NOT Gate
A B Y −VDD
0 0 1 −VDD
0 1 0
T1
1 0 0
Y
1 1 0 Y
tpd = 300 nsec A T2

A
Pdiss = 0.2 mw
Y
B
FOM = 60 PJ
B T3
Strong input 1 Strong input 0

PMOS  NMOS 
Weak input 0 Weak input 1
VDD VDD
1 1
VDD VDD
Where, VT = threshold voltage
CMOS NOT Gate
A T1 T2 Y
0 ON OFF 1
1 OFF ON 0 VDD
VDD
T1
T1
A Y
Y
T2
T2
179
IC Logic Families
Transfer Characteristics
V0 V0 V0
VDD CMOS VDD − VT NMOS VDD PMOS
V1 V1 V1
Lowest Power Dissipation

Pdiss = 0.01 mw
tpd = 70 nsec
FOM = 0.7 PJ
Fan out = 50
VDO
NM =
2
Power Dissipation
Static Power dissipation: During logic ‘0’ or logic ‘1’.
2
Dynamic Power dissipation: During transition from 0 → 1 or → 0, PD = cf VDO
A B T1 T2 T3 T4 Y VDD
0 0 ON ON OFF OFF 1
0 1 ON OFF OFF ON 1
1 0 OFF ON ON OFF 1
A T1 B T2
1 1 OFF OFF ON ON 0
A T3
B T4
Advantages of CMOS
(1) Extremely low power dissipation is even smaller than MOS logic
(2) The propagation delay is quite small as output impedance is small
180
IC Logic Families
Disadvantages of CMOS
(1) Difficult to fabricate on IC
(2) Low packing density (so they are not recommended for LSI or VLSI circuits)
Solved Examples
Problem:
The expression for output “Y” for the circuit given below is
+Vdd
A
B
B C
Solution: Y = A (B + C) = A + (B + C) = A + BC = A + BC
Problem:
The expression for output “Y” for the circuit given below is
VSS
P1
P2
A PMOS
PMOS
B N2
NMOS
N1
NMOS
181
IC Logic Families
Solution:
Given circuit can be re-draw as,
VSS
A P1 P2 PMOS
B N2
NMOS
A N1
(Where A and B are input and Y is output)

P1 and P2 are PMOS transistors which will be ON/short circuited for A = 0 and B = 0 respectively.
P1 and P2 are PMOS transistors which will be OFF/open circuited for A = 1 and B = 1 respectively.
N1 and N2 are NMOS transistors which will be ON/short circuited for A = 1 and B = 1 respectively.
N1 and N2 are NMOS transistors which will be OFF/open circuited for A = 0 and B = 0 respectively.
Above circuit shows a standard NAND gate representation of CMOS logic family, so that
output Y becomes,
Y= A ⋅ B
We can also make the truth table of above circuit, based on functionality of NMOS and
PMOS as,
Input PMOS NMOS Output
A B P1 P2 N1 N2 Y
0 0 ON ON OFF OFF 1
0 1 ON OFF OFF ON 1
1 0 OFF ON ON OFF 1
1 1 OFF OFF ON ON 0
182
IC Logic Families
So, the reduced truth table as,
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
The above table satisfy the characteristic of 2-input NAND operation so that, above
circuit becomes,
A
Y=A.B
B
Problem:
The expression for output “V0” for the circuit given below is
5V
X
PMOS
Y
V0
NMOS
Solution:
Given logic circuit of CMOS logic 5V
family is shown below and circuit
can be re-draw as, X P1
PMOS
Y P2
V0
X N1 N2 Y
NMOS
183
IC Logic Families
(Where X and Y are input and C is output).

P1 and P2 are PMOS transistors which will be ON/short circuited for X = 0 and Y = 0 respectively.
P1 and P2 are PMOS transistors which will be OFF/open circuited for X = 1 and Y = 1 respectively.
N1 and N2 are NMOS transistors which will be ON/short circuited for X = 1 and Y = 1 respectively.
N1 and N2 are NMOS transistors which will be OFF/open circuited for X = 0 and Y = 0 respectively.
Above circuit shows a standard NOR gate representation of CMOS logic family, so that
output C becomes,
C= X + Y
We can also make the truth table of above circuit, based on functionality of NMOS and
PMOS as,
Input PMOS NMOS Output
X Y P1 P2 N1 N2 Y
0 0 ON ON OFF OFF 1
0 1 ON OFF OFF ON 0
1 0 OFF ON ON OFF 0
1 1 OFF OFF ON ON 0
So, the reduced truth table as,
Input Output
X Y V0
0 0 1
0 1 0
1 0 0
1 1 0
Now, the K-map for output V0 is,
V0
Y
X 0 1
0 1 0
1 0 0
Thus the Boolean logic realized by the circuit is NOR gate.
184
IC Logic Families
Comparison of Logic Families
Power
Logic Propagation Noise
dissipation an-in Fan-out Cost
family delay (ns) margin (V)
(mW)
TTL 9 10 0.4 8 10 Low
ECL 1 50 0.25 5 10 High
MOS 50 0.1 1.5 8 10 Low
CMOS < 50 0.01 5 10 50 Low
I2L 1 0.1 0.35 5 8 Very Low
185
IC Logic Families
186
Semiconductor Memories
Chapter 7
Objective
• Understand various types of memory used in digital systems
• Learn the basic function of RAM and ROM
• Learn memory management in digital systems
• Easily create the difference between various types of memories
Computer Memory
Memory is defined as the basic unit of a computer where data and instructions are
stored. It is organized into locations. Every memory location is called one memory
word. The number of bits present in each location is called word length of the memory.
It is generally multiplied by 8 bits. The capacity of the memory is defined as the total
numbered location in the memory. The capacity is the product of memory locations and
word length of the memory every memory has specific address. The memory is used to
store information such as instructions, data, intermediate, and final results.
Classifications of Memory
A memory is classified according to its function, contents retention and data access
method. The performance of different memories is compared according to memory
speed, cost per bit, and power dissipation.
Types of memory
RAM ROM
SRAM DRAM PROM EPROM EEPROM
Classification of computer memory
Semiconductor memories are semiconductor devices in which the basic storage cells are
transistor circuits.
They are of two types:
(i) Random access memories (ii) Sequential access memories
187
The random access memories are of two types:

(a) Read Only Memory (ROM)
(b) Read and Write Memory (RAM)
The Rom is Again Classified into Several Types
Programmable ROM
Unlike ROM, it can be programmed by the user only once in its lifetime (by using a
special circuit known as PROM programmer).
Erasable Programmable ROM

Erasable Programmable ROM (EPROM) is an application in which data may change from
time to time might call for the use of EPROM. The data can be programmed again if
desired.
Electrically Erasable ROM

Electrically Erasable ROM (EEROM or Electrically Alterable ROM) is an application in
which a portion of data may change from time to time might call for the use of an
EEROM. It can be erased and programmed 10,000 times (both erasing and programming
take about 4 to 10 ms. In EEROM, any location can be selectively erased and
programmed).
Magnetic Based Memory

Magnetic based memories are of two types:
(i) Magnetic tape
(ii) Magnetic disk
Optical Medium Based Memories

Optical medium based memories are also of two types:
(i) Read type
(ii) Read/write type
They are similar to magnetic disks.
Note: The bit storage density is the highest for optical type memories and the
lowest for the semiconductor memories. There is nearly an order of magnitude
difference between the semiconductor and magnetic or the magnetic and
optical storage densities. However, semiconductor memories have the following
specialties for which they are used as the main memory and the others as the
secondary or auxiliary memories:
188
(i) (i) Small size

(ii) (ii) Low cost
(iii) (iii) High reliability
(iv) (iv) Ease of expansion of memory size
(v) (v) Electrical compatibility with the microprocessor
Memory Devices
In most of the digital system, the memory device is one of the most important
components. Especially for a microprocessor-based digital system, memory devices are a
must. Bus refers to the hardware lines through which mainly digital signals flow. Address
lines are unidirectional. Data lines are bidirectional and can both accept and leave data.
The I/O controls the input/output data. Therefore a memory device is a device in which
binary information can be stored. It comes in a variety of organizations: capacity (kilobyte
or megabyte) and speed (lower and higher speed).
System Memory and Standard Memory Devices

For RAM, the read access time or write access time for any memory location is constant.
Read/write (R/W) memory is a PM in which we can read from any memory location or
also in which we can write onto any memory location (store and read information).
A ROM is a memory device in which we can only read the contents of any memory
locations but cannot write onto any memory location. The difference between R/W and
ROM memories is that R/W memory is generally volatile memory unless it is battery
backed up, but a ROM is always nonvolatile.
Advantages of System Memory Device

(1) Its decoding circuit is on chip and no external decoding circuits are needed for
memory decoding
(2) Besides memory it also contains various I/O ports and timer/counters
(3) Data sheets are provided by the manufacturer of system memory devices with 8085 μp
Disadvantages of System Memory Devices

(1) It is not available from a variety of sources
(2) It is quite expensive
(3) It is not available in a variety of sizes, organizations and speed
Different Semiconductor Memories

Semiconductor memories are of the following types:
(1) Static bipolar RAM (R/W memory)
(2) Static MOS RAM (R/W memory)
189
(3) Dynamic MOS RAM (DMRAM or DRAM) (it is also R/W memory) It is just a flip-flop
with cross coupled transistors. Static bipolar RAM
Advantages and Disadvantages of Bipolar Static R/W Memory

In dynamic RAM, the information is stored at the capacitor according to charging and
discharging.
Advantage
The main advantage of bipolar static R/W memory is that it is of high speed.
Disadvantages
(1) It has very low packing density (Few numbers of bipolar RAM can be
accommodated in a small area), that is, the space required to fabricate a transistor
is quite large
(2) It consumes more power (as it requires high supply voltage and its input
impedance is not large) and it requires large voltage compared to MOS RAM
Advantages of Static MOS RAM

(1) It has very high packing density, that is, space required to fabricate a MOS
transistor is very small (as it requires high input impedance with high insulation at
input)
(2) It consumes less power
(3) It is quite inexpensive
(4) It can be operated with smaller voltage
(5) With the advent of improved IC technology, the speed of static MOS RAM is even
greater than static bipolar RAM
(6) MOS RAM chips have on-chip decoding circuits for which no external decoding
circuits are needed. If the decoding circuits are external then the speed of static
MOS RAM can be further increased. In MOS technology we can have NMOS and
PMOS technology. NMOSRAM has higher speed than PMOS RAM as the mobility
of electrons is higher than that of holes. Mobility is defined as the drift velocity
per unit applied electric field (E). As the E of the electron is less than hole so the
mobility μ is more
190
Dynamic MOS RAM

It is widely used as the primary or main memory of all recent microcomputer system
Advantages of DRAM
(1) Its packing density is very large, even larger than static MOS RAM. To store 1
bit, it requires only one transistor, whereas in static MOS RAM it requires four
transistors. 10 bits MOS static RAM requires 40 transistors whereas 10 bit dynamic
MOS RAM needs 10 transistors and 10 capacitors
(2) It requires little standby power
(3) It is quite cheaper
Disadvantages of DRAM
(1) It requires an external memory refresh controller circuit for periodic refreshing of
each DRAM cell
(2) It is slower than static MOS RAM. (Due to the capacitor discharging or charging
time) In a microcomputer system if the memory requirement is larger than DRAM
is always used and for memory requirement is lower we can use static MOS RAM
Different Types of ROM Read Only Memory

The read only memory (ROM) is a nonvolatile memory which is prepared by the
manufacturer according to the users specifications. A special mask is used so that its
contents can be permanently stored. It is quite expensive due to specially prepared
masks and also relatively faster. It cannot be programmed, that is, its content cannot be
changed. They have small access times (35–1200) ns.
Programmable Read Only Memory

The programmable read only memory (PROM) is also a nonvolatile memory. It can be
programmed only once by using a PROM programmer. It is less expensive compared to
ROM and also less slower than ROM. Once programmed its contents cannot be changed.
Example for one such device PROM is 74288 (25 × 8 bits PROM)
Erasable Programmable Read Only Memory

The erasable programmable read only memory (EPROM) can be erased as many times
as required by exposing its optical window to UV light for 20 to 30 min. It can be
programmed as many times as we want after erasing it.
Disadvantages of EPROM
(1) Selective on board erasing memory location is not possible
(2) Selective on board programming cannot be done, that is, programming should be
sequential. Programming pins for EPROM are large compared to RAM memory
191
Advantages of EPROM
(1) Available from a variety of sources and with various organization speed and
capacity
(2) Erasing time is quite large = 20 to 30 min
(3) It is not so expensive
Electrically Alterable PROM (EEPROM/EAPROM)

EEPROM stands for Electrically Erasable Programmable Read-only memory and it is
also called EAPROM. This type of memory is non-volatile in nature, which stores small
amounts of data.
Advantages of EAPROM
In this case we can selectively erase a particular location on board. Similarly, we can
perform selectively on board programming and selective on board erasing requires a
threshold voltage of 5 to 8 V. Erasing time is 5 to 10 ms and programming time is 250 μs
to 1 ms for a particular location.
Disadvantages of EAPROM
(2) It is not available from a variety of sources
(3) It is not popular as this technology is still not matured
Applications of ROM
(1) ROM can be used to realize in particular combination or sequential logic design
(2) ROM can be used to store the microinstructions of a control unit in a micro
programmed control system
(3) ROM is used for code conversion
(4) ROM is used for storing the lookup tables (as in calculator)
(5) It can be used to store the readymade subroutines or subroutine monitors programs
(6) ROM can be used in the character generator to store information of each character
to be generated on the CRT screen. This is called a character generator
(7) It can be used for effective emulation of other machines by microprocessors using
the firmware approach with ROM
(8) The ROM can be used to store data. The OS is to protect it from computer viruses
192
Difference between SRAM and DRAM
Sr.No. Parameter SRAM DRAM

1 Circuit configuration Each SRM cell is a flip Each DRAM unit consists
flop. of one MOSFET and a
capacitor
2 Number of components More Less (Only two)
per cell
3 Memory cell unit area Less then DRAM More then SRAM
4 Refreshing Not required Required
5 Cost More Less
6 Access Less. So there are faster More. So there are slower

memories memories
7 Power consumption Less More
193
194
Microprocessors
Chapter 8 – Microprocessors
Objective
• Understand various registers present in 8085 microprocessor
• Learn the instruction set of 8085 μp
• Write the program in Assembly Language 8085 μp
• Determine the output of the assembly language program
Introduction
Microprocessors are regarded as one of the most important devices in our everyday
machines called computers. It is an electronic circuit that functions as the central
processing unit (CPU) of a computer, providing computational control. It is also used in
other advanced electronic systems, such as computer systems printers, automobiles.
Microprocessors incorporate arithmetic and logic functional units as well as the
associate control logic, instruction processing circuitry and a portion of the memory
hierarchy. It is a semiconductor component designed by using VLSI technology and
includes ALU, CU (control unit), and resistor of the CPU in a single package.
Computer
CPU (MP)
ALU
I/P O/P
CU
Devices Devices
Resgister
Memory
A microprocessor is a multi-purpose, Programmable clock driven register and ALU

(arithmetic and logic unit) based electronic device. It reads binary instruction from a
storage device called memory, accepts binary data as an Input and processes data
according to instruction read, and provides results as an output. Microprocessor is
just like a human brain. The brain gets input from ears and eyes and sends processed
information to output devices such as hands, legs or faces with specific expressions.
195
Microprocessors
• Memory is outside the CPU i.e., memory is not a part of CPU

• Resistor present inside the CPU is not used as memory
Note:
• For a microprocessor, memory is connected externally.
• Busicom (Japan) is the first company who designed the calculator by using discrete
ALU, CU and memory
• After Busicom, Intel designed microprocessors in a single package.
• 1st microprocessor, 1971 → Intel 4004 → 4-bit.
• Bit → Binary digit (0 or 1).
• Nibble → 4-bit.
• Byte → 8-bits.
• Word length → Depends on type of processor.
Micro-Controller
ALU
Timer/
CU Memory
Counter
Resgister
Interfacing
Circuits
Microprocessor Microcontroller
• It contain ALU, CU and Resistors • It contain ALU,CU and Resistors
• No internal memory • Contain internal memory
• Containing interfacing circuits, Timer /

• No interfacing circuits, Timer/Counter
Counters
• Used for general purpose • Used for specific purpose
Application Application
E.g.: Intel 8085, 8086, M6800, Z80, i3, i7 E.g.: Intel 8051, 8031, PIC-8 bit/ 16 bit,
196
Microprocessors
• Program and data are stored in a memory and it is responsible to operate

microprocessors.
• Depending on the program and data storage technique, two technique are used:
(1) Von-Neumann Architecture (Princeton Architecture)
Harvard Architecture
Non-Neumann Architecture Harvard Architecture
Memory Memory Memory
Program
& Program Data
Data
• Program & data both are present in • Program and data are separately
same memory present in different memory
• E.g.: Intel 8085, Intel 8086 (MP) • E.g.: Intel 8051 (MC)
Basic Operations of the Processor

Opcode fetch (Instruction is opcode (operational code)
(1) Memory read
(2) Memory write
(3) I/O read
(4) I/O write
• The above 5-operations are called ‘Machine cycle’ or ‘Time of processing’.
I/O
MP Memory
Devices
Note: In the above figure, since only one memory block is present, it shows
program and data both are stored in the same memory, so it is von-neumann
architecture.
Opcode fetch
Reading the opcode byte and decodes, is known as opcode fetch [OPF]
197
Microprocessors
Instruction Fetch
Opcode fetch followed by operand read operation is known as instruction fetch.
IF = OPF + memory Read
And if followed by execution is known as processing
P = IF + E
Memory Read
Reading or accessing the data (stored in memory) from memory
Memory write
Sending or transferring data to memory
I/O Read
Accessing data from input port or device
I/O write
Transferring data to output port or device
System Bus
Typical system uses a number of busses, a collection of wires, which transmit binary
numbers, one bit per wire. A typical microprocessor communicates with memory and
other devices (input and output) using three busses: Address Bus, Data Bus and Control
Bus.
Address Bus
It is used to transfer the address of either memory or I/O device from the processor. It
is unidirectional (from microprocessor to memory I/O device). It defines the maximum
memory that can be connected to a processor given by the relation,
2n = N
Where n → number of address line
N → number of address or memory location.
The Address Bus consists of 16 wires for 8085 microprocessors, therefore 16 bits. Its
"width" is 16 bits. A 16 bit binary number allows 216 different numbers, or 32000 different
numbers, i.e., 0000000000000000 up to 1111111111111111. Because memory consists of
boxes, each with a unique address, the size of the address bus determines the size of
memory, which can be used. To communicate with memory the microprocessor sends an
address on the address bus, Ex. 0000000000000011 (3 in decimal), to the memory. The
memory then selects box number 3 for reading or writing data.
198
Microprocessors
Address bus System Bus
A computer bus that is used to specify a A computer bus that is used to transmit
physical address in the memory. data among components
Unidirectional Bidirectional
Helps to transfer memory addresses of Helps to send and receive data
data and IO
Width determines the amount of memory Width determines the data transferring
a system can address rate
Memory
Memory stores information such as instructions and data in binary format (0 or 1). It
provides this information to the microprocessor whenever it is needed.
• Memory is a collection of resistors.
• Resistors: Collection of flip-flops.
• If flip-flop is a memory unit or cell which can store a bit (0 or 1).
• Most of the memories are designed to hold 1 byte per location. Therefore memory
is represented in terms of bytes.
Memory Flip-Flop
Resister
00 R0 8 bits
R1 or
01
1-byte
10 R2
11
Rn
Relationship Between Address Line and Memory

2n = N
Where n → number of address line
N → number of address or memory location.
21 = 2 Byte
22 = 4 Byte
210 = 1 KiloByte (1 KB)
220 = MegaByte (1 MB)
199
Microprocessors
230 = 1 GigaByte (1 GB)

240 = 1 TeraByte (1 TB)
Solved Examples
Problem:
A processor has 33 address lines, calculate the maximum memory that can be connected
Solution: 233 = 23 × 230 = 8 (1GB) = 8GB
Problem:
A memory of 512 TB can be connected to the processor. Calculate the address line
required.
Solution: 2n = 512TB = 29 × 240 = 249 GigaByte (1 GB)

n = 49
Problem:
It is required to connect 100 MB to the processor. Calculate the minimum address lines.
Solution: 226 = 64MB < 100MB

227 = 128MB
Hence minimum address line =27
Problem:
The maximum memory that can be connected 8085 is?
Solution: address bus for 8085 microprocessor = 16
216 × 26 × 210
64 (1KB) → 64KB
64 × 1024 → 65,536 Bytes
Memory
Hence, 0 ← 0000H R0
1 ← 0001H R1
2 ← 0002H R2
64KB = 65,536 Bytes
Rn
65,536 ← FFFFH
200
Microprocessors
Note: Address of the memory locations are not stored in memory. It is stored in a
processor.
Data Bus
It is used to transfer data between processor, memory and I/O devices. Data bus is
bidirectional.
It is 8-bit in length for an 8085 microprocessor. Therefore, 28 combinations of binary
digits. Data bus used to transmit "data", i.e., information (results of arithmetic, etc)
between memory and the microprocessor. Size of the data bus determines what
arithmetic can be done. If only 8 bits wide, then the largest number is 11111111 (255 in
decimal). Therefore, larger numbers have to be broken down into chunks of 255. This
slows the microprocessor. Data Bus also carries instructions from memory to the
microprocessor. Size of the bus therefore limits the number of possible instructions to
256, each specified by a separate number.
There are no separate data lines or buses in 8085. The lower 8 address line can be used
both as address and data with the help of a control signal known as ALE (Address latch
enable)
1; All 16 lines → address bus


ALE 
0; A 15 − A 3 → address bus and AD7 − AD0 → Data bus
Address and Data Bus
A 15 − A 3
  AD7 − AD0

}
Higher order Lower order Multiplexed Address/Data bus
Address Bus Address Bus
Address
Data
WR RD RD WR
ALE A15 R0
0000H
A6 R1
AD7 Latch 1 0 0 1 0 0 1 1 R2
0003H
MP AD0
R
0003
Rn
Memory
201
Microprocessors
Control Bus
It is a group of different control signals required for various operations of the processor.
Control bus is partially uni-directional and partially bi-directional.
Control Busses are various lines which have specific functions for coordinating and
controlling microprocessor operations. E.g., read/not write line, single binary digit.
Control whether memory is being ‘written to’ (data stored in memory) or ‘read from’ (data
taken out of memory). May also include clock line(s) for timing/synchronizing, ‘interrupts’,
‘reset’ etc. Typically microprocessors have 10 control lines. Microprocessor cannot
function correctly without these vital control signals.
Note: If partially uni-directional and partially bi-directional is not given in the

options then prefer uni-directional.
Internal Architecture
Internal architecture is divided into five functional units:
• ALU(arithmetic logic unit)
• Resistor unit
• Timing and control unit
• Interrupt control unit
• Serial I/O control unit.
RST RST RST

INTR 5.5 6.5 7.5 TRAP SOD SID
INTR
Interrupt Control Serial I/O control
Internal Data Bus
Accumulator Temporary Instruction

Flags (5) W (8) Z (8)
(8) Reg. (8) Reg. (8)
B (8) C (8)
D (8) E (8)
Instruction
Decoder H (8) L (8)
ALU and Stack pointer
Machine 16
cycle Program counter
Encoder 16
Increment/Decrement
Address Latch
Crystal oscillator
X1 Timing & Control
Control Add.Buffer Add/Data
X2 Status DNA
Ready ALE RD WR IO/M S1 S0 Hold HLDA Reset in Reset out Clock out A15 − A8 AD7 − AD0
202
Microprocessors
Arithmetic Logic Unit (ALU)

The ALU performs the actual numerical and logic operation such as ‘add’, ‘subtract’,
‘AND’, ‘OR’, etc. It uses data from memory and accumulators to perform operations. It
is a combination of accumulator, temporary register, flag register and arithmetic & logic
circuit. The arithmetic unit performs bitwise fundamental arithmetic operations such as
addition and subtraction. The ALU also looks after the branching decisions.
Always stores the result of operation in the accumulator.
Register
The 8085 microprocessor includes six registers, one accumulator, and one flag register,
as shown in Figure. In addition, it has two 16-bit registers: the stack pointer and the
program counter.
There are two types of register.
(a) General purpose resistor
(b) Special purpose resistor
General Purpose Resistor

• There are 6-eight bit general purpose resistor these are B, C, D, E, H, L
• There are three 16-bit general purpose resistor these are BC, DE, HL (Resistor pair)
• Any of the resistor pairs can be used to point the memory. But HL pairs are known
as defined memory pointers.
Eg.: MOV C, M
Here ‘M’ indicates a memory contained or resistor whose address is present in an HL pair
only.
Special Purpose Resistor

Accumulator (A)
The accumulator is an 8-bit register that is a part of an arithmetic/logic unit (ALU). This
register is used to store 8-bit data and to perform arithmetic and logical operations. The
result of an operation is stored in the accumulator. The accumulator is also identified as
register A.
Program counter (PC)

It is a 16-bit register which deals with sequencing the execution of instructions. This
register is a memory pointer. Memory locations have 16-bit addresses, and that is why
this is a 16-bit register.
The function of the program counter is to point to the memory address from which
the next byte is to be fetched or the program counter contains the address of the next
instruction to be executed. When a byte (machine code) is being fetched, the program
counter is incremented by one to point to the next memory location.
203
Microprocessors
E.g.: MOV A, B
Op-Code Fetch
MP
Memory
8000H
XX
8001H
44
IR
XX
PC
8000
8001
Instruction Register (IR)

It is an 8-bit register which temporarily stores the current instruction of a program.
Latest instruction sent here from memory prior to execution. Decoder then takes
instruction and ‘decodes’ or interprets the instruction. Decoded instruction then
passed to the next stage. CPU storage this opcode in a register called the instruction
register. This opcode is further sent to the instruction decoder to select one of the 256
alternatives.
Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory pointer. It points to a
memory location in R/W memory, called the stack. The beginning of the stack is defined
by loading a 16-bit address in the stack pointer.
Stack: It is a part of R/W memory which is used to store temporary data and also the
content of a PC when subroutines are executed. The technique involved in stack is LIFO
(Last in first out).
Note:
• When data is stored or pushed into stack memory, stack pointer is decremented.
• When data is accessed from the memory stack, the pointer is incremented.
• A single register data cannot be stored in stack memory.
204
Microprocessors
Example: Describe the output of following code using graphical representation if stacks
pointer points to F008H
LXI D, 5566 H
PUSH D
MP Memory
0000H
LIFO
SP-2 = F006H 66
SP-1 = F007H 55
SP
w w = write
F008 SP = F008H 44
F007
F009H 33 D E
F006
. . 55 66
. .
. .
FFFFH
Flag Register
It is an 8-bit register. There are 5 flags which are set or reset after an operation
according to data conditions of the result in the accumulator and other registers. They
are called Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The most
commonly used flags are Zero, Carry, and Sign. The microprocessor uses these flags to
test data conditions.
As the result is stored in the accumulator, for most of the ALU operations flags are
affected by the content of the accumulator except for a few instructions.
Example: Increment & decrement
Note: Flags are affected or modified only for operations.
Sign Flag
After execution of any arithmetic and logical operation, if D7 of the result is 1, the sign
flag is set. Otherwise it is reset. D7 is reserved for indicating the sign; the remainder is
the magnitude of the number. If D7 is 1, the number will be viewed as a negative number.
If D7 is 0, the number will be viewed as a positive number.
Zero Flag
If the result of arithmetic and logical operation is zero, then zero flag is set otherwise
it is reset. It may also be affected for other general purpose registers in the same
instruction.
205
Microprocessors
E.g.: if A = [00H], then Z = 1
Auxiliary Flag
If D3 generates any carry when doing any arithmetic and logical operation, this flag is set.
Otherwise it is reset.
Parity Flag
If the result of arithmetic and logical operation contains an even number of 1's then this
flag will be set and if it is an odd number of 1's it will be reset.
Carry Flag
If any arithmetic and logical operation result in any carry the carry flag is set otherwise it
is reset.
D7 D6 D5 D4 D3 D2 D1 D0
S Z X AC X P X CY
These flags have critical importance in the decision-making process of the

microprocessor. The conditions (set or reset) of the flags are tested through the software
instructions. For example, the instruction JC (Jump on Carry) is implemented to change
the sequence of a program when the CY flag is set. The thorough understanding of flags
is essential in writing assembly language programs.
PSW (Program Status Word)

PSW is a combination of accumulator and flag registers. It is a 16 bit hardware register
that maintains the status of the program being executed. It shows the current status of
ALU operation.
PSW register pair
Accumulator Flag register
Solved Examples
Problem:
A = 15H, B = BEH, then find A + B = ? and also find the flags.
Solution: D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 1 0 1 0 1
1 0 1 1 1 1 1 0
0 1 1 0 1 0 0 1 1
CY
206
Microprocessors
Flag registers 90H
S Z X AC X P X CY
1 0 0 1 0 0 0 0
9 0
A + B = E3H
Problem: Find flags for 87H + 79H
Solution:
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 1 1 1
0 1 1 1 1 0 0 1
1 0 0 0 0 0 0 0 0
CY
Flag registers 55H
S Z X AC X P X CY
0 1 0 1 0 1 0 1
5 5
Temporary register
W, Z are the two 8-bit registers which are not accessible by the user. They are used by
the processor in some instruction
Note: There are no separate instruction for multiplication and division in 8085
Instruction Decoder, Machine Cycle Decoder

After the op-code is fetched into the IR instruction register, it is decoded in this block
with the help of a machine program. The number of machine cycles or operations is
assigned according to type of instruction.
Micro-Programs
It is a program written by a manufacturer to make the processor understand what an
instruction is or it indicates the type of operations to be performed for an instruction.
207
Microprocessors
Example: MOV B, C
Timing and Control Unit

Generates signals within the microprocessor to carry out the instruction, which has been
decoded. In reality causes certain connections between blocks of the microprocessor to
be opened or closed, so that data goes where it is required, and so that ALU operations
occur.
X1 & X2
• A crystal oscillator is connected between X1 & X2 pin to produce the necessary and
suitable clock frequency for the processor.
• A crystal is used as it produces stable oscillation compare to RC and LC oscillator.
• An internal clock generator takes the reference frequency and produces operating
frequency which is half of reference frequency and also other frequencies which
are required internally.
fcrystal
Operating frequency = fclock =
2
Operating frequency of 8085 is, fdk = 3MKZ and range is (3 to 6) MHZ
Important Control Signals

• ALE (Address Latch Enable)
It occurs during the first clock cycle of a machine state and enables the address to get
latched into the on chip latch of peripherals.
1; All 16 lines → address bus


=
ALE 0; A 15 − A 3 → address bus
 AD − AD → Data bus
 7 0
• RD = Read control signal

0 → Active
1 → Inactive
• WR = Write control signal

0 → Active
1 → Inactive
• IO /M = Status signal which indicates either memory or input output operation.
0; memory operation

IO / M = 
1; IO operation
208
Microprocessors
IO / M RD WR Control Signal Operation
0 0 1 Memory Read M/M read
0 1 0 Memory Write M/M write
1 0 1 IO/ R IO read
1 1 0 IO/ W IO write
• S1, S0 = These give the status of bus cycle for an operation
S1 S0 Status
0 0 Halt
0 1 Memory write
1 0 Memory read
1 1 Opcode fetch
• HOLD
This indicates if any other device is requesting the use of address and data bus.
Then the microprocessor transfers the control to the requesting device as soon
as the current cycle is over. After the process of requesting the device is over, the
control is transferred back to the microprocessor.
• HLDA
HLDA is the acknowledgment signal for HOLD. It indicates whether the HOLD signal
is received or not. After the execution of a HOLD request, HLDA goes low.
Regular path Memory
5 DMA operation
2
MP HOLD DMA
Controller
HLDA
3
4 1
HOLD
I/O
Regular path
209
Microprocessors
When more or huge data is to be transferred between memory and I/O at a faster rate
DMA operation is used, with the help of DMA controller.
• Reset-in
Low active I/P signal to reset the processor and PC is initialize to 0000H
• Reset-out
Output signal which indicates that processor is reset. It can be used to reset IO
devices.
• Clock-out
• O/P pin on which the same operating frequency of the processor is available. It can
be used to connect to an IO device for synchronizing operation.
• Ready
I/P pin to processor from a slow speed IO device. If ready is high then only the
processor will either transmit data & receive data from IO devices.
• Interrupt Control Unit

Trap, RST 6.5, RST 7.5, RST 5.5, INTR,
• Serial IO control unit

It is used for serial communication between processor and IO devices. Serial
communication means bit by bit transmission.
• SID
I/P pin through which processor receives serial data.
• SOD
O/P pin by which processor transmits serial data.
Note: Both SID and SOD are internally connected to D7 of the accumulator.
MAR
Memory address register is used to hold the address before it is placed on the address
bus.
MDR
Memory data register is used to hold the data before it is transferred to memory or when
it is accessed from memory to processor.
210
Microprocessors
Functional Description
Classification of Signal
(i) Address bus (unidirectional)
(ii) Data bus (Bi-directional)
(iii) Control and status signal (partially uni/Bi-directional)
(iv) Interrupt and externally initiated
(v) Serial IO ports
(vi) Power supply and frequency signal
X1 X2 Vcc Gnd (vi)
SID A15− A8 (Higher order

(v) address bus) (i)
SOD
AD7 − AD0 (Multiplexed Data
TRAP address bus) (ii)
RST 7.5 ALE
RST 6.5 RD
8085
RST 5.5 WR
(iii)
INTR IO/M
(iv) Control and status
S1
signal
S0
Ready
Reset-Out
Hold HLDA
Reset-in INTA
Clock-Out
Interrupts of 8085
It is an internal or external signal which may disturb or alter the sequence of execution of
the process. Interrupt is an event that demands the CPU. In general any microprocessor
is set to be in the fetch execute cycle of the main program, i.e. in processing of the main
program. If occurrence of interrupt event is recognize by the microprocessor then it
perform the following steps (known as interrupts switching steps
Main program
211
Microprocessors
0000H: 1st Instruction
1H
0H 100
150 C) =
1500H
) ← (P
.P
I.S
(PC S) =
Occurance of
to
interrupt event
(TO
s
ter
en
1000H : Current Instruction
µP
1001H : Next Instruction µP
ret
ur ns
P.C 1001H (PC to
)← M.P
(TO RET
Next Address S)
=1
or 001
H
Return Addres
12FFH : HLT
TOS =Top of the stack

ISR = Interrupt service routine
Step-1:
Microprocessor completes execution of commonly fetched instructions.
Step-2:
Microprocessor saves next address or written address available in the program counter
by pushing it into top of the stack & then program counter with vector address,
i.e., starting address of I.S.R
Step-3:
Microprocessor processes interrupt device routine, through fetch & execute cycle
Step-4:
At the end of I.S.R, when microprocessors execute RET interrupt. It retrieves contents of
TOS back into program counter & interrupt resumes main program processes
212
Microprocessors
Classification of Interrupts
Hardware Interrupts
These interrupts are available in the form of input pins i.e., physically available.
• 8085 has 5 hardware interrupts or external interrupts.
or TRAP/RST 4.5 Highest Priority
RST 7.5
RST 6.5
RST 5.5
INTR Lowest Priority
Non vectored Interrupt
• TRAP is both edge and level triggered. It is edge triggered such that it may be
responded quickly. It is level triggered in order to differentiate the original signal
from practical application and error signal due to noise.
• The signal on the TRAP pin must be high for at least 3 clock periods such that the
error signal due to noise may be avoided.
Software Interrupts
These interrupts are available in the form of instruction.
• 8085 has 8 software interrupts
RST 0 

RST 1 

RST 2 

RST 3 

RST 4 

RST 5  Eight, 1 Byte instruction

RST 6  (Priorlly is not needed here)


RST 7  Because processor don't execute two instruction at a time
213
Microprocessors
Maskable Interrupts
These interrupts can be either enabled or disable by the program. If enabled then only
the interrupt event is recognized by the microprocessor. If disable then occurrence of
interrupt event will be ignored by microprocessor.
• EI(Enable interrupt) & DI(Disable interrupt & SIM(Set interrupt mask) instruction are
provided for masking
• 8085 has 12 maskable interrupts & only one non-mask able interrupts is TRAP/RST 4.5
• All 12 maskable interrupts can be globally enabled or disabled by using ‘EI’ or ‘DI’
Non-Maskable Interrupts
These interrupts cannot be disabled, i.e., always exist in enabled state. 8085
microprocessor has only 1 non mask-able interrupt (TRAP/RST4.5) which is used in
emergency conditions.
• EI, DI & SIM instruction doesn’t affect TRAP
Vectored Interrupts
For these interrupts, vector address, i.e., starting address of I.S.R is prefixed by the
manufactures. 8085 microprocessor has a 12 vectored interrupts and these are:
RST 0 to RST 7 and RST 4.5, RST 5.5, RST 6.5, RST 7.5
• Any interrupt of 8085 in RST is a vectored interrupt
• ‘RST X’ ↔ Corresponding vector address which is completed by the machine
12 Vectored interrupts Vector address

RST 0 -------------------------------- 0000H
RST 1 -------------------------------- 0008H
RST 2 -------------------------------- 0010H
RST 3 -------------------------------- 0018H
RST 4 -------------------------------- 0020H
RST4.5 ------------------------------- 0024H
RST5 --------------------------------- 0028H
RST5.5 ------------------------------- 002CH
RST6 -------------------------------- 0030H
RST6.5 ------------------------------- 0034H
RST 7 -------------------------------- 0038H
RST 7.5 ------------------------------ 003CH
214
Microprocessors
Non-Vectored Interrupt
For these interrupt vectored addresses are not prefixed by the designer. As such for
servicing such interrupt external, dedicated hardware is required, i.e., external hardware
supplies not only required interrupt requests but also required vector addresses.
• 8085 has only 1 non vectored interrupt (INTR) i.e., interrupt request.
• 8259 PIC is normally used for serving non vectored interrupt.
µP
8085µ 8259 IC
Step 2 Step 1
RST 4.5 INTR IR 0

:
:
RST 7.5
:
Step 3
INTA ::
IR 7
RST 6.5
Step 4
Vector Address
P.C
RST 5.5 Data Bus Address Register
External hardware that sup-

plies interrupt request & re-
quested vector address
• In order to use INTR, the programmer must select one of the software interrupt
addresses to store the ISR of the I/O device.
• INTA Generates the pulse only to recognize the INTR interrupt.
• INTR is pseudo interrupt input which can be used for increasing the number of
interrupts of 8085, with the use of 8259 PIC.
• In normal mode of operation 8259PIC supports 8 interrupting devices in cascaded

mode of operation 8259PIC supports 64 interrupting devices.
• INTA is an active low interrupt ACK active pin. 8085 microprocessor generates on
active low signal via this INTA output, when it receives and recognizes interrupt
requests.
• INTR is monitored by the processor in the last clock period of an instruction.
• INTA Is required only for INTR not for vectored interrupt.
215
Microprocessors
• Every vectored interrupt in 8085 is given 8 bytes of memory to store the

corresponding program that must be executed in response to an interrupt which is
known as interrupt service routine (ISR)
• By default all the interrupts are disabled
Example: If external interrupt signal is received via

RST 4.5, then does the microprocessor initialize the PC with?
Solution:
Due to less memory between two interrupts.
We used JMP instruction.

For RST 4.5 PC initialize with 0024.
PC
0024H 0024H JMP
JMP 1500H
00
15
0040
Main Program
14FF
1500H
I.S.R
For
RST 4.5
15FFH
1600H I.S.R
For
RST 6
160FH USR = User
define sevice
1610H USR routine
Instructions Related to Interrupt

EI (Enable Interrupt): Use to enable maskable interrupt.
DI (Disable Interrupt): Use to disable maskable interrupt.
SIM (Set Interrupt Mask): Use to mask the interrupts or make them available.
RIM (Read Interrupt Mask): Use to know the status of pending interrupts.
216
Microprocessors
Programming Model
• Program: Set of instruction.
• Instruction: It is a command given to the computer to perform some specific task.
• Machine level language:
It is a binary means of communication with a computer through a design set of
instructions specific to a system.
• Assembly level language:
Instructions are written in separate words known as ‘Mnemonics’ which are
partially understood by the programmer.
MOV B,C 
Example:  Here MOV, ADD are Mnemonic (Easy to understand)
ADD D 
• Both assembly and machine level language are together called Machine level
language.
• Overall cycle of writing the program till execution:
Assembly Program
Assembler
Execute
Machine-Code
Decode (Microprogram)
Memory Op-Code Fetch
• Basic steps of execution of instruction:

(1) Op-code fetch
(2) Decode
(3) Execute
• Instruction format:
Op-code Operands
217
Microprocessors
• Op-code (Operation code):

It indicates the type of operation to be performed for an instruction.
• Operand:
It is a data on which operation is to be performed. Operand can be a register,
memory location register pair, 8-bit data or address, 16-bit data or address.
Length of an Instruction
• Number of bytes occupied by the instruction in the memory.
• There are three types of instruction classified as bases of length.
(1) 1-Byte Instruction

MOV

Example: Op-code A,C

operands

Example: MVI B, 77H

LXI H,9080H
Example:    
operands
[X → Register pair]
Op-code
(1 Byte) (2 Byte)
Example:
4000H: MOV A, C → XX
4001H: MVI B, 77H → yy, 77H
4003H: LXI H, 9030H → ZZ, 30H, 90H
Memory representation:
F → Fetch
R → Read
Note:
• Op-code is always fetch (In any type of process, fetch is always done first)
• Data is read or write
Memory Rule
In all memory related operations, the data present in the lower byte of register is
transferred to lower address location whereas higher byte data is transferred to high
address location and vice-versa.
218
Microprocessors
Standard Codes
B → 000
C → 001
D → 010 Memory (M) → 110
E → 011 BC → 00
H → 100 DE → 01
L → 101 HL → 10
A → 111 SP → 11
• Every register is given unique code, there 74 different op-codes in 8085 which
result 246 instructions
Addressing Modes
The mode of specifying operand address is known as addressing mode. There are various
formats specifying the operands. It indicates how the data is accessed for an instruction.
There are 5 types of addressing modes.
(1) Register addressing mode.
(2) Implicit/ implied addressing mode.
(3) Immediate addressing mode.
(4) Direct addressing mode.
(5) Indirect addressing mode.
(1) Register Addressing Mode

In this mode operand/s involved in operation is/are registers.
E.g.: MOV A,B; SPHL , PCHL, XCHG
ADD B; ADC H; DAD D; SUB A; SBB C; INR A; INX H; DCR B; DCX B
ANA B; ORA H; XRA A; CMP B
(2) Implicit /Implied Addressing Mode

In this mode operand is not given in the instruction and the machine assumes an
accumulator as the operand. If the address of source of data as well as address of
destination of result is fixed, then there is no need to give any operand algorithm
with the instruction such instruction are called as implicit addressing mode.
E.g.: DAA
RAL; RLC; RAR; RRC
(3) Immediate Addressing Mode

In this mode the operand (either 8-bit or 16-bit) is given in the instruction itself.
If 8/16 bit data required for executing the instruction is given along with the
instruction then such instructions are called immediate addressing mode.
219
Microprocessors
Example: MVI C, 66H; MVI M,54H; LXI SP, 2500H

ADI, 45H; ACI, 78H; SUI FFH; SBI A2H
ANI F4H; ORI 0FH; XRI 49H; CPI 41H
JMP 1000H; JNC 1400H……..JM 1488H; CALL 1200H; CNC 1532H………….CM 1258H
RST 0; ………………………………RST 7
(4) Direct Addressing Mode

In this mode the address of the operand is specified in the instruction. If 8/16 bit
data required for executing the instruction is present in memory location and a 16
bit address of this memory location is given along with the instruction, then such
instructions are called direct addressing mode instructions.
Example: LDA 9000H; OUT F4H; STA 200H; SHLD 4652H; LHLD 2145H
(5) Indirect Addressing Mode

In this mode address of the operand is made available in a register pointer. Indirect
addressing mode is also known as register indirect addressing mode.
Example: LDAX B; STAX B MOV B, M; MOV M, A; PUSH B; POP PSW; XTHL
ADD M; ADC M; SUB M; SBB M; JNR M; DCR M
ANA M; ORM XRA; CMP M
RET; RNC………………………RM
Timing Diagram
Timing diagram is pictorial representation of execution of an instruction with the help of
various control and status signal
T-State
It is one sub-division of an operation performed in one clock period. Sub-divisions are
internal states synchronized with the system clock.
1 1
f= 3MHZ;=
T = = 0.33 µ sec
clk
fclk 3 × 106
Machine Cycle
It is defined as the time required to access either memory or Input-Output or It is also
equivalent to the time required to transfer a data byte to memory or Input-Output. One
machine cycle may contain 3 to 6 T-State
Processor only does this 5 operation:
(1) F (Fetch)
(2) mr (Memory Read)
(3) mw (Memory Write)
220
Microprocessors
(4) IOR (Input-Output Read)

(5) IOW (Input-Output Write)
Instruction Cycle
It is time required to complete the execution in instruction. One instruction cycle may
contain 1 to 5 machine cycles:
(1) =
IC IFC + EC
(2) =
IC1B OPFC + EC
(3) IC2B = OPFC + mr1C + EC
(4) IC3B = OPFC + mr1C + mr2C + EC
Execution
• Internal 8 bit operation Will be performed during of OPFC.
• Internal 16 bit operation required two clock cycle extra (2T state).
• External 8 bit operation [MWC, MRC, IOWC, IORC], Required 3T state.
IC’s for Data Transfer Instructions

MVI A, 24H ⇒ 2 Byte instruction
⇒ OPFC + mrc
⇒ 2MC = 4T + 3T = 7T states
MVI M, 88H ⇒ 2 Byte instruction

⇒ OPFC+ mrc + Mwc
⇒ 3MC = 4T + 3T + 3T = 10T states
LXI SP, 2800H ⇒ 3 Byte instruction

⇒ OPFC+
⇒ 3MC = 4T + 3T + 3T = 10T states
MOV A, B ⇒ 1 Byte instruction

⇒ OPFC
⇒ 1MC = 4T states
SPHL ⇒ 1 Byte instruction

⇒ OPFC + 2T-[Extra 2T states required]
⇒ 4T + 2T = 6T [Special OPFC]
221
Microprocessors
Note:
• Op-code fetch MC’s are 2 types
• Normal OPFC = 4T
• Special OPFC = 6T
PCHL ⇒ 1 Byte instruction

⇒ OPFC + 2T
⇒ 6T states
XCHG ⇒ 1 Byte instruction

⇒ OPFC + 2T
⇒ 6T states
OUT F8H ⇒ 2B
⇒ OPFC + mr1c + IOW
⇒ 3MC = 4T + 3T + 3T = 10T states
IN F9H ⇒ 2B
⇒ OPFC + mc + IOR
⇒ 3MC = 4T + 3T + 3T = 10T states
MOV M, B ⇒ 1 Byte instruction

⇒ OPFC + MWC
MOV A, M ⇒ 1 Byte instruction

⇒ OPFC + MRC
STAX B ⇒ 1 Byte instruction

⇒ OPFC + MWC
LDAX D ⇒ 1 Byte instruction

⇒ OPFC + MRC
STA 2000H ⇒ 3 Byte instruction

⇒ OPFC + mr1c + mr2c + MWC
⇒ 4MC = 4T + 3T + 3T + 3T = 13T states
222
Microprocessors
LDA 2001H ⇒ 3 Byte instruction

⇒ OPFC + mr1c + mr2c + MWC
⇒ 4MC = 4T + 3T + 3T + 3T = 13T states
SHLD 4520H ⇒ 3 Byte instruction

⇒ OPFC + mr1c + mr2c + MW1C + MW2C
⇒ 5MC = 4T + 3T + 3T + 3T + 3T = 16T states
LHLD 6000H ⇒ 3 Byte instruction

⇒ OPFC + mr1c + mr2c + MR1C + MR2C
⇒ 5MC = 4T + 3T + 3T + 3T + 3T = 16T states
PUSH B ⇒ 1 Byte instruction

⇒ OPFC + MW1C + MW2C
⇒ 3MC = 4T + 2T + 3T + 3T = 12T states
POP D ⇒ 1 Byte instruction

⇒ OPFC + MR1C + MR2C
⇒ 3MC = 4T + 3T + 3T = 10T states
XTHL ⇒ 1 Byte instruction

⇒ OPFC + MR1C + MR2C + MW1C + MW2C
⇒ 5MC = 4T + 3T + 3T + 3T + 3T = 16T states
IC’s for Arithmetic & logical instructions

ADD B ⇒ 1 Byte instruction
⇒ OPFC
⇒ 1MC = 4T states
• ADC H, SUB B, SBB, INRH, DCR C, DAA, ANA B, ORA C, RAL, RLC, RAR, RRC
ADDM ⇒ 1 Byte instruction
⇒ OPFC + MRC
• ADO M, SUB M, SBB M, ORA M, XRA M, CMP M

ADI 84H ⇒ 2B
⇒ OPFC + mr1c
223
Microprocessors
• ACI F4H, SUI 44H, SBI 20H, ORI 40H, ANI 00H, XRI 10H, CPI 11H
DAD H ⇒ 1 Byte instruction
⇒ OPFC + BIC + BIC
⇒ 3MC = 4T + 3T + 3T = 10T
• BIC = Bus ideal cycle

INX B, DCX H ⇒ 1 Byte instruction
⇒ OPFC + 2T
INR M ⇒ 1 Byte instruction

⇒ OPFC + MRC + MWC
⇒ 3MC = 4T + 3T + 3T = 10T states
IC’s for Program Transfer Instructions

JMP 1000H ⇒ 3 Byte instruction
⇒ OPFC + mr1c + mr2c
⇒ 3MC = 4T + 3T + 3T = 10T
JNC 1000H ⇒ 3 Byte instruction

→ mr2c
⇒ OPFC + mr1c + [Variable machine cycle]
→X
Test result is true = 10T states

Test result is false = 7T states
JC 1001H, JPE 1200H, JPO Delay, JNZ 1010H, JZ 1210H, JP 1001H, JM 2100H
CALL 1641H ⇒ 3 Byte instruction
⇒ OPFC + mr1c + mr2c + 2T + Mw1C + Mw2C
⇒ 4T + 3T + 3T + 2T + 3T + 3T = 18T states
RST 1 ⇒ 1 Byte instruction

⇒ OPFC + 2T + Mw1C + Mw2C
⇒ 4T + 2T + 3T + 3T = 12T states
RST 0, RST 2, RST 3, RST 4, RST 5, RST6, RST 7

CNC 1500H ⇒ 3 Byte instruction
→ mr2c + Mw1c + Mw2c
⇒ OPFC + 2T + mr1c +
→X
224
Microprocessors

• CC 1000H, CPE 1100H, CPO Delay, CNZ 1010H, CZ 1111H, CP 1212H, CM LOOP
RET ⇒ 1 Byte instruction
⇒ OPFC + MR1C + MR2C
⇒ 4T + 3T + 3T = 10T states
RNC ⇒ 1 Byte instruction

→ MR1C + MR2C
⇒ OPFC + 2T +
→X

• RC, RPE, RPO, RNZ, RZ, RM, RP
IC’s of M.C. Instructions

HLT ⇒ 1 Byte instruction
⇒ OPFC + 1T-[BIC]
NOP ⇒ 1 Byte instruction

⇒ OPFC
⇒ 4T states
• EI, DI, SIM, RIM
Note: Maximum number of T-States possible for an instruction in 8085 is 18.
Timing Diagram
It is a representation of various control signals generated during execution of an
instruction.
Following Buses and control signals must be shown in the timing diagram.
• High order address buses.
• Lower order address/data buses.
• ALE
• RD
• WR
• IO /M
225
Microprocessors
E.g.: 6000 H: MVI A, 99H
Instruction cycle
Steps A15
Op-code fetch Memory read
(1) Fetch T1 T2 T3 T4 T5 T6 T7
(2) Decode
µs
0.33µ
(3) Execute
ALE
A15 − A8 60H Unknown 60H
AD7 − AD0 Z
00H XX 01H 99H
IO/M, IO/M = 0 S1 = 1, S0 = 0
IO/M = 0 S1 S0 = 1
S1 S0
RD
• Machine cycle: (here 2-machine cycle)

(1) Op-code fetch
(2) Memory read
• 7 T-states
• For any instruction to be executed, first machine cycle is op-code fetch which may
be of 4 or 6 T-state
T1 State
• ALE = 1 (high) is indicating all 16 lines are acting as address buses
• contain higher byte of address present in program counter (PC)
• AD7 − AD0 contain lower byte of PC
• IO/M = 0 indicating memory operation
• S1 = S0 = 1 for fetch
• RD = 1, inactive as there is no ‘data bus’ available
T2 State
• As ALE becomes low, AD7 − AD0 act as data bus
• When RD is activated, op-code from the memory location is accessed onto the
data bus.
T2 State
• Op-code from the data bus is accessed into instruction register (IR)
226
Microprocessors
Note: It requires 2T-States to access either on op-code or data byte from a

memory location into a processor after the address is latch.
T4 State
• The op-code is decoded (D) and execution may also be completed for some
instruction like MOV A,B; but the instruction considered a memory read operation is
required.
• Status of higher order bus (address) is unknown
Memory Read
T5 State
• ALE is high in order to point next memory location
• T6 and T7 are similar to fetch except that S1 = 1, S2 = 1 for memory use.
• 99H is accessed into Accumulator (A) in T6 and T7 for the instruction given.
Conclusion:
• Length of instruction = 2 byte
• No of machine cycle = 2 (F, R)
• Total T-State = 7 (F → 4, R → 3)
• Total execution time = count period no of T-State count value
1 1
= × T - States × C.V= × 7 × 1= 2.31 µ sec
fclk 3 × 106
• T-State:
Min Max
Fetch 4 6
Machine cycle 3 6
Instruction 4 18
Note:
• The number of machine cycles required for execution of an instruction may or may
not be equal to length of instruction.
• ALE is high in the first T-State of a machine cycle.
227
Microprocessors
Instruction Set Classification
Instruction
Type of operation Length of instruction
(i) Data transfer (copy) instruction (i) 1 Byte instruction
(ii) Arithmetic instruction (ii) 2 Byte instruction
(iii) Logical instruction (iii) 3 Byte instruction
(iv) Branching instruction
(v) Machine control instruction
Notations
r = 8 bit register
rs = 8 bit source register
rd = 8 bit destination register
r16 or rp = 16 bit register pair or 16 bit pointer
Data 8 = 8 bit data

Num 16 = 16 bit data
Addr 16 = 16 bit address of memory location
Add 8 = 8 bit port address
A = Accumulator
PSW = Program status word
M = Memory location contents pointed by HL pointers
• Every instruction consist of 2 parts
(1) Opcode (2) Operand
Data Transfer Instruction

In this group the data is transferred from one location known as ‘source’ to another
location known as ‘destination’. It may in between:-
(a) Register to Register: MOV B, C
(b) Register to Memory: MOV D, M; MOV M, E
(c) Register to I/O: IN 20H; OUT 40H
(d) Register to data: MVI A, 55H
228
Microprocessors
Syntax Operation
MVI r, data 8 (r) <= data 8
LXI rp, NUM 16 (rp) <= NUM 16
MVI M, data 8 ((HL)) <= data 8
MOV rd, rs (rd) <= (rs)
SPHL (SP) <= (HL)
PCHL (PC) <= (HL)
XCHG (DE) <=> (HL)
OUT Add 8 (Add 8) <= (A)
IN Add 8 (A) <= (Add 8)
MOV M, r ((HL)) <= (r)
MOV r, M (r) <= ((HL))
STAX rp ((rp)) <= (A)
LDAX rp (A) <= ((rp))
LDA Add 16 (A) <= (Add 16)
STA Add 16 (Add 16) <= (A)
(Add 16) <= (L)
SHLD Add 16 (Add 16 + 1) <= (H)
2 memory write operation
(L) <= (Add 16)
LHLD Add 16 (H) <= (Add 16 + 1)
2 memory read operation
((SP)-1) <= (rH)
PUSH rp ((SP)-2) <= (rL)
(SP) decremented by 2
(rL) <= ((SP))
POP rp (rH) <= ((SP) + 1)
(SP) incremented by 2
(TOS) <=> (HL)

XTHL
TOS = Top of the Stack
229
Microprocessors
SP is unchanged after the execution
POPH followed by PUSH H
Note:
• In almost all data transfer operation, the contain of source is unchanged after the
execution
• Flags are not affected for execution of data transfer groups of instructions, since
ALU is not involved.
• Working principle of stack is LIFO i.e. last pushed number will be popped out first
• Stack pointer contents are decremented by 2 for execution of PUSH and CALL
instruction.
• When PUSH instruction is executed stack pointer decrement first & writes to the
decremented address.
• Stack pointer contents are incremented by 2 for execution of POP and RETURN
instruction.
• When POP instruction is executed, the stack pointer first reads the increment.
• Stack pointer contents is unaltered for XTHL instruction since XTHL = POPH
followed by PUSH H.
Example: 3000H: MOV C, M if M = 77H
IR
XX
3000H XX F
.
.
D .
3500H 77 W
H L C C
35 00 77 77
Example: 3400H; MOV M, E if (E) = 66H
IR
XX
3000H XX F
.
PC .
3400 D .
3401
3500H 66 W
H L E C
35 00 77 77
230
Microprocessors
Example: 3800H: MVI A, FFH
IR
XX
3800H XX Fetch (F)
3801H FF
R
PC
3800 D A
3801
FF
A
FF
Example: 4000H: MVI M, 33H if (HL) = 4600H
Z IR
33 XX 4000H XX F
R
4001H 33
PC .
4000 D . 33 Z
4001 .
4002 W
4600H 33
H L
46 00
Example: 4700H: LXI H, 5000H
IR
XX 4700H XX F
4701H 00
PC R
4702H 50 R
4700 D
4701 H L
4702 50 00
4703
H L
50 00
231
Microprocessors
Example: 5100H: LDA 5400H if (5400H) = 89H
W Z IR
54 00 XX 5100H XX F
5101H 33
R
PC 5102H 54 R
D .
5100 W Z
5101 .
. 54 00
5102
R
5103 5400H 89
A
89 A
89
Example: 5000H: STA 6000H, If (A) = 3FH
W Z IR
60 00 XX 5600H XX F
5601H 00
R
PC 5602H 60 R
D .
5600 W Z
5601 .
. 60 00
5602
W
5603 6000H 3F
A
3F A
3F
Example: LDAX H doesn’t exist, not design because it is some as MOV A, M

Example: 6200H: LDAX B if (BC) = 6300H & ((BC)) = 79H
IR
XX 6200H XX F
.
6300H
.
PC
.
D
6200 W
79
6201
A
B C A 79
63 00 79
232
Microprocessors
Example: STAX H doesn’t exist, not possible because same as MOV M, A

Example: 6400H: STAX B if (A) = 23H & (BC) = 6900
IR
XX 6400H XX F
.
.
PC
.
D
6400
6900H 28 W
6401
A
B C A 28
69 00 28
Example: 7000H: PUSH D if (DE) = 9876H & (SP) = F005H
D E IR
98 76 XX 7000H XX F
.
.
PC
.
D
7000
SP-2 = F003H 76
7001 W
SP-1 = F004H 98
SP
SP = F005H WW
F005
.
F004 D E
.
F003 98 76
.
Example: 7300H: POP H if (HL) = 4030H & (SP) = D00B

IR
XX 7300H XX F
.
.
PC .
D
7300
SP = D009H 30
7301 R
SP SP + 1 = D00AH 40
R
D009 SP + 2 = D00BH WW
D00A .
. H L
D00B
. 40 30
FFFFH
233
Microprocessors
Example: 7700H: IN 50H
Z IR
XX 7000H XX F
50
50 R
7701H
Z
D 50
PC
Port address 50H
7700
7701
7702 A I/P
Device
WW
Example: 8000H: OUT 70H
Z IR
XX 8000H XX F
70
70 R
8001H
Z
D 70
PC
Port address 70H
8000
8001
8002 A O/P
Device
43
234
Microprocessors
Example: E000H: LHLD E400H

If (E400H) = 46
(E401H) = 8A
WZ
E4 00 IR XX F
E000H
E4 01 XX 00
E001H R
E4 R
E002H
.
W Z
PC D .
. E4 00
E000
H L E400H 46
E001
E401H 8A R R
E002 8A 89
E003
H L
8A 46
Example: E600H: SHLD E800H if (HL) = 3957H
WZ
EB 00 IR E600H XX F
XX 00
E601H R
EB R
E602H
.
W Z
PC D .
. EB 00
E600
H L E800H 57
E601 W
E801H 39 W
E602 39 57
E603
H L
39 57
235
Microprocessors
Arithmetic Instruction
• No multiplexer/division operation is supported by 8085.
• 8085 microprocessor has an accumulator based ALU i.e., in most of the arithmetic
& logical operations accumulator is one of the source operands and also acts as
destination operand for result storage.
(a) Addition; ADD C
(b) Subtraction; SUB M
(c) Increment; INX H
(d) Decrement; DCR M
Syntax Operation
Add r (A) <= (A) + (r)
DAA Decimal adjust after addition
DAD rp (HL) + (rp) => (HL)
ADC r (A) <= (A) + (r) + (CY)
ADD M (A) <= (A) + ((HL))
ADC M (A) <= (A) + ((HL)) + (CY)
ADI data 8 (A) <= (A) + data 8
ACI data 8 (A) <= (A) + data 8 + (CY)
SUB r (A) <= (A) − (r)
SBB r (A) <= (A) − (r) − (CY)
SUB M (A) <= (A) − ((HL))
SBB M (A) <= (A) − ((HL)) − (CY)
SUI data 8 (A) <= (A) - data 8
SBI data 8 (A) <= (A) − data 8 − (CY)
INR r (r) <= (r) + 1
INX rp (rp) <= (rp) + 1
INR M (M) <= ((HL)) + 1
DCR r (r) <= (r) − 1
DCR rp (rp) <= (rp) − 1
DCR M (M) <= ((HL)) − 1
236
Microprocessors
• DAD instruction is a special instruction for performing 16 bit addition.
• For subtraction operation microprocessors use 2’s complement technique.
• After subtraction operation, the carry flag is to be complemented.
• If CD = 1, then result in accumulator is positive (should be treated to be existing in

2’s complement form of its original magnitude)
• If CD = 0, then result in accumulator is negative (should be treated as its original

magnitude)
• 16 bit increment & decrement operations are not performed by ALU, As such flags
are not affected for the execution of INX & DCX operation.
• INR & DCR instruction affects all flags except the CY flag.
• For DAD Accumulator is unchanged after the operation. If there is carry out of 16-
bit, carry flag is affected, remaining flags are unchanged
• DAA is the only instruction which works with the status of auxiliary carry flag
(AC) in BCD conversion. It is used after addition. It converts 8-bit data present in
the accumulator into two 4-bit BCD numbers. It uses the following condition for
execution, after varying the content of accumulator
If D3 − D0 > 9 or AC = 1; Add 6
If D7 − D4 > 9 or CY = 1; Add 6
Example: ADD C
DAA
If (A) = (89)BCD, (C) = 77BCD
(89)BCD = 1 0 0 0 1 0 0 1
(77)BCD = 0 1 1 1 0 1 1 1
CY = 1 = 0 0 0 0 0 0 0 0
AC and CY = 1 are one then add 6
0 0 0 0 0 0 0 0
CY 0 1 1 0 0 1 1 0
0 0 1 1 0 0 1 1 0 = 66H
(A) <= 66H
237
Microprocessors
Example: ADD B if (A) = F9H & (B) = 68H
F9 = 1 1 1 1 1 0 0 1
68 = 0 1 1 0 1 0 0 0
CY = 1 0 1 1 0 0 0 0 1
(A) <= 61
S Z X AC X P X CY
0 0 0 1 0 0 0 1
Example: 8000H: ADD M if (A) = 38 & M = C7
38 = 0 0 1 1 1 0 0 0
C7 = 1 1 0 0 0 1 1 1
CY = 0 1 1 1 1 1 1 1 1
(A) <= FFH

S Z X AC X P X CY
1 0 0 0 0 1 0 0
Example: ADI 2EH if (A) = 5B
5B = 0 1 0 1 1 0 1 1
2E = 0 0 1 0 1 1 1 0
CY = 0 1 0 0 0 1 0 0 1
(A) <= 89
S Z X AC X P X CY
1 0 0 1 0 0 0 0
Example: A600H: ADC M if CY = 1, (A) = 89 & M = 76
1
89 = 1 0 0 0 1 0 0 1
76 = 0 1 1 1 0 1 1 0
CY = 1 0 0 0 0 0 0 0 0
238
Microprocessors
(A) <= 00H

S Z X AC X P X CY
0 1 0 1 0 1 0 1
Example: SUB C if (A) = 94H & (C) = 31H
Manual Processor
A−C A+C
94 = 1 0 0 1 0 1 0 0 94 = 1 0 0 1 0 1 0 0
−31 = 1 1 0 0 1 1 1 1 +CF = 1 1 0 0 1 1 1 1
CY = 1 0 1 1 0 0 0 1 1 CY = 1 0 1 1 0 0 0 1 1
S Z X AC X P X CY S Z X AC X P X CY
0 0 0 * 0 1 0 0 0 0 0 1 0 1 0 1
In manual method we are not able to find ‘AC’ flag but the method used by processor
have capability to determine (assign) Auxiliary flag (AC)
Trick
Find ‘AC’ by using a manual method.
If result lower Nibble<Accumulator lower Nibble
Then AC = 1
Else AC = 0
Example: SUI 9CH if (A) = 24
24 = 0 0 1 0 0 1 0 0
−9C = 0 1 1 0 0 1 0 0
CY = 0 1 0 0 0 1 0 0 0
S Z X AC X P X CY
1 0 0 0 0 1 0 0
Example: SBB H if (A) = 5A (H) = 9E

Borrow = 1
H = 9E + 1 = 9F
239
Microprocessors
5A = 0 1 0 1 1 0 1 0
−9F = 0 0 1 0 0 0 0 1
CY = 0 0 1 1 1 1 0 1 1
S Z X AC X P X CY
1 0 0 0 0 1 0 1
Example: SBI AEH if (A) = 68
68 = 0 1 1 0 1 0 0 0
−AE = 0 1 0 1 0 0 1 0
CY = 0 1 0 1 1 1 0 1 0
S Z X AC X P X CY
1 0 0 0 0 0 0 1
Example: INR C if (C) = FF
FF = 1 1 1 1 1 1 1 1
+1 = 0 0 0 0 0 0 0 1
CY = 0 0 0 0 0 0 0 0 0
S Z X AC X P X CY
0 1 0 1 0 1 0 X'
X' → Previous status
Example: C000H: INR M if M = 8F
8F = 1 0 0 0 1 1 1 1
+1 = 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0
S Z X AC X P X CY
1 0 0 1 0 1 0 X'
240
Microprocessors
Example: INX H if (HL) = FFFFH
FFFF = 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 No flag will affect
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Example: D000H: DCR M if M = 00H
00 = 0 0 0 0 0 0 0 0
−1 = 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
S Z X AC X P X CY
1 0 0 0 0 1 0 X’
Example: DCX D if (DE) = F000H
F000 = 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
−1 = 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
No flag will affect
Example: F000H: DAD B if (BC) = F00F & (HL) = 9876

(BC) + (HL)
F00F = 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1
+9876 = 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0
CY = 1 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1
(HL) = 8886H
241
Microprocessors
Logical instruction
8085 microprocessor has an accumulator base ALU i.e., in most of the logical operations,
one of the source operands is accumulator and also destination operands for result
storage.
(a) AND; ANA D
(b) OR; ORI FFH
(c) Ex-OR; XRA M
(d) Compare; CDI 00H
(e) Compliment; CMA
(f) Rotate; RRC
Syntax Operation
AND accumulator with r
ANA r
(A) <= (A)∧(r)
ANA M (A) <= (A)∧((HL))
ANI data 8 (A) <= (A)∧data 8
ORA r (A) <= (A)∨(r)
ORA M (A) <= (A)∨((HL))
ORI data 8 (A) <= (A)∨data 8
XRA r (A) <= (A)∀(r)
XRA M (A) <= (A)∀((HL))
XRI data 8 (A) <= (A)∀data 8
CMP r (A) − (r)
CMP M (A) − ((HL))
CPI data 8 (A) − data 8
CMA Complement contents of accumulator
CMC CY <= CY
STC CY <= 1
RLC Rotate accumulator left
RAL Rotate accumulator left through carry
RRC Rotate accumulator right
RAR Rotate accumulator right through carry
242
Microprocessors
• For CMP M operation results are not stored in ‘M’, it differs from SUB instruction.
We have to check status from flags.
• CMA instruction is used for 1’s complement performing.
• Rotate operations include only change of carry flag. No other flags are affected
using rotate operation.
• For any AND operation AC = 1 & CY = 0
For any OR operation AC = 0 & CY = 0
Set by microprocessor, remaining flags depend on results
• Comparison is performed by doing internal subtraction but result is not stored
in accumulator i.e. both the operands involved in comparison are unaltered. Flag
register is updated after comparison operation.
Z CY (A) – (B) Result
1 0 Zero (A) = (B)
0 0 Positive (A)>(B)
0 1 Negative (A)<(B)
Sign flag depends on the subtraction of (A) − (B)

Instructions which make the Accumulator reset
• XRA A
• ANI 00H
• MVI A, 00H
Since XRA A takes less machine cycles, we prefer it because it saves memory and
increases the speed of operation. Since MVI A, 00H has also the same machine cycles
but in this operation flags are different for different values but in XRA A, flags are not
affected.
RAL
CY
MSB D6 D5 D4 D3 D2 D1 LSB
243
Microprocessors
RLC
CY
RAR
CY
RRC
CY
244
Microprocessors
Application of Rotate Operation

• Used to find number is odd or even and also help to find no is +Ve or −Ve
• Suppose a data is given as 1 001100 0
 , we can identify the number is even or odd
MSB LSB
by just looking LSB, if LSB = 0then number is even otherwise odd or if LSB = 1, then
number is odd otherwise even. If we want to judge the no is +ve or −ve, then if MSB
−ve number), if MSB = 0 (+ve number), but in microprocessor it is not possible
= 1 (−
to judge directly. So we use the carry flag to check the condition above.
• Rotate left: If we want to check +ve or −ve number, then use RAL (Rotate left with
carry). Thus carry flag content MSB. Now by check carry flag we identify +ve or −ve.
• Rotate right: By using RAR carry flag condition LSB check carry flag. If CY = 1 (odd
number) and if CY = 0 (even number)
Effect of Arithmetic and Logical Instruction on Flags

• Flags are affected for arithmetic & logic operations only.
• Addition, subtraction , compare, decimal adjust instruction affect CY, Z, S, AC, P
flags
• INR & DCR affect S, Z, AC & P flags. We can’t detect overflow using INR instruction
• INX & DCX don’t affect any flags because the processor can process 8 bit data. This
is performed by the Dec/Inc unit of the register array.
• DAD, CMC, STC, Rotate affect only carry flag
• OR & XOR affect all the flags, reset AC = 0, CY = 0
Example: ANA C if (A) = 55 & (C) = AA
55 = 0 1 0 1 0 1 0 1
AA = 1 0 1 0 1 0 1 0
0 0 0 0 0 0 0 0
S Z X AC X P X CY
0 1 0 1 0 1 0 0
Example: ORA L if (A) = DB & (L) = 59
DB = 1 1 0 1 1 0 1 1
59 = 0 1 0 1 1 0 0 1
1 1 0 1 1 0 1 1
245
Microprocessors
S Z X AC X P X CY
1 0 0 0 0 1 0 0
Z = 0 & CY = 0
A > B, Positive number
Example: XRA A if (A) = FF
FF = 1 1 1 1 1 1 1 1
FF = 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
S Z X AC X P X CY
0 1 0 0 0 1 0 0
Example: CMP C if (A) = 59 & (C) = BE
A−C
59 = 0 1 0 1 1 0 0 1
−BE = 0 1 0 0 0 0 1 0
1 0 0 1 1 0 1 1
S Z X AC X P X CY
1 0 0 0 0 1 0 1
Example: RRC If (A) = 57H & CY = 0

CY
1
0 1 0 1 0 1 1 1
1 0 1 0 1 0 1 1
(A) <= AB
246
Microprocessors
Example: RAR If (A) = 6CH & CY = 1
CY
0 1 1 0 1 1 0 0
1 0 1 1 0 1 1 0
(A) <= B6
Branching Instruction
This group of instruction is also called a program transfer control group. In this group
the control program is transferred from one location to another conditionally or
unconditionally. These instructions operate on the program counter and in turn change
or alter the sequence of processing.
Conditional Instruction
They depend on the status of flags affected for previous ALU operation (except Auxiliary
carry flag (AC)).
• When the condition is true, control of the program is transferred to the 16-bit
address. 3 machine cycles i.e., 10T states consumed.
• When the condition is false, the very next instruction is executed. 2 machine cycles
i.e., 7T states are consumed.
Test Conditions
CY = 0 P=0 Z=0 S=0
CY = 1 P=1 Z=1 S=1
• AC can’t be tested, it is used only for internal BCD arithmetic operation
247
Microprocessors
JUMP Instruction
Syntax Operation
JNC Add 16 Jump to address if CY = 0
JC Add 16 Jump to address if CY = 1
JPO Add 16 Jump to address if odd parity (P = 0)
JPE Add 16 Jump to address if even parity (P = 1)
JNZ Add 16 Jump to address if No zero (Z = 0)
JZ Add 16 Jump to address if zero (Z = 1)
JP Add 16 Jump to address if plus (S = 0)
JM Add 16 Jump to address if minus (S = 1)
• There are 9 jump instructions (8-Conditional and 1-Unconditional) and each

instruction requires a 3-machine cycle. Hence total machine cycle required to
execute all 9 jump instruction 9 × 3 = 27 machine cycles
Example: (C) = 02H

3000H XX
3000H: MVI C, 02H
3001H 02
Loop: 3002H: DCR C yy
3002H
3003H: JNC LOOP 3003H zz Fetch
3006H: HLT 3004H 02
R
3005H 30 R
3006H ww
W Z
30 02
+1
PC 3000
3006
3003
• In this above program if the content of register ‘c’ is ’n’. The loop executes for
n-times where the condition is true for (n − 1) times and false only once.
• When the condition is false, PC is incremented twice to execute the next

instruction.
• The operation of the remaining conditional jump instruction is similar to JNZ except
that flags are different.
248
Microprocessors
CALL Instruction
Syntax Operation
CNC Add 16 CALL address if CY = 0
CC Add 16 CALL address if CY = 1
CPO Add 16 CALL address if P = 0
CPE Add 16 CALL Address if P = 1
CNZ Add 16 CALL Address if Z = 0
CZ Add 16 CALL Address if Z = 1
CP Add 16 CALL Address if S = 0
CM Add 16 CALL Address if S = 1
• When a condition is true, operation is similar to un-condition call that is 5 machine

cycle i.e., 18 T-States
• When condition is false, 2 machine cycle i.e., 9 T-States are consumed
• When the condition is false SP(Stack Pointer) is unchanged
Return Instruction
Syntax Operation
RNC Return if no carry (CY = 0)
RC Return if carry (CY = 1)
RPO Return if odd parity (P = 0)
RPE Return if even parity (P = 1)
RNZ Return if no zero (Z = 0)
RZ Return if zero (Z = 1)
RP Return if plus (S = 0)
RM Return if minus (S = 1)
• Return instruction is used as last instruction of a Subroutine or interrupt service

Subroutine
• PCHL instruction is equivalent to unconditional Jump instruction.
• When the condition is true operation is similar to unconditional return except that
fetch is of 6 T-States i.e.
• When the condition is false only one machine cycle i.e., 6 T-State is consumed.
249
Microprocessors
• RST n instructions i.e., software interrupt instructions are equivalent to

unconditional CALL instruction.
• Conditional jump instructions are used for iteration control.
Unconditional Instruction
The control of the program is transferred to the 16-bit address unconditionally.
Syntax Operation
JMP Add 16 (PC) <= Address
((SP) − 1) <= (PCH)
CALL Add 16 ((SP) − 2) <= (PCL)
& (PC) <= Add 16
(PCL) <= ((SP))

RET
(PCH) <= ((SP) + 1)
PCHL (PC) <= (HL)
((SP) − 1) <= (PCH)
RET n ((SP) − 2) <= (PCL)
& (PC) <= [8n]16
• Term used for call in ‘c’ language is called function calling, but in microprocessor,
function is termed as ‘Subroutine’
• If length of instruction is large, it term as ‘Procedure’
• If length of instruction is small it terms as ‘Macro’
• Call instructions are used to call subroutine main program
Subroutine
Set or group of instructions which perform specific functions written as a separate
program away from the main program is known as subroutine.
When CALL is executed,
Step-1: The content of PC or address of instruction next to call is push onto stack
memory, then SP → SP − 2.
Step-2: The control of the program is transferred to the subroutine address and
execution continues. When RET is executed,
Step-1: The data present at top of stack (2 Bytes) pointed by SP is accessed or loaded
into the program counter. Therefore SP → SP + 2
250
Microprocessors
Step-2:
Control of the program is transferred to the 16-bit address and execution continues.
When RST n is executed,
Step-1: The content of PC or address of instruction next to RST n is push down to stack
memory, therefore SP → SP − 2.
Step-2: Control of the program is transferred to the vector address of RST n and execution
complete.
• CALL & RET operations are known as subroutine handling operations. CALL
instruction is used for transferring the program control to a subroutine from main
program and RET instruction is used for transferring control program back to main
program from subroutine.
Example: (BC) = 1234H & (A) = 34

LXI B, 1234 H
MOV A, C
JMP QUIT
ORI FFH
}
ANI FFH These are not executed because of jump instruction
OUIT: HLT
Example: Main Program:

6000H .
6000H .
.
.
.
6005H XX F
.
6005H : CALL RZ CALL 6006H 00
R
6007H 80
6008H: NOP R
PC 6008H yy
6009H: HLT
6009H x'x'
. W Z
.
. 80 00
RZ: 8000H 8000H
. +1
8004H: RET RZ
8004H zz 8001
.
.
.
SP-2 = F004H 0B
W
SP-1 = F005H 60 W
SP = F006H ww 6008
.
8001
.
. PC
FFFFH
251
Microprocessors
Machine Control Instruction

This group of instructions control internal actions of the machine.
• HLT 1 Byte instruction

It is used to stop the execution of a program. If the process enters into a Halt
acknowledgement cycle. One or more than one wait states are included for every
clock period. Internally PC is disconnected from the address bus as there is no
provision for the next op-code fetch. So the program stops. A reset or hardware
interrupt required to come out of Halt state.
• Nop 1 Byte Instruction

No operation is performed by the instruction but a delay of 4-T states is included
in execution time. It is used to write delay programs and also when communicating
with slow speed peripheral devices.
Example: MVI C, 03H

L1: JNZ L1
HLT
C = 03
02, Z = 0 True
01, Z = 0 True
00, Z = 1 False
Let above program provide ‘x’ second delay, then if we introduce ‘NOP’, then delay
increases by 4 T-states.
• DI (Disable interrupt) → 1 Byte instruction.

It is used to disable the maskable interrupt. Used at initial instruction of ISR such
that the processor may not be disturb by another interrupt.
• EI (Enable interrupt) → 1 Byte instruction It is used to enable maskable interrupt.

Used at initial instruction of main program and at last instruction of an ISR, such
that the processor may be ready to serve another interrupt. Internally enabled
interrupt flip-flop is set.
• SIM (Set interrupt mask) → 1 Byte instruction.

It is a multipurpose instruction used to mask the interrupts or make them available
valid only for RST 7.5, RST 6.5, RST 5.5. It is used along with the content of
Accumulator. It is also used to transfer serial data out the processor through SOD
pin.
252
Microprocessors
SOD pin
D7 D6 D5 D4 D3 D2 D1 D0
SOD SDE X R 7.5 MSE M 7.5 M 6.5 M 5.5
Serial O/P
data if 1 = Masked
0 = Available
Reset
Serial data RST 7.5 F.F Mask set enable
Enable 1 = Reset
1 = D2 − D0 = Valid/significant
1 = Enable SOD
0 = D2 − D0 = Invalid/Insignificnt
0 = Disable SOD
• It is not a register, it is a format only
• ‘D3’ bit is the control over D2 − D0, if it is 1 they are valid/significant else invalid/
insignificant
• D0 − D2 indicate whether interrupt mask or available
• D4 is an extra provision for RST 7.5 to reset
• D6 is control bit over D7
• D7, serial data to be transmitted through SOD pin
Example: After the execution of following instruction, find

(i) Interrupt Mask (ii) Serial data transmitted (iii) Interrupt Available
EI
MVI A, 4CH
SIM
Solution: 4C → 01001100
0 1 0 0 1 1 0 0
SOD SDE X R7.5 MSE M7.5 M6.5 M5.5
(i) Interrupt masked → RST 7.5 (see D3 then D2)

(ii) Interrupt available → RST 6.5, RST 5.5 (rest D1, D0)
(iii) Serial data transmitted → ’0’ (See D7)
253
Microprocessors
• RIM(Read interrupt mask) → 1 Byte instruction

It is a multipurpose instruction used to know the status of interrupt and also to
receive serial data into the processor through SID pin. Valid only for RST 7.5, RST
6.5, RST 5.5. After execution of RIM instruction, status is loaded or copied into the
accumulator. It is reverse of SIM
SID pin
D7 D6 D5 D4 D3 D2 D1 D0
SID I7.5 I6.5 I5.5 IE 7.5 6.5 5.5
Serial I/P
data Status of pending if 1 = Masked
Interrupts 0 = Available
1 = Pending
Interrupt Enable Flip-Flop
1 = Interrupt Enable (For EI)
0 = Interrupt Disable (For DI)
D3 indicates whether interrupt enable or disable

• D0 − D2 indicate whether interrupt masked or available.
• D4 − D6 indicates status of pending interrupt
• D7 is the serial data received into the processor through the SID pin.
Example: The content of Accumulator after execution of RIM instruction is 9CH. Find:
(i) Interrupt masked
(ii) Interrupt available
(iii) Interrupt pending
(iv) Serial data received
Solution: 9CH = 10011100
1 0 0 1 1 1 0 0
SID I7 I6 I5 IE 7.5 6.5 5.5
(i) RST 7.5 (See D3 then D2)

(ii) RST 6.5, RST 5.5 (See D3 then D0, D1)
(iii) RST 5.5 (See D4)
(iv) ‘1’ (See D7)
254
Microprocessors
Note:
SIM → Control the interrupt
RIM → Represent status of interrupt
Conclusion:
* PUSH Rp 
 * POP Rp 
* CALL  SP → SP − 2  SP SP + 2
* RST n  * Retun 
Solved Examples
Problem:
9900H: LXI H, 1230H
9903H: PCHL
9904H: MVI A, FFH
9906H: HLT
What is content of “A” after execution of above program
Solution:
Since, PCHL operation changes the PC to 9906H, hence instruction at 9904H is not
executed. Hence content of A is undefined.
Problem:
After the execution, what is the content of SP and data present at CFFEH
LXI SP, FF00H
LXI H, D000H
SPHL
PUSH B
POP B
HLT
Solution:
(SP) = FF00H
(HL) = D000H
(SP) = D000H
SP = D000H after PUSH & POP operation because PUSH and POP cancel out each other
At CFFEH → 00H (When push perform, SP → SP-2 i.e., CFFEH and at this position lower
bit of HL is place i.e., 00H)
255
Microprocessors
Problem:
Write an assembly language program (ALP) to perform Ex-Or operation between first two
memory location data and store the content of flag register and accumulator to the next
memory location.
Solution:
LDA 6000H
MOV B,A
LDA 6001
XRA B
LXI SP 6004
PUSH PSW
HLT
B = E7 = 1 1 1 0 0 1 1 1
A = −B1 = 1 0 0 0 0 0 0 1
0 1 1 0 0 1 1 0
S Z X AC X P X CY
0 0 0 0 0 1 0 0
(A) <= 66H

(PSW) = 6604H
Problem:
Write an assembly language program to access a data byte from port address 70H
compliment it, rotate the result left side for 5 times. Store the resultant value at 900FH
after transferring it to port add 90H.
Solution:
IN 70H
CMA
MVI B, 05 H
L1: RLC
DCR B
JNZ: L1
OUT 90H
STA 900FH
HLT
256
Microprocessors
Problem:
LHLD 7000H
LXI D, 7003H
7000H 02
LDAX D
7001H 70
MOV B,M
ANA B 7002H BD
DAD H 7003H 3C
SPHL
PUSH PSW
HLT
Then find the address stored in SP and Top of stack & also find the value stored in the
accumulator.
Solution:
(i) H = 70, L = 02
D = 70, E = 02
(ii) A = 3C
(iii) B = BD
(iv) 3C = 0 0 1 1 1 1 0 0
BD = 1 0 1 1 1 1 0 1
0 0 1 1 1 1 0 0 = 3CH
S Z X AC X P X CY
0 0 0 1 0 1 0 0
PSW = 3C14H
7002
(v) 7002
E004
(vi) SP → E004
(vii) SP → E002
Top of stack = 14H

(A) = 3C
257
Microprocessors
Problem:
Write an assembly language program for 8085 to transfer 4-bytes of data starting from
7000 to 8000H.
Solution:
LXI H 7000H
LXI D 8000H
MVI B, 04H
Rept: MOV A,M
STAX D
INX H
INX D
DCR B
JNZ: Rept
HLT
Problem:
Find the content of SP and data present at the top of the stack after the execution of
program
900H: LXI SP, FF00H
9003H: LXI H, 9009H
9006H: PCHL
9007H: MVI B, 66H
9009H: CALL R1
900CH: JMP QUIT
R1 : 900FH: XRA A
9010H: RP
QUIT: 9011H: HLT
Solution:
SP = FF00H SP-2 = FEFEH 0C
HL = 9009H SP-1 = FEFFH 90
PC = 9009 SP = FF00H 55
90 0C
B = 66H
Due to Call instruction, the contents of Program Counter are stored in Stack and Program
counter contains the address of the subroutine.
258
Microprocessors
PC = 900F & SP=FEFEH

A = 00H & Z = 1, P = 1, CY = 0, AC = 0, S = 0
S= 0 i.e., return to 900CH
PC = 900CH
Hence, at the top of SP, after execution of program = 55 at address FF00H, but content
of SP is OC, 90, 55 as shown in diagram with address
Timer And Counter Problem

Microprocessor does not contain any timer or counter, micro-controller content timer
or counter. There is no timer or counter in 8085 but program logic can be interpreted to
write time delay and count the events.
• Total execution time = clock period No of T-State count value.
1
• Total execution time = × T − States × C.V
fclk
• Count values means the number of times that program executes (i.e., no of time
program runs during loop).
Solved Examples
Problem:
Find the total execution time for a program of 8085 it consumes 450 T-States when
crystal frequency is 6MHZ.
Solution:
fcrystal 6MHz
( fclk )
Operating frequency = =
2
= 3MHz
2
1
T.E.T= × 450 × 1= 150 µsec
3 × 106
Problem:
Find the total execution time for the following program.
Operating frequency is 5 MHz
T-State
LXI D, 66CCH - 10
MOV A,E - 4
ANA D - 4
JNC L4 - 7/10
259
Microprocessors
MVI B, 77H - 7
L4: STA 5000H - 13
HLT - 5
Solution:
(DE) = 66CCH & (A) = CCH
ANA D ⇒ CC = 1 1 0 0 1 1 0 0
66 = 0 1 1 0 0 1 1 0
0 1 0 0 0 1 0 0
S Z X AC X P X CY
0 0 0 1 0 1 0 0
JNC → Jump if no carry condition is true

Now, Total T-States = 10 + 4 + 4 + 10 + 13 + 5 = 46
1
Total execution time = × 46 × 1 = 9.2 µs
5 × 106
Problem:
How many times loop execute, if Z = 0
L1: LXI B, 0003H
DCX B
JNZ L1
HLT
Solution:
DCX → B Never effect flag
(BC) = 0003H
Since, Z = 0, hence JNZ is always true
Thus loop will be rotating infinite no of times
Problem:
How many times loop execute,
XRA A
L1: LXI B, 0003H
260
Microprocessors
DCX B
JNZ L1
HLT
Solution:
XRA A → Z = 1 (it affect zero flags)
Hence, JNZ is executed and condition is false
So, n = 1
In this question, DCX B does not affect flags but because of XRA A flag already affect and
Z=1
Memory Interfacing
memory location = 2Number of address i/p lines
• A memory with n address i/p lines will have 2n bytes.
• Number of address i/p lines is going to decide the memory.
Example: For 10 address line, 210 bytes = 1KB memory
Memory Mapping
Given names to or addressing memory location is known as memory mapping, Memory
map indicates starting and ending and range of a memory chip.
Calculating Starting and Ending Address for a Memory Chip

Step-1: Find the no of address lines according to capacity of memory.
Step-2: Put equivalent no of 1’s as that of the address line and find the hexadecimal
value that must be added or subtracted to get the ending or starting address.
Solved Examples
A15
A14
Problem:
A13
Find the memory map A12
A11
for given interfacing logic.
A10 CS RD WR
A0
.
.
. 1 KB
.
. n = 10
.
.
.
A9
261
Microprocessors
Solution:
For chip select, NAND gate output must be zero it happens only when:
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 = AB00H
1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 = ABFFH
Hence AB00 to ABFFH
Problem:
Find the memory map for given interfacing logic.
A15
A14
A13
A12
A11 CS RD WR
A0
.
.
. 2 KB
.
. 11 address
. line
.
.
A10
Solution:
For chip select, NAND gate output must be zero it happens only when:

1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 = 8800H
1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 = 8FFFH
Hence 8800H to 8FFFH
Problem:
Find the ending address of a 4KB ROM if starting address is C3A9H.
262
Microprocessors
Solution:
4 KB = 12 address line [4KB = 212 ⇒ n = 12]
C3A9 → Starting address

+ 0FFF
D3A8 → Ending address
Problem:
Calculate the starting address for a 8KB RAM if the ending address is 60AB H.
Solution:
8 KB = 13 address line [8KB = 213 ⇒ n = 13]
60AB → Starting or ending address

−1FFF
40AC → Starting address
Problem:
A15
A14
E Y0
Y1
A13 C A0 CS
Y2 .
Decoder .
Y3 . 2 KB
A12 B
Y4 .
. RAM
Y5 A10
A11 A
Y6
Y7
Find starting and ending address
Solution:
C B A
O/P
A13 A12 A11
1 0 0 Y4
263
Microprocessors

1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 = A000H
1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 = A7FFH
Address Mapping Techniques

The processor identifies an I/O device in two types:
(1) I/O mapped I/O.
(2) Memory mapped I/O.
I/O Mapped I/O

• I/O devices are treated by microprocessors as I/O devices.
• I/O address space is separately available and distinct from memory address space.
• I/O devices are recognized with 8 bit port addresses and hence microprocessors
can differentiate between location and I/O devices.
Memory Mapped I/O Techniques

• Memory devices are treated by microprocessors as memory addresses.
• I/O address space is a part of memory address space i.e., a portion of memory
space is allowed for I/O devices.
• I/O devices are recognized with 16 bit addresses and hence microprocessors can’t
differentiate between memory location I/O devices.
I/O mapped I/O Memory mapped I/O
• This device address is 16-bit. Thus A0 • In this I/O device address is 8-bit. Thus
to A15 lines are used to generate device A0 to A7 or A8 to A15 lines are used to
address generate device address
• I/O has 8-bit port address • I/O has 16-bit address

• 28 → 256; 256 I/P and 256 O/P devices • 216 → 65, 536; Address are shared
are possible between memory and I/O
• Instruction used: • Instruction used:

IN 8 bit port address LDA 16 bit address
OUT 8 bit port address STA 16 bit address
(All arithmetic instruction related to
memory, ADDM, SUB M….)
• Control signals • Control signals

MEMR, IOR, IOW MEMR, MEMW
264
Microprocessors
265

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Digital Electronics

Chapter 1 – Number Systems

Advantages of Digital Representation Over Analog Representation

Introduction to Number Systems

Definition and Importance

Few Important Points to Define a Number System

(i) Base of the number systems such as 2, 8, 10 or 16

Base or Radix (R) of a Number System

Various Numbering Systems

S.NO. Name of the number system Base/Radix

Positional Number Systems

Example: Maximum value of digit in decimal number system = (10 – 1) = 9.

Example: 75610 = 7 × 102 + 5 × 101 + 6 × 100

84 83 82 81 80 ∙ 8−1 8−2 8−3 8−4

Decimal to Radix-r Conversion

(a) Integer Number

(b) Fractional Number

(B) Convert the fractional part of decimal to binary equivalent

Integer Quotient Remainder

0.832 × 8 = 6.656 6 Go from top

0.656 × 8 = 5.248 5 to Bottom

0.984 × 8 = 7.872 etc. 7

Radix-r to Decimal Conversion

Solution: 2578 = 2 × 82 + 5 × 81 + 7 × 80 = 128 + 40 + 7 = 17510.

Solution: 1AF.2316 = 1 × 162 + 10 × 161 + 15 × 160 + 2 × 16-1 + 3 × 16−2 = (431.13678…)10

Numbers with Different Bases

Solution: 2 -> 0010

Why Octal or Hexadecimal?

• Binary to Gray Code Conversion

• Gray Code to Binary Conversion

(137)10 -> (000100110111)BCD

Solution: BCD equivalent of (48)10 = (01001000)2

Representation of Various Decimal Numbers in Binary Codes

Decimal Binary Gray BCD Excess-3

0 0000 0000 0000 0011

1 0001 0001 0001 0100

2 0010 0011 0010 0101

3 0011 0010 0011 0110

4 0100 0110 0100 0111

5 0101 0111 0101 1000

6 0110 0101 0110 1001

7 0111 0100 0111 1010

8 1000 1100 1000 1011

9 1001 1101 1001 1100

• Radix complement: also called as r’s complement

• Diminished radix complement: also called as (r − 1)’s complement

Given a number ‘N’ in base ‘r’ having ‘n’ digits:

• (r − 1)’s complement is defined as (rn − 1) − N

• r’s complement is defined as rn − N

• So, r’s complement can be derived from (r-1)’s complement by adding 1

• 1’s complement of a number can be directly obtained by complementing all the

Solution: 1’s complement of (10110011)2 = (01001100)2

Signed and Unsigned Magnitude Representation

Representation in Sign Magnitude Form

Signed 2’s Signed 1’s Signed Magnitude

+6 0110 0110 0110

+5 0101 0101 0101

+4 0100 0100 0100

+3 0011 0011 0011

+2 0010 0010 0010

+1 0001 0001 0001

+0 0000 0000 0000

-0 ------ 1111 1000

-1 1111 1110 1001