Digital Principles and System Design

DPSD

UNIT II and III-COMBINATIONAL CIRCUITS

Logic Gates
Logic gates have one or more inputs and only one output. The output is active only for certain input combinations. Logic gates are the building blocks of any digital circuit. Logic gates are also called switches. With the advent of integrated circuits, switches have been replaced by TTL (Transistor Transistor Logic) circuits and CMOS circuits. Here I give example circuits on how to construct simples gates. Symbolic Logic Boolean algebra derives its name from the mathematician George Boole. Symbolic Logic uses values, variables and operations. Inversion A small circle on an input or an output indicates inversion. See the NOT, NAND and NOR gates given below for examples.

Digital Principles and System Design

Multiple Input Gates

DPSD

Given commutative and associative laws, many logic gates can be implemented with more than two inputs, and for reasons of space in circuits, usually multiple input, complex gates are made. You will encounter such gates in real world (maybe you could analyze an ASIC lib to find this).

AND OR NOT BUF NAND NOR XOR XNOR

AND Gate The AND gate performs logical multiplication, commonly known as AND function. The AND gate has two or more inputs and single output. The output of AND gate is HIGH only when all its inputs are HIGH (i.e. even if one input is LOW, Output will be LOW). If X and Y are two inputs, then output F can be represented mathematically as F = X.Y, Here dot (.) denotes the AND operation. Truth table and symbol of the AND gate is shown in the figure below. Symbol

Truth Table X 0 0 1 1 Y 0 1 0 1 F=(X.Y) 0 0 0 1

Two input AND gate using "diode-resistor" logic is shown in figure below, where X, Y are inputs and F is the output.

Digital Principles and System Design

DPSD

Circuit

If X = 0 and Y = 0, then both diodes D1 and D2 are forward biased and thus both diodes conduct and pull F low. If X = 0 and Y = 1, D2 is reverse biased, thus does not conduct. But D1 is forward biased, thus conducts and thus pulls F low. If X = 1 and Y = 0, D1 is reverse biased, thus does not conduct. But D2 is forward biased, thus conducts and thus pulls F low. If X = 1 and Y = 1, then both diodes D1 and D2 are reverse biased and thus both the diodes are in cut-off and thus there no drop in voltage at F. Thus F is HIGH. is

Switch Representation of AND Gate In the figure below, X and Y are two switches which have been connected in series (or just cascaded) with the load LED and source battery. When both switches are closed, current flows to LED.

Three Input AND gate Since we have already seen how a AND gate works and I will just list the truth table of a 3 input AND gate. The figure below shows its symbol and truth table. Circuit

Digital Principles and System Design

DPSD

Truth Table X 0 0 0 0 1 1 1 1 OR Gate

Y 0 0 1 1 0 0 1 1

Z 0 1 0 1 0 1 0 1

F=X.Y.Z 0 0 0 0 0 0 0 1

The OR gate performs logical addition, commonly known as OR function. The OR gate has two or more inputs and single output. The output of OR gate is HIGH only when any one of its inputs are HIGH (i.e. even if one input is HIGH, Output will be HIGH). If X and Y are two inputs, then output F can be represented mathematically as F = X+Y. Here plus sign (+) denotes the OR operation. Truth table and symbol of the OR gate is shown in the figure below. Symbol

Truth Table X 0 0 1 1 Y 0 1 0 1 F=(X+Y) 0 1 1 1

Two input OR gate using "diode-resistor" logic is shown in figure below, where X, Y are inputs and F is the output. Circuit

If X = 0 and Y = 0, then both diodes D1 and D2 are reverse biased and thus both the diodes are in cut-off and thus F is low. If X = 0 and Y = 1, D1 is reverse biased, thus does not conduct. But D2 is forward biased, thus conducts and thus

Digital Principles and System Design

pulling F to HIGH.

DPSD

If X = 1 and Y = 0, D2 is reverse biased, thus does not conduct. But D1 is forward biased, thus conducts and thus pulling F to HIGH. If X = 1 and Y = 1, then both diodes D1 and D2 are forward biased and thus both the diodes conduct and thus F is HIGH. Switch Representation of OR Gate In the figure, X and Y are two switches which have been connected in parallel, and this is connected in series with the load LED and source battery. When both switches are open, current does not flow to LED, but when any switch is closed then current flows.

Three Input OR gate Since we have already seen how an OR gate works, I will just list the truth table of a 3-input OR gate. The figure below shows its circuit and truth table.

Truth Table X 0 0 0 0 1 1 1 1 Y2 = I4 + I5 + I6 +I7

Y 0 0 1 1 0 0 1 1

Z 0 1 0 1 0 1 0 1

F=X+Y+Z 0 1 1 1 1 1 1 1

Based on the above equations, we can draw the circuit as shown below Circuit

Digital Principles and System Design

DPSD

Example - Decimal-to-Binary Encoder Decimal-to-Binary take 10 inputs and provides 4 outputs, thus doing the opposite of what the 4-to-10 decoder does. At any one time, only one input line has a value of 1. The figure below shows the truth table of a Decimal-to-binary encoder.

Truth Table I0 1 0 0 0 0 0 0 0 0 0 I1 0 1 0 0 0 0 0 0 0 0 I2 0 0 1 0 0 0 0 0 0 0 I3 0 0 0 1 0 0 0 0 0 0 I4 0 0 0 0 1 0 0 0 0 0 I5 0 0 0 0 0 1 0 0 0 0 I6 0 0 0 0 0 0 1 0 0 0 I7 0 0 0 0 0 0 0 1 0 0 I8 0 0 0 0 0 0 0 0 1 0 I9 0 0 0 0 0 0 0 0 0 1 Y3 0 0 0 0 0 0 0 0 1 1 Y2 0 0 0 0 1 1 1 1 0 0 Y1 0 0 1 1 0 0 1 1 0 0 Y0 0 1 0 1 0 1 0 1 0 1

From the above truth table , we can derive the functions Y3, Y2, Y1 and Y0 as given below. Y3 = I8 + I9 Y2 = I4 + I5 + I6 + I7 Y1 = I2 + I3 + I6 + I7 Y0 = I1 + I3 + I5 + I7 + I9 Priority Encoder If we look carefully at the Encoder circuits that we got, we see the following limitations. If more then two inputs are active simultaneously, the output is unpredictable or rather it is not what we expect it to be. This ambiguity is resolved if priority is established so that only one input is encoded, no matter how many inputs are active at a given point of time. The priority encoder includes a priority function. The operation of the priority encoder is such that if two or more inputs are active at the same time, the input having the highest priority will take precedence. Example - 4to3 Priority Encoder The truth table of a 4-input priority encoder is as shown below. The input D3 has the highest priority, D2 has next highest priority, D0 has the lowest priority. This means output Y2 and Y1 are 0 only when none of the inputs D1, D2, D3 are high and only D0 is high. A 4 to 3 encoder consists of four inputs and three outputs, truth table and symbols of which is shown below.

Digital Principles and System Design

Truth Table D3 0 0 0 0 1 D2 0 0 0 1 x D1 0 0 1 x x D0 0 1 x x x Y2 0 0 0 0 1 Y1 0 0 1 1 0

DPSD

Y0 0 1 0 1 0

Now that we have the truth table, we can draw the Kmaps as shown below. Kmaps

From the Kmap we can draw the circuit as shown below. For Y2, we connect directly to D3.

We can apply the same logic to get higher order priority encoders.

Digital Principles and System Design

Multiplexer A multiplexer (MUX) is a digital switch which connects data from one of n sources to the output. A number of

DPSD

select inputs determine which data source is connected to the output. The block diagram of MUX with n data sources of b bits wide and s bits wide select line is shown in below figure.

MUX acts like a digitally controlled multi-position switch where the binary code applied to the select inputs controls the input source that will be switched on to the output as shown in the figure below. At any given point of time only one input gets selected and is connected to output, based on the select input signal. Mechanical Equivalent of a Multiplexer The operation of a multiplexer can be better explained using a mechanical switch as shown in the figure below. This rotary switch can touch any of the inputs, which is connected to the output. As you can see at any given point of time only one input gets transferred to output.

Example - 2x1 MUX A 2 to 1 line multiplexer is shown in figure below, each 2 input lines A to B is applied to one input of an AND gate. Selection lines S are decoded to select a particular AND gate. The truth table for the 2:1 mux is given in the table below.

Symbol

Digital Principles and System Design

DPSD

Truth Table S 0 1

Y A B

Design of a 2:1 Mux To derive the gate level implementation of 2:1 mux we need to have truth table as shown in figure. And once we have the truth table, we can draw the K-map as shown in figure for all the cases when Y is equal to '1'. Combining the two 1' as shown in figure, we can drive the output y as shown below Y = A.S' + B.S

Truth Table B 0 0 0 0 1 1 1 1 Kmap

A 0 0 1 1 0 0 1 1 0

S 0 1 1 0 1 0 1

Y 0 0 1 0 0 1 1 1

Circuit

Example : 4:1 MUX A 4 to 1 line multiplexer is shown in figure below, each of 4 input lines I0 to I3 is applied to one input of an AND gate. Selection lines S0 and S1 are decoded to select a particular AND gate. The truth table for the 4:1 mux is given in the table below.

Digital Principles and System Design

DPSD

Symbol

CKT

Truth Table S1 0 0 1 1

S0 0 1 0 1

Y I0 I1 I2 I3

Larger Multiplexers Larger multiplexers can be constructed from smaller ones. An 8-to-1 multiplexer can be constructed from smaller multiplexers as shown below.

Example - 8-to-1 multiplexer from Smaller MUX Truth Table S2 0 0 0 0 1 1 1 1

S1 0 0 1 1 0 0 1 1

S0 0 1 0 1 0 1 0 1

F I0 I2 I3 I4 I5 I6 I7

Digital Principles and System Design

Circuit

DPSD

Example - 16-to-1 multiplexer from 4:1 mux \ DEMULTIPLEXER: They are digital switches which connect data from one input source to one of n outputs. Usually implemented by using n-to-2n binary decoders where the decoder enable line is used for data input of the de-multiplexer. The figure below shows a de-multiplexer block diagram which has got s-bits-wide select input, one b-bits-wide data input and n b-bits-wide outputs.

Mechanical Equivalent of a De-Multiplexer The operation of a de-multiplexer can be better explained using a mechanical switch as shown in the figure below. This rotary switch can touch any of the outputs, which is connected to the input. As you can see at any given point of time only one output gets connected to input.

Digital Principles and System Design

DPSD

1-bit 4-output de-multiplexer using a 2x4 binary decoder.

Example: 1-to-4 De-multiplexer Symbol

Truth Table S1 0 0 1 1

S0 0 1 0 1

F0 D 0 0 0

F1 0 D 0 0

F2 0 0 D 0

F3 0 0 0 D

BOOLEAN IMPLEMENTATION: Earlier we had seen that it is possible to implement Boolean functions using decoders. In the same way it is also possible to implement Boolean functions using muxers and de-muxers. Implementing Functions Multiplexers Any n-variable logic function can be implemented using a smaller 2n-1-to-1 multiplexer and a single inverter (e.g 4-to-1 mux to implement 3 variable functions) as follows. Express function in canonical sum-of-minterms form. Choose n-1 variables as inputs to mux select lines. Construct the truth table for the function, but grouping inputs by selection line values (i.e select lines as most significant inputs). Determine multiplexer input line i values by comparing the remaining input variable and the function F for the corresponding selection lines value i. We have four possible mux input line i values:

Digital Principles and System Design

DPSD

Connect to 0 if the function is 0 for both values of remaining variable. Connect to 1 if the function is 1 for both values of remaining variable. Connect to remaining variable if function is equal to the remaining variable. Connect to the inverted remaining variable if the function is equal to the remaining variable inverted.

Example: 3-variable Function Using 8-to-1 mux Implement the function F(X,Y,Z) = S(1,3,5,6) using an 8-to-1 mux. Connect the input variables X, Y, Z to mux select lines. Mux data input lines 1, 3, 5, 6 that correspond to the function minterms are connected to 1. The remaining mux data input lines 0, 2, 4, 7 are connected to 0.

Example: 3-variable Function Using 4-to-1 mux Implement the function F(X,Y,Z) = S(0,1,3,6) using a single 4-to-1 mux and an inverter. We choose the two most significant inputs X, Y as mux select lines. Construct truth table. Truth Table Select i 0 0 1 1 2 2 3 3 X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 F 1 1 0 1 0 0 1 0 Mux Input i 1 1 Z 0 0 Z' Z'

Circuit

Digital Principles and System Design

DPSD

We determine multiplexer input line i values by comparing the remaining input variable Z and the function F for the corresponding selection lines value i when XY=00 the function F is 1 (for both Z=0, Z=1) thus mux input0 = 1 when XY=01 the function F is Z thus mux input1 = Z when XY=10 the function F is 0 (for both Z=0, Z=1) thus mux input2 = 0 when XY=11 the function F is Z' thus mux input3 = Z'

Example: 2 to 4 Decoder using Demux

Mux-Demux Application Example This enables sharing a single communication line among a number of devices. At any time, only one source and one destination can use the communication line.

INTRODUCTION Arithmetic circuits are the ones which perform arithmetic operations like addition, subtraction, multiplication, division, parity calculation. Most of the time, designing these circuits is the same as designing muxers, encoders and decoders. In the next few pages we will see few of these circuits in detail. Adders Adders are the basic building blocks of all arithmetic circuits; adders add two binary numbers and give out sum and carry as output. Basically we have two types of adders. Half Adder. Full Adder.

Digital Principles and System Design

DPSD

Half Adder Adding two single-bit binary values X, Y produces a sum S bit and a carry out C-out bit. This operation is called half addition and the circuit to realize it is called a half adder. Truth Table X 0 0 1 1 Symbol

Y 0 1 0 1 Circuit

SUM 0 1 1 0

CARRY 0 0 0 1

S (X,Y) = (1,2) S = X'Y + XY' S=X Y CARRY(X,Y) = (3) CARRY = XY

Full Adder Full adder takes a three-bits input. Adding two single-bit binary values X, Y with a carry input bit C-in produces a sum bit S and a carry out C-out bit. Truth Table X 0 0 0 0 1 1 1 1

Y 0 0 1 1 0 0 1 1

Z 0 1 0 1 0 1 0 1

SUM 0 1 1 0 1 0 0 1

CARRY 0 0 0 1 0 1 1 1

SUM (X,Y,Z) = (1,2,4,7) CARRY (X,Y,Z) = (3,5,6,7)

Digital Principles and System Design

DPSD

Kmap-SUM

Kmap-CARRY

SUM = X'Y'Z + XY'Z' + X'YZ' SUM = X Y Z

CARRY = XY + XZ + YZ

Full Adder using AND-OR The below implementation shows implementing the full adder with AND-OR gates, instead of using XOR gates. The basis of the circuit below is from the above Kmap. Circuit-SUM Circuit-CARRY

Full Adder using AND-OR Circuit-SUM Circuit-CARRY

Digital Principles and System Design

n-bit Carry Ripple Adder An n-bit adder used to add two n-bit binary numbers can be built by connecting n full adders in series. Each full adder represents a bit position j (from 0 to n-1). Each carry out C-out from a full adder at position j is connected to the carry in C-in of the full adder at higher position j+1. The output of a full adder at position j is given by: Sj= Xj Cj+1 = Xj . Yj + Xj . Cj + Y . Cj In the expression of the sum Cj must be generated by the full adder at lower position j. The propagation delay in each full adder to produce the carry is equal to two gate delays = 2 D Since the generation of the sum requires the propagation of the carry from the lowest position to the highest position , the total propagation delay of the adder is approximately: Total Propagation delay = 2 nD 4-bit Carry Ripple Adder Adds two 4-bit numbers: X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 producing the sum S = S3 S2 S1 S0 , C-out = C4 from the most significant position j=3 Total Propagation delay = 2 nD = 8D or 8 gate delays Yj Cj

DPSD

Larger Adder Example: 16-bit adder using 4 4-bit adders. Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15) producing a 16-bit Sum S (bits S0 to S15) and a carry out C16 from the most significant position.

Digital Principles and System Design

DPSD

Propagation delay for 16-bit adder = 4 x propagation delay of 4-bit adder = 4 x 2 nD = 4 x 8D = 32 D or 32 gate delays Carry Look-Ahead Adder The delay generated by an N-bit adder is proportional to the length N of the two numbers X and Y that are added because the carry signals have to propagate from one full-adder to the next. For large values of N, the delay becomes unacceptably large so that a special solution needs to be adopted to accelerate the calculation of the carry bits. This solution involves a "look-ahead carry generator" which is a block that simultaneously calculates all the carry bits involved. Once these bits are available to the rest of the circuit, each individual three-bit addition (Xi+Yi+carry-ini) is implemented by a simple 3-input XOR gate. The design of the look-ahead carry generator involves two Boolean functions named Generate and Propagate. For each input bits pair these functions are defined as: Gi = Xi . Yi Pi = Xi + Yi The carry bit c-out(i) generated when adding two bits Xi and Yi is '1' if the corresponding function Gi is '1' or if the c-out(i1)='1' and the function Pi = '1' simultaneously. In the first case, the carry bit is activated by the local conditions (the values of Xi and Yi). In the second, the carry bit is received from the less significant elementary addition and is propagated further to the more significant elementary addition. Therefore, the carry_out bit corresponding to a pair of bits Xi and Yi is calculated according to the equation: carry_out(i) = Gi + Pi.carry_in(i-1) For a four-bit adder the carry-outs are calculated as follows carry_out0 = G0 + P0 . carry_in0 carry_out1 = G1 + P1 . carry_out0 = G1 + P1G0 + P1P0 . carry_in0 carry_out2 = G2 + P2G1 + P2P1G0 + P2P1P0 . carry_in0 carry_out3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1 . carry_in0 The set of equations above are implemented by the circuit below and a complete adder with a look-ahead carry generator is next. The input signals need to propagate through a maximum of 4 logic gate in such an adder as opposed to 8 and 12 logic gates in its counterparts illustrated earlier.

Digital Principles and System Design

DPSD

Sums can be calculated from the following equations, where carry_out is taken from the carry calculated in the above circuit sum_out0 = X 0 sum_out1 = X 1 sum_out2 = X 2 sum_out3 = X 3 Y0 Y1 Y2 Y3 carry_out0 carry_out1 carry_out2 carry_out3

BCD Adder BCD addition is the same as binary addition with a bit of variation: whenever a sum is greater than 1001, it is not a valid BCD number, so we add 0110 to it, to do the correction. This will produce a carry, which is added to the next BCD position. Add the two 4-bit BCD code inputs. Determine if the sum of this addition is greater than 1001; if yes, then add 0110 to this sum and generate a carry to the next decimal position

Digital Principles and System Design

Subtracter

DPSD

Subtracter circuits take two binary numbers as input and subtract one binary number input from the other binary number input. Similar to adders, it gives out two outputs, difference and borrow (carry-in the case of Adder). There are two types of subtracters. Half Subtracter. Full Subtracter.

Half Subtracter The half-subtracter is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow). The logic symbol and truth table are shown below. Symbol

Truth Table X 0 0 1 1 Y 0 1 0 1 D 0 1 1 0 B 0 1 0 0

From the above table we can draw the Kmap as shown below for "difference" and "borrow". The boolean expression for the difference and Borrow can be written.

From the equation we can draw the half-subtracter as shown in the figure

Digital Principles and System Design

DPSD

Full Subtracter A full subtracter is a combinational circuit that performs subtraction involving three bits, namely minuend, subtrahend, and borrow-in. The logic symbol and truth table are shown below. Symbol

Truth Table X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Bin 0 1 0 1 0 1 0 1 D 0 1 1 0 1 0 0 1 Bout 0 1 1 1 0 0 0 1

From above table we can draw the Kmap as shown below for "difference" and "borrow". The boolean expression for difference and borrow can be written. D = X'Y'Bin + X'YBin' + XY'Bin' + XYBin = (X'Y' + XY)Bin + (X'Y + XY')Bin' = (X Y)'Bin + (X Y)Bin' = X Y Bin Bout = X'.Y + X'.Bin + Y.Bin

From the equation we can draw the half-subtracter as shown in figure .

Digital Principles and System Design

DPSD

From the above expression, we can draw the circuit below. If you look carefully, you will see that a full-subtracter circuit is more or less same as a full-adder with slight modification.

Parallel Binary Subtracter Parallel binary subtracter can be implemented by cascading several full-subtracters. Implementation and associated problems are those of a parallel binary adder, seen before in parallel binary adder section. Below is the block level representation of a 4-bit parallel binary subtracter, which subtracts 4-bit Y3Y2Y1Y0 from 4-bit X3X2X1X0. It has 4-bit difference output D3D2D1D0 with borrow output Bout.

Serial Binary Subtracter A serial subtracter can be obtained by converting the serial adder using the 2's complement system. The subtrahend is stored in the Y register and must be 2's complemented before it is added to the minuend stored in the X register. The circuit for a 4-bit serial subtracter using full-adder is shown in the figure below.

Digital Principles and System Design

Comparators

DPSD

Comparators can compare either a variable number X (xn xn-1 ... x3 x2 x1) with a predefined constant C (cn cn-1 ... c3 c2 c1) or two variable numbers X and Y. In the first case the implementation reduces to a series of cascaded AND and OR logic gates. If the comparator answers the question 'X>C?' then its hardware implementation is designed according to the following rules: The number X has two types of binary figures: bits corresponding to '1' in the predefined constant and bits corresponding to '0' in the predefined constant. The bits of the number X corresponding to '1' are supplied to AND gates The bits corresponding to '0' are supplied to OR logic gates If the least significant bits of the predefined constant are '10' then bit X0 is supplied to the same AND gate as bit X1. If the least significant bits of the constant are all '1' then the corresponding bits of the number X are not included in the hardware implementation. All other relations between X and C can be transformed in equivalent ones that use the operator '>' and the NOT logic operator as shown in the table below. Initial relationship to be tested X&lt;C X<= C X >= C Equivalent relationship to be implemented NOT (X>C-1) NOT (X>C) X>C-1

The comparison process of two positive numbers X and Y is performed in a bit-by-bit manner starting with the most significant bit: If the most significant bits are Xn='1' and Yn='0' then number X is larger than Y. If Xn='0' and Yn='1' then number X is smaller than Y. If Xn=Yn then no decision can be taken about X and Y based only on these two bits.

If the most significant bits are equal then the result of the comparison is determined by the less significant bits Xn-1 and Yn-1. If these bits are equal as well, the process continues with the next pair of bits. If all bits are equal then the two numbers are equal.

MEMORIES Semiconductor memories are classified in different ways. A distinction is made between read-only (ROM) and readwrite (RWM) memories. The contents RWMs can be changed in a short time for a virtually unlimited number of times and contents of ROMs are mostly useful for frequent reading and occasional writing. Since RWM memories use active circuitry

Digital Principles and System Design

DPSD

(transistors) to store the information, they belong to the class of called volatile memories. This is because he data would be lost when the supply voltage is turned off. Read-only memories, on the other hand, encode information by the presence or absence of devices. Their data cannot be modified and they belong to the class of nonvolatile memories. That means the stored data is lost by the disconnection of supply voltage. Table 1 : Classification Semiconductor Memories RWM Random Access Non Random Access SRAM DRAM FIFO E2PROM Shift Register FLASH Static Random Access Memory (SRAM) A single SRAM memory cell is shown in Fig. 5. Two NMOS and two PMOS transistors (M1 to M4) forms the simple latch to store the data and two pass NMOS transistors (M5 and M6) are controlled by Word Line to pass Bit Line and into the cell. Programmable ROM

NVRWM ROM EPROM Mask-programmed ROM

with values that are desired to be stored A Write operation is performed by first charging the Bit Line and in the memory cell. Setting the Word Line high performs the actual write operation, and the new data is latched into the circuit.

A Read operation is initiated by pre-charging both Bit Line and

to logic 1.

Word Line is set high to close NMOS pass transistors to put the contents stored in the cell on the Bit Line and . Transistors M1 to M4 constitute the latch and are constantly toggling back and forth. During these switching the power consumption in CMOS circuits takes place and therefore, the sizes of these transistors are kept as small as possible. NMOS transistors are basically switches opening and closing access to the SRAM cell. To minimize the propagation delay caused by these transistors their sizes are kept relatively larger. Dynamic Random Access Memory (DRAM) DRAM stores each bit in a storage cell consisting of a capacitor and a transistor. Capacitors tend to lose their charge rather quickly; thus, the need for recharging. The presence or absence of charge in the capacitor determines whether the cell contains a '1' or a '0'. The Read operation begins by precharging the bit line to an intermediate value, .

The word line is raised to a high potential and the charge stored on capacitor is shared with that on the bit line. The change in the bit line voltage is given by the change on the bit line capacitor when the charge stored on capacitor C is shared with the bit line. Based on the access pattern, RWMs are classified as random access class and serial memories. FIFO (first-in-firstout) is an example for serial memories. Most memories belong to the random access class, which means memory

Digital Principles and System Design

DPSD

locations can be read or written in random order. One would expect memories of this class to be called RAM (random access memory); nevertheless for historic reasons, RAM has been reserved for random access RWM memories. That means though most ROM units also provide random access, but the acronym RAM should not be used for them. VOLATILE MEMORIES Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) are volatile memories. SRAM is used as a cache memory in computers since it offers the fastest write/read (~8ns) speed among all memories. Hardware design of a single SRAM cell consists of 6 transistors. A DRAM cell consists of one transistor and one capacitor and it is based on the charge stored in a capacitor. It is superior to SRAM because of its low cost per bit storage; nevertheless it is slower (`50ns). In DRAM, the stored charge in the capacitor can be maintained only for few milli-seconds and therefore, an extra hardware circuit is needed to periodically refresh the data periodically. NON-VOLATILE MEMORIES Based on the programmability of the devices non-volatile memories are categorized as follows. Writing data into ROMs is possible only at the time of manufacturing the devices and used only for reading the data stored. Even though these devices are less in cost the constraint that they are to be programmed at the time of manufacturing is an inconvenience. PROM devices are one time programmable ROM. At the time of device manufacturing every cell is stored with "1" and can be programmed by customer once. But, single write phase makes them unattractive. For instance, a single error in the programming process or application makes the device unusable. EPROM is Erasable PROM. Multiple times programming feature is added in EPROM. In this case, first whole memory is to be erased by shining ultraviolet light. The erase process is slow and can take from seconds to several minutes, depending on the intensity of the UV source. Programming takes several (5-10) /word. EPROM cell is extremely simple and dense, making it possible to fabricate large memories at a low cost. EPROMs were therefore attractive in applications that not require frequent programming. Electrically-Erasable PROM (EEPROM) can be erased without removing from board, unlike in UV erasable where memory must be removed from the board. The voltage approximately applied for programming is 18V. In addition, it is a reverse process; means by applying high negative voltage at gate can erase the cell. Another advantage over EPROM is that EEPROM can be programmed for 105 cycles. C C