Lecture Note 292311150242100
Lecture Note 292311150242100
TOPICS COVERED:-
1. Introduction to the general concept of microprocessor
2. I/O subsystem , programming the system
3. ALU
4. Instruction execution, instruction word format
5. Addressing modes
6. Address/data/control bus
7. Tristate bus
8. Interfacing i/o device
9. Data transfer scheme
10. Architectural advancement of microprocessor
11. Evolution of processor
INTRODUCTION
A computer basically consists of the following parts:-
1. I/O devices
2. Memory
3. CPU
The CPU is the brain of the computer irrespective of its size. The CPU normally consists of a large
scale integrationcircuit called Microprocessor and works as central processing unit of a
microcomputer.
Input Devices give data or information as an input to the CPU and it processes the data or
information given by the devices. Memory stores the data or information, Output Devices give the
required data as output to the user.
A digital component in which one microprocessor has been provided to act as a CPU is known as
Microcomputer. Desktop computer, laptop computer, palm computer, notebook are the ones which
contain only one microprocessor to act as a CPU.
Microprocessor:-
• An ALU is a combinational circuit that performs arithmetic and logical operation on the data
stored in accumulator.
• Results of operation by ALU are placed back in the accumulator.
• Typical operations performed by ALU includes add, shift/rotate, compare, increment,
decrement, AND, OR, XOR, complement, clear, pre-set etc.
• Apart from performing these operation, ALU also contains important information about
certain conditions that occur during these mathematical operation.
• These conditions i.e. occurrence of carry, borrow, zero, negative or even parity results are
stored in register called flag register and the individual bits are called flag bits.
• The number of bits is the most important factor determining the capabilities of the
processor. Hence the size of ALU defines the size of the microprocessor.
Instruction Execution
The microprocessor performs operations by accepting instructions from the user. Every
program consists of a sequence of instructions. The commands of n instruction set are called
‘mnemonics’. A command is understood by the CPU only when it is converted into
equivalent single byte hexadecimal opcodes with or without one-byte or two byte data or
address.
An instruction consists of:-
1. Opcode (operational code)
2. Operand(Operational End)
Instruction format
Intel 8085 handles 8 bit of data as it is an 8 bit microprocessor. It is designed to process 8 bit of data at a
time. If a 16 bit data has to be stored then they are stored in consecutive memory locations.
8 bit or 16 bit data may be directly given in the instruction. E.g. ADI 07H, LXI 7051H etc.
The address of the memory location or I/O devices may be given in the instruction itself. Ex LDA
8582H, IN 02H etc.
In some instructions only one register is specified. Ex ADD B
In some instructions we write two registers. Ex MOV D,E
In some instructions the data is implicit or implied. Ex CMA, RRC, RAL.
Addressing Modes
Addressing modes are an asset of the instruction set architecture in most CPU designs. The
various addressing modes that are defined in a given instruction set architecture define how
machine language instructions in that architecture identity the operand of each instruction. An
addressing mode specifies how to calculate the effective memory address of an operand by
using information held in register and/or constants contained within machine instruction or
elsewhere.
In type of addressing mode the address of the operand or the data is given to the instruction itself. This
type of mode is used to accept data from outside devices to store the data in the accumulator and send
the data stored in the accumulator to the output devices.
E.g. IN 02 (to accept the data from the port 02h and store the same in the accumulator)
OUT 01H (send the data from the accumulator to the output port)
In type of addressing mode the address is provided through the registers. Here the operand is GPR.
E.g. MOV Rd,Rs (move a copy of data from the source register to the destination register)
ADD B (add the content of b to the accumulator and the value is stored in the accumulator)
In type of addressing mode the address of the operand or the data is specified by a pair of register
before the execution of the instruction itself. Here the address of the memory is not directly given in the
instruction. The address of the memory resides in H-L pair and this has been already specified in an
earlier instruction.
E.g. LXI H, 8175; MOV B, M (move the data from memory specified by H-l pair to the register b)
LXI H, 8763; ADD M (Add the content of memory specified of the H-L pair to the accumulator)
in type of addressing mode the data is directly associated in the instruction itself. It loads immediate
data to the destination provided in the instruction.
ADI 62H (add 62 to the accumulator content and store the result in the accumulator)
There are certain instruction which are operated on the content of the accumulator. These types of
construction don’t require any address of the operand.
Eg. CMA (it finds the 1’s compliment of the data present in the accumulator and stores in accumulator)
RAL (rotate the content of accumulator left through carry)
BUS Structure
Various Input or Output
put devices and memory devices are connected to the CPU by a group of
conductors i.e. copper wires called buses. A typical microprocessor communicates with memory
and other I/O devices using 3 busses such as: - 1) Address bus 2) Data Bus 3) Control Bus
Address Bus:-
It carries the address of memory location or I/O devices that the CPU wants to access. When an
address is sent by the CPU, all devices connected to CPU through it receives the address but only
that device will respond which has also received tthe
he chip enable signal from CPU. The address
bus is Unidirectional i.e. address can send by microprocessor only. The number of memory
location that can be addressed by the CPU is determined by the number of address lines.
Data Bus:-
Control bus:-
The Tristate
tate logic devices have 3 states i.e. 0, 1, high impedance. Apart from input line it has a
third line called ENABLE. When the ENABLE line is activated the logic gate performs its
designated functions. But when ENABLE is disabled, it goes into a state High Impedance state.
I.e. gets disconnected from the rest of the circuit
In a tristate bus, there are a number of logic devices connected. Situations arise when you don’t need
the outputs of all of them simultaneously. In the diagra
diagram
m given above there are 3 logic devices given in a
bus, A, B and C. Sometimes we won’t need the outputs of al the 3. The output may require only one or
two of them to function at a time. In those situations, the ENABLE line is used to disconnect the logic
device which is not required. A Bus with this kind of feature is called a tristate bus.
ENABLE INPUT OUTPUT
0 0 0
1 1
1 0 OR 1 OR HIGH IMPEDANCE
There are two schemes for allocation of addresses memories and input and output devices:-
devices:
In this scheme the address assigned to memory locations can also be assigned to I/O devices. Since the
same address may be assigned to a memory location or an I/O device, the microprocessor must issue a
signal to distinguish whether the address on the address bus is for a memory location or an I/O device.
In this scheme I/O devices are treated the as a memory location and one address is assigned tot it. A
certain range of address is assigned to the devices and thereafter addresses are assigned to different
memory locations. In this scheme all the data transfer instructions of the microprocessor can be used
for both memory and I/O device.
ages of memory mapped I/O scheme over I/O mapped I/O scheme:
Advantages scheme:-
1. The IO read write instructions in I/O mapped I/O require the transfer from an IO port to
accumulator. The same data is then transferred to other registers from accumulator thus
wasting one instruction
uction and time. But with memory mapped scheme device can do transaction
with any of the registers.
2. The address modes of memory mapped scheme is more powerful than IO mapped IO. So more
efficient handling of IO devices can be achieved if they are interface
interfacedd to microprocessor in
memory mapped IO mechanism.
Serial data transfer: - Normally data transfer between two processors takes place serially. In this
mode the data is transferred serially one bit at a time. Due to this the in
in-connecting
connecting wires are
reduced in size.
Parallel data transfer: - The programmed I/O data transfer scheme, the user program controls
the data transfer. Parallel data transfer maybe of two types:
types:-
1. Synchronous: - This type of data transfer is used when device which sends data and devices
which receives data are synchronised with the same clock. Works when IO devices and the
CPU works with the same speed. IN/OUT instructions are used to transfer data from IO
devices to memory and vice versa. Generally used in IO mapped IO scheme, can also be used
with memory mapped IO scheme with proper memory read/write instruction. Data is
transferred as soon as CPU gives instruction to do so. There is no need to check if the device
is ready or not.
2. Asynchronous: - It means at “regular intervals”. This type of data transfer scheme is used
when speed of the IO device does not match with that of CPU. There is no predictability of
timing characteristics. The microprocessor always pings the other device to check whether
it’s ready or not. During initiation the CPU checks whether device is ready to transfer data,
before the actual transfer of data the memory keeps sending signal to IO device. This is
called handshaking. The CPU sends initialising signal to device during start and after actual
data transfer.
Interrupt Data transfer scheme: - The program initiates the program and then executes the
main program. When IO device is ready to transfer data, the interrupt signal becomes high.
The CPU completes the task at hand and then it attends to the IO device. It transfers the
data to the stack and then executes a subroutine called ISS (interrupt Service Subroutine).
ISS execution transfers data from IO device to memory and vice versa.
Direct memory access: - For bulk transfer to or from IO device the above mentioned
techniques might prove inefficient. So DMA process is ideal for transferring huge amount of
data. The IO device requests the microprocessor by sending a signal. After receiving this
request signal the CPU disconnects itself from memory and IO devices by tristating address,
data and control bus. The CPU sends the acknowledge signal to IO device. After this data
transfer takes place, and on completion IO device withdraws DMA request.
Advancement of architecture of microprocessor
1. Cache memory: - To speed up execution of data, a buffer between the CPU and memory
is used. It consists of high speed static ram. Execution speed is equal to microprocessor
speed.
2. Pipelining:- This is used to speed up execution of instruction. While the execution unit is
working on instructions, the queue in a CPU fetches the next set of instructions. As soon
as the working on instruction is over, the next set of instructions are fed into the
execution unit. There is no time wasted in fetching instructions. This technique is called
pipelining.
3. Multitasking or memory management: - Due to growth in hardware complexity of
computers, they were used in time sharing working environment. That means a fixed
amount of time is allocated to different programmes. To achieve relocatablity
segmented scheme is used.
4. Virtual memory system:- In this scheme the complete program is divided into several
pgs. and stored in hard disk. At same time the main memory is divided into small pages.
By this we can swap the pages between hard disk and main memory. This task is
performed by the operating system. Main memory size is bigger than physical memory
size which is correct.
EVOLUTION OF MICROPROCESSORS
FIRST GENERATION :
The first microprocessor is intel 4004. PMOS microprocessor introduced in he year 1971 nt the intel
corporation, USA. The enhanced version of this is intel 4040. Memory addressing capacity is 1kb, clock
frequency is 750 khz. No of pins is 16 and clock freq is defined as the no instruction that can be executed
in one sec.
SECOND GENERATION
The first 8 bit is microprocessor is intel 8008 introduced in the year 1972 which is a 8 bit
pmosmicroprocessor .in the year 1973, intel 8080 which is an 8 bit, nmos microprocessor was in
traduced which is faster and compatible to TTL than that of pmos technology. But intel 8080 requires
three power supplies so in the year 1975 intel 8085 , an 8 bit nmos microprocessor was introduced
which requires one power supply ie +5v dc. Memory addressing : -64 kb , clock frequency – 1mhz to
6mhz. No of pins 40.
THIRD GENERATION
In 1975, a 16 bit microprocessor was developed which is anhmos microprocessor. Memory addressing
capacity: i mb to 16 mb, clock frequency 6 to 12.5 mhz, no of pins -40
Intel 80186 and 80188 are integrated microprocessors beside cpu. They contain some additional
components that are PIC, DMA, PC Or timer, clock generator, peripheral chip select logic. Programmable
state generator and local bus controller etc. In intel 80286 besides cpu it has integrated memory
management unit, four level memory protections, it supports virtual memory and operating systems.
FOURTH GENERATION
After 1980, 32 bit microprocessors were produced. The first 32 bit microprocessor is iAPX 432. This is
not popular as it is eventually disconnected. The most powerful and very popular 32 bit microprocessor
is intel 80386. In short it is called intel-386. Memory addressing capacity 4gb, clock frequency-20 mhz to
in ghz. No of pins is 132 or more.
MODULE -2
INTEL 8086- HARDWARE ARCHITECTURE
INTRODUCTION:-
LIMITATION OF 8 BIT MICROPROCESSORS:
1. LOW SPEED OF EXICUTION
2. LOW MEMORY ADDRESSING CAPABILITY
3. LIMITED NUMBER OF GENERAL PURPOSE REGISTERS
4. LESS POWERFUL INSTRUCTION SET.
NOTE: - All these limitation of these 8 bit microprocessors were being over carried by a new
powerful output of 8086.
FEATURES OF 8086:
The function of both of these two units is that they perform their operation together. The BIU reads
the instruction operational codes from memory and store them into the instruction registers and at
the time of execution the instruction in the instruction register. Due to the fetching and execution of
an instruction happen together the 8286 microprocessors is called parallel processors.
BUS INTERFACE UNIT (BIU):
1. The bus interface unit contains the circuit for physical address calculation and pre decoding
instruction byte queue.
2. The BIU makes the system bus signal available for external interfacing of the device.
3. The unit is responsible for establishing communication with external device and
peripherals are including memory via the bus.
4. The complete physical address from contents which is 20bits long is generated using
segment and offset register.
5. For a generation of physical address from contents of these two registers the content of a
segment register also called as segment address is shifted left bit wise 4-times and to this
result, content of an offset register also called an offset address is added to produce a 20 bit
physical address.
6. The bus interface unit has a separate address to perform this procedure for obtaining a
physical address while addressing mode the segment address values is to be taken from an
appropriate segment register depending upon the offset may be the content of IP,
BX,SI,DI,SP,BP or an intermediate 16 bit values depending upon addressing mode.
7. In case of 8085 once operational code is fetched and decoded the external bus remain free
for same time while the processor internally executes.
While the fetched instruction is executed internally, the external bus is used
to fetch the machine code of the next instruction and arrange it I a queue known as
“PREDECODED INSTRUCTION BYTE QUEUE”.
8. The operational code is fetching by BIU and EU executes the previously decode instruction
concurrently. The BIU along with the EU perform a pipe line.
9. The BIU thus manages the complete interface execution unit with memory and input and
output decides under the control of timing and control unit.
EXECUTION UNIT:
1. The execution unit contains the register.
2. It has 16 bit ALU, able to perform arithmetic and logical operations.
3. The 16 bit flag register reflects the result of execution by the ALU.
4. The decoding unit decodes the opcode bytes issued from the instruction byte queue.
5. The execution unit may pass the result to the bus interface unit for storing them in memory.
FUNCTIONS:
These are the time multiplexed memory input , output address and data bus pins. The address part
(A0-A15) is transferred in T1 clock cycle and data are transferred in T2, T3, TW, T4 clock cycle. These
signals are stored by address latch enable (ALE) signals generated at a beginning of T1 states these
AD0- AD15 pins are traced in order to make AD0-AD15 lines receive the data signal.
0 0 EXTRA SEGMENT
0 1 STACK SEGMENT
1 0 CODE SEGMENT
1 1 DATA SEGMENT
• PIN NO.- 34
• TYPE- OUTPUT.
• FUNCTION
During T1 period (BHE)’ is low read , write and intercept acknowledgement operations ,
when a data byte is transferred on the data bus to form an odd address location or a 16 bit
transfer takes place from an even address on (D0-D15) data bus, the function of (BHE)’ is
shown in the table below.
(BHE)’ A0 OPERATION
0 0 16 BIT TRANSFER
1 1 NONE
READY:
PIN NO.- 22
TYPE- INPUT
FUNCTION:
The microprocessors sample , the ready signal at rising edge clock during T3 clock cycle, if the
signal is active high then microprocessors enter no wait states in its internal operation , otherwise
its enter wait state , in its internal operation.
INTR:
PIN NO.V- 18
TYPE- INPUT
FUNCTION:
This signal is sampled during last clock of each instruction to determine whether the
microprocessor should enter into an interrupt acknowledgement cycle.
(TEST)’:
PIN NO - 23
TYPE – INPUT
FUNCTION:
The signal is used in wait instruction before execution the instruction microprocessor check the
(TEST)’ pin status.
If TEST =1, then microprocessor will not enter into wait state , that is - execution will continue.
If TEST = 0, then the microprocessor will enter into wait state.
NMI(NON MARKABLE INTERRUPT):
PIN- 17
TYPE: - INPUT
FUNCTION:
This signal cannot be makeable internally by software. this is a edge triggered signal which cause a
type 2 interrupt when signal is active high interrupt service is vector to via an interrupt vector.
RESET:
PIN NO.- 21
TYPE- INPUT
FUNCTION:-
When this pin is high it immediate reset the microprocessor, When the pin status is high
immediately the segment count is FFFFH and so the base address at that moment is FFFF0H
3. REGISTER ORGANISATION:-
The INTEL 8086 contains the following register
(a) General purpose register
(b) Pointer and index register
(c) Segment register
(d) Instruction pointer
(e) Status Flags
(a) General Purpose register:-
(i) The AX, BX, CX and DX are the general purpose 16-bit register.
(ii) AX is used as 16-bit accumulator.
(iii) AX ->AH (For higher 8-bit)
AL (For lower 8-bit)
BX-> Serve as base register for the computation of memory address.
CX-> Used as counter in case of multi-iteration .
DX-> used for memory addressing when the data are transferred between i/o port and memory
using certain i/o instruction.
(b) Pointer and index register:-
(i) The Pointer IP,BP and SP usually contain in offset within the code and stack (Back SP and BP )
segment.
(ii) The index register are used as general purpose register as well as for offset storage in case of
indexed.
(iii)The register SI is generally used to store the offset of source data segment while the register Di
used to store the offset of destination in data or extra segment. The index register are particularly
useful for string manipulation.
SP- Stack Pointer
BP-Back Pointer
SI- Source Index
DI-Destination Index
IP- Index Pointer
(c) Segment register:-
CODE SEGMENT:-
It is used for addressing a memory location in the code segment of the memory ,where
the executable programmable is stored.
DATA SEGMENT:-
Data segment register points the data segment memory ,Where the data is reside.
EXTRA SEGMENT:-
It also refers to a segment which essentially is another data segment of the memory.
So extra segment also contains data.
STACK SEGMENT:-
It is used for addressing stack segment of
Memory i.e. memory which is used to store stacks data. It may be noted that all these
segments are the logical segment .They may or may not be physically separated.
(d) Instruction register:-
(i) The instruction pointer in 8086 acts as Program counter.
(ii) It points to the address of the next instruction to be executed .it’s content is
automatically incremented when the execution of program proceed further.
(f) Status Flags:-
The 8086 has a 16 bit flag register
(3)Auxiliary Flag:-
Set to be 1 when there is an unsigned overflow for low nibble (4 bits).
(4)Zero Flag:-
Set to be 1 when result is zero, for non-zero results this flag is set to 0.
(5)Sign Flag:-
Set to 1 when result is negative, when result is positive it is set to 0.
(6) Trap Flag:-
It is set; the processor enters the single step execution mode or a trap interrupt generated
after execution of each instruction.
(7)Direction Flag:-
This is used string manipulation instruction D=0, then the string is processed beginning
from lower address to the higher address.
D=1, then the string is processed beginning higher address to the lower address.
(8)Interrupt Flag:-
This flag is set, the mask able interrupt recognized by the CPU otherwise they are ignored.
(9)Overflow Flag:-
This flag is set, if an overflow occurs i.e. if the result signed operation is large enough to
accommodate in a destination register.
EF1:-
Pin no : 14
Type : Input
Function: It is called alternate clock input. It supplies externally generated clock signal.
The clock signal at EF1 is called fundamental frequency.
F/C’:-
Pin no. 18
Type : Input
Function: It is used for clock source selection whether the 8284 clock generator retake
clock source from x1, x2 or EF1.
OSC:-
Pin no : 12
Type : Output
Function: OSC is an oscillator output running at crystal or EF1 frequency.
PCLK:-
Pin no : 2
Type : Output
Function: It is TTL clock signal output for circuit. The frequency of PCLK is half of clock
frequency i.e. 50% duty cycle.
CSYNC:-
Pin no : 1
Type: Output
Function: It is used to synchronise the clock signal in a multiprocessor environment.
When CSYNC=1 the 8284 clock generator /driver is stopped.
When CSYNC=0 the clock output restart.
RES’:-
Pin no : 11
Type : Input
Function: This pin is called reset logic input. This signal is given by an external device
to reset the 8086 microprocessor.
RESET:-
Pin no : 10
Type : Output
Function: For a smooth operation the reset signal must be synchronised with clock.
RDY1, RDY2:-
Pin no : 4,6
Type : Input
Function: This pin enables the bus cycle extension by in sorting wait state between T3
and T4 clock period.
READY:-
Pin no : 5
Type : Output
Function: These pins are called wait state ready inputs. It is used by slower devices
to request for extension of bus cycle.
AEN1’, AEN2’:-
Pin no : 3,7
Type : Input
Function: To support multi bus configuration two ready inputs RDY1, RDY2 are
active. The AEN1’ and AEN2’ are there to provide arbitrate bus priorities when both
RDY1 and RDY2 are active.
ASYNC’:-
Pin no : 15
Type: This pin is called ready synchronization selection input. It selects either one or
two stage of synchronization for RDY1 and RDY2.
VCC:-
Pin no : 18
Function: connect to power source +5V.
GND:-
Pin no : 9
Type: Connect to ground.
The 8286 and 8287 are bidirectional system bus buffers or drivers. When the T pin is low,
the data at pins B. Will be sent to output through pin A.
When T is high the data at a pin will be send to output through pin B. OE’ is
low during data transfer operation.
The function of these two chips is same. The only difference lies with their drive capacity.
The 8286 transfers the data without altering them where as 8287 alter the data while
sending.
Generally the 8286 is used. The T pin 8286 is connected to DT/R’ pin of 8086
microprocessor and OE’ pin is connected to DEN’ pin of 8086 microprocessor.
MWTC’:-
Pin no : 9
Type : Output
Function : It is called Write control signal
AMWC’:-
Pin no : 8
Type : Output
Function : Advance memory write control signal its function is similar to MWTC’
IORC’:-
Pin no : 13
Type : Output
Function: I/O device read control signal.
IOWC’:-
Pin no : 11
Type: Output
Function: I/O device write control signal.
AIOWC’:-
Pin no : 12
Type : Output
Function: This pin is called advance I/O device write control signal. It activate just
before the IOWC’.
INTA’:-
Pin no : 14
Type : Output
Function: This pin is called interrupt acknowledgment. This signal is given by the
microprocessor to interrupting programme.
MCE/PDEN’:-
Pin no : 7
Type : Output
Function: This pin is called cascade /Peripheral data enable. It is used with 8259
programmable interrupt controller.
ALE:-
Pin no : 5
Type : Output
Function: Address latch enable pin.
DT/R’:-
Pin no: 4
Type : Output
Function : Data direction control signal
DEN:-
Pin no : 16
Type : Output
Function : data buffer control signal
GND:-
Pin no : 10
The 8288 Works In 2 mode like
I/O bus mode
System bus mode
T2:
In T2 state the bus is turned around.
RD’ status is low due to data read operation starts.
DEN’ status is made low to enable the 8286 transceiver.
DEN’ is made high if it was made low in T1 state.
The status is placed on A16 to A19 lines. All the activates start in T2 and continuous till
T4.
T3:
M/IO’ goes low.
RD’ goes high.
The status bits output on A16/S3 – A19/S6 will as shown in figure.
8. TIMING DIGRAM OF (MEMORY / IO ) WRITE:-
T1:
Ale is high.
BHE’ signal is made high / low depending on 8 / 16 bit write at odd or even address
boundary.
M/IO’ is made high to indicate memory operation. it remains high during the entire bus
cycle.
DT/R’ is high and remains high to indicate data transfer from microprocessor to
memory.
Address is put on the address bus. The falling edge of ALE is used to latch the address
from the address bus.
DEN’ goes low to enable the 8286 transceiver.
T2:
WR’ signal goes low due to write operation.
BHE’ goes low if it was made high in T1.
In T2 bus state is turned around.
Status is put on the address lines A16-A19 lines.
T3:
Data is placed on AD0-AD15.
T4:
M/IO’ goes low.
WR’ goes high.
DT/R’ goes low.
DEN’ goes high.
The 8282 latch is used to DE multiplex the address /Data bus line to separate address and
data bus .
The ALE (Address Latch Enable) Signal is used to latch the address from address and data
lines.
The 8284 clock generator is used to provide the CLK, READY, signals to the 8086
microprocessor.
The 8284 generates the ready signal in synchronization with clock based on input at RDY1
pin. The RDY2 pin is connected in this configuration.
The reset the 8086 microprocessor the reset pin remain high for 50ms.
The data bus is bidirectional in nature. To create a separate data bus from address/data bus
two Intel 8286 bidirectional bus Transceiver is used.
DT/R’ and DEN’ signal output of8086 microprocessor or are connected to 8086 as T and OE’
respectively.
10.INTERRUPT:-
An interrupt is an external event which informs the CPU that a device needs service.
Normally Program can be interrupt by three ways
(a)By External device
(b)By a special instruction In the program
(c)By the occurrence of some condition.
HARDWARE INTERRUPT:-
An interrupt caused by an external signal is referred as a hardware interrupt.
SOFTWARE INTERRUPT:-
Conditional interrupts or interrupts caused by special instructions are called software interrupt.
(i) TYPE-0 INTERRUPT:-
The divided by zero interrupt (type-0) automatically interrupt the 8086 when a divide
error occurs.
The interrupt will occur if the quotient resulting from a division instruction or an IDIV
(Integer Division) instruction is too large to fit in the destination register.
(iv)TYPE-3 INTERRUPT:-
Type-3 interrupt or break point is a very special single byte software interrupt.
The type-3 interrupt is produced by execution of the unit INT-3 instruction.
The main use of the type-3 interrupt is to implement a break point function in a system or
used debugging software.
In type-3 interrupt the system executes the instruction up to the break point and then
goes to the breakpoint procedure unlike the single step feature, which stop executing
about each instructions.
(v)TYPE-4 INTERRUPT:-
The interrupt on overflow is a type -4 interrupt and occurs when the flag is set and
INTO instruction executed.
The 8086 of will be set if the signed result or arithmetic operation on two signed
number is too large to represented in the destination result or memory location.
In maximum mode two signal RQ’/GT0’ and RQ1’/GT1’ are used for direct memory
access operation.
The DMA request and DMA acknowledgment signal are received on same line.
Thus RQ’/GT0’ and RQ1’/GT1’ are two channels for DMA by which two separate
external devices can access memory directly.
The external device make a request for DMA by sending a low pulse at RQ’/GT’ ,The
8086 microprocessor samples the RQ’/GT’ signal at low to high transition of clock
period.
The 8086 microprocessor acknowledgement the DMA request at the end of current bus
cycle by sending a low pulse on the same RQ’/GT’ pin .The address/data and control
signal float at the same time.
After competition of memory operation the external devices informs the 8086
microprocessor by sending a low pulse on the RQ”/GT’ pin .The 8086 microprocessor
by sending a low on this pin and low –to-high transition of clock regains the control of
lines.
8086 8088
1.8086 microprocessors is a 16 bit 1. The 8086 microprocessor is an 8bit
microprocessor, with 16bit internal and microprocessor with 16 bit internal and
external data bus. 8bit external data bus.
3. The instruction queue Length is 6 byte. 3. The instruction queue length is 4 byte.
4.8086 has 16 data pins ,So it fetch two byte 4.8088 has8 data pin .so whenever one
of instruction code only when two register register of iq become vacant then 8088 will
Of IQ (instruction queue) become code fetch in the instruction code byte.
byte.
Vacant.
5.The BHE’ pin used along With A0 to 5. Unlike the 8086, BHE’is not present in
access low, high Or Both byte from memory 8088. Therefore the external memory
location. interface will not have even byte from a
memory location.
MODULE 3
Instruction Set of 8086
The 8086 instructions are categorized into the following main types.
The programmable peripheral interface i s a low cost interfacing circuit used in many applications.its
function is to perform input output operation.it contains 3 I/O ports, 24 I/O pins which can be
programmed in three different modes.The various I/O operations can be performed by writing
instructions in its internal control word register. Along basic I/O operation it also performs time delay
generation counting generating signals and interrupts.
Features
DATABUS BUFFER
The 8 bit bidirectional data bus connected to data bus of the micro processor. The direction of
the data bus are decided by the read and write control signals . in read operation it transmit
data to the system bus and in write operation it receives data from system bus.
0 1 PORT B
1 0 PORT C
PIN CONFIGURATION
PA7-PA0
these 8 bit port lines act as input and output lines depending on control word loaded in control word
register(CWR)
Upper port c line act as input lines used for generation of hand shake lines in mode 1 a or mode 2.
PC3-PC0
Lower port c lines act as i/o lines can be used for hand shake signals.
PB7-PB0
these 8 bit port lines act as input and output lines depending on control word loaded in control word
register(CWR)
Input line driven by mp .it should be low to indicate read operation
Input line driven by mp .it should be low to indicate write operation.
Chip select
=0 ,8255 is selected else rejected and read write operation are neglected.
if
A1-A0
0 1 0 0 0 Port A->data
bus
1 0 0 0 0 Data bus to
port A
1 0 0 0 1 Data bus to
port B
1 0 0 1 0 Data bus to
port C
1 0 0 1 1 DATA BUS TO
CWR
X X 1 X X Data bus
tristated
1 1 0 X X Data bus
tristated
D0 –D7
These databus lines are used to carry data or control word to /from mp.
RESET
BSR MODE
1.This mode is used to set/reset the individual bits or ports(PC0---PC7)by writing appropriate control
word in CWR.
2.A control D7=0 is called BSR mode and it does not alter any previously tranamitted control word with
D7=1(parallei I/O mode) henceI/On operation of port A and B are not affected by BSR mode.
MODE 0 OPERATION
de, the ports can be used for simple I/O operations without handshaking signals. Port A, port B provide
simple I/O operation. The two halves of port C can be either used together as an additional 8-bit port, or
they can be used as inIn this modividual 4-bit ports. Since the two halves of port C are independent, they
may be used such that one-half is initialized as an input port while the other half is initialized as an output
port.
and A1 lines.
• The CPU then issues an RD signal to read the data from the external peripheral device via the
The
image …
• In the output mode, the CPU sends data to 8255 via system data bus and then the external
peripheral ports receive this data via 8255 port.
• CPU first selects the 8255 chip by making CS low. It then selects the desired port using A0 and
The
image …
A1 lines.
CPU then issues a WR signal to write data to the selected port via the system data bus. This data is
The
image …
then received by the external peripheral device connected to the selected port
MODE
1
When
we
wish
to use
port A
or
port B
for
handshake (strobed) input or output operation, we
Case 1
initialise that port in mode 1 (port A and port B can be initilalised to operate in different modes, i.e., for
e.g., port A can operate in mode 0 and port B in mode 1). Some of the pins of port C function as
handshake lines.
For port B in this mode (irrespective of whether is acting as an input port or output port), PC0, PC1 and
PC2 pins function as handshake lines.
If port A is initialised as mode 1 input port, then, PC3, PC4 and PC5 function as handshake signals. Pins
PC6 and PC7 are available for use as input/output lines.
1. Two ports i.e. port A and B can be used as 8-bit i/o ports.
2. Each port uses three lines of port c as handshake signal and remaining two signals can be used
as i/o ports.
3. Interrupt logic is supported.
4. Input and Output data are latched.
1. IBF(Input Buffer Full)-It is an output indicating that the input latch contains information.
2. STB(Strobed Input)-The strobe input loads data into the port latch, which holds the
information until it is input to the microprocessor via the IN instruction.
3. INTR(Interrupt request)-It is an output that requests an interrupt. The INTR pin becomes a
logic 1 when the STB input returns to a logic 1, and is cleared when the data are input from the
port by the microprocessor.
1. OBF(Output Buffer Full)-It is an output that goes low whenever data are output(OUT) to the
port A or port B latch. This signal is set to a logic 1 whenever the ACK pulse returns from the
external device.
2. ACK(Acknowledge)-It causes the OBF pin to return to a logic 1 level. The ACK signal is a
response from an external device, indicating that it has received the data from the 82C55 port.
3. INTR(Interrupt request)-It is a signal that often interrupts the microprocessor when the
external device receives the data via the signal. this pin is qualified by the internal INTE(interrupt
enable) bit.
4. INTE(Interrupt enable)-It is neither an input nor an output; it is an internal bit programmed to
enable or disable the INTR pin. The INTE A bit is programmed using the PC6 bit and INTE B is
programmed using the PC2 bit
Case 2
Case 3
Mode 2
Only group A can be initialised in this mode. Port A can be used for bidirectional handshake data
transfer. This means that data can be input or output on the same eight lines (PA0 - PA7). Pins PC4 - PC7
are used as handshake lines for port A. The remaining pins of port C (PC0 - PC3) can be used as
input/output lines if group B is initialised in mode 0 or as handshaking for port b if group B is initialised
in mode 1. In this mode, the 8255 may be used to extend the system bus to a slave microprocessor or to
transfer data bytes to and from a floppy disk controller.
INTR
This is an output signal given or generated by 8255 generated by 8255.A high on this output signal can
be used to interupt the mp for both input and output..
INPUT OPERATION
(strobe input)
1.
This is an active low input signal when peripheral write data to the input buffer the peripheral generates a
to indicate the 8255 that it has written data
signal1.
It is high in output signal and data loaded in the in larch and available in output buffer.
3.INTE1
OUTPUT OPERATION
1.
2.
It is internal flip flop signal controlled by bit set reset mode using pc6 bit of part B. i
The Intel 8254 is a counter/timer device designed to solve the common timing control
problems in microcomputer system design. It provides three independent 16-bit counters, each
capable of handling clock inputs upto 10 MHz.All modesare software programmable. The 8254
is a superset of the 8253.The 8254 uses HMOS technology and comes in a 24-pin plastic or
CERDIPP PACKAGE.
PIN CONFIGURATION
rrrryrrrRPin Description
D7-D0 1-8 I/O-DATA: Bi-directional three state data bus lines,connected to
system data bus.
CLK 09 I- CLOCK 0: Clock input of Counter 0.
OUT 0 10O-OUTPUT 0: Output of Counter 0.
GATE 0 11 I-GATE 0: Gate input of Counter 0.
GND 12 GROUND: Power supply connection.
A1 A0 Selects
0 0 Counter 0
0 1Counter 1
10 Counter 2
1 1 Control Word Register
CLK 2 18 I CLOCK 2: Clock input of Counter 2.
OUT 2 17 O OUT 2: Output of Counter 2.
GATE 2 16 I GATE 2: Gate input of Counter 2.
CLK 1 15 I CLOCK 1: Clock input of Counter 1.
GATE 1 14 I GATE 1: Gate input of Counter 1.
OUT 1 13 O OUT 1: Output of Counter 1.
FUNCTIONAL DESCRIPTION
The 8254 is a programmable interval timer/counterdesigned for use with Intel microcomputer
systems.It is a general purpose, multi-timing element that canbe treated as an array of I/O ports
in the system
software.The 8254 solves one of the most common problems in any microcomputer system, the
generation of accuratetime delays under software control. Instead ofsetting up timing loops in
software, the programmerconfigures the 8254 to match his requirements and
programs one of the counters for the desired delay.After the desired delay, the 8254 will
interrupt theCPU. Software overhead is minimal and variablelength delays can easily be
accommodated.Some of the other counter/timer functions commonto microcomputers which can
be implemented withthe 8254 are:
This 3-state, bi-directional, 8-bit buffer is used to interface the 8254 to the system bus.
READ/WRITE LOGIC
The Read/Write Logic accepts inputs from the system bus and generates control signals for the
otherfunctional blocks of the 8254. A1 and A0 select oneof the three counters or the Control
Word Register
to be read from/written into. A ``low'' on the RD inputtells the 8254 that the CPU is reading one
of thecounters. A ``low'' on the WR input tells the 8254that the CPU is writing either a Control
Word or aninitial count. Both RD and WR are qualified by CS;RD and WR are ignored unless
the 8254 has beenselected by holding CS low.
The Control Word Register (see Figure 4) is selectedby the Read/Write Logic when A1,A0e11. If
theCPU then does a write operation to the 8254, thedata is stored in the Control Word Register
and isinterpreted as a Control Word used to define theoperation of the Counters.TheControl
Word Register can only be written to;status information is available with the Read-
BacknCommand.
These three functional blocks are identical in operation,so only a single Counter will be
described. The Counters are fully independent. Each Countermay operate in a different
Mode.The Control Word Register is shown in the figure; itis not part of the Counter itself, but its
contents determinehow the Counter operates whenlatched, contains the current contents of the
ControlWord Register and status of the output and nullcount flag. (See detailed explanation of
the ReadBack command.)
The actual counter is labelled CE (for ``Counting Element'').It is a 16-bit presettable
synchronous downcounter.OLM and OLL are two 8-bit latches. OL stands for``Output Latch'';
the subscripts M and L stand for
``Most significant byte'' and ``Least significant byte''respectively. Both are normally referred to
as oneunit and called just OL. These latches normally ``follow''the CE, but if a suitable Counter
Latch Command
is sent to the 8254, the latches ``latch'' thepresent count until read by the CPU and then returnto
``following'' the CE. One latch at a time is enabledby the counter's Control Logic to drive the
internal
bus. This is how the 16-bit Counter communicatesover the 8-bit internal bus. Note that the CE
itselfcannot be read; whenever you read the count, it isthe OL that is being read. Similarly, there
are two 8-bit registers called CRMand CRL (for ``Count Register''). Both are normally
referred to as one unit and called just CR. When anew count is written to the Counter, the count
isstored in the CR and later transferred to the CE. TheControl Logic allows one register at a
time to beloaded from the internal bus. Both bytes are transferredto the CE simultaneously.
CRM and CRL arecleared when the Counter is programmed. In thisway, if the Counter has
been programmed for onebyte counts (either most significant byte only or leastsignificant byte
only) the other byte will be zero.Note that the CE cannot be written into; whenever a
count is written, it is written into the CR.The Control Logic is also shown in the diagram.CLK n,
GATE n, and OUT n are all connected to theoutside world through the Control Logic.
The 8254 is a component of the Intel Microcomputer Systems and interfaces in the same
manner as all other peripherals of the family. It is treated by thesystem's software as an array of
peripheral I/Oports; three are counters and the fourth is a control register for MODE
programming.Basically, the select inputs A0,A1 connect to the A0,
A1 address bus signals of the CPU. The CS canbederived directly from the address bus using a
linearselect method. Or it can be connected to the outputof a decoder, such as an Intel 8205 for
larger systems
Counters are programmed by writing a Control Wordand then an initial count.The Control Words
are written into the Control WordRegister, which is selected when A1,A0e 11. TheControl Word
itself specifies which Counter is beingprogrammed.
By contrast, initial counts are written into the Counters,not the Control Word Register. The
A1,A0inputsare used to select the Counter to be writteninto. The format of the initial count is
determined bythe Control Word used.
Mode Definitions
The following are defined for use in describing theoperation of the 8254.
CLK Pulse: a rising edge, then a falling edge, inthat order, of a Counter's CLK input.Trigger: a
rising edge of a Counter's GATEinput.
Counter loading: the transfer of a count from the CRto the CE (refer to the ``Functional
Description''
Mode 0 is typically used for event counting. After theControl Word is written, OUT is initially low,
and willremain low until the Counter reaches zero. OUT thengoes high and remains high until a
new count or anew Mode 0 Control Word is written into the Counter.GATEe 1 enables counting;
GATE e 0 disablescounting. GATE has no effect on OUT.
After the Control Word and initial count are written toa Counter, the initial count will be loaded
on the nextCLK pulse. This CLK pulse does not decrement thecount, so for an initial count of N,
OUT does not gohigh until N a 1 CLK pulses after the initial count iswritten.If a new count is
written to the Counter, it will beloaded on the next CLK pulse and counting will continuefrom the
new count. If a two-byte count is written,
the following happens:
1) Writing the first byte disables counting. OUT is setlow immediately (no clock pulse required)
2) Writing the second byte allows the new count tobe loaded on the next CLK pulse.
This allows the counting sequence to be synchronizedby software. Again, OUT does not go high
untilNa1 CLK pulses after the new count of N is written.If an initial count is written while GATE e
0, it will still be loaded on the next CLK pulse. When GATEgoes high, OUT will go high N CLK
pulses later; noCLK pulse is needed to load the Counter as this hasalready been done.
OUT will be initially high. OUT will go low on the CLKpulse following a trigger to begin the one-
shot pulse,and will remain low until the Counter reaches zero. OUT will then go high and remain
high until the CLKpulseafter the next trigger.After writing the Control Word and initial count,
theCounter is armed. A trigger results in loading theCounter and setting OUT low on the next
CLK pulse,thus starting the one-shot pulse. An initial count of Nwill result in a one-shot pulse N
CLK cycles in duration.
The one-shot is retriggerable, hence OUT willremain low for N CLK pulses after any trigger.
Theone-shot pulse can be repeated without rewriting thesame count into the counter. GATE has
no effect on
OUT.If a new count is written to the Counter during aoneshotpulse, the current one-shot is not
affected unlessthe counter is retriggered. In that case, theCounter is loaded with the new count
and the oneshotpulse continues until the new count expires.
MODE 2: RATE GENERATOR
This Mode functions like a divide-by-N counter. It is typically used to generate a Real Time
Clock interrupt.OUT will initially be high. When the initial counthas decremented to 1, OUT goes
low for one CLKpulse. OUT then goes high again, the Counter reloadsthe initial count and the
process is repeated.Mode 2 is periodic; the same sequence is repeated
indefinitely. For an initial count of N, the sequencerepeats every N CLK cycles.GATEe1 enables
counting; GATE e 0 disablescounting. If GATE goes low during an output pulse,OUT is set high
immediately. A trigger reloads theCounter with the initial count on the next CLK pulse;
OUT goes low N CLK pulses after the trigger. Thusthe GATE input can be used to synchronize
theCounter.After writing a Control Word and initial count, theCounter will be loaded on the next
CLK pulse. OUTgoes low N CLK Pulses after the initial count is written.This allows the Counter
to be synchronized bysoftwarealso.Writing a new count while counting does not affectthe
current counting sequence. If a trigger is receivedafter writing a new count but before the endof
the current period, the Counter will be loaded withthe new count on the next CLK pulse and
countingwill continue from the new count. Otherwise, thenew count will be loaded at the end of
the currentcounting cycle. In mode 2, a COUNT of 1 is illegal.
OUT will be initially high. When the initial count expires,OUT will go low for one CLK pulse and
thengo high again. The counting sequence is ``triggered''by writing the initial count.GATEe1
enables counting; GATE e 0 disablescounting. GATE has no effect on OUT.After writing a
Control Word and initial count, theCounter will be loaded on the next CLK pulse. ThisCLK pulse
does not decrement the count, so for an initial count of N, OUT does not strobe low until N a1
CLK pulses after the initial count is written.If a new count is written during counting, it will
beloaded on the next CLK pulse and counting will continuefrom the new count. If a two-byte
count is written,the following happens:
1) Writing the first byte has no effect on counting.
2) Writing the second byte allows the new count to
be loaded on the next CLK pulse.This allows the sequence to be ``retriggered'' bysoftware. OUT
strobes low N a 1 CLK pulses after
the new count of N is written.231164±11
READ-BACK COMMAND
The third method uses the Read-Back Command.This command allowsthe user to check the
countvalue, programmed Mode, and currentstates of the OUT pin and Null Count flag of the
selected counter(s).Thecommand applies to the counters selected by settingtheir corresponding
bits D3, D2, D1 e 1. The read-back command maybe used to latch multiplecounter output
latches (OL) by setting the
COUNT bit D5 e 0 and selecting the desired counter(s). This single command is functionally
equivalentto several counter latch commands, one foreach counter latched. Each counter's
latched countis held until it is read (or the counter is reprogrammed).The counter is
automatically unlatchedwhen read, but other counters remain latched until
they are read. If multiple count read-back commandsare issued to the same counter without
reading thecount, all but the first are ignored; i.e., the countwhich will be read is the count at the
time the first read-back command was issued.The read-back command may also be used to
latchstatus information of selected counter(s) by settingSTATUS bit D4 e 0. Status must be
latched to beread; status of a counter is accessed by a read fromthatcounter.The counter status
format is shown in Figure 11. BitsD5 through D0 contain the counter's programmedMode
exactly as written in the last Mode ControlWord. OUTPUT bit D7 contains thecurrent state ofthe
OUT pin. This allows the user to monitor thecounter's output via software, possibly eliminating
some hardware from a system.
DIRECT MEMORY ACCESS CONTROLER 8237
The 8237A Multimode Direct Memory Access (DMA) Controller is a peripheral interface circuit
for microprocessorsystems. It is designed to improve system performance by allowing external
devices to directly transferinformation from the system memory. Memory-to-memory transfer
capability is also provided. The 8237A
offers a wide variety of programmable control features to enhance data throughput and system
optimizationand to allow dynamic reconfiguration under program control.
The 8237A is designed to be used in conjunction with an external 8-bit address latch. It contains
four independent
channels and may be expanded to any number of channels by cascading additional controller
chips. Thethree basic transfer modes allow programmability of the types of DMA service by the
user. Each channel canbe individually programmed to Autoinitialize to its original condition
following an End of Process (EOP). Eachchannel has a full 64K address and word count
capability.
5.MODE
REGISTER:
Each of the DMA
channel has
an 8- bit mode
register.Bits
0 and 1 determine
which of the
4 channel is
to be written.Bits
2 and 3 indicates
the type of
DMA transfer.Bit
4 indicates
wheather auto
intialization is selected
or not.
6.REQUEST REGISTER:
Each channel has a request bit associated with it,in the request register.these are non-
maskable.This register is cleared by a reset.
7.MASK REGISTER:
Sometimes it may be
required to disable a
DMA request of a
certain
channel.This bit is set when the corresponding channel produces an EOP signal ‘if the channel
is not programmed for auto initialization.The register is set to FFH after a reset operation.This
disables all the DMA requests till the mask register is cleared.
8.STATUS REGISTER:
The status register keeps the track of all the DMA channel pending requests and status of their
terminal counts.The bits d0 –d3 are set every time ,the corresponding channel reaches TC.These
are cleared upon reset and also on each status read operation.Bits d4-d7 are set,if the
corresponding
channel request
service
PIN
CONFIGURATION
OF 8237
PIN
DESCRIPTION
CLOCK :Clock Input controls the internal operations of the8237A and its rate of data transfers.
The input may be driven at upto 5 MHz for the 8237A-5.
: Chip Select is an active low input used to selectthe 8237A as an I/O device during the Idle
cycle. This allows CPUcommunication on the data bus
RESET: Reset is an active high input which clears the Command,Status, Request and
Temporary registers. It also clears the first/last flip/flop and sets the Mask register. Following a
Reset thedevice is in the Idle cycle.
READY: Ready is an input used to extend the memory read andwrite pulses from the 8237A to
accommodate slow memories orI/O peripheral devices. Ready must not make transitions during
itsspecified setup/hold time
.
HOLD ACKNOWLEDGE: The active high Hold Acknowledge fromthe CPU indicates that it has
relinquished control of the system
DMA REQUEST: The DMA Request lines are individualasynchronous channel request inputs
used by peripheral circuitstoobtain DMA service. In fixed Priority, DREQ0 has the highestpriority
and DREQ3 has the lowest priority. A request is generatedby activating the DREQ line of a
channel. DACK will acknowledge the recognition of DREQ signal. Polarity of DREQ
isprogrammable. Reset initializes these lines to active high. DREQmust be maintained until the
corresponding DACK goes active.
DATA BUS: The Data Bus lines are bidirectional three-statesignals connected to the system
data bus. The outputs areenabled in the Program condition during the I/O Read to outputthe
contents of an Address register, a Status register, theTemporary register or a Word Count
register to the CPU. Theoutputs are disabled and the inputs are read during an I/O Writecycle
when the CPU is programming the 8237A control registers.During DMA cycles the most
significant 8 bits of the address are output onto the data bus to be strobed into an external latch
byADSTB. In memory-to-memory operations, data from the memorycomes into the 8237A on
the data bus during the read-frommemorytransfer. In the write-to-memory transfer, the data
busoutputs place the data
: I/O Read is a bidirectional active low three-state line.In the Idle cycle, it is an input control
signal used by the CPU toread the control registers. In the Active cycle, it is an output
controlsignal used by the 8237A to access data from a peripheral during aDMA Write transfer.
: I/O Write is a bidirectional active low three-state line.In the Idle cycle, it is an input control
signal used by the CPU toload information into the 8237A. In the Active cycle, it is an
outputcontrol signal used by the 8237A to load data to the peripheral
during a DMA Read transfer.
:End of Process is an active low bidirectionalsignal. Information concerning the completion
of DMA services isavailable at the bidirectional EOP pin. The 8237A allows anexternal signal to
terminate an active DMA service. This isaccomplished by pulling the EOP input low with an
external EOPsignal. The 8237A also generates a pulse when the terminal count(TC) for any
channel is reached. This generates an EOP signalwhich is output through the EOP line. The
reception of EOP, eitherinternal or external, will cause the 8237A to terminate the service,reset
the request, and, if Autoinitialize is enabled, to write the baseregisters to the current registers of
that channel. The mask bit andTC bit in the status word will be set for the currently active
channelby EOP unless the channel is programmed for Autoinitialize. In thatcase, the mask bit
remains unchanged. During memory-to-memorytransfers, EOP will be output when the TC for
channel 1 occurs.EOP should be tied high with a pull-up resistor if it is not used toprevent
erroneous end of process inputs.
A0 –A3:The four least significant address lines arebidirectional three-state signals. In the Idle
cycle they are inputsand are used by the CPU to address the register to be loaded orread. In
the Active cycle they are outputs and provide the lower 4bits of the output address.
A4 – A7: The four most significant address lines are three-stateoutputs and provide 4 bits of
address. These lines are enabledonly during the DMA service.
HRQ :This is the Hold Request to the CPU and isused to request control of the system bus. If
the correspondingmask bit is clear, the presence of any valid DREQ causes 8237A toissue the
HRQ.
DACK0 –DACK3 :DMA Acknowledge is used to notify theindividual peripherals when one has
been granted a DMA cycle.The sense of these lines is programmable.
AEN :Address Enable enables the 8-bit latchcontaining the upper 8 address bits onto the
system address bus.AEN can also be used to disable other system bus drivers duringDMA
transfers. AEN is active HIGH.
:The Memory Read signal is an active low threestateoutput used to access data from the
selected memorylocation during a DMA Read or a memory-to-memory transfer.
:The Memory Write is an active low three-stateoutput used to write data to the selected
memory location during aDMA Write or a memory-to-memory transfer.
PIN5: This pin should always be at a logic HIGH level. An internalpull-up resistor will establish a
logic high when the pin is leftfloating. It is recommended however, that PIN5 be connected
toVCC.
In Single Transfer modethe device is programmed to make one transfer only.The word count
will be decremented and the addressdecremented or incremented following eachtransfer. When
the word count ``rolls over'' from zero
to FFFFH, a Terminal Count (TC) will cause an Autoinitializeif the channel has been
programmed to doso.DREQ must be held active until DACK becomes activein order to be
recognized. If DREQ is held activethroughout the single transfer, HRQ will go inactiveand
release the bus to the system. It will again goactive and, upon receipt of a new HLDA,
anothersingle transfer will be performed. In 8080A, 8085AH,
8088, or 8086 system, this will ensure one full machinecycle execution between DMA transfers.
Detailsof timing between the 8237A and other buscontrol protocols will depend upon the
characteristicsof the microprocessor involved.
In Block Transfer mode thedevice is activated by DREQ to continue makingtransfers during the
service until a TC, caused byword count going to FFFFH, or an external End ofProcess (EOP) is
encountered. DREQ need only be
held active until DACK becomes active. Again, anAutoinitialization will occur at the end of the
serviceif the channel has been programmed for it.
CASCADE MODE
This mode is used to cascademore than one 8237A together for simple systemexpansion. The
HRQ and HLDA signals from the additional8237A are connected to the DREQ andDACK
signals of a channel of the initial 8237A. Thisallows the DMA requests of the additional device
topropagate through the priority network circuitry ofthe preceding device. The priority chain is
preservedand the new device must wait for its turn to acknowledgerequests. Since the cascade
channel of theinitial 8237A is used only for prioritizing the additionaldevice, it does not output
any address or control.
The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data
communication. As a peripheral device of a microcomputer system, the 8251 receives parallel data from
the CPU and transmits serial data after conversion. This device also receives serial data from the outside
and transmits parallel data to the CPU after conversion.
Block diagram of the 8251 USART (Universal Synchronous Asynchronous Receiver Transmitter)
The 8251 functional configuration is programed by software. Operation between the 8251 and a CPU is
executed by program control. Table 1 shows the operation between a CPU and the device.
Table 1 Operation between a CPU and 8251
Mode instruction is used for setting the function of the 8251. Mode instruction will be in "wait for write"
at either internal reset or external reset. That is, the writing of a control word after resetting will be
recognized as a "mode instruction."
• Synchronous/asynchronous mode
• Character length
• Parity bit
Command is used for setting the operation of the 8251. It is possible to write a command whenever
necessary after writing a mode instruction and sync characters.
• Transmit Enable/Disable
• Receive Enable/Disable
• Internal resetting
It is possible to see the internal status of the 8251 by reading a status word. The bit configuration of
status word is shown in Fig. 5.
PIN DESCRIPTION-
D 0 to D 7 (l/O terminal)
This is bidirectional data bus which receive control words and transmits data from the CPU and sends
status words and received data to CPU.
A "High" on this input forces the 8251 into "reset status." The device waits for the writing of "mode
instruction." The min. reset width is six clock inputs during the operating status of CLK.
CLK signal is used to generate internal device timing. CLK signal is independent of RXC or TXC. However,
the frequency of CLK must be greater than 30 times the RXC and TXC at Synchronous mode and
Asynchronous "x1" mode, and must be greater than 5 times at Asynchronous "x16" and "x64" mode.
WR (Input terminal)
This is the "active low" input terminal which receives a signal for writing transmit data and control words
from the CPU into the 8251.
RD (Input terminal)
This is the "active low" input terminal which receives a signal for reading receive data and status words
from the 8251.
CS (Input terminal)
This is the "active low" input terminal which selects the 8251 at low level when the CPU accesses. Note:
The device won’t be in "standby status"; only setting CS = High.
This is an output terminal for transmitting data from which serial-converted data is sent out. The device
is in "mark status" (high level) after resetting or during a status when transmit is disabled. It is also
possible to set the device in "break status" (low level) by a command.
This is an output terminal which indicates that the 8251is ready to accept a transmitted data character.
But the terminal is always at low level if CTS = high or the device was set in "TX disable status" by a
command. Note: TXRDY status word indicates that transmit data character is receivable, regardless of
CTS or command. If the CPU writes a data character, TXRDY will be reset by the leading edge or WR
signal.
This is an output terminal which indicates that the 8251 has transmitted all the characters and had no
data character. In "synchronous mode," the terminal is at high level, if transmit data characters are no
longer remaining and sync characters are automatically transmitted. If the CPU writes a data character,
TXEMPTY will be reset by the leading edge of WR signal. Note : As the transmitter is disabled by setting
CTS "High" or command, data written before disable will be sent out. Then TXD and TXEMPTY will be
"High". Even if a data is written after disable, that data is not sent out and TXE will be "High".After the
transmitter is enabled, it sent out.
This is a clock input signal which determines the transfer speed of transmitted data. In "synchronous
mode," the baud rate will be the same as the frequency of TXC. In "asynchronous mode", it is possible to
select the baud rate factor by mode instruction. It can be 1, 1/16 or 1/64 the TXC. The falling edge of
TXC sifts the serial data out of the 8251.
RXD (input terminal)
This is a terminal which indicates that the 8251 contains a character that is ready to READ. If the CPU
reads a data character, RXRDY will be reset by the leading edge of RD signal. Unless the CPU reads a data
character before the next one is received completely, the preceding data will be lost. In such a case, an
overrun error flag status word will be set.
This is a clock input signal which determines the transfer speed of received data. In "synchronous
mode," the baud rate is the same as the frequency of RXC. In "asynchronous mode," it is possible to
select the baud rate factor by mode instruction. It can be 1, 1/16, 1/64 the RXC.
This is a terminal whose function changes according to mode. In "internal synchronous mode." this
terminal is at high level, if sync characters are received and synchronized. If a status word is read, the
terminal will be reset. In "external synchronous mode, "this is an input terminal. A "High" on this input
forces the 8251 to start receiving data characters.
In "asynchronous mode," this is an output terminal which generates "high level"output upon the
detection of a "break" character if receiver data contains a "low-level" space between the stop bits of
two continuous characters. The terminal will be reset, if RXD is at high level. After Reset is active, the
terminal will be output at low level.
This is an input port for MODEM interface. The input status of the terminal can be recognized by the
CPU reading status words.
This is an output port for MODEM interface. It is possible to set the status of DTR by a command.
This is an output port for MODEM interface. It is possible to set the status RTS by a command.
8279 Programmable keyboard/display interface controller simultaneously drives the display of the
system interfaces the keyboard with microprocessor, scans keyboard if any key is pressed or
not.Transmitts the data after getting it from the microprocessor
Features
BLOCK DIAGRAM
DATA BUFFER
1. Bidirectional,3 state 8 bit data bus used to connect to the system bus
I/O CONTROL
3. When write data is activated is receives data from the system bus.
2. contents of these registers are automatically updated to accept next data entry by mp
16 * 8 DISPLAY RAM
1.contains 16 byte of data to be displayed on 16 7-segment display in the encoded scan mode.
4. In encoded scan mode 8279 uses 1st 8 locations and in decoded mode, it uses 1st 4 locations.
CONTROL AND TIMING REGISTERS
1. debounces, encodes and stores encoded value into FIFO closure in scanned keyboard mode
In sensor matrix mode the debounce logic is inhibited and contents of RETURN lines are directly
transferred to the corresponding location of sensor RAM
DISPLAY REGISTERS
2. divided into 2 nibbles called nibble A and nibble B. Both these nibbles can be inhibited or blanked
individually.
3.also provides proper key scan , row scan, display scans and debounce timings
SCAN COUNTER
1.SL0 - SL3 are used to scan keyboardmatrix and display the digits.
2. in encoded mode, it provides 3 or 4 bit binary count on scan lines .In decoded mode, the 2 bits of
count are decoded on scan lines.
RETURN
2. The status logic generates an interrupt request after each FIFO read operation till FIFO is empty.
3.in scanned sensor mode it acts as a sensor RAM mode .each row of sensor RAM is loaded with
sensor matrix.
Type-input
This is an active low input signal used to select the 8279 for normal read or write operation.
(READ) -
type-input
This is an active low signal and a low on this i/p enables the 8279 to send data to the MP.
When this pin is low MP will write data or control words into the 8279.
A0-When it is high it indicates the transfer of a command or status info. and when this is low it indicates
the transfer of data.
CLK-
RESET-
IRQ-
When there is a data in FIFO sensor RAM the interrupt o/p goes high.
SL0-SL3-
RL0-RL7-
These lines are connected to one terminal of keys while the other terminal is connected to the decoded
scan lines.
SHIFT-
In the scanned keyboard mode the status of the shift i/p line is stored along with each keys code in FIFO.
CNTL/STB-
Used as control i/p in the keyboard mode and stored in FIFO on a key closer.
The o/ p pin is used to blank the display during the digit switching or by blanking display command.
These pins will work as the o/p ports .To scan the display & keyboard the data from these lines is
synchronised with the scan lines.
VCC-
GND-
1. Scanned keyboard mode : allows key matrix to be interfaced either in encoded mode or decoded
mode . In decoded mode 4 x 8 matrix is interfaced and in encoded mode 8 x 8 keyboard is
interfaced. The code key pressed with CNTL and SHIFT is stored in FIFO RAM.
2..scanned sensor mode :in encoded mode 8 x 8 sensor matrix and in decoded mode 4 x 8 sensor
matrix is interfaced
3. Strobbedinput :if control line goes low data on return line is stored in FIFO byte by byte.
1. Display Scan: provides 8 or 16 characters multiplexed displays organised as dual 4 bit or single 8
bit display units
2.Display Entry: it allows options for data entry into the display either left entry or right entry.
1.KEYBOARD MODES
when a key is pressed ,it enters into FIFO (if at least 1 byte is free ),an interrupt is generated
to inform CPU about previous key closure, if found no entry is made to the FIFO.If 2 keys are
pressed no keys are detected or scanned.
Validity of this mode depends on N key rollover mode. when 2 keys are pressed
simultaneously, error flag is set, it prevents further writing but sends interrupt to CPU for read
operation. With command CF=1,error flag can be set.
debounce logic is inhibited.8 byte FIFO RAM acts as 8 x 8 bit memory matrix .
When the data is entered from the left side of the display unit it is called left entry mode.Adress 15 of
the RAM contains the right most display character and address 0of the display RAM contains the left
most display character.
In this mode the first entry to be displayed is entered on the rightmost display. The next entry is also
placed in the right most display but after the previous display i shift left by one display position.
A0
0 0 0 D D K K K 1
D D DISPLAY MODES
K K K Keyboard modes
1 1 0 Strobbed input
encoded scan
1 1 1 Strobbed input
decoded scan
B.)PROGRAMMABLE CLOCK
Clock for operation is obtained by dividing the external clock input signal by programmable constant
called prescaler
D7 D6 D5 D4 D3 D2 D1 D1 A0
0 0 1 P P P P P 1
D7 D6 D5 D4 D3 D2 D1 D1 A0
0 1 0 AI X A A A 1
X- Don’t care
AL—auto increment
D7 D6 D5 D4 D3 D2 D1 D1 A0
0 1 1 AI A A A A 1
1 0 0 AI A A A A 1
D7 D6 D5 D4 D3 D2 D1 D1 A0
1 0 1 X IW IW BL BL 1
D7 D6 D5 D4 D3 D2 D1 D1 A0
D7 D6 D5 D4 D3 D2 D1 D1 A0
1 1 1 E X X X X 1
For N-KEY ROLLOVER MODE ,if E bit is set to be 1,8279 operates in special error mode.
The key code is entered as a byte code into the FIFO RAM after a valid key closure in the
following in the scanned keyboard mode.
CNTL SHIFT D5 D4 D3 D2 D1 D0
The data from the return lines is directly entered into an appropriate row of sensor RAM that identifies
the row of sensor that changed its status in sensor matrix mode.
It is used in keyboard and strobbed input mode to indicate error. If FIFO is full and write is attempted
then overrun error occurs .If FIFO is empty and read is attempted then underrun error occurs.
D7 D6 D5 D4 D3 D2 D1 D0
Du S/E O U F N N N
D0, D1, D2—number of character that are available for reading from FIFO