Vivekananda Institute of Technology

Sector-36, NRI Road, Jagatpura, Jaipur-303012 (Raj.) Website: www.vitj.ac.in

E-Mail: [email protected] Ph.: 0141-2851000 (Approved By AICTE, Ministry of HRD,
Government of India & Affiliated to Rajasthan Technical University, Kota)

Department of Computer Science and Engineering

Digital Electronics
Course Code: 3CS3-04

UNIT – IV – Fundamental Concepts

\

Combinational Circuits:
Combinational logic circuit design, adder, subtractor, BCD adder, encoder,
Unit - 4
decoder, BCD to 7-segment decoder, multiplexer, demultiplexer.

Text Books:
Digital Circuits and Design, S Salivahanan, Vikas Publishing House Pvt. Ltd.

Reference Books:
Modern Digital Electronics, R. P. Jain, Tata McGraw-Hill.

By: Rahul Mishra

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 IV. Combinational Circuits
4.1 Introduction:
The digital system consists of two types of circuits, namely
• Combinational circuits
• Sequential circuits

Combinational circuit consists of logic gates whose output at any time is determined from the
present combination of inputs. The logic gate is the most basic building block of combinational
logic. The logical function performed by a combinational circuit is fully defined by a set of
Boolean expressions.

Sequential logic circuit comprises both logic gates and the state of storage elements such as
flip-flops. As a consequence, the output of a sequential circuit depends not only on present
value of inputs but also on the past state of inputs.
In the previous chapter, we have discussed binary numbers, codes, Boolean algebra and
simplification of Boolean function and logic gates. In this chapter, formulation and analysis of
various systematic designs of combinational circuits will be discussed.
A combinational circuit consists of input variables, logic gates, and output variables. The logic
gates accept signals from inputs and output signals are generated according to the logic circuits
employed in it. Binary information from the given data transforms to desired output data in this
process. Both input and output are obviously the binary signals, i.e., both the input and output
signals are of two possible states, logic 1 and logic 0.

Block diagram of a combinational logic circuit

For n number of input variables to a combinational circuit, 2n possible combinations of binary

input states are possible. For each possible combination, there is one and only one possible
output combination. A combinational logic circuit can be described by m Boolean functions
and each output can be expressed in terms of n input variables.

DESIGN PROCEDURE:
• The problem is stated.
• Identify the input and output variables.
• The input and output variables are assigned letter symbols.
• Construction of a truth table to meet input -output requirements.
• Writing Boolean expressions for various output variables in terms of input
variables.

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 • The simplified Boolean expression is obtained by any method of minimization—
algebraic method, Karnaugh map method, or tabulation method.
• A logic diagram is realized from the simplified boolean expression using
logicgates.

The following guidelines should be followed while choosing the preferred form for hardware
implementation:
• The implementation should have the minimum number of gates, with the gates used
having the minimum number of inputs.
• There should be a minimum number of interconnections.
• Limitation on the driving capability of the gates should not be ignored.

ARITHMETIC CIRCUITS – BASIC BUILDING BLOCKS:

In this section, we will discuss those combinational logic building blocks that can be used to
perform addition and subtraction operations on binary numbers. Addition and subtraction are
the two most commonly used arithmetic operations, as the other two, namely multiplication
and division, are respectively the processes of repeated addition and repeated subtraction.
The basic building blocks that form the basis of all hardware used to perform the arithmetic
operations on binary numbers are half-adder, full adder, half-subtractor, full- subtractor.

4.2 Half-Adder:
A half-adder is a combinational circuit that can be used to add two binary bits. It has two inputs
that represent the two bits to be added and two outputs, with one producing the SUM output
and the other producing the CARRY.

Block schematic of half-adder

The truth table of a half-adder, showing all possible input combinations and the corresponding
outputs are shown below.

Truth table of half-adder

Inputs Outputs
A B Carry (C) Sum (S)
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

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K-map simplification for carry and sum:

The Boolean expressions for the SUM and CARRY outputs are given by the equations,
Sum, S = A’B+ AB’
Carry, C = A . B
The first one representing the SUM output is that of an EX-OR gate, the second one
representing the CARRY output is that of an AND gate.
The logic diagram of the half adder is,

Logic Implementation of Half-adder

4.3 Full-Adder:
A full adder is a combinational circuit that forms the arithmetic sum of three input bits. It
consists of 3 inputs and 2 outputs.
Two of the input variables, represent the significant bits to be added. The third input
represents the carry from previous lower significant position. The block diagram of full adder
is given by,

Block schematic of full-adder

The full adder circuit overcomes the limitation of the half-adder, which can be used to add two
bits only. As there are three input variables, eight different input combinations are possible.
The truth table is shown below,

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Truth Table:

Inputs Outputs
A B Cin Sum (S) Carry (Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

To derive the simplified Boolean expression from the truth table, the Karnaugh map method
is adopted as,

The Boolean expressions for the SUM and CARRY outputs are given by the equations,
Sum, S = A’B’Cin+ A’BC’in + AB’C’in +ABCin
Carry, Cout = AB+ ACin +BCin.

The logic diagram for the above functions is shown as,

54
Implementation of full-adder in Sum of Product
The logic diagram of the full adder can also be implemented with two half- adders and one
OR gate. The S output from the second half adder is the exclusive-OR of Cin and the output of
the first half-adder, giving

= C‘in (A‘B+AB‘) + Cin (A‘B+AB‘) ‘ [(x‘y+xy‘) ‘= (xy+x‘y‘)]

= C‘in (A‘B+AB‘) + Cin (AB+A‘B‘)
= A‘BC‘in + AB‘C‘in + ABCin + A‘B‘Cin.

and the carry output is,

Carry, Cout = AB+ Cin (A’B+AB’)
= AB+ A‘BCin+ AB‘Cin
= AB (Cin+1) + A‘BCin+ AB‘Cin [Cin+1= 1]
= ABCin+ AB+ A‘BCin+ AB‘Cin
= AB+ ACin (B+B‘) + A‘BCin
= AB+ ACin+ A‘BCin
= AB (Cin+1) + ACin+ A‘BCin [Cin+1= 1]
= ABCin+ AB+ ACin+ A‘BCin
= AB+ ACin+ BCin (A +A‘)
= AB+ ACin+ BCin.

Implementation of full adder with two half-adders and an OR gate

4.4 Half -Subtractor:

Block schematic of half-subtractor

A half-subtractor is a combinational circuit that can be used to subtract one binary digit from
another to produce a DIFFERENCE output and a BORROW output. The BORROW output
here specifies whether a ‗1‘has been borrowed to perform the subtraction.
The truth table of half-subtractor, showing all possible input combinations and the
corresponding outputs are shown below.
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Input Output
A B Difference (D) Borrow (Bout)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

K-map simplification for half subtractor:

The Boolean expressions for the DIFFERENCE and BORROW outputs are given by the
equations,
Difference, D = A’B+ AB’
Borrow, Bout = A’. B

The first one representing the DIFFERENCE (D)output is that of an exclusive-OR gate, the
expression for the BORROW output (Bout) is that of an AND gate with input A complemented
before it is fed to thegate.
The logic diagram of the half adder is,

Logic Implementation of Half-Subtractor

Comparing a half-subtractor with a half-adder, we find that the expressions for the SUM and
DIFFERENCE outputs are just the same. The expression for BORROW in the case of the half-
subtractor is also similar to what we have for CARRY in the case of the half-adder. If the input
A, ie., the minuend is complemented, an AND gate can be used to implement the BORROW
output.

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4.5 Full Subtractor:
A full subtractor performs subtraction operation on two bits, a minuend and a subtrahend, and
also takes into consideration whether a ‗1‘has already been borrowed by the previous adjacent
lower minuend bit ornot.
As a result, there are three bits to be handled at the input of a full subtractor, namely the two
bits to be subtracted and a borrow bit designated as Bin. There are two outputs, namely the
DIFFERENCE output D and the BORROW output Bo. The BORROW output bit tells whether
the minuend bit needs to borrow a ‗1‘from the next possible higher minuend bitBlock
schematic of full-adder

The truth table for full-subtractor is,

Inputs Outputs
A B Bin Difference(D) Borrow(Bout)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-map

simplification for full-subtractor:

The Boolean expressions for the DIFFERENCE and BORROW outputs are given by the
equations,
Difference, D = A’B’Bin+ A’BB’in + AB’B’in +ABBin

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Borrow, Bout = A’B+ A’Cin +BBin.
The logic diagram for the above functions is shown as,

Implementation of full-Subtractor using Half Subtractors

The logic diagram of the full-subtractor can also be implemented with two half- subtractors
and one OR gate. The difference,D output from the second half subtractor is the Ex -OR of
Bin and the output of the first half-subtractor, giving

= B‘in (A‘B+AB‘) + Bin (A‘B+AB‘)‘ [(x‘y+xy‘)‘= (xy+x‘y‘)]

= B‘in (A‘B+AB‘) + Bin (AB+A‘B‘)
= A‘BB‘in + AB‘B‘in + ABBin + A‘B‘Bin .

and the borrow output is,

Borrow, Bout = A’B+ Bin (A’B+AB’)’ [(x‘y+xy‘)‘= (xy+x‘y‘)]
= A‘B+ Bin (AB+A‘B‘)
= A‘B+ ABBin+ A‘B‘Bin
= A‘B (Bin+1) +ABBin+ A‘B‘Bin [Cin+1= 1]
= A‘BBin+ A‘B+ ABBin+ A‘B‘Bin
= A‘B+ BBin (A+A‘) + A‘B‘Bin [A+A‘= 1]
= A‘B+ BBin+ A‘B‘Bin
= A‘B (Bin+1) +BBin+ A‘B‘Bin [Cin+1= 1]
= A‘BBin+ A‘B+ BBin+ A‘B‘Bin

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= A‘B+ BBin+ A‘Bin (B +B‘)
= A‘B+ BBin+ A‘Bin.
Therefore,
we can implement full-subtractor using two half-subtractors and OR gate as,

Implementation of full-subtractor with two half-subtractors and an OR gate

4.6 Binary Adder (Parallel Adder):

Fig. 4-bit binary parallel Adder

The 4-bit binary adder using full adder circuits is capable of adding two 4-bit numbers
resulting in a 4-bit sum and a carry output as shown in figure below. Since all the bits of augend
and addend are fed into the adder circuits simultaneously and the additions in each position are
taking place at the same time, this circuit is known as parallel adder.

Let the 4-bit words to be added be represented by, A3A2A1A0= 1111 and B3B2B1B0= 0011.

The bits are added with full adders, starting from the least significant position, to form the sum
it and carry bit. The input carry C0 in the least significant position must be
• The carry output of the lower order stage is connected to the carry input of the next
higher order stage. Hence this type of adder is called ripple-carry adder.
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In the least significant stage, A0, B0 and C0 (which is 0) are added resulting in sum S0 and carry
C1. This carry C1 becomes the carry input to the second stage. Similarly in the second stage,
A1, B1 and C1 are added resulting in sum S1 and carry C2, in the third stage, A2, B2 and C2 are
added resulting in sum S2 and carry C3, in the third stage, A3, B3 and C3 are added resulting in
sum S3 and C4, which is the output carry. Thus the circuit results in a sum (S3S2S1S0) and a carry
output (Cout).
4.7 Binary Subtractor (Parallel Subtractor):
The subtraction of unsigned binary numbers can be done most conveniently by means of
complements. The subtraction A-B can be done by taking the 2‘s complement of B and adding
it to A. The 2‘s complement can be obtained by taking the 1‘s complement and adding 1 to the
least significant pairofbits. The 1‘scomplement can be implemented with inverters and a 1 can
be added to the sum through the input carry.

The circuit for subtracting A-B consists of an adder with inverters placed between each data
input B and the corresponding input of the full adder. The input carry C0 must be equal to
1 when performing subtraction. The operation thus performed becomes A, plus the 1‘s
complement of B, plus1. This is equal to A plus the 2‘s complement of B.

Fig. 4-bit Parallel Subtractor

4.8 Parallel Adder/ Subtractor:

Fig. 4-Bit Adder Subtractor

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The addition and subtraction operation can be combined into one circuit with one common
binary adder. This is done by including an exclusive-OR gate with each full adder. A 4-bit
adder Subtractor circuit is shown below.
The mode input M controls the operation. When M= 0, the circuit is an adder and when M=1,
the circuit becomes a Subtractor. Each exclusive-OR gate receives input M and one of the
inputs of B. When M=0, we have B Ex-OR 0 = B. The full adders receive the value of B, the
input carry is 0, and the circuit performs A plus B. When M=1, we have B Ex –OR 1= B‘ and
C0=1. The B inputs are all complemented and a 1 is added through the input carry. The circuit
performs the operation A plus the 2‘s complement of B. The exclusive-OR with outputV is for
detecting an overflow.
4.9 DECODERS:

General structure of decoder

A decoder is a combinational circuit that converts binary information from ‗n‘input
lines to a maximum of ‗2n‘unique output lines. The encoded information is presented as
‗n‘inputs producing ‗2n‘possible outputs. The 2n output values are from 0 through 2n-1. A
decoder is provided with enable inputs to activate decoded output based on data inputs. When
any one enable input is unasserted, all outputs of decoder aredisabled.

Binary Decoder (2 to 4 decoder):

A binary decoder has ‗n‘bit binary input and a one activated output out of 2n outputs. A binary
decoder is used when it is necessary to activate exactly one of 2n outputs based on an n-bit

input value.
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2-to-4 Line decoder
Here the 2 inputs are decoded into 4 outputs, each output representing one of the minterms of the
two input variables.

Inputs Outputs

Enable A B Y3 Y2 Y1 Y0

0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

As shown in the truth table, if enable input is 1 (EN= 1) only one of the outputs (Y0 – Y3),
is active for a giveninput. The output Y0 is active, ie., Y0= 1 when inputs A= B= 0, Y1 is active
when inputs, A= 0 and B= 1, Y2 is active, when input A= 1 and B= 0, Y3 is active, when inputs
A= B= 1.
3 to-8 Line Decoder:
A 3-to-8 line decoder has three inputs (A, B, C) and eight outputs (Y 0- Y7). Based on
the 3 inputs one of the eight outputs is selected.
The three inputs are decoded into eight outputs, each output representing one of the
minterms of the 3-input variables. This decoder is used for binary-to-octal conversion. The
input variables may represent a binary number and the outputs will represent the eight digits in
the octal number system. The output variables are mutually exclusive because only one output
can be equal to 1 at any one time. The output line whose value is equal to 1 represents the
minterm equivalent of the binary number presently available in the input lines.
Inputs Outputs
A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

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 3-to-8 line decoder
Applications of decoders:
• Decoders are used in counter system.
• They are used in analog to digitalconverter.
• Decoder outputs can be used to drive a displaysystem.

4.10 ENCODERS:
An encoder is a digital circuit that performs the inverse operation of a decoder. Hence, the
opposite of the decoding process is called encoding. An encoder is a combinational circuit that
converts binary information from 2n input lines to a maximum of ‗n‘ unique output lines.

General structure of Encoder

It has 2n input lines, only one which 1 is active at any time and ‗n‘ output lines. It encodes one
of the active inputs to a coded binary output with ‗n‘ bits. In an encoder, the number of outputs
is less than the number of inputs.

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Octal-to-Binary Encoder:
It has eight inputs (one for each of the octal digits) and the three outputs that generate the
corresponding binary number. It is assumed that only one input has a value of 1 at any given
time.

Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
The encoder can be implemented with OR gates whose inputs are determined directly from the
truth table. Output z is equal to 1, when the input octal digit is 1 or 3 or 5 or 7. Output y is 1
for octal digits 2, 3, 6, or 7 and the output is 1 for digits 4, 5, 6 or 7. These conditions can be
expressed by the following output Boolean functions:

z= D1+ D3+ D5+ D7

y= D2+ D3+ D6+ D7 x= D4+ D5+ D6+ D7

The encoder can be implemented with three OR gates. The encoder defined in the below table,
has the limitation that only one input can be active at any given time. If two inputs are active
simultaneously, the output produces an undefined combination.
For eg., if D3 and D6 are 1 simultaneously, the output of the encoder may be 111. This does not
represent either D6 or D3. To resolve this problem, encoder circuits must establish an input
priority to ensure that only one input is encoded. If we establish a higher priority for inputs
with higher subscript numbers and if D3 and D6 are 1 at the same time, the output will be 110
because D6 has higher priority than D3.

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Octal-to-Binary Encoder
Another problem in the octal-to-binary encoder is that an output with all 0‘s is generated when
all the inputs are 0; this output is same as when D0 is equal to 1. The discrepancy can be resolved
by providing one more output to indicate that atleast one input is equal to 1.

Priority Encoder:
A priority encoder is an encoder circuit that includes the priority function. In priority encoder,
if two or more inputs are equal to 1 at the same time, the input having the highest priority will
take precedence.
In addition to the two outputs x and y, the circuit has a third output, V (valid bit indicator). It
is set to 1 when one or more inputs are equal to 1. If all inputs are 0, there is no valid input and
V is equal to 0.

The higher the subscript number, higher the priority of the input. Input D3, has the highest
priority. So, regardless of the values of the other inputs, when D3 is 1, the output for xy is 11.
D2 has the next priority level. The output is 10, if D2= 1 provided D3= 0. The output for D1 is
generated only if higher priority inputs are 0, and so on down the priority levels.

Truth table:
Inputs Outputs
D0 D1 D2 D3 x y V
0 0 0 0 x x 0
1 0 0 0 0 0 1
x 1 0 0 0 1 1
x x 1 0 1 0 1
x x x 1 1 1 1
Although the above table has only five rows, when each don‘t care condition is replaced first by
0and then by 1, we obtain all 16 possible input combinations. For example, the third row in the
table with X100 represents minterms 0100 and 1100. The don‘t care condition is replaced by 0
and 1 as shown in the table below.

Modified Truth table:

Inputs Outputs
D0 D1 D2 D3 X y V
0 0 0 0 X x 0
1 0 0 0 0 0 1
0 1 0 0
0 1 1
1 1 0 0
0 0 1 0
0 1 1 0
1 0 1
1 0 1 0
1 1 1 0

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 0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

K-map Simplification:

The priority encoder is implemented according to the above Boolean functions.

Logic Diagram of Priority Encoder

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4.11 MULTIPLEXER: (Data Selector)
A multiplexer or MUX, is a combinational circuit with more than one input line, one output
line and more than one selection line. A multiplexer selects binary information present from
one of many input lines, depending upon the logic status of the selection inputs, and routes it
to the output line. Normally, there are 2n input lines and n selection lines whose bit
combinations determine which input is selected. The multiplexer is often labeled as MUX in
block diagrams.

Block diagram of Multiplexer

A multiplexer is also called a data selector, since it selects one of many inputs and steers the
binary information to the output line.
2-to-1- line Multiplexer:
The circuit has two data input lines, one output line and one selection line, S. When S= 0, the
upper AND gate is enabled and I0 has a path to the output.
When S=1, the lower AND gate is enabled and I1 has a path to the output.

Logic diagram
The multiplexer acts like an electronic switch that selects one of the two sources.
Truth table:
S Y
0 I0
1 I1

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4-to-1-line Multiplexer:
A 4-to-1-line multiplexer has four (2n) input lines, two (n) select lines and one output line. It
is the multiplexer consisting of four input channels and information of one of the channels can
be selected and transmitted to an output line according to the select inputs combinations.
Selection of one of the four input channel is possible by two selection inputs.

4-to-1-Line Multiplexer

Each of the four inputs I0 through I3, is applied to one input of AND gate. Selection lines S1
and S0 are decoded to select a particular AND gate. The outputs of the AND gate are applied
to a single OR gate that provides the 1-line output.
Function table:
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

To demonstrate the circuit operation, consider the case when S1S0= 10. The AND gate associated
with input I2 has two of its inputs equal to 1 and the third input connected to I2. The other three
AND gates have atleast one input equal to 0, which makes their outputs equal to 0. The OR
output is now equal to the value of I2, providing a path from the selected input to the output.

The data output is equal to I0 only if S1= 0 and S0= 0; Y= I0S1‘S0‘. The data output is equal to
I1 only if S1= 0 and S0= 1; Y= I1S1‘S0. The data output is equal to I2 only if S1= 1 and S0= 0;
Y= I2S1S0‘. The data output is equal to I3 only if S1= 1 and S0= 1; Y= I3S1S0.
When these terms are ORed, the total expression for the data output is,
Y= I0S1’S0’+ I1S1’S0 +I2S1S0’+ I3S1S0.
As in decoder, multiplexers may have an enable input to control the operation of the unit. When
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the enable input is in the inactive state, the outputs are disabled, and when it is in the active
state, the circuit functions as a normal multiplexer.

Application:
The multiplexer is a very useful MSI function and has various ranges of applications in data
communication. Signal routing and data communication are the important applications of a
multiplexer. It is used for connecting two or more sources to guide to a single destination among
computer units and it is useful for constructing a common bus system. One of the general
properties of a multiplexer is that Boolean functions can be implemented by this device.

Implementation of Boolean Function using MUX:

Any Boolean or logical expression can be easily implemented using a multiplexer. If a
Booleanexpression has(n+1) variables, then ‗n‘ of these variablescan be connected to the select
lines of the multiplexer. The remaining single variable along with constants 1 and 0 is used
as the input of the multiplexer. For example, if C is the single variable, then the inputs of the
multiplexers are C, C‘, 1 and 0. By this method any logical expression can be implemented. In
general, a Boolean expression of (n+1) variables can be implemented using a multiplexer with
2n inputs.

1. Implement the following boolean function using 4: 1 multiplexer,

F (A, B, C) = ∑m (1, 3, 5, 6).

Implementation table:
Apply variables A and B to the select lines. The procedures for implementing the function
are:
• List the input of themultiplexer
• List under them all the minterms in two rows as shownbelow.
The first half of the minterms is associated with A‘ and the second half with A. The given
function is implemented by circling the minterms of the function and applying the following
rules to find the values for the inputs of the multiplexer.
• If both the minterms in the column are not circled, apply 0 to the corresponding input.
• If both the minterms in the column are circled, apply 1 to the corresponding input.
• If the bottom minterm is circled and the top is not circled, apply C to the input.
• If the top minterm is circled and the bottom is not circled, apply C‘ to the input.

Implementation Table:

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 Fig. Multiplexer Implementation

2. F (x, y, z) = ∑m (1, 2, 6, 7)
Solution: Implementation table:

Fig. Multiplexer Implementation

3. F ( A, B, C) = ∑m (1, 2, 4, 5)

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Fig. Implementation table

Multiplexer Implementation:

4. F( P, Q, R, S)= ∑m (0, 1, 3, 4, 8, 9, 15)

Implementation table:

Multiplexer Implementation:

5)Implement the Boolean function using 8: 1 and also using 4:1 multiplexer
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F (A, B, C, D) = ∑m (0, 1, 2, 4, 6, 9, 12, 14)

Implementation table:

Multiplexer Implementation (Using 8: 1 MUX):

Using 4: 1 MUX:

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6. F (A, B, C, D) = ∑m (1, 3, 4, 11, 12, 13, 14, 15)

Solution:
Variables, n= 4 (A, B, C, D) Select lines= n-1 = 3 (S2, S1, S0)
2n-1 to MUX i.e., 23 to 1 = 8 to 1 MUX
Input lines= 2n-1 = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)

Implementation table:

Multiplexer Implementation:

7)Implement the Boolean function using 8: 1multiplexer.

F (A, B, C, D) = A’BD’ + ACD + B’CD + A’C’D.
Solution:
Convert into standard SOP form,
= A‘BD‘ (C‘+C) + ACD (B‘+B) + B‘CD (A‘+A) + A‘C‘D (B‘+B)
= A‘BC‘D‘ + A‘BCD‘+ AB‘CD + ABCD +A‘B‘CD + AB‘CD +A‘B‘C‘D+ A‘BC‘D
= A‘BC‘D‘ + A‘BCD‘+ AB‘CD + ABCD +A‘B‘CD +A‘B‘C‘D+ A‘BC‘D
= m4+ m6+ m11+ m15+ m3+ m1+ m5
= ∑m (1, 3, 4, 5, 6, 11, 15)

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Implementation table:

Multiplexer Implementation:

4.12 DEMULTIPLEXER:

Demultiplex means one into many. Demultiplexing is the process of taking information from
one input and transmitting the same over one of several outputs.
A demultiplexer is a combinational logic circuit that receives information on a single input
and transmits the same information over one of several (2n) output lines.

Block diagram of Demultiplexer

The block diagram of a demultiplexer which is opposite to a multiplexer in its operation is
shown above. The circuit has one input signal, ‗n‘select signals and 2n output signals. The select
inputs determine to which output the data input will be connected. As the serial data is changed
to parallel data, i.e., the input caused to appear on one of the n output lines, the demultiplexer
is also called a ―data distributer‖ or a ―serial-to-parallel converter‖ .

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1-to-4 Demultiplexer:

Logic Symbol
A 1-to-4 demultiplexer has a single input, Din, four outputs (Y0 to Y3) and two select inputs
(S1 and S0). The input variable Din has a path to all four outputs, but the input information is
directed to only one of the output lines. The truth table of the 1-to-4 demultiplexer is shown
below. Truth table of 1-to-4 demultiplexer
Enable S1 S0 Din Y0 Y1 Y2 Y3
0 x x X 0 0 0 0
1 0 0 0 0 0 0 0
1 0 0 1 1 0 0 0
1 0 1 0 0 0 0 0
1 0 1 1 0 1 0 0
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 0
1 1 1 0 0 0 0 0
1 1 1 1 0 0 0 1
From the truth table, it is clear that the data input, Din is connected to the output Y0, when S1=
0 and S0= 0 and the data input is connected to output Y1 when S1= 0 and S0= 1. Similarly, the
data input is connected to output Y2 and Y3 when S1= 1 and S0= 0 and when S1= 1 and S0= 1,
respectively. Also, from the truth table, the expression for outputs can be written as follows,

Logic diagram of 1-to-4 demultiplexer

Y0= S1’S0’Din Y1= S1’S0Din Y2= S1S0’Din Y3= S1S0Din

Now, using the above expressions, a 1-to-4 demultiplexer can be implemented using four 3-
input AND gates and two NOT gates. Here, the input data line Din, is connected to all the AND
gates. The two select lines S1, S0 enable only one gate at a time and the data that appears on the
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input line passes through the selected gate to the associated output line.

1- to-8 Demultiplexer:
A 1-to-8 demultiplexer has a single input, Din, eight outputs (Y0 to Y7) and three select inputs
(S2, S1 and S0). It distributes one input line to eight output lines based on the select inputs. The
truth table of 1-to-8 demultiplexer is shown below.
Truth table of 1-to-8 demultiplexer
Din S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 x x x 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
From the above truth table, it is clear that the data input is connected with one of the eight
outputs based on the select inputs. Now from this truth table, the expression for eight outputs
can be written as follows:
Y0= S2‘S1‘S0‘Din Y4= S2 S1‘S0‘Din Y1= S2‘S1‘S0Din Y5= S2 S1‘S0Din
Y2= S2‘S1S0‘Din Y6= S2 S1S0‘Din Y3= S2‘S1S0Din Y7= S2S1S0Din

Logic diagram of 1-to-8 demultiplexer

1) Design 1:8 demultiplexer using two 1:4DEMUX.

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2) Implement full subtractor using demultiplexer.

Inputs Outputs
A B Bin Difference(D) Borrow(Bout)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

4.13 MAGNITUDE COMPARATOR:

A magnitude comparator is a combinational circuit that compares two given numbers (A and
B) and determines whether one is equal to, less than or greater than the other. The output is in
the form of three binary variables representing the conditions A= B, A>B and A<B, if A andB
are the two numbers being compared.

Fig. Block diagram of magnitude comparator

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For comparison of two n-bit numbers, the classical method to achieve the Boolean expressions
requires a truth table of 22n entries and becomes too lengthy and cumbersome.

2- bit Magnitude Comparator:

The truth table of 2-bit comparator is given in table below— Truth table:

Inputs Outputs
A3 A2 A1 A0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

K-map Simplification:

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Logic Diagram:

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References
1. Morris Mano, Digital Design, Prentice Hall of India, 2001.
2. S.Salivahanan and S.Arivazhagan―Digital Electronics‖, Ist Edition, Vikas Publishing
House pvt Ltd, 2012.
3. Ronald J.Tocci, Digital System Principles and Applications, PHI, 6th Edition, 1997
Question Bank
Part A
1. Define combinational logic circuit
2. Define half adder and full adder
3. Define half subtractor and full subtractor
4. Draw a block diagram of half adder and show the truth table
5. Draw the schematic of a full subtractor circuit and show the truth table of full
subtractor.
6. Draw the schematic of a full adder circuit and give its truth table.
7. Write the logic expressions for the difference and borrow of a full subtractor.
8. Design a 4 bit parallel adder
9. Define multiplexer
10. Write the truth table of 4:1 multiplexer.
11. Differentiate between multiplexer and demultiplexer.
12. Demonstrate priority encoder.
13. List the purpose of magnitude comparator?
14. Draw the circuit diagram and truth table of 4 to 2 encoder.

Part B
1. Develop a full adder using two half adders.
2. Design a half adder combinational circuit.
3. Explain the operation of full adder with the help of logic diagram and truth table
4. Draw and explain the working of 4 bit parallel adder and 4 bit parallel subtractor.
5. Construct 4-bit parallel adder/subtractor using Full adders and EXOR gates
6. Draw the circuit of 3 to 8 decoder and explain
7. Design and implement a full adder circuit using a 3:8 decoder.
8. Explain the octal to binary encoder.
9. Design a 4 bit priority encoder.
10. Describe the working of 8:1 multiplexer
11. Implement the following Boolean function using 4:1 multiplexer.F(A,B,C)= Σm
(1,3,5,6)
12. Design a 1:8 demultiplexer.
13. Design a 2 bit comparator using gates.

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