Lpvlsi Unit V
Lpvlsi Unit V
where ε si and ε ox are silicon and oxide permittivities, L, tox, Wdm, and Xj
are chan-nel length, gate oxide thickness, depletion depth, and junction
depth, respectively.
In order to get best of both the worlds, i.e. a smaller delay of low-Vt
devices and a smaller power consumption of high-Vt devices, a balanced
mix of both low-Vt and high-Vt devices may be used. The following two
approaches can be used to reduce leakage power dissipation in the standby
mode.
ii The leakage current is also reduced due to body effect, because the body
of all the three transistors is reverse-biased with respect to the source.
iii As the source-to-drain voltages for all the transistors are reduced, the
subthreshold current due to drain-induced barrier lowering (DIBL)
effect will also be lesser. As a consequence, the leakage currents will be
minimum when all the transistors are turned off, which happens when
the input vector is 0000. The leakage cur-rent passing through the
circuit depends on the input vectors applied to the gate and it will be
different for different input vectors. For example, for a three-input
NAND gate shown in Fig. 9.8b, the leakage current contributions for
different input vectors are given in Table 9.1. It may be noted that the
highest leakage current is 99 times the lowest leakage current. The
current is lowest when all the transistors in series are OFF, whereas the
leakage current is highest when all the transistors are ON.
Although the basic concept of using sleep transistors for power gating is simple, the
actual implementation of the switching fabric involves many highly technology-
specific issues. First and foremost among the issues is the architectural issue to decide
whether to use only header switch using pMOS transistors or use only footer switch
using nMOS transistors or use both. Some researchers have advocated the use of both
types of switches. However, for designs at 90 nm or smaller than 90 nm, either the
header or footer switch is recommended due to the tight voltage margin, significant IR
drop and large area, and delay penalties when both types of transistors are used.
Various issues to be addressed for switching fabric design are:
•Header-versus-footer switch
Similarly, isolation cell to clamp the output to ‘1’ logic level can be
accomplished using an OR gate If we want to clamp the output to the last
value, it is necessary to use a latch to hold the last value.
• A scan-based approach based on the reuse of scan chains to store state off
chip
Scan-Based Approach Scan chains used for built-in self-test (BIST) can
be reused. During power-down sequence, the scan register outputs are
routed to an on-chip or off-chip memory. In this approach, there can be
significant saving of chip area.
accumulates in the capacitor and voltage builds up. As the time progresses,
the voltage across the resistor decreases with a consequent reduction in
current through the circuit. At any instant of time, Vdd = IR + Q/C, where Q
is the charge stored in the capacitor. Figure 10.1b shows how conventional
charging of a capacitor leads to the dissipation of an energy of 1/2CLV 2dd.
• In the case of adiabatic charging, the charge moves from the power
supply slow-ly but efficiently (dissipating lesser energy).
Step 4: After the charging is complete, the output signal pair remains
stable and can be used as inputs to the next stage of the circuit.
Step 1: Replace each pull-up nMOS network and the pull-down pMOS
network of the static CMOS circuit with transmission gates.
Step 2: Use the expanded pull-up network to drive the true output load capacitance.
Figure 10.5a shows the schematic diagram of a static CMOS circuit with
its pull-up and pull-down blocks. Figure 10.5b shows the transformed
adiabatic circuit where both the networks are used to charge and discharge
the load capacitances adiabati-cally. Figure 10.6 shows the realization of
the adiabatic AND/NAND gate based on
the above procedure. In this way, the adiabatic realization of any function
can be performed. It may be noted that the number of transistors required
for the realization of the adiabatic circuit is larger than that of the static
CMOS realization of the same function.
The power clock generators can be grouped into two main types:
asynchronous and synchronous. Asynchronous power clock generators are
free running circuits that use feedback loops to self-oscillate without any
external timing signals. Figure 10.7 illustrates two commonly used
asynchronous power clock generators: 2N and 2N2P power clock
generators. These are simple, dual-rail LC oscillators where the active
elements are cross-coupled pairs of NMOS and PMOS transistors.
Asynchronous structures are associated with several problems. Using
phase-locked loops or synchronizers such as self-timed first-in-first-out
(FIFO) memory devices would not be energy- and area-efficient solutions
to this problem. In such cases, the synchronous power clock generators
provide a better alternative in terms of efficiency.
The switch devices are shown as nMOS transistors in Fig. 10.11, yet
some of them may be successively connected to constant voltage sources
Vi through an array of switches replaced by pMOS transistors to prevent
the undesirable threshold volt-age drop problem and the substrate-bias
effects at higher voltage levels.
b. Delay constraint: the profile length is within the delay budget; and