En DM00226326
En DM00226326
Application note
Using the hardware real-time clock (RTC) in low-power modes with
STM32L0 Series and STM32L4 Series MCUs
Introduction
A real-time clock (RTC) is a computer clock that keeps track of the current time. Although
the RTCs are often used in personal computers, servers and embedded systems, they are
also present in almost any electronic device that requires an accurate time keeping. The
microcontrollers supporting the RTC can be used for chronometers, alarm clocks, watches,
small electronic agendas, and many other devices.
This application note describes the features of the real-time clock (RTC) controller embedded
in the ultra-low-power STM32L0 Series and STM32L4 Series microcontrollers and the steps
required to configure the RTC for the use with the calendar, alarm, periodic wakeup unit,
tamper detection, timestamp and calibration applications.
Software examples are then provided to show how to use the RTC in the low-power modes
and how to ensure the tampering detection and timestamp while the main supply is switched
off and the MCU is supplied by an alternate battery.
The X-CUBE-RTC embedded software package is delivered with this application note,
containing the source code of the RTC examples and all the embedded software modules
required to run the examples.
Contents
6 Reference documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
List of tables
List of figures
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Configure the time format (12h Set FMT bit in RTC_CR FMT = 0: 24 hour/day format
6
or 24h) register FMT = 1: AM/PM hour format
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Note: The RTCSEL[1:0] bits are the RCC Control/status register (RCC_CSR) [17:16] bits
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Note: The RTCSEL[1:0] bits are the backup domain control register (RCC_BDCR) [9:8] bits
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where:
• RTCCLK can be any clock source: HSE_RTC, LSE or LSI
• PREDIV_A can be 1,2,3,..., or 127
• PREDIV_S can be 0,1,2,..., or 32767
Table 2 shows several ways to obtain the calendar clock (ck_spre) = 1 Hz.
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1. RTC_ALRMAR is an RTC register. The same fields are also available for the RTC_ALRMBR register.
2. RTC_ALRMASSR is an RTC register. The same field is also available for the RTC_ALRMBSSR register.
3. Maskx are bits in the RTC_ALRMAR register that enable/disable the RTC_ALARM fields used for alarm A.
For more details, refer to Table 4.
4. Mask ss are bits in the RTC_ALRMASSR register.
An alarm consists of a register with the same length as the RTC time counter. When the
RTC time counter reaches the value programmed in the alarm register, a flag is set to
indicate that an alarm event occurred.
The STM32Lx RTC alarm can be configured by hardware to generate different types of
alarms. For more details, refer to Table 4.
Caution: If the second field is selected (MSK0 bit reset in RTC_ALRMAR or RTC_ALRMBR), the
synchronous prescaler division factor PREDIV_S set in the RTC_PRER register must be at
least 3 to ensure a correct behavior.
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Note: Mask ss is the most significant bit in the sub-second alarm. This bit is compared to the
synchronous prescaler register.
The alarm sub-second can be configured using the mask ss bit in the alarm sub-second
register. Table 5: Alarm sub-second mask combinations shows the configuration
possibilities for the mask register and provides an example with the following settings:
• Select LSE as the RTC clock source (for example LSE = 32768 Hz).
• Set the Asynchronous prescaler to 127.
• Set the Synchronous prescaler to 255 (the calendar clock is equal to 1Hz).
• Set the alarm A sub-second to 255 (put 255 in the SS[14:0] field).
There is no comparison on sub-second for alarm. The alarm is The alarm is activated every
0
activated when the second unit is incremented. 1 second
Only the AlarmA_SS[0] bit is compared to the RTC sub-second The alarm is activated every
1
register RTC_SSR (1/128) s
Only the AlarmA_SS[1:0] bit is compared to the RTC sub-second The alarm is activated every
2
register RTC_SSR (1/64) s
Only the AlarmA_SS[2:0] bit is compared to the RTC sub-second The alarm is activated every
3
register RTC_SSR (1/32) s
Only the AlarmA_SS[3:0] bit is compared to the RTC sub-second The alarm is activated every
4
register RTC_SSR (1/16) s
Only the AlarmA_SS[4:0] bit is compared to the RTC sub-second The alarm is activated every
5
register RTC_SSR 125 ms
Only the AlarmA_SS[5:0] bit is compared to the RTC sub-second The alarm is activated every
6
register RTC_SSR 250 ms
Only the AlarmA_SS[6:0] bit is compared to the RTC sub-second The alarm is activated every
7
register RTC_SSR 500 ms
Only the AlarmA_SS[7:0] bit is compared to the RTC sub-second
8 The alarm is activated every 1 s
register RTC_SSR
Only the AlarmA_SS[8:0] bit is compared to the RTC sub-second
9 The alarm is activated every 1 s
register RTC_SSR
Only the AlarmA_SS[9:0] bit is compared to the RTC sub-second
10 The alarm is activated every 1 s
register RTC_SSR
Only the AlarmA_SS[10:0] bit is compared to the RTC sub-second
11 The alarm is activated every 1 s
register RTC_SSR
Only the AlarmA_SS[11:0] bit is compared to the RTC sub-second
12 The alarm is activated every 1 s
register RTC_SSR
Only the AlarmA_SS[12:0] bit is compared to the RTC sub-second
13 The alarm is activated every 1 s
register RTC_SSR
Only the AlarmA_SS[13:0] bit is compared to the RTC sub-second
14 The alarm is activated every 1 s
register RTC_SSR
Only the AlarmA_SS[14:0] bit is compared to the RTC sub-second
15 The alarm is activated every 1 s
register RTC_SSR
Note: The overflow bit in the sub-second register (bit15) is never compared.
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When RTCCLK= 32768 Hz, the minimum timebase/wakeup resolution is 61.035 µs, and the
maximum resolution is 488.28 µs. As a result:
• The minimum timebase/wakeup period is (0x0001 + 1) x 61.035 µs = 122.07 µs.
The timebase/wakeup timer counter WUT[15:0] cannot be set to 0x0000 with
WUCKSEL[2:0]=011b (fRTCCLK/2) because this configuration is prohibited. Refer to the
STM32Lx reference manuals for more details.
• The maximum timebase/wakeup period is (0xFFFF+ 1) x 488.28 µs = 32 s.
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The user can compute the clock deviation using the RTC_CALIB signal, then update the
calibration block. It is possible to check the calibration result using the calibration output 512
Hz or 1 Hz for the RTC_CALIB signal. Refer to Table 13: Advanced RTC features.
A smooth calibration consists of masking and adding N (configurable) 32 kHz pulses that
are well distributed in a configurable window (8 s, 16 s or 32 s).
The number of masked or added pulses is defined using CALP and CALM in the
RTC_CALR register.
By default, the calibration window is 32 seconds. It can be reduced to 8 or 16 seconds by
setting the CALW8 bit or the CALW16 bit in the RTC_CALR register:
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It is not possible to check the “Synchronization” Shift function using the RTC_CALIB output
since the shift operation has no impact on the RTC clock, other than adding or subtracting a
few fractions from the calendar counter.
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Note: The reference clock calibration and the RTC synchronization (shift feature) cannot be used
together.
The reference clock calibration is the best (ensures a high calibrated time) if the 50 Hz is
always available. If the 50 Hz input is lost, the RTC accuracy is provided by the LSE crystal.
The reference clock detection cannot be used in Vbat mode.
The reference clock calibration can only be used if the user provides a precise 50 or 60 Hz
input.
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Provided that the time-stamp function is enabled, the calendar is saved in the time-stamp
registers (RTC_TSTR, RTC_TSDR, RTC_TSSSR) when an internal or external time-stamp
event is detected. When a time-stamp event occurs, the time-stamp flag bit (TSF) in the
RTC_ISR register is set.
The events that can generate a timestamp are:
– An edge detection on the RTC_TS I/O
– A tamper event detection (from all RTC_TAMP I/Os)
– A switch to VBAT when the main supply if powered off (STM32L4x devices only)
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1. If the power consumption is not a concern, the internal 40 kΩ pull-up resistor can be used.
Note: With the edge detection, the sampling and precharge features are deactivated.
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Using the level detection (tamper filter set to a non-zero value), the tamper input pin can be
precharged by resetting TAMPPUDIS through an internal resistance before sampling its
state. In order to support the different capacitance values, the length of the pulse during
which the internal pull-up is applied can be 1, 2, 4 or 8 RTCCLK cycles.
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Note: When the internal pull-up is not applied, the I/Os Schmitt triggers are disabled in order to
avoid an extra consumption if the tamper switch is open.
The trade-off between the tamper detection latency and the power consumption through the
weak pull-up or external pull-down can be reduced by using a tamper sampling frequency
feature. The tamper sampling frequency is determined by configuring the TAMPFREQ bits
in the RTC_TAMPCR register. When using the LSE at 32768 Hz as the RTC clock source,
the sampling frequency can be 1, 2, 4, 8, 16, 32, 64, or 128 Hz.
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When the system is woken up from low-power modes (SYSCLK was off), the application
must first clear the RSF bit, and then wait until it is set again before reading the calendar
registers. This ensures that the value read by the application is the current calendar value,
and not the value before entering the low-power mode.
By setting the “BYPSHAD” bit to ‘1’ in the RTC_CR register, the calendar values are taken
directly from the calendar counters instead of reading the shadow register. In this case, it is
not mandatory to wait for the synchronization time, but the calendar registers consistency
must be checked by the software. The user must read the required calendar field values.
The read operation must then be performed again. The results of the two read sequences
are then compared. If the results match, the read result is correct. If they do not match, the
fields must be read one more time, and the third read result is valid.
Note: After resetting the BYPSHAD bit, the shadow registers may be incorrect until the next
synchronization. In this case, the software should clear the “RSF” bit then wait for the
synchronization (“RSF” should be set) and finally read the shadow registers.
Alarm event X X
RTC_ALARM
Wakeup event X X
RTC Outputs
512 Hz X X
RTC_CALIB
1 Hz X X
The RTC is designed to minimize the power consumption: the Real-Time Clock functionality
only adds typically 300nA to the current consumption.
The RTC keeps working in reset mode and its registers are only reset by a VDD or VBAT
power-on, if both supplies have previously been powered off. As the RTC register values
are not lost after a system reset, the calendar keeps the correct time and date until VDD and
VBAT power down.
Note: In the STM32L0 Series, the VBAT mode is not available.
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JP7
PA0
JP12
JP17
USB
Power-Supply
User LEDs
Supply the board using the USB cable. For this example to work, the user needs to tie PA0
(tamper pin 2) to 0. In order to do that :
• Remove jumper JP7
• Connect CN7 pin 37 to GND.
Note: PC13 (tamper pin 1) connected to the blue push-button was not used in this demonstration
firmware as it is connected to an external pull-down resistor preventing the use of the
tamper detection on level with internal pull-up (lowest consumption mode).
For more information, refer to [3].
Supply the board using the USB cable. In this example, the user uses the B1 push button to
simulate the external tamper event. The user can observe the software "private variables"
on LED LD2 and CN5 Pin 6 (SCK/D13). Details regarding the LED LD2 behavior are
available in main.c file.
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The user can observe these "private variables" using the live watch feature in the debugger.
The user can observe these "private variables" on LED LD2 and CN5 Pin 6 (SCK/D13).
Regarding the LED LD2 behavior, see details in main.c file.
LED1_Green_Tamper_event_detected 0 OFF
LED2_Red_Power_On_Reset_occurred 1 ON
LED3_Red_Error 0 OFF
LED4_Blue_Reset_occurred 1 ON
LED1_Green_Tamper_event_detected 1 ON
LED2_Red_Power_On_Reset_occurred 1 ON
LED3_Red_Error 0 OFF
LED4_Blue_Reset_occurred 1 ON
LED1_Green_Tamper_event_detected 0 OFF
LED2_Red_Power_On_Reset_occurred 0 OFF
LED3_Red_Error 0 OFF
LED4_Blue_Reset_occurred 1 ON
LED1_Green_Tamper_event_detected 1 ON
LED2_Red_Power_On_Reset_occurred 0 OFF
LED3_Red_Error 0 OFF
LED4_Blue_Reset_occurred 1 ON
6 Reference documentation
7 Revision history
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