ISA 2 Regular Solution-1
ISA 2 Regular Solution-1
ISA 2 Regular Solution-1
1.a With neat diagram explain data flow for interrupt cycle.
• Thus, the contents of the PC are transferred to the MBR to
be written into memory.
• The special memory location reserved for this purpose is
loaded into the MAR from the control unit.
• It might, for example, be a stack pointer.
• The PC is loaded with the address of the interrupt routine.
(3 marks) • As a result, the next instruction cycle will begin by fetching
• The current contents of the PC must be saved so that the the appropriate instruction. (2 marks)
processor can resume normal activity after the interrupt.
b Assume a superscalar pipeline capable of fetching and decoding two instructions at a time, having three 5
separate functional units and having two instances of the write-back pipeline stage.
i. I1 requires three cycles to execute
ii. I3 and I4 compete for the same execution unit
iii. I5 requires two cycles to execute
iv. I5 and I6 compete for the same execution unit
Show the issue and completion policies for out-of-order issue and out-of-order completion
c What is cache coherence? Explain the software method to deal with the same. 5
d Explain various multicore organization alternatives. (4x1 mark for each figure + 1 mark explanation) 5
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B. V. B. College of Engineering & Technology
I1 & I2: RAW I1 & I3: WAW I2 & I3: WAR I3 & I4: RAW I4 & I5: RAW (1 mark each)
(2 marks)
(5 marks)
b A microprocessor provides an instruction capable of moving a set of ASCII values from one area of memory to another. 5
The fetching takes 6 clock cycles and decoding of the instruction takes 2 clock cycles. Thereafter, it takes 10 clock cycles
to transfer each ASCII value. The microprocessor is clocked at a rate of 8GHz.
a. Determine the length of the instruction cycle for the case of 32 ASCII characters.
b. What is the worst-case delay for acknowledging an interrupt if the instruction is non-interruptible?
c. Repeat part (b) assuming the instruction can be interrupted at the beginning of each transfer.
a. The length of the clock cycle is 0.125ns. The length of the instruction cycle for this case is
[8+(10 x 32)] x 0.125 = 41ns……..(1 mark)
b. The worst case delay is when the interrupt occurs just after the start of the instruction, which is 41ns. ……..(1 mark)
c. In this case, the instruction can be interrupted after the instruction fetch, which takes 6 clock cycles, so the delay is
(6 x 0.125 = 0.75ns), the instruction can be interrupted after the instruction decode, which takes 2 clock cycles, so
the delay is (2 x 0.125 = 0.25ns). The instruction can be interrupted between byte transfers, which results in a delay
of no more than 10 clock cycles = 1.25 ns. Hence worst case delay is 1.25ns. ……..(3 marks)
c Consider a situation in which there are 5 SMPs P1, P2, P3, P4 and P5. All of them have a cache and use the MESI protocol. 5
Initially, P1 and P3 have a copy of ‘x’. With a neat state diagram and relevant signals explain transitions that take place for
the following sequence of events:
i. P4 intends to modify x.
ii. P5 intends to modify x
Earlier known as
B. V. B. College of Engineering & Technology
(5 marks)