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Module - 1 Notes
Module - 1 Notes
Code Code
Generation Generation
Greater
Complexity Processor Processor
RISC CISC
Q. What are the silent features of ARM instruction set are suitable for embedded applications?
Answer:
In the following ways that make the ARM instruction set suitable for embedded applications:
Variable cycle execution for certain instructions—Not every ARM instruction executes in a
single cycle. For example, load-store-multiple instructions vary in the number of execution cycles
depending upon the number of registers being transferred.
Inline barrel shifter leading to more complex instructions—The inline barrel shifter is a
hardware component that preprocesses one of the input registers before it is used by an instruction.
This expands the capability of many instructions to improve core performance and code density.
Thumb 16-bit instruction set—ARM enhanced the processor core by adding a second 16-bit
instruction set called Thumb that permits the ARM core to execute either 16- or 32-bit instructions.
Conditional execution— An instruction is only executed when a specific condition has been
satisfied. This feature improves performance and code density by reducing branch instructions.
Enhanced instructions—The enhanced digital signal processor (DSP) instructions were added to
the standard ARM instruction set to support fast 16×16-bit multiplier operations.
Or
With a neat diagram explain the different hardware components of an embedded device based on ARM
core.
Answer: Figure shown below shows a typical embedded device based on ARM core. Each box represents
a feature or function.
ARM ROM
Processor Memory Controller FLASH ROM
SRAM
DRAM
Interrupt Controller
AHB-external bridge External bus
AHB Arbiter
AHB-APB bridge
Ethernet
Real-time clock
Counter/timers
Console Serial UARTs
ARM processor based embedded system hardware can be separated into the following four main
hardware components:
o The ARM processor: The ARM processor controls the embedded device. Different
versions of the ARM processor are available to suits the desired operating characteristics.
o Controllers: Controllers coordinate important blocks of the system. Two commonly found
controllers are memory controller and interrupt controller.
o Peripherals: The peripherals provide all the input-output capability external to the chip
and responsible for the uniqueness of the embedded device.
o Bus: A bus is used to communicate between different parts of the device.
ARM Bus Technology
o Embedded devices use an on-chip bus that is internal to the chip and that allows different
peripheral devices to be interconnected with an ARM core.
o There are two different classes of devices attached to the bus.
The ARM processor core is a bus master—a logical device capable of initiating a
data transfer with another device across the same bus.
Peripherals tend to be bus slaves—logical devices capable only of responding to
a transfer request from a bus master device.
AMBA Bus Protocol
o
The Advanced Microcontroller Bus Architecture (AMBA) was introduced in 1996 and has
been widely adopted as the on-chip bus architecture used for ARM processors.
o The first AMBA buses introduced were the ARM System Bus (ASB) and the ARM
Peripheral Bus (APB).
o Later ARM introduced another bus design, called the ARM High Performance Bus (AHB).
o AHB provides higher data throughput than ASB because it is based on a centralized
multiplexed bus scheme rather than the ASB bidirectional bus design.
MEMORY
o An embedded system has to have some form of memory to store and execute code.
o Figure below shows the memory trade-offs: the fastest memory cache is physically located
nearer the ARM processor core and the slowest secondary memory is set further away.
o Generally the closer memory is to the processor core, the more it costs and the smaller its
capacity.
PERIPHERALS
o Embedded systems that interact with the outside world need some form of peripheral
device.
o Controllers are specialized peripherals that implement higher levels of functionality within
the embedded system.
o Memory controller: Memory controllers connect different types of memory to the
processor bus.
o Interrupt controller: An interrupt controller provides a programmable governing policy
that allows software to determine which peripheral or device can interrupt the processor at
any specific time.
Answer:
An embedded system requires software to drive it. Figure below shows typical software
components required to control an embedded device.
Each software components in the stack uses a higher level of abstraction to separate the code from
the hardware device.
Applications
Operating System
Initialization Divice drivers
Hardware device
An ARM core as functional units connected by data buses, as shown in Figure1, where, the arrows
represent the flow of data, the lines represent the buses, and the boxes represent either an operation
unit or a storage area.
The instruction decoder translates instructions before they are executed.
The ARM processor, like all RISC processors, uses a load - store architecture.
Load instructions copy data from memory to registers, and conversely the store instructions copy
data from registers to memory.
There are no data processing instructions that directly manipulate data in memory.
ARM instructions typically have two source registers, Rn and Rm, and a single destination register,
Rd. Source operands are read from the register file using the internal buses A and B, respectively.
The ALU (arithmetic logic unit) or MAC (multiply-accumulate unit) takes the register values Rn
and Rm from the A and B buses and computes a result.
Data processing instructions write the result in Rd directly to the register file.
Load and store instructions use the ALU to generate an address to be held in the address register
and broadcast on the Address bus.
One important feature of the ARM is that register Rm alternatively can be preprocessed in the barrel
shifter before it enters the ALU.
After passing through the functional units, the result in Rd is written back to the register file using
the Result bus.
For load and store instructions the incrementer updates the address register before the core reads or
writes the next register value from or to the next sequential memory location.
REGISTERS
Q5. Explain briefly the active registers available in user mode.
OR
With a neat diagram explain the different general purpose registers of ARM processors.
Answer: Figure shown below shows the active registers available in user mode. All the registers shown
are 32 bits in size.
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
cpsr
-
There are up to 18 active registers: 16 data registers and 2 processor status registers. The data
registers are visible to the programmer as r0 to r15.
The ARM processor has three registers assigned to a particular task: r13, r14 and r15.
Register r13: Register r13 is traditionally used as the stack pointer (sp) and stores the head of the
stack in the current processor mode.
Register r14: Register r14 is called the link register (lr) and is where the core puts the return address
whenever it calls a subroutine.
Register r15: Register r15 is the program counter (pc) and contains the address of the next
instruction to be fetched by the processor.
In addition to the 16 data registers, there are two program status registers: current program status
register (cpsr) and saved program status register (spsr).
CPSR (Current Program Status Register)
Q6. Explain the various fields in current program status register (CPSR) with neat diagram.
Answer: Figure below shows the basic layout of a generic program status register.
N Z C V I F T Mode
Function
Mode Mode[4:0]
Abort 10111
Fast interrupt request 10001
Interrupt request 10010
Supervisor 10011
System 11111
Undefined 11011
User 10000
When cpsr bit 5, T=1, then the processor is in Thumb state. When T=0, the processor is in ARM
state.
The cpsr has two interrupt mask bits, 7 and 6 (I and F) which control the masking Interrupt request
(IRQ) and Fast Interrupt Request (FIR).
Condition flags are updated by comparisons and the result of ALU operations that specify the S
instruction suffix.
For example, if SUBS subtract instruction results in a register value of zero, then the Z flag in the
cpsr is set.
Processor Mode
Answer:
PIPELINE
Q9. With neat diagram explain the various blocks in a 3 stage pipeline of ARM processor
organization.
OR
Explain ARM pipeline with 3,5,6 stages.
Answer:
Pipeline is the mechanism to speed up execution by fetching the next instruction while other
instruction are being decoded and executed.
Figure 1 shows the ARM7 three-stage pipeline.
Cycle 1 ADD
Time
Cycle 2 SUB ADD
The pipeline design for each ARM family differs. For example, the ARM9 core increases the
pipeline length to five stages as shown in the figure below.
The ARM10 increases the pipeline length still further by adding a sixth stage as shown in the figure
below.
As the pipeline length increases the amount of work done at each stage is reduced, which allows
the processor to attain a higher operating frequency. This in turn increases the performance.
Pipeline Executing Characteristics
a. The ARM pipeline has not processed an instruction until it passes completely through the
execute stage. For example, an ARM7 pipeline (with three stages) has executed an instruction
only when the fourth instruction is fetched. Figure below shows an instruction sequence on an
ARM7 pipeline.
Figure 1: ARM instruction sequence
b. In the execute stage, the pc always points to the address of the instruction plus 8 bytes. In other
words, the pc always points to the address of the instruction being executed plus two
instructions ahead as shown in figure 2 below
Reset vector is the location of the first instruction executed by the processor when power is applied.
This instruction branches to the initialization code.
Undefined instruction vector is used when the processor cannot decode the instruction.
Software interrupt vector is called when SWI instruction is executed. The SWI is frequently used
as the mechanism to invoke an operating system routine.
Prefetch abort vector occurs when the processor attempts to fetch an instruction from an address
without the correct access permissions.
Data abort vectors is similar to a prefetch abort but is raised when an instruction attempts to access
data memory without the correct access permissions.
Interrupt request vector is used by external hardware to interrupt the normal execution flow of
the processor.
Fast interrupt request vector is similar to the interrupt request but is reserved for hardware
requiring faster response times.
Core Extensions
Q11. Discuss the following with neat diagrams
a. Von Neumann architecture with cache
b. Harvard architecture with TCM
OR
Discuss all 3 core extensions.
Answer:
There are three core extensions wrap around ARM processor: cache and tightly coupled memory, memory
management and the coprocessor interface.
1. Cache and tightly coupled memory: The cache is a block of fast memory placed between main
memory and the core. With a cache the processor core can run for the majority of the time without
having to wait for data from slow external memory.
o ARM has two forms of cache. The first found attached to the Von Neumann-style cores. It
combines both data and instruction into a single unified cache as shown in the figure 1
below.
Figure 1: A simplified Von Neumann architecture with cache.
o The second form, attached to the Harvard-style cores, has separate cache for data and
instruction as shown figure 2
o A cache provides an overall increase in performance but will not give predictable
execution.
o But for real-time systems it is paramount that code execution is deterministic.
o This is achieved using a form of memory called tightly coupled memory (TCM).
o TCM is fast SRAM located close to the core and guarantees the clock cycles required to
fetch instructions or data.
o By combining both technologies, ARM processors can behave both improved performance
and predictable real-time response. The following diagram shows an example of core with
a combination of caches and TCMs as shown in figure 3
Figure 3: combining both technologies
2. Memory management:
Embedded systems often use multiple memory devices. It is usually necessary to have a method to
help organize these devices and protect the system from applications trying to make appropriate
accesses to hardware.
This is achieved with the assistance of memory management hardware.
ARM cores have three different types of memory management hardware- no extensions provide no
protection, a memory protection unit (MPU) providing limited protection and a memory
management unit (MMU) providing full protection.
o Nonprotected memory is fixed and provides very little flexibility. It normally used for
small, simple embedded systems that require no protection from rogue applications.
o Memory protection unit (MPU) employs a simple system that uses a limited number of
memory regions. These regions are controlled with a set of special coprocessor registers,
and each region is defined with specific access permission but don’t have a complex
memory map.
o Memory management unit (MMU)are the most comprehensive memory management
hardware available on the ARM. The MMU uses a set of translation tables to provide fine-
grained control over memory.
These tables are stored in main memory and provide virtual to physical address
map as well as access permission. MMU designed for more sophisticated system
that supports multitasking.
3. Coprocessors:
A coprocessor extends the processing features of a core by extending the instruction set or by
providing configuration registers.
More than one coprocessor can be added to the ARM core via the coprocessor interface.
The coprocessor can be accessed through a group of dedicated ARM instructions that provide a
load-store type interface.
The coprocessor can also extend the instruction set by providing a specialized instructions that can
be added to standard ARM instruction set to process vector floating-point (VFP) operations.
These new instructions are processed in the decode stage of the ARM pipeline. If the decode stage
sees a coprocessor instruction, then it offers it to the relevant coprocessor.
But, if the coprocessor is not present or doesn’t recognize the instruction, then the ARM takes an
undefined instruction exception.