DCP Notes
DCP Notes
DCP Notes
ON
Digital Computing Platforms
()
Prepared by
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
B.Tech (EEE)– III-II Sem L T P C
3 0 0 3
DIGITAL COMPUTING PLATFORMS
Course Objectives:
Architecture and designing of 8086 Microprocessor with Assembling language programming
and interfacing with various modules
Understand the Interfacing of 8086 with various advanced communication devices
Designing of 8051 Microcontroller with Assembling language programming and interfacing
with various modules
To know about Assembly Language Programs for the Digital Signal Processors and usage of
Interrupts
To understand Xilinx programming and understanding of Spartan FPGA board
Course Outcomes:
Understand the basic architecture & pin diagram of 8086 microprocessor, 8051
Microcontroller, DSP Processor and FPGA Processors
Apply the concepts to design Assembly language programming to perform a given task,
Interrupt service routines for all interrupt types
Design Real time applications by writing Assembly Language Programs for the Digital Signal
Processors, Xilinx programming for Spartan FPGA boards and use Interrupts for real-time
control applications
Analyse various real time systems by using various controllers
UNIT I INTRODUCTION TO MICROPROCESSORS
Historical background- Evolution of microprocessors up to 64-bit. Architecture of 8086
microprocessor, special function of general purpose registers. 8086 flag registers and functions of 8086
flags – Addressing modes of 8086 – Instruction set of 8086 – Assembler directives - Pin diagram 8086
– Minimum mode and maximum mode of operation - Timing diagrams - CISC and ARM Processors.
UNIT IIASSEMBLY LANGUAGE PROGRAMMING & I/O INTERFACE
Assembler directives – macros – simple programs involving logical – branch instructions – sorting –
evaluating arithmetic expressions - string manipulations – 8255 PPI - various modes of operation - A/D
- D/A converter interfacing, Memory interfacing to 8086 – interrupt structure of 8086 – vector interrupt
table – interrupt service routine – interfacing interrupt controller 8259 - Need of DMA – serial
communication standards – serial data transfer schemes.
UNIT III8051 MICRO CONTROLLER PROGRAMMING AND APPLICATIONS
Introduction to micro controllers, Functional block diagram, Instruction sets and addressing modes,
interrupt structure – Timer – I/O ports – serial communication. Data transfer, manipulation, Control and
I/O instructions – simple programming exercises key board and display interface – Closed loop control
of servo motor – stepper motor control.
UNIT IVINTRODUCTION TO TMS320LF2407 DSP CONTROLLER
Basic architectural features - Physical Memory - Software Tools. Introduction to Interrupts - Interrupt
Hierarchy - Interrupt Control Registers. C2xx DSP CPU and Instruction Set: Introduction & code
Generation - Components of the C2xx DSP core - Mapping External Devices to the C2xx core -
peripheral interface - system configuration registers - Memory - Memory Addressing Modes -
Assembly Programming Using the C2xx DSP Instruction set.
UNIT V FIELD PROGRAMMABLE GATE ARRAYS (FPGA)
Introduction to Field Programmable Gate Arrays – CPLD Vs FPGA – Types of FPGA – Xilinx,
XC3000 series - Configurable logic Blocks (CLB) – Input / Output Block (IOB) – Programmable
Interconnect Point (PIP) – Xilinx 4000 series – HDL programming –overview of Spartan 3E and Virtex
II pro FPGA boards- case study.
Textbooks:
1. Ramesh S. Gaonkar, DI Architecture Programming and Applications with8085, Penram Intl.
Publishing, 6th Edition, 2013
2. Ray A. K., Bhurchandi K. M., Advanced Microprocessor and Peripherals, Tata McGraw-
Hill Publications, 3rd Edition, 2013.
Reference Books:
1. Microprocessor and Interfacing by Douglas V Hall, 2 nd Edition, Tata McGraw hill, 1992
2. Microprocessor, Nilesh B Bahadure, PHI, 2010.
3. The 8051 Micro Controller Architecture, Programming and Applications by Kenneth J
Ayala, Pearson International publishing (India).
4. Hamid A. Tolyat, DSP Based Electro Mechanical Motion Control, CRC press, 2004.
5. Application Notes from the webpage of Texas Instruments.
6. XC 3000 series datasheets (version 3.1). Xilinx Inc., USA, 1998
7. XC 4000 series datasheets (version 1.6). Xilinx Inc., USA, 1999
8. Wayne Wolf, FPGA based system design, Prentice hall, 2004.
instructions from a storage device called memory accepts binary data as input and processes data
according to those instructions and provides results as output
EVOLUTION OF MICROPROCESSORS:
The microprocessor age began with the advancement in the IC technology to put all necessary
functions of a CPU into a single chip.
Intel started marketing its first microprocessor in the name of Intel 4004 in 1971. This was a4-bit
microprocessor having 16-pins in a single chip of PMOS technology. This was called the first generation
microprocessor. The Intel 4004 along with few other devices was used for making calculators. The 4004
instruction set contained only 45 instructions. Later in 1971, INTEL Corporation released the 8008 an
extended 8-bit version of the 4004 microprocessor. The 8008 addressed an expanded memory size
(16KB) and 48 instructions.
Limitations of first generation microprocessors is small memory size, slow speed and instruction set
limited its usefulness.
Second generation microprocessors:
The second generation microprocessor using NMOS technology appeared in the market in the year 1973.
The Intel 8080, an 8-bit microprocessor, of NMOS technology was developed in the year 1974 which
required only two additional devices to design a functional CPU. The
advantages of second generation microprocessors were
Large chip size (170x200 mil) with 40-pins. More chips on decoding circuits.
Ability to address large memory space (64-K Byte) and I/O ports(256). More powerful instruction sets.
Dissipate less power.
The 8080 microprocessor addresses more memory and execute additional instructions, but executes
them 10 times faster than 8008.The 8080 has memory of 64 KB whereas for 8008 16 KB only. In 1977,
INTEL, introduced 8085 which was an updated version of 8080 last 8-bit processor.
The main advantages of 8085 were its internal clock generator, internal system controller and
higher clock frequency.
Third Generation Microprocessor:
In 1978, INTEL released the 8086 microprocessor, a year later it released 8088. Both devices were 16 bit
microprocessors, which executed instructions in less than 400ns.The 8086 and 8088 addresses 1MB of
memory and rich instruction set to 246.16-bit processors were designed using HMOS technology. The
Intel 80186 and 80188 were the improved versions of Intel 8086 and8088, respectively. In addition to 16-
bit CPU, the 80186 and 80188 had programmable peripheral devices integrated on the same package.
Fourth Generation Microprocessor:
The single chip 32-bit microprocessor was introduced in the year 1981 by Intel as iAPX 432. The other
4thgeneration microprocessors were; Bell Single Chip Bellmac-32, Hewlett-Packard, National NSl
6032,Texas Instrument99000. Motorola 68020 and 68030. The Intel in the year 1985 announced the 32-
bit microprocessor(80386). The 80486 has already been announced and is also a 32-bit microprocessor.
The 80486 is a combination 386 processor a math coprocessor, and a cache memory controller on a single
chip.
The Pentium is a 64-bit superscalar processor. It can execute more than one instruction at a time
and has a full 64-bit data bus and 32-bit address bus. Its performance is double than 80486.
Features of 8086:
-
-fetches up to 6 instruction bytes from memory and queues them in order to speed up
instruction execution.
Architecture of 8086:
8086 has two blocks BIU and EU.
The BIU performs all bus operations such as instruction fetching, reading and writing operands for
memory and calculating the addresses of the memory operands. The instruction bytes are transferred
to the instruction queue.
EU executes instructions from the instruction byte queue.
Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution
mechanism which is called as Pipelining. This results in efficient use of the system bus and system
performance.
BIU contains Instruction queue, Segment registers, IP, address adder.
EU contains control circuitry, Instruction decoder, ALU, Flag register.
The BIU is responsible for performing all external bus operations.
Specifically it has the following functions:
Instructions fetch Instruction queuing, Operand fetch and storage, Address relocation and Bus control.
The BIU uses a mechanism known as an instruction stream queue to implement pipeline architecture.
This queue permits pre-fetch of up to six bytes of instruction code. Whenever the queue of the BIU
is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to
read or write operands from memory, the BIU is free to look ahead in the program by pre-
fetching the next sequential instruction.
These pre-fetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two
For example: The physical address of the next instruction to be fetched is formed by combining the
current contents of the code segment CS register and the current contents of the instruction pointer IP
register.
The BIU is also responsible for generating bus control signals such as those for memory read or write
and I/O read or write.
Execution Unit:
The EU extracts instructions from top of the queue in the BIU, decodes them, generates operands if
necessary, passes them to the BIU and requests it to perform the read or write bus cycles to memory or
I/O and perform the operation specified by the instruction on the operands.
During the execution of the instruction, the EU tests the status and control flags and updates them based
on the results of executing the instruction.
If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the
queue.
When the EU executes a branch or jump instruction, it transfers control to a location corresponding to
another set of sequential instructions.
When ever this happens, the BIU automatically resets the queue and then begins to fetch instructions
from this new location to refill the queue.
default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP)
registers is located in the stack segment. SS register can be changed directly using POP instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By
default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and
index register (SI, DI) is located in the data segment.DS register can be changed directly using POP and
LDS instructions.
Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and
used as a 16-bit register AX. AL in this case contains the low order byte of the word, and AH contains
the high-order byte. Accumulator can be used for I/O operations and string manipulation.
Base register consists of two 8-bit registers BL and BH, which can be combined together and used as a
16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-
order byte. BX register usually contains a data pointer used for based, based indexed or register indirect
addressing.
Count register consists of two 8-bit registers CL and CH, which can be combined together and used as
a 16-bit register CX. When combined, CL register contains the low order byte of the word, and CH
contains the high-order byte. Count register can be used in Loop, shift/rotate instructions and as a
counter in string manipulation,.
Data register consists of two 8-bit registers DL and DH, which can be combined together and used as a
16-bit register DX. When combined, DL register contains the low order byte of the word, and DH
contains the high-order byte. Data register can be used as a port number in I/O operations. In integer 32-
bit multiply and divide instruction the DX register contains high-order word of the initial or resulting
number.
program proceeds further. The contents of IP and CS register are used to compute the memory address of
the instruction code to be fetched.
General purpose register Segment register Pointer and Index
Flag register of 8086: It is a 16-bit register, also called flag register or Program Status Word (PSW).
Seven bits remain unused while the rest nine are used to indicate the conditions of flags. The status flags
of the register are shown below in Fig.
Out of nine flags, six are condition flags and three are control flags. The control flags
are TF (Trap), IF (Interrupt) and DF (Direction) flags, which can be set/reset by the
programmer, while the condition flags [OF (Overflow), SF (Sign), ZF (Zero), AF (Auxiliary
Carry), PF (Parity) and CF (Carry)] are set/reset depending on the results of some arithmetic or
logical operations during program execution.
CF is set if there is a carry out of the MSB position resulting from an addition operation or if a
borrow is needed out of the MSB position during subtraction.
PF is set if the lower 8-bits of the result of an operation contains an even number if
there is a carry out of bit 3 resulting from an addition operation or borrow required from bit 4 into
bit 3 during subtraction operation.
ZF is set if the result of an arithmetic or logical operation is zero.
SF is set if the MSB of the result of an operation is 1. SF is used with unsigned numbers.
OF is used only for signed arithmetic operation and is set if the result is too large to be fitted in the
number of bits available to accommodate it.
The three control flags of 8086 are TF, IF and DF. These three flags are programmable,
i.e., can be set/reset by the programmer so as to control the operation of the processor.
When TF (trap flag) is set (=1), the processor operates in single stepping mode i.e., pausing after
each instruction is executed. This mode is very useful during program development or program
debugging.
When an interrupt is recognized, TF flag is cleared. When the CPU returns to the main program from
ISS (interrupt service subroutine), by execution of IRET in the last line of ISS, TF flag is restored to
its value that it had before interruption.
TF cannot be directly set or reset. So indirectly it is done by pushing the flag register on the stack,
changing TF as desired and then popping the flag register from the stack.
When IF (interrupt flag) is set, the maskable interrupt INTR is enabled otherwise disabled (i.e.,
when IF = 0).
IF can be set by executing STI instruction and cleared by CLI instruction. Like TF flag, when an
interrupt is recognized, IF flag is cleared, so that INTR is disabled. In the last line of ISS when IRET
is encountered, IF is restored to its original value. When 8086 is reset, IF is cleared, i.e., resetted.
DF (direction flag) is used in string (also known as block move) operations. It can be set by STD
instruction and cleared by CLD. If DF is set to 1 and MOVS instruction is executed, the contents of
the index registers DI and SI are automatically decremented to access the string from the highest
memory location down to the lowest memory location.
Direct Addressing mode: In this mode, the instruction operand specifies the memory address where
data is located.
Example: MOV AX, [5000H]; Data is available in 5000H memory location
Effective Address (EA) is computed using 5000H as offset address and content of DS as segment
address.
EA=10H*DS+5000H
Register Addressing mode: In this mode, the data is stored in a register and it is referred using
particular register. All the registers except IP may be used in this mode.
Register Relative Addressing mode: In this mode, the data is available at an effective address
formed by adding an 8-bit or 16-bit displacement with the content of any one of the registers BX, BP,
SI, DI in the default segments.
Example: MOV AX, 50H [BX];
EA=10H * DS + 50H +[BX]
Based Indexed Addressing mode: In this mode, the contents of a base register (BX or BP) is added
to the contents of an index register (SI or DI), the resulting value is a pointer to location where data
resides.
Example: MOV AX, [BX] [SI];
Control Transfer Instructions: In control transfer instruction, the control can be transferred to
some predefined address or the address somehow specified in the instruction after their execution.
For the control transfer instructions, the addressing modes depend upon whether the destination
location is within the segment or different segments. It also depends upon the method of passing the
destination address to the processor. Depending on this control transfer instructions are categorized
as follows:
Intra segment Direct mode: In this mode, the address to which control is to be transferred lies in
the same segment in which control transfer instruction lies and appears directly in the instruction as
an immediate displacement value.
Intra segment Indirect mode: In this mode, the address to which control is to be transferred lies in
the same segment in which control transfer instruction lies but it is passed to the instruction
indirectly.
Inter segment Direct mode: In this mode, the address to which control is to be transferred lies in a
different segment in which control transfer instruction lies and appears directly in the instruction as
an immediate displacement value.
Inter segment Indirect mode: In this mode, the address to which control is to be transferred lies in
a different segment in which control transfer instruction lies but it is passed to the instruction
indirectly.
Memory segmentation, as implemented for 8086, gives rise to the following advantages:
Although the address bus is 20-bits in width, memory segmentation allows one to work with
registers having width 16-bits only.
It allows instruction code, data, stack and portion of program to be more than 64 KB long by using
more than one code, data, extra segment and stack segment.
In a time-shared multitasking environment when the program moves over from one
program to another, the CPU will simply have to reload the four segment registers with the
Because the logical address range is from 0000 H to FFFF H, the same can be loaded at any place
in the memory.
Instruction Set of 8086:
There are 117 basic instructions in the instruction set of 8086.The instruction set of 8086 can be
divided into the following number of groups, namely:
1. Data copy / Transfer instructions 2. Arithmetic and Logical instructions
3. Branch instructions 4. Loop instructions
5. Machine control instructions 6. Flag Manipulation instructions
7. Shift and Rotate instructions 8. String instructions
Data copy / Transfer instructions: The data movement instructions copy values from one location to
another. These instructions include MOV, XCHG, LDS, LEA, LES, PUSH, PUSHF, PUSHFD,
POP,POPF, LAHF, AND SAHF.
MOV The MOV instruction copies a word or a byte of data from source to a destination. The destination
can be a register or a memory location. The source can be a register, or memory location or
immediate data. MOV instruction does not affect any flags. The mov instruction takes several different
forms:
The MOV instruction cannot:
1. Set the value of the CS and IP registers.
2. Copy value of one segment register to another segment register (should copy to general register
first). MOV CS, DS (Invalid)
3. Copy immediate value to segment register (should copy to general register first). MOV CS, 2000H
(Invalid)
Example:
ORG 100h
MOV AX, 0B800h ; set AX = B800h
MOV DS, AX ; copy value of AX to DS.
MOV CL, 'A' ; CL = 41h (ASCII code).
The XCHG Instruction: Exchange This instruction exchanges the contents of the specified source and
destination operands, which may be registers or one of them, may be a memory location. However,
exchange of data contents of two memory locations is not permitted.
Example: MOV AL, 5 ; AL = 5
MOV BL, 2 ; BL = 2
XCHG AL,BL ; AL = 2, BL = 5
PUSH: Push to stack; this instruction pushes the contents of the specified register/memory location on to
the stack. The stack pointer is decremented by 2, after each execution of the instruction. The actual
current stack-top is always occupied by the previously pushed data. Hence, the push operation decrements
SP by two and then stores the two byte contents of the operand onto the stack. The higher byte is pushed
first and then the lower byte. Thus out of the two decremented stack addresses the higher byte occupies
the higher address and the lower byte occupies the lower address.
1. PUSH AX
2. PUSH DS
3. PUSH [500OH] ; Content of location 5000H and 5001 H in DS are pushed onto the stack.
POP: Pop from Stack this instruction when executed loads the specified register/memory location with
the contents of the memory location of which the address is formed using the current stack
segment and stack pointer as usual. The stack pointer is incremented by 2. The POP instruction serves
exactly opposite to the PUSH instruction.
1. POP BX
2. POP DS
3. POP [5000H]
PUSHF: Push Flags to Stack The push flag instruction pushes the flag register on to the stack; first the
upper byte and then the lower byte will be pushed on to the stack. The SP is decremented by 2, for each
push operation. The general operation of this instruction is similar to the PUSH operation.
POPF: Pop Flags from Stack The pop flags instruction loads the flag register completely (both bytes)
from the word contents of the memory location currently addressed by SP and SS. The SP is incremented
by 2for each pop operation.
LAHF: Load AH from Lower Byte of Flag This instruction loads the AH register with the lower byte of
the flag register. This instruction may be used to observe the status of all the condition code flags (except
overflow) at a time.
SAHF: Store AH to Lower Byte of Flag Register This instruction sets or resets the condition code flags
(except overflow) in the lower byte of the flag register depending upon the corresponding bit positions in
AH. If a bit in AH is 1, the flag corresponding to the bit position is set, else it is reset.
LEA: Load Effective Address The load effective address instruction loads the offset of an operand in the
specified register. This instruction is similar to MOV, MOV is faster than LEA.
LEA cx, [bx+si] ; CX (BX+SI) mod 64K If bx=2f00 H; si=10d0H cx 3fd0H
The LDS AND LES instructions:
LDS and LES load a 16-bit register with offset address retrieved from a memory location then load
either DS or ES with a segment address retrieved from memory.
This instruction transfers the 32-bit number, addressed by DI in the data segment, into the BX and DS
registers.
LDS and LES instructions obtain a new far address from memory.
offset address appears first, followed by the segment address
This format is used for storing all 32-bit memory addresses.
A far address can be stored in memory by the assembler.
LDS BX,DWORD PTR[SI]
BL [SI];
BH [SI+1]
DS [SI+3:SI+2]; in the data segment
LES BX,DWORD PTR[SI]
BL [SI];
BH [SI+1]
ES [SI+3:SI+2]; in the extra segment
I/O Instructions: The 80x86 supports two I/O instructions: in and out15. They take the forms: In
ax, port
in ax, dx
out port, ax
out dx, ax
port is a value between 0 and 255.
The in instruction reads the data at the specified I/O port and copies it into the accumulator. The
out instruction writes the value in the accumulator to the specified I/O port.
Arithmetic instructions: These instructions usually perform the arithmetic operations, like addition, subtraction,
multiplication and division along with the respective ASCII and decimal adjust instructions. The increment and
decrement operations also belong to this type of instructions.
The ADD and ADC instructions: The add instruction adds the contents of the source operand to the
destination operand. For example, add ax, bx adds bx to ax leaving the sum in the ax register. Add
computes dest :=dest+source while adc computes dest :=dest+source+C where C represents the
value in the carry flag. Therefore, if the carry flag is clear before execution, adc behaves exactly like the
add instruction.
Example: CF=1
AX=98
DX=78 CX=94
BX=9E AX=2C
Both instructions affect the flags identically. They set the flags as follows:
The overflow flag denotes a signed arithmetic overflow.
The carry flag denotes an unsigned arithmetic overflow.
The sign flag denotes a negative result (i.e., the H.O. bit of the result is one).
The zero flag is set if the result of the addition is zero.
The auxiliary carry flag contains one if a BCD overflow out of the L.O. nibble occurs.
The parity flag is set or cleared depending on the parity of the L.O. eight bits of the result. If there is
even number of one bits in the result, the ADD instructions will set the parity flag to one (to denote even
parity). If there is an odd number of one bits in the result, the ADD instructions clear the parity flag (to
denote odd parity).
The INC instruction: The increment instruction adds one to its operand. Except for carry flag, inc sets
the flags the same way as Add ax, 1 same as inc ax. The inc operand may be an eight bit, sixteen bit. The
inc instruction is more compact and often faster than the comparable add reg, 1 or add mem, 1 instruction.
The AAA and DAA Instructions
The aaa (ASCII adjust after addition) and daa (decimal adjust for addition) instructions support
BCD arithmetic. BCD values are decimal integer coded in binary form with one decimal digit(0..9) per
nibble. ASCII (numeric) values contain a single decimal digit per byte, the H.O. nibble of the byte should
The aaa and daa instructions modify the result of a binary addition to correct it for ASCII
or decimal arithmetic. For example, to add two BCD values, you would add them as though they were
binary numbers and then execute the daa instruction afterwards to correct the results.
Note: These two instructions assume that the add operands were proper decimal or ASCII values. If you
add binary(non-decimal or non-ASCII) values together and try to adjust them with these instructions, you
will not produce correct results.
Aaa (which you generally execute after an add, adc, or xadd instruction) checks the
value in al for BCD overflow. It works according to the following basic algorithm:
if ( (al and 0Fh) > 9 or (AuxC =1) ) then al := al + 6
else
ax := ax +6 endif
ah := ah + 1
AuxC := 1 ;Set auxilliary carry Carry := 1 ; and carry flags. Else
AuxC := 0 ;Clear auxilliary carry Carry := 0 ; and carry flags.
add al=08 +06; al=0E >9 al=0E+06=04
ah=00+01=01
al=04+03=08, now al<9,
so only clear ah=0
endif
al := al and 0Fh
The aaa instruction is mainly useful for adding strings of digits where there is exactly one decimal digit
per byte in a string of numbers.
The daa instruction functions like aaa except it handles packed BCD values rather than the one
digit per byte unpacked values aaa handles. As for aaa, urpose is to add strings of BCD digits
(with two digits per byte). The algorithm for daa is
if ( (AL and 0Fh) > 9 or (AuxC = 1)) then al=24+77=9B, as B>9 add 6 to al
al := al + 6 al=9B+06=A1, as higher nibble A>9, add 60
AuxC := 1 ;Set Auxilliary carry. to al, al=A1+60=101
Endif Note: if higher or lower nibble of AL <9 then
if ( (al > 9Fh) or (Carry = 1)) then no need to add 6 to AL
al := al + 60h
Carry := 1; ;Set carry flag.
Endif
EXAMPLE:
Assume AL = 0 0 1 1 0 1 0 1, ASCII
5 BL = 0 0 1 1 1 0 0 1, ASCII 9
ADDAL,BL Result: AL= 0 1 1 0 1 1 1 0 = 6EH,which is incorrect
BCD AAA Now AL = 00000100, unpacked BCD 4.
CF = 1 indicates answer is 14 decimal
NOTE: OR AL with 30H to get 34H, the ASCII code for 4. The AAA instruction works only on the AL
register. The AAA instruction updates AF and CF, but OF, PF, SF, and ZF are left undefined.
EXAMPLES:
AL = 0101 1001 = 59 BCD ; BL = 0011 0101 = 35
BCD ADD AL, BL AL = 1000 1110 = 8EH
DAA Add 01 10 because 1110 > 9 AL = 1001 0100 = 94
BCD AL = 1000 1000 = 88 BCD BL = 0100 1001 = 49 BCD
ADD AL, BL AL = 1101 0001, AF=1
DAA Add 0110 because AF =1, AL = 11101 0111 =
D7H 1101 > 9 so add 0110 0000
AL = 0011 0111= 37 BCD, CF =1
The DAA instruction updates AF, CF, PF, and ZF. OF is undefined after a DAA instruction.
If ASCII codes for the result are desired, use next instruction OR AX, 3030H Put 3 in upper nibble of
each byte.
AX = 0011 0100 0011 0101 = 3435H, which is ASCII code for 45
The Division Instructions: DIV, IDIV, and AAD
The 80x86 divide instructions perform a 64/32 division (80386 and later only), a 32/16division or a 16/8
division. These instructions take the form:
Div reg For unsigned division
Div mem
Idiv reg For signed division
Idiv mem
The div instruction computes an unsigned division. If the operand is an eight bit operand ,div divides the
ax register by the operand leaving the quotient in al and the remainder(modulo) in ah. If the operand is a
16 bit quantity, then the div instruction divides the 32 bit quantity in dx ax by the operand leaving the
quotient in ax and the remainder in .
Note: If an overflow occurs (or you attempt a division by zero) then the80x86 executes an INT 0
(interrupt zero).
The aad (ASCII Adjust before Division) instruction is another unpacked decimal operation. It splits apart
unpacked binary coded decimal values before an ASCII division operation. The aad instruction is useful
for other operations. The algorithm that describes this instruction is
al := ah*10 + al AX=0905H; BL=06; AAD; AX=AH*10+AL=09*10+05=95D;
convert decimal to hexadecimal; 95D=5FH; al=5f;
DIV BL; AL/BL=5F/06; AX=05(AH)0F(AL) ah := 0
EXAMPLE:
AX = 0607H unpacked BCD for 67 decimal CH = 09H, now
adjust to binary
AAD Result: AX = 0043 = 43H = 67 decimal
DIV CH Divide AX by unpacked BCD in CH
Quotient: AL = 07 unpacked BCD Remainder:
AH = 04 unpacked BCD Flags undefined after DIV
NOTE: If an attempt is made to divide by 0, the 8086 will do a type 0 interrupt.
CBW-Convert Signed Byte to Signed Word: This instruction copies the sign of a byte in AL to all the
bits in AH. AH is then said to be the sign extension of AL. The CBW operation must be done before a
signed byte in AL can be divided by another signed byte with the IDIV instruction. CBW affects no flags.
EXAMPLE:
AX = 00000000 10011011 155 decimal
CBW Convert signed byte in AL to signed word in AX
Result: AX = 11111111 10011011 155 decimal
CWD-Convert Signed Word to Signed Double word: CWD copies the sign bit of a word in AX to all
the bits of the DX register. In other words it extends the sign of AX into all of DX. The CWD operation
must be done before a signed word in AX can be divided by another signed word with the IDIV
instruction. CWD affects no flags.
EXAMPLE:
DX = 00000000 00000000
AX = 11110000 11000111 3897 decimal
CWD Convert signed word in AX to signed double word in DX:AX
Result DX = 11111111 11111111
AX = 11110000 11000111 3897 decimal
Logical, Shift, Rotate and Bit Instructions: The 80x86 family provides five logical instructions, four
rotate instructions, and three shift instructions. The logical instructions are and, or, xor, test, and not; the
rotates are ror, rol, rcr, and rcl; the shift instructions are shl/sal, shr, and sar.
The Logical Instructions: AND, OR, XOR, and NOT: The 80x86 logical instructions operate on a bit-
by-bit basis. Except not, these instructions affect the flags as follows:
They clear the carry flag.
They clear the overflow flag.
They set the zero flag if the result is zero, they clear it otherwise.
They copy the H.O. bit of the result into the sign flag.
They set the parity flag according to the parity (number of one bits) in the result.
They scramble the auxiliary carry flag.
The not instruction does not affect any flags.
The AND instruction sets the zero flag if the two operands do not have any ones in corresponding bit
positions. AND AX, BX
The OR instruction will only set the zero flag if both operands contain zero. OR AX, BX
The XOR instruction will set the zero flag only if both operands are equal. Notice that the xor
operation will produce a zero result if and only if the two operands are equal. Many programmers
commonly use this fact to clear a sixteen bit register to zero since an instruction of the form
xor reg16, reg16; XOR AX, AX is shorter than the comparable mov reg,0 instruction.
You can use the and instruction to set selected bits to zero in the destination operand. This is known as
masking out data; Likewise, you can use the or instruction to force certain bits to one in the destination
operand;
The Shift Instructions: SHL/SAL, SHR, SAR: The 80x86 supports three different shift instructions (shl
and sal are the same instruction):shl (shift left), sal (shift arithmetic left), shr (shift right), and sar (shift
arithmetic right).
SHL/SAL: These instructions move each bit in the destination operand one bit position to the left the
number of times specified by the count operand. Zeros fill vacated positions at the L.O. bit; the H.O.
bit shifts into the carry flag.
The shl/sal instruction sets the condition code bits as follows:
The carry flag contains the last bit shifted out of the H.O. bit of the operand.
The overflow flag will contain one if the two H.O. bits were different prior to a single bit shift. The
overflow flag is undefined if the shift count is not one.
The zero flag will be one if the shift produces a zero result.
The sign flag will contain the H.O. bit of the result.
The parity flag will contain one if there are an even number of one bits in the L.O. byte of the result.
The A flag is always undefined after the shl/sal instruction.
The shift left instruction is especially useful for packing data. For example, suppose
you have two nibbles in al and ah that you want to combine. You could use the
following code to do this:
shl ah, 4 ;
or al, ah ;Merge in H.O. four bits.
Of course, al must contain a value in the range 0..F for this code to work properly (the
shift left operation automatically clears the L.O. four bits of ah before the or instruction).
SHL OPERATION
H.O. four bits of al are not zero before this operation, you can easily clear them with an
and instruction:
shl ah, 4 ;Move L.O. bits to H.O. position.
and al, 0Fh ;Clear H.O. four bits.
or al, ah ;Merge the bits.
Since shifting an integer value to the left one position is equivalent to multiplying that
value by two, you can also use the shift left instruction for multiplication by powers
of two:
shl ax, 1 ;Equivalent to AX*2
shl ax, 2 ;Equivalent to AX*4
shl ax, 3 ;Equivalent to AX*8
SAR: The sar instruction shifts all the bits in the destination operand to the right one
bit, replicating the H.O. bit.
two. Each shift to the right divides the value by two. Multiple right shifts divide the
previous shifted result by two, so multiple shifts produce the following results:
SAR OPERATION
sar ax, 1 ;Signed division by 2 sar
ax, 2 ;Signed division by 4 sar ax,
3 ;Signed division by 8 sar ax, 4
;Signed division by 16 sar ax, 5
;Signed division by 32 sar ax, 6
;Signed division by 64 sar ax, 7
;Signed division by 128 sar ax, 8
;Signed division by 256
There is a very important difference between the sar and idiv instructions. The idiv instruction always
truncates towards zero while sar truncates results toward the smaller result. For positive results, an
arithmetic shift right by one position produces the same result as an integer division by two. However, if
the quotient is negative, idiv truncates towards zero while sar truncates towards negative infinity.
SHR: The shr instruction shifts all the bits in the destination operand to the right one bit shifting a zero
into the H.O. bit
SHR OPERATION
The shift right instruction is especially useful for unpacking data. shifting an unsigned integer value to the
right one position is equivalent to dividing that value by two, you can also use the shift right instruction
for division by powers of two:
shr ax, 1 ;Equivalent to AX/2
shr ax, 2 ;Equivalent to AX/4
shr ax, 3 ;Equivalent to AX/8
shr ax, 4 ;Equivalent to AX/16
The Rotate Instructions: RCL, RCR, ROL, and ROR
The rotate instructions shift the bits around, just like the shift instructions, except the bits shifted out of
the operand by the rotate instructions re-circulate through the operand. They include rcl(rotate through
carry left), rcr(rotate through carry right), rol(rotate left), and ror(rotate right). These instructions all take
the forms :rcldest, count roldest, count rcr dest, count ror dest, count
RCL: The rcl(rotate through carry left), as its name implies, rotates bits to the left, through the carry
flag, and back into bit zero on the right. The rcl instruction sets the flag bits as follows:
The carry flag contains the last bit shifted out of the H.O. bit of the operand.
If the shift count is one, rcl sets the overflow flag if the sign changes as a result of the rotate. If the count
is not one, the overflow flag is undefined.
The rcl instruction does not modify the zero, sign, parity, or auxiliary carry flags.
instruction moves a sequence of bytes from one memory location to another. The cmps instruction
compares two blocks of memory. The scas instruction scansa block of memory for a particular value.
These string instructions often require three operands, a destination block address, a source block address,
and (optionally) an element count. For example, when using the movs instruction to copy a string, you
need a source address, a destination address, and a count (the number of string elements to move).The
operands for the string instructions include:
CX (count) register,
The REP/REPE/REPZ and REPNZ/REPNE Prefixes: The repeat prefixes tell the 80x86 to do a multi-
byte string operation. The syntax for the repeat prefix is:
Field:
Label repeat mnemonic operand ; comment
For MOVS:
Rep movs {operands}
For CMPS:
Repe cmps Repz cmps
{operands} {operands} Repne cmps {operands} Repnz cmps
{operands}
For SCAS:
Repe scas {operands} Repz scas {operands} Repne scas {operands} repnz scas {operands}
For STOS:
epstos {operands}
When specifying the repeat prefix before a string instruction, the string instruction repeats cx
times. Without the repeat prefix, the instruction operates only on a single byte,word, or double word.
If the direction flag is clear, the CPU increments si and di after operating upon eachstring element.
If the direction flag is set, then the 80x86 decrements si and di after processing eachstring element. The
direction flag may be set or cleared using the cld (clear direction flag) and std (setdirection flag)
instructions.
The MOVS Instruction: The movsb (move string, bytes) instruction fetches the byte at address ds:si,
stores it at address es:di, and then increments or decrements the si and di registers by one. If the rep prefix
is present, the CPU checks cx to see if it contains zero. If not, then it moves the byte from ds:si to es:di
and decrements the cx register. This process repeats until cx becomes zero. The syntax is :
{REP} MOVSB {REP} MOVSW
The CMPS Instruction: The cmps instruction compares two strings. The CPU compares the string
referenced by es:di to the string pointed at by ds:si. Cx contains the length of the two strings (whenusing
the rep prefix). The syntax is: {REPE} CMPSB {REPE} CMPSW
To compare two strings to see if they are equal or not equal, you must compare corresponding
Therepe prefix accomplishes
this operation. It will compare successive elements in a string as long as they are equal and cx is greater
than zero.
The SCAS Instruction: The scas instruction, by itself, compares the value in the accumulator (al or ax)
against the value pointed at by es:di and then increments (or decrements) di by one or two. The CPU sets
the flags according to the result of the comparison. When using the repne prefix (repeat while not equal),
scas scans the string searching for the first string element which is equal to the value in the accumulator.
The scas instruction takes the following forms:{REPNE} SCASB {REPNE} SCASW The STOS
Instruction: The stos instruction stores the value in the accumulator at the location specified byes:di.
After storing the value, the CPU increments or decrements di depending upon the state of the direction
flag. Its primary use is to initialize arrays and strings to a constant value. {REP} STOSB
{REP} STOSW
The LODS Instruction: The lods instruction copies the byte or word pointed at by ds:si into the al or ax
register, after which it increments or decrements the si register by one or two.{REP} LODSB
{REP} LODSW
Flag Manipulation and Processor Control Instructions: These instructions control the functioning of
the available hardware inside the processor chip. These are categorized into two types; (a) flag
manipulation instructions and (b) machine control instructions.
The flag manipulation instructions directly modify some of the flags of 8086. The machine control
instructions control the bus usage and execution. The flag manipulation instructions and their functions
are as follows:
CLC - Clear carry flag CMC - Complement carry flag STC - Set carry flag
CLD - Clear direction flag STD - Set direction flag CLI - Clear interrupt flag
STI - Set interrupt flag
These instructions modify the carry(CF), direction(DF) and interrupt(IF) flags directly. The DF and IF,
which may be modified using the flag manipulation instructions, further control the processor operation;
like interrupt responses and auto-increment or auto-decrement modes.
The machine control instructions supported by 8086 and 8088 are listed as follows along with
their functions. These machine control instructions do not require any operand.
WAIT - Wait for Test input pin to go low HLT - Halt the processor NOP No
Operation ESC - Escape to external device like NDP (numeric co-processor) LOCK Bu
lock instruction prefix.
After executing the HLT instruction, the processor enters the halt state. The two ways to pull it out of the
halt state are to reset the processor or to interrupt it.
When NOP instruction is executed, the processor does not perform any operation till 4 clock
cycles, except incrementing the IP by one. It then continues with further execution after 4 clock cycles.
ESC instruction when executed, frees the bus for an external master like a coprocessor or
peripheral devices.
The LOCK prefix may appear with another instruction. When it is executed, the bus access is not
allowed for another master till the lock prefixed instruction is executed completely. This instruction is
used in case of programming for multiprocessor systems.
The WAIT instruction when executed holds the operation of processor with the current status till
the logic level on the TEST pin goes low. The processor goes on inserting WAIT states in the instruction
cycle, till the TEST pin goes low. Once the TEST pin goes low, it continues further execution.
Program Flow Control Instructions: The control transfer instructions are used to transfer the control
from one memory location to another memory location. In 8086 program control instructions belong to
three groups: unconditional transfers, conditional transfers, and subroutine call and return instructions.
Unconditional Jumps: The jmp (jump) instruction unconditionally transfers control to another point in
the program. Intra segment jumps are always between statements in the same code segment. Intersegment
jumps can transfer control to a statement in a different code segment.
JMP Address
instruction.
Instruction LOOP works with respect to contents of CX. CX must be preloaded with a count that
represents the number of times the loop is to be repeat.
Whenever the loop is executed, contents at CX are first decremented then checked to determine if
they are equal to zero.
If CX=0, loop is complete and the instruction following loop is executed.
A subroutine is a special segment of program that can be called for execution from any point in a program.
Whenever we need the subroutine, a single instruction is inserted in to the main body of the program to call
subroutine.
Transfers the flow of the program to the procedure.
CALL instruction differs from the jump instruction because a CALL saves a return address on the
stack.
The return address returns control to the instruction that immediately follows the CALL in a program when
a RET instruction executes.
To branch a subroutine the value in the IP or CS and IP must be modified.
After execution, we want to return the control to the instruction that immediately follows the one called the
subroutine i.e., the original value of IP or CS and IP must be preserved.
Execution of the instruction causes the contents of IP to be saved on the stack. (this time (SP) (SP) -2 )
A new 16-bit (near-proc, mem16, reg16 i.e., Intra Segment) value which is specified by the instructions
operand is loaded into IP.
Examples: CALL 1234H
CALL BX
CALL [BX]
Return Instruction: RET instruction removes an address from the stack so the program returns to the
instruction following the CALL
Every subroutine must end by executing an instruction that returns control to the main program.
This is the return (RET) instruction.
By execution the value of IP or IP and CS that were saved in the stack to be returned back to their
corresponding registers. (this time (SP) (SP)+2 )
MACROS: The macro directive allows the programmer to write a named block of source statements,
then use that name in the source file to represent the group of statements. During the assembly phase, the
assembler automatically replaces each occurrence of the macro name with the statements in the macro
definition.
Macros are expanded on every occurrence of the macro name, so they can increase the length of
the executable file if used repeatable. Procedures or subroutines take up less space, but the increased
overhead of saving and restoring addresses and parameters can make them slower. In summary, the
advantages and disadvantages of macros are,
Advantages
Repeated small groups of instructions replaced by one macro
Errors in macros are fixed only once, in the definition
Duplication of effort is reduced
In effect, new higher level instructions can be created
Programming is made easier, less error prone
Generally quicker in execution than subroutines
Disadvantages
In large programs, produce greater code size than procedures
When to use Macros
To replace small groups of instructions not worthy of subroutines
To create a higher instruction set for specific applications
To create compatibility with other computers
To replace code portions which are repeated often throughout the program
IO
IO
IO
IO
BHE
BHE
RD
RD
FFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
EPROM
FE000 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
FDFFF 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
SRAM
FC000 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 Word transfer through D15-D0 Both even & odd banks in SRAM
0 0 1 Lower byte transfer through D7-D0 Even bank in SRAM
0 1 0 Higher byte through D15-D8 Odd bank in SRAM
1 0 0 Word transfer through D15-D0 Both even & odd banks in EPROM
1 0 1 Lower byte transfer through D7-D0 Even bank in EPROM
1 1 0 Higher byte through D15-D8 Odd bank in EPROM
IO
IO
IO
IO
BHE
BHE
RD
RD
FFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
EPROM
FE000 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
FDFFF 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
SRAM
FC000 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 Word transfer through D15-D0 Both even & odd banks in SRAM
0 0 1 Lower byte transfer through D7-D0 Even bank in SRAM
0 1 0 Higher byte through D15-D8 Odd bank in SRAM
1 0 0 Word transfer through D15-D0 Both even & odd banks in EPROM
1 0 1 Lower byte transfer through D7-D0 Even bank in EPROM
1 1 0 Higher byte through D15-D8 Odd bank in EPROM
NIT -III
8051 MICRO CONTROLLER PROGRAMMING AND APPLICATIONS
Introduction to Microcontrollers:
8051 is one of the first most popular microcontroller also known as MCS-51. It was introduced by
Intel in the year 1981. Initially it came out as N-type metal-oxide-semiconductor (NMOS) based
microcontroller, but later versions were based on complementary metal-oxide-semiconductor(CMOS)
technology. These microcontrollers were named as 80C51, where C in the name tells that it is based
on CMOS technology.
It is an 8-bit microcontroller which means data bus is of 8-bits. Therefore, it can process 8-bits at a
time. It is used in wide variety of embedded systems like robotics, remote controls, automotive
industry, telecom applications, power tools etc
The figure also shows the usual CPU components: program counter, ALU,working
registers, and clock circuits.'
The A (accumulator) register is the most versatile of the two CPU registers and is
used for many operations, including addition, subtraction, integer multiplication
and division, and Boolean bit manipulations. The A register is also used for all
data transfers between the 8051 and any external memory. The B register is used
with the A register for multiplication and division operations and has no other
function other than as a location where data may be stored.
Flags are I -bit registers provided to store the results of certain program
instructions. Other instructions can test the condition of the flags and make
decisions based upon the flag states. In order that the flags may be conveniently
addressed, they are grouped inside the program status word (PSW) and the power
control (PCON) registers.
The 8051 has four math flags that respond automatically to the outcomes of math
operations and three general-purpose user flags that can be set to I or cleared to 0
by the programmer as desired. The math flags include carry (C), auxiliary carry
(AC), overflow (OV), and parity (P). User flags are named FO, GFO, and GF1;
they are general-purpose flags that may be used by the programmer to record
some event in the program. Note that all of the flags can be set and cleared by the
programmer at will. The math flags, however, are also affected by math
operations.
The program status word is shown in Figure. The PSW contains the math flags,
user program flag FO, and the register select bits that identify which of the four
generalpurpose register banks is currently in use by the program. The remaining
two user flags, GFO and GFl, are stored in PCON,
Detailed descriptions of the math flag operations will be discussed in chapters
that
cover the opcodes that affect the flags. The user flags can be set or cleared using
data move instructions.
2. 3 Instruction sets
8051 has about 111 instructions. These can be grouped into the following categories
Arithmetic Instructions
Logical Instructions
Data Transfer instructions
Boolean Variable Instructions
Program Branching Instructions
The following nomenclatures for register, data, address and variables are
used while writeinstructions
A: Accumulator
B: "B" register
C: Carry bit
Rn: Register R0 - R7 of the currently selected register bank
Direct: 8-bit internal direct address for data. The data could be in lower 128bytes of
RAM (00 - 7FH) or it could be in the special function register (80 - FFH).
@Ri: 8-bit external or internal RAM address available in register R0 or R1. This is
used
for indirect addressing mode.
#data8: Immediate 8-bit data available in the instruction.
#data16: Immediate 16-bit data available in the instruction.
Addr11: 11-bit destination address for short absolute jump. Used by instructions AJMP
& ACALL. Jump range is 2 kbyte (one page).
Addr16: 16-bit destination address for long call or long jump.
Rel: 2's complement 8-bit offset (one - byte) used for short jump (SJMP) and all
conditional jumps.
bit: Directly addressed bit in internal RAM or SFR
Note 1:
MOV A , #72H
After instruction
“MOV A,72H ” the content of 72’th byte of RAM replace in accumulator
MOV A, R3 ≡ MOV A, R3
MOV A, #25
MOV B, #65H
MUL AB
• DIV AB ;A = A/B,
• B = A mod B
• ;B=0EH, A=99H
MOV A,#25
B,#10
MOV
AB ;A=2, B=5
DIV
SETB bit ; bit=1
CLR bit ; bit=0
SETB C ; CY=1
SETB P0.0 ;bit 0 from port 0 =1
SETB P3.7 ;bit 7 from port 3 =1
SETB ACC.2 ;bit 2 from ACCUMULATOR
=1
SETB 05 ;set high D5 of RAM loc. 20h
Note:
CLR
instruction is
as same as
SETB i.e.:
CLR C ;CY=0
But following instruction is only for CLR:
CLR A ;A=0
DEC byte ;byte=byte-1
INC byte ;byte=byte+1
INC R7
DEC A
DEC 40H ; [40]=[40]-1
ANL - ORL – XRL
Bitwise
Logical
Operations:
AND, OR,
XOR
EXAMPLE:
MOV R5,#89H
ANL R5,#08H
In the register addressing mode the source or destination data should be present in a register (R0 to R7).
These are some examples of Register Addressing Mode.
MOV A, R5
MOV R2, #45H
MOV RO, A
In 8051, there is no instruction like MOVR5, R7. But we can get the same result by using this
instruction MOV R5, 07H, or by using MOV 05H, R7. But this two instruction will work when the
selected register bank is RB0. To use another register bank and to get the same effect, we have to add
the starting address of that register bank with the register number. For an example, if the RB2 is
selected, and we want to access R5, then the address will be (10H + 05H = 15H), so the instruction will
look like this MOV 15H, R7. Here 10H is the starting address of Register Bank 2.
Direct Addressing Mode
In the Direct Addressing Mode, the source or destination address is specified by using 8-bit data in the
instruction. Only the internal data memory can be used in this mode. Here some of the examples of
direct Addressing Mode.
MOV 80H, R2
MOV R6, 60H
MOV R0, 05H
The first instruction will send the content of registerR6 to port P0 (Address of Port 0 is 80H). The
second one is forgetting content from 45H to R2. The third one is used to get data from Register R5
(When register bank RB0 is selected) to register R5.
Register indirect addressing Mode
In this mode, the source or destination address is given in the register. By using register indirect
addressing mode, the internal or external addresses can be accessed. The R0 and R1 are used for 8-bit
addresses, and DPTR is used for 16-bit addresses, no other registers can be used for addressing
purposes. Let us see some examples of this mode.
MOV 0E5, @R0
MOV @R6, P0
MOV @R2, 60H
In the instructions, the @ symbol is used for register indirect addressing. In the first instruction, it is
showing that theR0 register is used. If the content of R0 is 40H, then that instruction will take the data
which is located at location 40H of the internal RAM. In the second one, if the content of R6 is 30H,
then it indicates that the content of port P0 will be stored at location 30H in the internal RAM
MOV A, @RI
MOVX @DPTR,, A
In these two instructions, the X in MOVX indicates the external data memory. The external data
memory can only be accessed in register indirect mode. In the first instruction if the R0 is holding 40H,
then A will get the content of external RAM location40H. And in the second one, the content of A is
overwritten in the location pointed by DPTR.
Indexed addressing mode
In the indexed addressing mode, the source memory can only be accessed from program memory only.
The destination operand is always the register A. These are some examples of Indexed addressing mode.
MOVC A, @A+PC
MOVC A, @A+ DPTR
The C in MOVC instruction refers to code byte. For the first instruction, let us consider A holds 30H.
And the PC value is1125H. The contents of program memory location 1155H (30H + 1125H) are moved
to register A
• EA : Global enable/disable.
• --- : Undefined.
• ET2 :Enable Timer 2 interrupt.
• ES :Enable Serial port interrupt.
Interrupt Vectors:
During Idle Mode, the Microcontroller will stop the Clock Signal to the ALU
(CPU) but it is given to other peripherals like Timer, Serial, Interrupts, etc. In order
to terminate the Idle Mode,you have to use an Interrupt or Hardware Reset.
In the Power Down Mode, the oscillator will be stopped and the power will be
reduced to 2V. Toterminate the Power Down Mode, you have to use the Hardware
Reset.
Apart from these two, the PCON Register can also be used for few additional
purposes. TheSMOD Bit in the PCON Register is used to control the Baud Rate
of the Serial Port.
There are two general purpose Flag Bits in the PCON Register, which can be
used by theprogrammer during execution.
SCON (Serial Control)
The Serial Control or SCON SFR is used to control the 8051 Microcontroller’s
Serial Port. It islocated as an address of 98H. Using SCON, you can control the
Operation Modes of the Serial Port, Baud Rate of the Serial Port and Send or
Receive Data using Serial Port.
SCON Register also consists of bits that are automatically SET when a byte of data
is transmittedor received.
TCON (Timer Control)
Timer Control or TCON Register is used to start or stop the Timers of 8051
Microcontroller. Italso contains bits to indicate if the Timers has overflowed. The
TCON SFR also consists of Interrupt related bits.
The TMOD or Timer Mode register or SFR is used to set the Operating Modes of
the Timers T0and T1. The lower four bits are used to configure Timer0 and the
higher four bits are used to configure Timer1.
The Gatex bit is used to operate the Timerx with respect to the INTx pin or
regardless of theINTx pin.
Peripheral
Data
Registers
SBUF (Serial
Data Buffer)
The Serial Buffer or SBUF register is used to hold the serial data while
transmission orreception.
Internal RAM:
The 128-byte internal RAM, which is shown generally in Figure 2.1 and in detail
in Figure 2.5, is organized into three distinct areas:
4. A general-purpose RAM area above the bit area, from 30h to 7Fh,
addressable as bytes.
Figure Pin diagram of 8051
PortO:
Port 0 pins may serve as inputs, outputs, or, when used together, as a bi-
directional loworder address and data bus for external memory. For example,
when a pin is to be used as an input, a 1 must be written to the corresponding port
0 latch by the program, thus turning both of the output transistors off, which in
turn causes the pin to "float" in a highimpedance state, and the pin is essentially
connected to the input buffer.
When used as an output, the pin latches that are programmed to a 0 will turn on
the
lower FET, grounding the pin. All latches that are programmed to a 1 still float;
thus, external pull up resistors will be needed to supply a logic high when using
port 0 as an output.
When port 0 is used as an address bus to external memory, internal control
signals
switch the address lines to the gates of the Field Effect Transistories (FETs). A
logic I on an address bit will turn the upper FET on and the lower FET off to
provide a logic high at the pin. When the address bit is a zero, the lower FET is
on and the upper FET off to provide a logic low at the pin.
29
After the address has been formed and latched into external circuits by the
Address Latch Enable (ALE) pulse, the bus is turned around to become a data
bus. Port 0 now reads data from the external memory and must be configured as
an input, so a logic 1 is automatically written by internal control logic to all port 0
latches.
Port l
Port 1 pins have no dual functions. Therefore, the output latch is connected
directly to the gate of the lower FET, which has an FET circuit labeled "Internal
FET Pull up" as an active pull up load.
Used as an input, a 1 is written to the latch, turning the lower FET off; the
pinand the input to the pin buffer are pulled high by the FET load. An external
circuit can overcome the high impedance pull up and drive the pin low to input a
0 or leave the input high for a 1.
If used as an output, the latches containing a I can drive the input of an external
circuit high through the pull up. If a 0 is written to the latch, the lower FET is on,
the pull up is off, and the pin can drive the input of the external circuit low.
To aid in speeding up switching times when the pin is used as an output, the
internal FET pull up has another FET in parallel with it. The second FET is
turned on for two oscillator time periods during a low-to-high transition on the
pin, as shown in Figure 2.7.
This arrangement provides a low impedance path to the positive voltage supply to
help reduce rise times in charging any parasitic capacitances in the external
circuitry.
Port 2
Port 2 may be used as an input/output port similar in operation to port 1. The
alternate use of port 2 is to supply a high-order address byte in conjunction with
the port 0 low-order byte to address external memory.
Port 2 pins are momentarily changed by the address control signals when
supplying the high byte of a 16-bit address. Port 2 latches remain stable when
30
external memory is addressed, as they do not have to be turned around (set to 1)
for data input as is the case for port 0.
Port3
Port 3 is an input/output port similar to port I. The input and output functions can
be programmed under the control of the P3 latches or under the control of various
other special function registers. The port 3 alternate uses are shown in the
following table:-
Unlike ports 0 and 2, which can have external addressing functions and change
all
eight port bits when in alternate use, each pin of port 3 may be individually
programmed to be used either as I/O or as one of the alternate functions.
External Memory
The system designer is not limited by the amount of internal RAM and ROM
available on chip. Two separate external memory spaces are made available by
the 16-bit PC and DPTR and by different control pins for enabling external ROM
31
and RAM chips. Internal control circuitry accesses the correct physical memory,
depending upon the machine cycle state and the op code being executed.
There are several reasons for adding external memory, particularly program
memory, when applying the 8051 in a system. When the project is in the
prototype stage, the expense—in time and money—of having a masked internal
ROM made for each program "try" is prohibitive.
External RAM, which is accessed by the DPTR, may also be needed when 128
bytes of internal data storage is not sufficient. External RAM, up to 64K bytes,
may also be added to any chip in the 8051 family.
32
internal and external ROM automatically; the 8031, having no internal ROM,
must have EA grounded.
Figure 2.9 shows the timing associated with an external memory access cycle.
During any memory access cycle, port 0 is time multiplexed. That is, it first
provides the lower byte of the 16-bit memory address, then acts as a bidirectional
data bus to write or read a byte of memory data. Port 2 provides the high byte of
the memory address during the entire memory read/write cycle.
The lower address byte from port 0 must be latched into an external register to
save
the byte. Address byte save is accomplished by the ALE clock pulse that provides
the correct timing for the '373 type data latch. The port 0 pins then become free to
serve as a data bus.
If the memory access is for a byte of program code in the ROM, the PSEN
(program store enable) pin will go low to enable the ROM to place a byte of
program code on the data bus. If the access is for a RAM byte, the WR (write) or
RD (read) pins will go low, enabling data to flow between the RAM and the data
bus.
The ROM may be expanded to 64K by using a 27512 type EPROM and
connecting the remaining port 2 upper address lines AI4-A15 to the chip.
At this time the largest static RAMs available are 32K in size; RAM can be
expanded to 64K by using two 32K RAMs that are connected through address
A14 of port 2. The
33
Figure Interfacing 8086 with external memory
first 32K RAM (OOOOh-7FFFh) can then be enabled when AI5 of port 2 is low,
and the second 32K RAM (SOOOh-FFFFh) when A15 is high, by using an
inverter.
Note that the WR and RD signals are alternate uses for port 3 pins 16 and 17.
Also,
port 0 is used for the lower address byte and data; port 2 is used for upper address
bits. The use of external memory consumes many of the port pins, leaving only
port 1 and parts of port 3 for general I/O.
34
The 8051 microcontroller is parallel device that transfers eight bits of data
simultaneously over eight data lines to parallel I/O devices. Parallel data transfer
over a long is very expensive. Hence, a serial communication is widely used in
long distance communication. In serial data communication, 8-bit data is
converted to serial bits using a parallel in serial out shift register and then it is
transmitted over a single data line. The data byte is always transmitted with least
significant bit first.
35
Asynchronous serial data communication a single byte is transmitted at a time.
Data Clock 1 Clock2 Baud rate:
The rate at which the data is transmitted is called baud or transfer rate. The baud
rate is the reciprocal of the time to send one bit. In asynchronous transmission,
baud rate is not equal to number of bits per second. This is because; each byte is
preceded by a start bit and followed by parity and stop bit. For example, in
synchronous transmission, if data is transmitted with 9600 baud, it means that
9600 bits are transmitted in one second. For bit transmission time = 1 second/
9600 = 0.104 ms. Over the years, dozens of serial protocols have been crafted to
meet particular needs of embedded systems.
1. USB (universal serial bus), and Ethernet, are a couple of the well- known
computing serial interfaces.
2. Other very common serial interfaces include SPI, I2C, RS-232 and so on.
3. Each of these serial interfaces can be sorted into one of two groups:
synchronous or asynchronous.
4. A Synchronous serial interface always pairs its data line(s) with a clock signal,
so all devices on a synchronous serial bus share a common clock. This often
allows faster serial transfer, but it also requires at least one extra wire between
communicating devices. Examples of synchronous interfaces include SPI, and
I2C. Asynchronous means that data is transferred without support from an
external clock signal. Minimizes the required wires and I/O pins, but we need to
put some extra effort into reliably transferring and receiving data. 5. The
Universal Asynchronous Receiver/Transmitter (UART) controller is the key
component of the serial communications subsystem. UART is also a common
integrated feature in most microcontrollers. The UART takes bytes of data and
transmits the individual bits in a sequential fashion. At the destination, a second
UART re-assembles the bits into complete bytes. Communication can be “full
duplex” (both send and receive at the same time) or “half duplex” (devices take
turns transmitting and receiving). 6. The Universal Synchronous/Asynchronous
Receiver/Transmitter (USART) controller is another implementation of the serial
port. UART supports only asynchronous mode, whereas USART supports both
36
asynchronous and synchronous modes. Unlike Ethernet, Firewire etc., there is no
specific port for UART/USART. They are commonly used in conjugation with
protocols like RS- 232, RS-434 etc.
SCON (Serial Control)
The Serial Control or SCON SFR is used to control the 8051 Microcontroller’s
Serial Port. It islocated as an address of 98H. Using SCON, you can control the
Operation Modes of the Serial Port, Baud Rate of the Serial Port and Send or
Receive Data using Serial Port.
SCON Register also consists of bits that are automatically SET when a byte of data
is transmittedor received.
37
Rules for UART The asynchronous serial protocol has a number of built-in rules -
mechanisms that help ensure robust and error-free data transfers. These
mechanisms compensate the non-existence of the common clock signal: Baud
Rate: The baud rate specifies how fast data is sent over a serial line. It’s usually
expressed in units of bits-per-second (bps). This value determines how long the
transmitter holds a serial line high/low or at what period the receiving device
samples it’s line. Baud rates can be just about any value within reason. The only
requirement is that both devices operate at the same rate. Common baud rate is
9600 bps. Other “standard” baud are 1200, 2400, 4800, 19200, 38400, 57600,
and 115200. Framing the data Each block (usually a byte) of data transmitted is
actually sent in a packet or frame of bits. Frames are created by appending
synchronization and parity bits to our data. Some symbols in the frame have
configurable bit sizes. Data chunk :The amount of data in each packet can be set
to anything from 5 to 9 bits. Certainly, the standard data size is your basic 8-bit
byte, but other sizes have their uses. A 7-bit data chunk can be more efficient than
8, especially if you’re just transferring 7-bit ASCII characters. After agreeing on
a character-length, both serial devices also have to agree on the endianness of
their data. Is data sent mostsignificant bit (msb) to least, or vice-versa? If it’s not
otherwise stated, you can usually assume that data is transferred least-significant
bit (lsb) first. Synchronization bits: The synchronization bits are two or three
special bits transferred with each chunk of data. They are the start bit and the
stop bit(s), and mark the beginning and end of a packet. There is always only one
start bit, but the number of stop bits is configurable to either one or two (though
it’s commonly left at one). The start bit is always indicated by an idle data line
going from 1 to 0, while the stop bit(s) will transition back to the idle state by
holding the line at 1. Parity bits: Parity is optional, and not very widely used. It
can be helpful for transmitting across noisy mediums, but it’ll also slow down
data transfer a bit and requires both sender and receiver to implement error-
handling (usually, received data that fails must be re-sent). A variety of
communication protocols have been developed based on serial communication in
the past few decades. Some of them are: SPI – Serial Peripheral Interface: It is a
38
three-wire based communication system. One wire each for Master to slave and
Vice-versa, and one for clock pulses. There is an additional SS (Slave Select)
line, which is mostly used when we want to send/receive data between multiple
ICs. I2C – Inter-Integrated Circuit : Pronounced eye-two-see or eye-square-see,
this is an advanced form of USART. The transmission speeds can be as high as
400KHz. The I2C bus has two wires – one for clock, and the other is the data
line, which is bi-directional – this being the reason it is also sometimes (not
always – there are a few conditions) called Two Wire Interface (TWI). It is a new
and revolutionary technology invented by Philips. FireWire – Developed by
Apple. High-speed buses capable of audio/video transmission. The bus contains
a number of wires depending upon the port, which can be either a 4-pin one, or a
6-pin one, or an 8-pin one. Ethernet : Used mostly in LAN connections, the bus
consists of 8 lines, or 4 Tx/Rx pairs. Universal serial bus (USB). Most popular
of all serial interfaces. Is used for virtually all type of connections. The bus has 4
lines: VCC, Ground, Data+, and Data-.
8051 SERIAL COMMUNICATION
The 8051 supports a full duplex serial port. Three special function registers
support serial communication.
1. SBUF Register: Serial Buffer (SBUF) register is an 8-bit register. It has
separate SBUF registers for data transmission and for data reception. For a byte
of data to be transferred via the TXD line, it must be placed in SBUF register.
Similarly, SBUF holds the 8-bit data received by the RXD pin and read to accept
the received data.
2. SCON register: The contents of the Serial Control (SCON) register are shown
below. This register contains mode selection bits, serial port interrupt bit (TI and
RI) and also the ninth data bit for transmission and reception (TB8 and RB8).
3. PCON register: The SMOD bit (bit 7) of PCON register controls the baud rate
in asynchronous mode transmission.
SERIAL COMMUNICATION MODES Mode 0 In this mode serial port runs in
synchronous mode. The data is transmitted and received through RXD pin and
TXD is used for clock output.
39
In this mode the baud rate is 1/12 of clock frequency. Mode 1 In this mode SBUF
becomes a 10 bit full duplex transceiver. The ten bits are 1 start bit, 8 data bit and
1 stop bit. The interrupt flag TI/RI will be set once transmission or reception is
over. In this mode the baud rate is variable and is determined by the timer 1
overflow rate. Baud rate = [2smod/32] x Timer 1 overflow Rate = [2smod/32] x
[Oscillator Clock Frequency] / [12 x [256 – [TH1]]] Mode 2 This is similar to
mode 1 except 11 bits are transmitted or received. The 11 bits are, 1 start bit, 8
data bit, a programmable 9th data bit, 1 stop bit. Baud rate = [2smod/64] x
Oscillator Clock Frequency Mode 3 This is similar to mode 2 except baud rate is
calculated as in mode 1
40
AC<-AC+B
41
AC<-AC-B-Carry flag
42
It will set the carry flag to 0
Carry flag<-0
Clear carry CLRC CLRC
Disable
interrupt DI DI It will disable the interrupt
3. Shift Instructions :
Shifts are operations in which the bits of a word are moved to the left or right. Shift instructions
may specify either logical shifts, arithmetic shifts, or rotate-type operations.
Typical Shift Instructions –
Name Mnemonic
43
3. 10 simple programming exercises key board and display interface
The key board here we are interfacing is a matrix keyboard. This key board is designed with a particular
rows and columns. These rows and columns are connected to the microcontroller through its ports of the
micro controller 8051. We normally use 8*8 matrix key board. So only two ports of 8051 can be easily
connected to the rows and columns of the key board.
When ever a key is pressed, a row and a column gets shorted through that pressed key and all the
other keys are left open. When a key is pressed only a bit in the port goes high. Which indicates
microcontroller that the key is pressed. By this high on the bit key in the corresponding column is
identified.
Once we are sure that one of key in the key board is pressed next our aim is to identify that key.
To do this we firstly check for particular row and then we check the corresponding column the key
board.
To check the row of the pressed key in the keyboard, one of the row is made high by making one
of bit in the output port of 8051 high . This is done until the row is found out. Once we get the row next
out job is to find out the column of the pressed key. The column is detected by contents in the input
ports with the help of a counter. The content of the input port is rotated with carry until the carry bit is
set.
The contents of the counter is then compared and displayed in the display. This display is
designed using a seven segment display and a BCD to seven segment decoder IC 7447.
The BCD equivalent number of counter is sent through output part of 8051 displays the number of
pressed key.
The programming algorithm, program and the circuit diagram is as follows. Here program is explained
with comments.
44
Circuit diagram of INTERFACING KEY BOARD TO 8051.
Keyboard is organized in a matrix of rows and columns as shown in the figure. The microcontroller
accesses both rows and columns through the port.
1. The 8051 has 4 I/O ports P0 to P3 each with 8 I/O pins, P0.0 to P0.7,P1.0 to P1.7,
P2.0 to P2.7, P3.0 to P3.7. The one of the port P1 (it understood that P1 means P1.0
to P1.7) as an I/P port for microcontroller 8051, port P0 as an O/P port of
microcontroller 8051 and port P2 is used for displaying the number of pressed key.
2. Make all rows of port P0 high so that it gives high signal when key is pressed.
3. See if any key is pressed by scanning the port P1 by checking all columns for non
zero condition.
4. If any key is pressed, to identify which key is pressed make one row high at a time.
5. Initiate a counter to hold the count so that each key is counted.
6. Check port P1 for nonzero condition. If any nonzero number is there in
[accumulator], start column scanning by following step 9.
7. Otherwise make next row high in port P1.
8. Add a count of 08h to the counter to move to the next row by repeating steps from
step 6.
9. If any key pressed is found, the [accumulator] content is rotated right through the
carry until carry bit sets, while doing this increment the count in the counter till
carry is found.
10. Move the content in the counter to display in data field or to memory location
11. To repeat the procedures go to step 2.
45
to check that whether any key is pressed
after identifying the row to check the colomn following steps are followed
46
servomotors / Servo Drivers
Introduction Features
Principles Classifications
Engineering Data Further Information
Explanation of Terms Troubleshooting
Related Contents
Servomotors / Servo Drivers
o Products
Primary Contents
Features
Principles
Top of page
Features
Precise, High-speed Control
Servomotors excel at position and speed control.
Precise and flexible positioning is possible.
47
Servomotors do not stall even at high speeds. Deviations due to large external forces are corrected
because encoders are used to monitor movement.
Fully-closed Loop
The most reliable form of closed loop. A fully-closed loop is used when high precision is required.
The motor is controlled while directly reading the position of the machine (workpiece or table) using a
linear encoder and comparing the read position with the command value (target value). Therefore, there
is no need to compensate for gear backlash between the motor and mechanical system, feed screw pitch
error, or error due to feed screw torsion or expansion.
Fully-closed Loop System Configuration Example
Semi-closed Loop
This method is commonly used in servo systems.
It is faster and has better positioning precision than an open loop.
Typically an encoder or other detector is attached behind the motor. The encoder detects the rotation
angle of a feed screw (ball screw) and provides it as feedback of the machine (workpiece or table) travel
position. This means that the position of the machine is not detected directly.
The characteristics depend on where the detector is installed.
Opposite of
Installation location of Motor side of
Behind motor motor side of
detector feed screw
feed screw
Compensation Compensation
Gear backlash ←
required not required
Ball screw or nut torsion Affected ← Hardly affected
Ball screw expansion or
Affected ← ←
contraction
Compensation
Ball screw pitch error ← ←
required
Semi-closed Loop System Configuration Example
48
3.12 stepper motor control
In Bipolar stepper motor there is just four wires coming out from two sets of coils, means there are no
common wire.
Stepper motor is made up of a stator and a rotator. Stator represents the four electromagnet coils which
remain stationary around the rotator, and rotator represents permanent magnet which rotates. Whenever
the coils energised by applying the current, the electromagnetic field is created, resulting the rotation of
rotator (permanent magnet). Coils should be energised in a particular sequence to make the rotator
rotate. On the basis of this “sequence” we can divide the working method of Unipolar stepper motor in
three modes: Wave drive mode, full step drive mode and half step drive mode.
Wave drive mode: In this mode one coil is energised at a time, all four coil are energised one after
another. It produces less torque in compare with Full step drive mode but power consumption is less.
Following is the table for producing this mode using microcontroller, means we need to give Logic 1 to
the coils in the sequential manner
49
Full Drive mode: In this, two coil are energised at the same time producing high torque. Power
consumption is higher. We need to give Logic 1 to two coils at the same time, then to the next two coils
and so on.
Steps A B C D
1 1 1 0 0
2 0 1 1 0
3 0 0 1 1
4 1 0 0 1
Half Drive mode: In this mode one and two coils are energised alternatively,
means firstly one coil is energised then two coils are energised then again one coil
is energised then again two, and so on. This is combination of full and wave drive
mode, and used to increase the angular rotation of the motor.
Steps A B C D
1 1 0 0 0
2 1 1 0 0
3 0 1 0 0
4 0 1 1 0
50
5 0 0 1 0
6 0 0 1 1
7 0 0 0 1
8 1 0 0 1
Interfacing with 8051 is very easy we just need to give the 0 and 1 to the four wires of stepper motor
according to the above tables depending on which mode we want to run the stepper motor. And rest two
wires should be connected to a proper 12v supply (depending on the stepper motor). Here we have used
the unipolar stepper motor. We have connected four ends of the coils to the first four pins of port 2 of
8051 through the ULN2003A.
51
8051 doesn’t provide enough current to drive the coils so we need to use a current driver IC that is
ULN2003A. ULN2003A is the array of seven NPN Darlington transistor pairs. Darlington pair is
constructed by connecting two bipolar transistors to achieve high current amplification. In ULN2003A,
7 pins are input pins and 7 pins are output pins, two pins are for Vcc (power supply) and Ground. Here
we are using four input and four output pins. We can also use L293D IC in place of ULN2003A for
current amplification.
You need to find out four coil wires and two common wires very carefully otherwise motor will not
rotate. You can find it out by measuring resistance using multimeter, multimeter won’t show any
readings between the wires of two phases. Common wire and the other two wire in the same phase
should show the same resistance, and the two end points of the two coils in the same phase will show the
twice resistance in compared with resistance between common point and one end point.
52
Two mark questions and Answers
The special function register are stack pointer, index pointer (DPL and DPH), I/O port addresses,
status(PSW) and accumulator.
The accumulator registers (A and B at addresses OEOh and OFOh, respectively) are used to store
temporary values and the results of arithmetic operations.
3. What is PSW?
Program status word (PSW) is the set of flags that contains the status information and is considered as
one of the special function register.
Stack pointer (SP) is a 8 bit wide register and is incremented before the data is stored into the stack
using PUSH or CALL instructions.
It contains 8-bit stack top address. It is defined anywhere in the on-chip 128-byte RAM. After reset, the
SP register is initialized to 07.
After each write to stack operation, the 8-bit contents of the operand are stored onto the stack, after
incrementing the SP register by one.
It is not a top-down data structure. It is allotted an address in the special function register bank.
5. What is data pointer (DTPR)?
It is a 16-bit register that contains a higher byte (DPH) and lower byte (DPL) of a 16-bit external data
RAM address.
53
It is accessed as a 16-bit register or two 8-bit registers. It has been allotted two addresses in the special
function register bank, for its two bytes DPH and DPL.
Oscillator circuit is used to generate the basic timing clock signal for the operation of the circuit using
crystal oscillator.
7. What is the purpose of using instruction register?
Instruction register is used for the purpose of decoding the opcode of an instruction to be executed and
gives information to the timing and control unit generating necessary signals for the execution of the
instruction.
ALE/PROG is an address latch enable output pulse and indicates that valid address bits available on the
respective pins.
The ALE pulses are emitted at a rate of one-sixth of the oscillator frequency. The signal is valid only for
external memory accesses.
It may be used for external timing or clockwise purpose. One ALE pulse is skipped during each access
to external data memory.
9. Explain the two power saving mode of operation. The two power saving modes of operation are:
I. Idle mode:
In this mode, the oscillator continues to run and the interrupt, serial port and timer blocks are active, but
the clock to the CPU is disabled. The CPU status is preserved. This mode can be terminated with a
hardware interrupt or hardware reset signal. After this, the CPU resumes program execution from where
it left off.
II. Power down mode:
In this mode, the on-chip oscillator is stopped. All the functions of the controller are held maintaining
the contents of RAM. The only way to terminate this mode is hardware reset. The reset redefines all the
SFRs but the RAM contents are left unchanged.
54
10. Differentiate between program memory and data memory. i. In stores the programs to be
executed.
ii. It stores only program code which is to be executed and thus it need not be written, so it is
implemented using EPROM It stores the data, line intermediate results, variables and constants required
for the execution of the program.
The data memory may be read from or written to and thus it is implemented using RAM.
10 mark questions
1. List all the registers used in 8051 microcontroller in brief.
2. Draw the pin diagram of 8051 microcontroller and explain each one.
3. Draw the memory organization of micro controller 8051 and eplain.
4. What are all addressing modes of micro controller 8051? explain with examples.
5. Draw the block diagram of 8051 microcontroller and explain.
6. What is 8051 micro-controller system? ? Give its block diagram representation? Also describe
its all ports in details?
55
UNIT 4
4.1 INTRODUCTION
The LF2407 DSP controller offers 40 million instructions per second (MIPS)
performance. This high processing speed of the C2xx CPU allows users to compute
parameters in real time rather than look up approximations from tables stored in memory. This
fast performance is well suited for processing control parameters in applications such as notch
filters or sensor less motor control algorithms where a large amount of calculations must be
computed quickly.
While the “brain” of the LF2407 DSP is the C2xx core, the LF2407 contains several
control-orientated peripherals onboard (see Fig. 3.1). The peripherals on the LF2407 make
virtually any digital control requirement possible. Their applications range from analog to digital
conversion to pulse width modulation (PWM) generation. Communication peripherals make
possible the communication with external peripherals, personal computers, or other DSP
processors. Below is a brief listing of the different peripherals onboard the LF2407 followed by a
graphical layout depicted in Fig. 3.1.
1
• Serial Peripheral Interface (SPI) – synchronous serial port
• Serial Communications Interface (SCI) – asynchronous serial port
• General-Purpose bi-directional digital I/O (GPIO) pins
• Watchdog Timer (“time-out” DSP reset device for system integrity)
Figure 3.1 Graphical overview of DSP core and peripherals on the LF2407.
4.2 Brief Introduction to Peripherals
The following peripherals are those that are integrated onto the LF2407 chip. Refer to
Fig. 1.1 to view the pin-out associated with each peripheral.
2
Event Managers (EVA, EVB)
There are two Event Managers on the LF2407, the EVA and EVB. The Event Manager is
the most important peripheral in digital motor control. It contains the necessary functions
needed to control electromechanical devices. Each EV is composed of functional “blocks”
including timers, comparators, and capture units for triggering on an event, PWM logic
circuits, quadrature-encoder–pulse (QEP) circuits, and interrupt logic.
The Analog-to-Digital Converter (ADC)
The ADC on the LF2407 is used whenever an external analog signal needs to be
sampled and converted to a digital number. Examples of ADC applications range from
sampling a control signal for use in a digital notch filtering algorithm or using the ADC in a
control feedback loop to monitor motor performance. Additionally, the ADC is useful in motor
control applications because it allows for current sensing using a shunt resistor instead of an
expensive current sensor.
The Control Area Network (CAN) Module
While the CAN module will not be covered in this text, it is a useful peripheral for
specific applications of the LF2407. The CAN module is used for multi-master serial
communication between external hardware. The CAN bus has a high level of data integrity
and is ideal for operation in noisy environments such as in an automobile, or industrial
environments that require reliable communication and data integrity.
Serial Peripheral Interface (SPI) and Serial Communications Interface (SCI)
The SPI is a high-speed synchronous communication port that is mainly used for
communicating between the DSP and external peripherals or another DSP device. Typical
uses of the SPI include communication with external shift registers, display drivers, or ADCs.
The SCI is an asynchronous communication port that supports asynchronous serial (UART)
digital communication between the CPU and other asynchronous peripherals that use the
standard NRZ (non-return-to-zero) format. It is useful in communication between external
devices and the DSP. Since these communication peripherals are not directly related to motion
control applications, they will not be discussed further in this text.
3
Watchdog Timer (WD)
The Watchdog timer (WD) peripheral monitors software and hardware operations and
asserts a system reset when its internal counter overflows. The WD timer (when enabled) will
count for a specific amount of time. It is necessary for the user’s software to reset the WD
timer periodically so that an unwanted reset does not occur. If for some reason there is a
CPU disruption, the watchdog will generate a system reset. For example, if the software enters
an endless loop or if the CPU becomes temporarily disrupted, the WD timer will overflow and a
DSP reset will occur, which will cause the DSP program to branch to its initial starting point.
Most error conditions that temporarily disrupt chip operation and inhibit proper CPU function
can be cleared by the WD function. In this way, the WD increases the reliability of the CPU, thus
ensuring system integrity.
General Purpose Bi-Directional Digital I/O (GPIO) Pins
Since there are only a finite number of pins available on the LF2407 device, many of the
pins are multiplexed to either their primary function or the secondary GPIO function. In
most cases, a pin’s second function will be as a general-purpose input/output pin. The GPIO
capability of the LF2407 is very useful as a means of controlling the functionality of pins and
also provides another method to input or output data to and from the device. Nine 16-bit control
registers control all I/O and shared pins. There are two types of these registers:
• I/O MUX Control Registers (MCRx) – Used to control the multiplexer selection that
Chooses between the primary function of a pin or the general-purpose I/O function.
• Data and Direction Control Registers (PxDATDIR) – Used to control the data and data
Direction of bi-directional I/O pins.
Phase Locked Loop (PLL) Clock Module
The phase locked loop (PLL) module is basically an input clock multiplier that allows
the user to control the input clocking frequency to the DSP core. External to the LF2407, a
clock reference (can oscillator/crystal) is generated. This signal is fed into the LF2407 and is
multiplied or divided by the PLL. This new (higher or lower frequency) clock signal is then
used to clock the DSP core. The LF2407’s PLL allows the user to select a multiplication
factor ranging from 0.5X to 4X that of the external clock signal. The default value of the PLL
is 4X.
4
Memory Allocation Spaces
The LF2407 DSP Controller has three different allocations of memory it can use: Data,
Program, and I/O memory space. Data space is used for program calculations, look-up
tables, and any other memory used by an algorithm. Data memory can be in the form of the on-
chip random access memory (RAM) or external RAM. Program memory is the location of user’s
program code. Program memory on the LF2407 is either mapped to the off-chip RAM
(MP/MC- pin =1) or to the on-chip flash memory (MP/MC- = 0), depending on the logic value
of the MP/MC-pin.
I/O space is not really memory but a virtual memory address used to output data to
peripherals external to the LF2407. For example, the digital-to-analog converter (DAC) on the
TM
Spectrum Digital evaluation module is accessed with I/O memory. If one desires to output
data to the DAC, the data is simply sent to the configured address of I/O space with the “OUT”
command. This process is similar to writing to data memory except that the OUT command is
used and the data is copied to and outputted on the DAC instead of being stored in memory.
The LF2407 has 544 words of 16 bits each in the on-chip DARAM. These 544 words are
partitioned into three blocks: B0, B1, and B2. Blocks B1 and B2 are allocated for use only as
data memory. Memory block B0 is different than B1 and B2. This memory block is normally
configured as Data Memory, and hence primarily used to hold data, but in the case of the B0
block, it can also be configured as Program Memory. B0 memory can be configured as
program or data memory depending on the value of the core level “CNF” bit.
• (CNF=0) maps B0 to data memory.
• (CNF=1) maps B0 to program memory.
The LF2407 also has 2K of single-access RAM (SARAM). The addresses associated
with the SARAM can be used for both data memory and program memory, and are software
configurable to the internal SARAM or external memory.
5
Non-Volatile Flash Memory
The LF2407 contains 32K of on-chip flash memory that can be mapped to program space
if the MP/MC-pin is made logic 0 (tied to ground). The flash memory provides a permanent
location to store code that is unaffected by cutting power to the device. The flash memory can be
electronically programmed and erased many times to allow for code development. Usually, the
external RAM on the LF2407 Evaluation Module (EVM) board is used instead of the flash for
code development due to the fact that a separate “flash programming” routine must be performed
to flash code into the flash memory. The on-chip flash is normally used in situations where the
DSP program needs to be tested where a JTAG connection is not practical or where the DSP
needs to be tested as a “stand-alone” device. For example, if a LF2407 was used to develop a
DSP control solution to an automobile braking system, it would be somewhat impractical to have
a DSP/JTAG/PC interface in a car that is undergoing performance testing.
4.1.1 Introduction to the C2xx DSP Core and Code Generation
The heart of the LF2407 DSP Controller is the C2xx DSP core. This core is a 16-bit fixed
point processor, meaning that it works with 16-bit binary numbers. One can think of the C2xx as
the central processor in a personal computer. The LF2407 DSP consists of the C2xx DSP core
plus many peripherals such as Event Managers, ADC, etc., all integrated onto one single chip.
4.1.2. The Components of the C2xx DSP Core
The DSP core (like all microprocessors) consists of several subcomponents necessary to
perform arithmetic operations on 16-bit binary numbers. The following is a list of the multiple
subcomponents found in the C2xx core which we will discuss further:
• A 32-bit central arithmetic logic unit (CALU)
• A 32-bit accumulator (used frequently in programs)
• Input and output data-scaling shifters for the CALU
• A (16-bit by 16-bit) multiplier
• A product-scaling shifter
• Eight auxiliary registers (AR0 – AR7) and an auxiliary register arithmetic unit
(ARAU)
Each of the above components is either accessed directly by the user code or is indirectly
used during the execution of an assembly command.
6
Central Arithmetic Logic Unit (CALU)
The C2xx performs 2s-complement arithmetic using the 32-bit CALU. The CALU uses
16-bit words taken from data memory, derived from an immediate instruction, or from the 32-
bit multiplier result. In addition to arithmetic operations, the CALU can perform Boolean
operations. The CALU is somewhat transparent to the user. For example, if an arithmetic
command is used, the user only needs to write the command and later read the output from the
appropriate register. In this sense, the CALU is “transparent” in that it is not accessed directly by
the user.
Accumulator
The accumulator stores the output from the CALU and also serves as another input to the CALU
(many arithmetic commands perform operations on numbers that are currently stored in the
accumulator; versus other memory locations). The accumulator is 32 bits wide and is divided
into two sections, each consisting of 16 bits. The high-order bits consist of bits 31 through 16,
and the low-order bits are made up of bits 15 through 0. Assembly language instructions are
provided for storing the high- and low-order accumulator words to data memory. In most cases,
the accumulator is written to and read from directly by the user code via assembly commands. In
some instances, the accumulator is also transparent to the user (similar to the CALU operation in
that it is accessed “behind the scenes”).
Scaling Shifters
The C2xx has three 32-bit shifters that allow for scaling, bit extraction, extended arithmetic, and
overflow-prevention operations. The scaling shifters make possible commands that shift data left
or right. Like the CALU, the operation of the scaling shifters is “transparent” to the user. For
example, the user needs only to use a shift command, and observe the result. Any one of the
three shifters could be used by the C2xx depending on the specific instruction entered. The
following is a description of the three shifters:
• Input data-scaling shifter (input shifter): This shifter left-shifts 16-bit input data by 0 to 16
bits to align the data to the 32-bit input of the CALU. For example, when the user uses a
command such as “ADD 300h, 5”, the input shifter is responsible for first shifting the data in
memory address “300h” to the left by five places before it is added to the contents of the
accumulator.
7
• Output data-scaling shifter (output shifter): This shifter left-shifts data from the accumulator
by 0 to 7 bits before the output is stored to data memory. The content of the accumulator
remains unchanged. For example, when the user uses a command such as “SACL 300h, 4”,
the output shifter is responsible for first shifting the contents of the accumulator to the left by
four places before it is stored to the memory address “300h”.
Product-scaling shifter (product shifter): The product register (PREG) receives the output
of the multiplier. The product shifter shifts the output of the PREG before that output is sent
to the input of the CALU. The product shifter has four product shift modes (no shift, left shift
by one bit, left shift by four bits, and right shift by six bits), which are useful for performing
multiply/accumulate operations, fractional arithmetic, or justifying fractional products.
Multiplier
The multiplier performs 16-bit, 2s-complement multiplication and creates a 32-bit result.
In conjunction with the multiplier, the C2xx uses the 16-bit temporary register (TREG) and the
32-bit product register (PREG).
The operation of the multiplier is not as “transparent” as the CALU or shifters. The
TREG always needs to be loaded with one of the numbers that are to be multiplied. Other than
this prerequisite, the multiplication commands do not require any more actions from the user
code. The output of the multiply is stored in the PREG, which can later be read by the user code.
Auxiliary Register Arithmetic Unit (ARAU) and Auxiliary Registers
The ARAU generates data memory addresses when an instruction uses indirect addressing to
access data memory (more on indirect addressing will be covered later along with assembly
programming). Eight auxiliary registers (AR0 through AR7) support the ARAU, each of which
can be loaded with a 16-bit value from data memory or directly from an instruction. Each
auxiliary register value can also be stored in data memory. The auxiliary registers are mainly
used as “pointers” to data memory locations to more easily facilitate looping or repeating
algorithms. They are directly written to by the user code and are automatically incremented or
decremented by particular assembly instructions during a looping or repeating operation. The
auxiliary register pointer (ARP) embedded in status register ST0 references the auxiliary register.
The status registers (ST0, ST1) are core level registers where values such as the Data Page (DP)
and ARP located.
8
4.2. System Configuration Registers
The System Control and Status Registers (SCSR1, SCSR2) are used to configure or
display fundamental settings of the LF2407. For example, these fundamental settings include the
clock speed (clock pre-scale setting) of the LF2407, which peripherals are enabled,
microprocessor/microcontroller mode, etc. Bits are controlled by writing to the corresponding
data memory address or the logic level on an external pin as with the
microprocessor/microcontroller (MP/MC) select bit. The bit descriptions of these two registers
(mapped to data memory) are listed below.
System Control and Status Register 1 (SCSR1) — Address 07018h
Bit 15 Reserved
Bit 14 CLKSRC. CLKOUT pin source select
0 CLKOUT pin has CPU Clock (40 MHz on a 40-MHz device) as the output
1 CLKOUT pin has Watchdog clock as the output
Bits 13–12 LPM (1:0). Low-power mode select
These bits indicate which low-power mode is entered when the CPU executes the IDLE
instruction. Description of the low-power modes:
9
Bits 11–9
PLL Clock prescale select. These bits select the PLL multiplication factor for the input clock.
Bit 8 Reserved
Bit 7 ADC CLKEN. ADC module clock enable control bit.
0 Clock to module is disabled (i.e., shut down to conserve power).
1 Clock to module is enabled and running normally.
Bit 6 SCI CLKEN. SCI module clock enable control bit.
0 Clock to module is disabled (i.e., shut down to conserve power).
1 Clock to module is enabled and running normally.
10
Bit 1 Reserved
Bit 0 ILLADR. Illegal Address detect bit
If an illegal address has occurred, this bit will be set. It is up to software to clear this bit
following an illegal address detects. This bit is cleared by writing a 1 to it and should be cleared
as part of the initialization sequence. Note: An illegal address will cause a Non-Mask able
Interrupt (NMI).
System Control and Status Register 2 (SCSR2) — Address 07019h
11
Bit 5 Watchdog Override. (WD protect bit)
After RESET, this bit gives the user the ability to disable the WD function through
software (by setting the WDDIS bit = 1 in the WDCR). This bit is a clear-only bit and defaults to
a 1 after reset.
Note: This bit is cleared by writing a 1 to it.
0 Protects the WD from being disabled by software. This bit cannot be set to 1 by
software. It is a clear-only bit, cleared by writing a 1.
1 This is the default reset value and allows the user to disable the WD through the
WDDIS bit in the WDCR. Once cleared, however, this bit can no longer be set to 1 by software,
thereby protecting the integrity of the WD timer.
Bit 4 XMIF Hi-Z Control
This bit controls the state of the external memory interface (XMIF) signals.
0 XMIF signals in normal driven mode; i.e., not Hi-Z (high impedance).
1 All XMIF signals are forced to Hi-Z state.
Bit 3 Boot Enable
This bit reflects the state of the BOOT_EN / XF pin at the time of reset. After reset and device
has “booted up”, this bit can be changed in software to re-enable Flash memory visibility or
return to active Boot ROM.
0 Enable Boot ROM — Address space 0000 — 00FF is now occupied by the on-
chip Boot ROM Block. Flash memory is totally disabled in this mode. Note: There is no on-chip
boot ROM in ROM devices (i.e., LC240xA)
1 Disable Boot ROM — Program address space 0000 — 7FFF is mapped to on-
chip Flash memory in the case of LF2407A and LF2406A. In the case of LF2402A, addresses
0000 – 1FFF are mapped
Bit 2 Microprocessor/Microcontroller Select
This bit reflects the state of the MP/MC pin at time of reset. After reset, this bit can be changed
in software to allow dynamic mapping of memory on and off chip.
0 Set to Microcontroller mode — Program Address range 0000 — 7FFF is mapped
internally (i.e., Flash)
1 Set to Microprocessor mode — Program Address range 0000 — 7FFF is mapped
externally (i.e., customer provides external memory device.)
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Bits 1–0 SARAM Program/Data Space Select
DON PON SARAM status
0 0 SARAM not mapped (disabled), address space allocated to external memory
0 1 SARAM mapped internally to Program space
1 0 SARAM mapped internally to Data space
1 1 SARAM block mapped internally to both Data and Program spaces.
This is the default or reset value
4.3. Memory Addressing Modes
There are three basic memory addressing modes used by the C2xx instruction set. The three
modes are:
• Immediate addressing mode (does not actually access memory)
• Direct addressing mode
• Indirect addressing mode
4.4.1 Immediate Addressing Mode
In the immediate addressing mode, the instruction contains a constant to be manipulated by the
instruction. Even though the name “immediate addressing” suggests that a memory location is
accessed, immediate addressing is simply dealing with a user-specified constant which is usually
included in the assembly command syntax. The “#” sign indicates that the value is an immediate
address (just a constant). The two types of immediate addressing modes are:
Short-immediate addressing. The instructions that use short-immediate addressing have an 8-
bit, 9-bit, or 13-bit constant as the operand.
For example, the instruction:
LACL #44h ; loads lower bits of accumulator with
; Eight-bit constant (44h in this case)
Note: The LACL command will work only with a short 8-bit constant. If you want to load a long
16-bit constant, then use the LACC command.
Long-immediate addressing. Instructions that use long-immediate addressing have a 16-bit
constant as an operand. This 16-bit value can be used as an absolute constant or as a 2s-
complement value.
For example, the instruction:
LACC #4444h ; loads accumulator with up to a 16-bit
13
; Constant (4444h in this case)
If you need to use registers or access locations in data memory, you must use either direct or
indirect addressing.
4,5. Direct Addressing Mode
In direct addressing, data memory is first addressed in blocks of 128 words called data
pages. The entire 64K of data memory consists of 512 DPs labeled 0 through 511, as shown in
the Fig. 3.2. The current DP is determined by the value in the 9-bit DP pointer in status register
ST0. For example, if the DP value is “0 0000 0000”, the current DP is 0. If the DP value is “0
0000 0010”, the current data page is 2. The DP of a particular memory address can be found
easily by dividing the address (in hexadecimal) by 80h.
For example: For the data memory address 0300h, 300h/80h = 6h so the DP pointer is 6h.
Likewise, the DP pointer for 200h is 4h.
14
Figure 3.3 Data page and offset make up a 16-bit memory address.
When you use direct addressing, the processor uses the 9 DP bits and the 7 LSBs of the
instruction to obtain the true memory address. The following steps should be followed when
using direct addressing:
1 Set the DP. Load the appropriate value (from 0 to 511 in decimal or 0-1FF in hex) into
the DP. The easiest way to do this is with the LDP instruction. The LDP instruction loads
the DP directly to the ST0 register without affecting any other bits of the ST0.
15
shown following the program code. Before the ADD instruction is executed, the opcode is
loaded into the instruction register. Together, the DP and the seven LSBs of the instruction
register form the complete 16-bit address, 0000 0010 0000 10012 (0209h).
In Example 2, the ADD instruction references a data memory address that is generated as
shown following the program code. For any instruction that performs a shift of 16, the shift value
is not embedded directly in the instruction word; instead, all eight MSBs contain an opcode that
not only indicates the instruction type, but also a shift of 16. The eight MSBs of the instruction
word indicate an ADD with a shift of 16.
Example 1 Using Direct Addressing with ADD (Shift of 0 to 15)
16
In Example 3, the ADDC instruction references a data memory address that is generated
as shown following the program code. You should note that if an instruction does not perform
shifts (such as the ADDC instruction), all eight MSBs of the instruction contain the opcode for
the instruction type.
Example 3 Using Direct Addressing with ADDC
17
4.5.2 Indirect Addressing Mode
Indirect addressing is a powerful way of addressing data memory. Indirect addressing
mode is not dependent on the current data page as is direct addressing. Instead, when using
indirect addressing you load the memory space that you would like to access into one of the
auxiliary registers (ARx). The current auxiliary register acts as a pointer that points to a specific
memory address.
The register pointed to by the ARP is referred to as the current auxiliary register or
current AR. To select a specific auxiliary register, load the 3-bit auxiliary register pointer (ARP)
with a value from 0 to 7. The ARP can be loaded with the MAR instruction or by the LARP
instruction. An ARP value can also be loaded by using the ARx operand after any instruction
that supports indirect addressing as seen below.
Example of using MAR:
ADD *, AR1 ; Adds using current *, then makes AR1 the
; New current AR for future uses
Example of using LARP
LARP #2 ; this will make AR2 the current AR
The C2xx provides four types of indirect addressing options:
No increment or decrement. The instruction uses the content of the current auxiliary
register as the data memory addresses but neither increments nor decrements the content
of the current auxiliary register.
Increment or decrement by 1. The instruction uses the content of the current auxiliary
register as the data memory address and then increments or decrements the content of the
current auxiliary register by one.
Increment or decrement by an index amount. The value in AR0 is the index amount.
The instruction uses the content of the current auxiliary register as the data memory
address and then increments or decrements the content of the current auxiliary register by
the index amount.
Increment or decrement by an index amount using reverse carry. The value in AR0 i
the index amount. After the instruction uses the content of the current auxiliary register as
the data memory address, that content is incremented or decremented by the index
18
amount. The addition and subtraction process is accomplished with the carry propagation
reversed and is useful in fast Fourier transforms algorithms.
Table 4.1 displays the various operands that are available for use with instructions while using
indirect addressing mode.
Example 1 illustrates how the instruction register is loaded with the value shown when the ADD
instruction is fetched from program memory.
Example 1. Indirect Addressing—No Increment or Decrement
19
Example 2, illustrates how the instruction register is loaded with the value shown when the ADD
instruction is fetched from program memory.
Example 2. Indirect Addressing—Increment by 1
20
4.6 Assembly Programming Using the C2xx DSP Instruction Set
The complete detailed instruction set for the C2xx DSP core can be found in the Texas
Instruments TMS320F/C24x DSP Controllers Reference Guide: CPU and Instruction Set;
Literature Number: SPRU160C. This reference guide contains a complete descriptive listing on
syntax, operands, binary opcode, instruction execution order, status bits affected by the
instruction, number of memory words required to store the instruction, and clock-cycles used by
the instruction. The Texas Instruments documentation on the assembly instruction set is very
well written. Each assembly instruction has a complete explanation of the instruction, all
optional operands, and several examples of the instructions used. Since including the instruction
set and complete documentation would make this book excessively long, we will assume the
reader has access to the documentation referred to above.
We will therefore focus on developing code, not the instruction set itself. Each command starts
with the basic assembly instruction. Each command supports specific addressing modes and
options. For example, the ADD command will work with direct, indirect, and immediate
addressing. In addition to the basic command, many instructions have additional options that
may be used with the instruction. For example, the ADD command supports left shifting of the
data before it is added to the accumulator.
The following is the instruction syntax for the ADD command:
ADD dma [, shift] ; Direct addressing
ADD dma, 16 ; Direct with left shift of 16
ADD ind [, shift [, ARn]] ; Indirect addressing
ADD ind, 16 [, ARn] ; Indirect with left shift of 16
ADD #k ; short immediate addressing
ADD #lk [, shift] ; Long immediate addressing
The following is a list of the various notations used in C2xx syntax examples:
Italics Italic symbols in instruction syntax represent variables.
Example:
LACC dma, you can use several ways to address the dma (data memory address).
LACC *
Or
LACC 200h
21
Or
LACC v ; where “v” is any variable assigned to data memory
Where *, 200h, and v are the data memory addresses
Boldface Characters Boldface characters must be included in the syntax.
Example:
LAR dma, 16 ; direct addressing with left shift of 16
LAR AR1, 60h, 16 ; load auxiliary AR1 register with the memory contents of 60h that
was left shifted 16 bits
Example:
LACC dma, [shift] ; optional left shift from 0, 15; defaults to 0
LACC main_counter, 8 ; shifts contents of the variable “main_counter” data 8 places to
the left before loading accumulator
[ ] An optional operand may be placed in the placed here.
Example:
LACC ind [, shift [, AR n]_] Indirect addressing
LACC * ; load Accum. W/contents of the memory
; Location pointed to by the current AR.
LACC *, 5 ; load Accum. With the contents of the memory
; Location pointed to by the current AR after
; The memory contents are left shifted by 5
; Bits.
LACC *, 0, AR3 ; load Accum. With the contents of the memory
; Location pointed to by the current AR after
; The memory contents are left shifted by 5
; Bits. Now you have the option of choosing
; A new AR. In this case, AR3 will become the
; New AR.
[, x1 [, x2]] Operands x1 and x2 are optional, but you cannot include x2 without also including
x1.
22
It is optional when using indirect addressing to modify the data. Once you supply a left
shift value from 0…15 (even a shift of 0), then you have the option of changing to a new current
auxiliary register (AR).
# The # sign is prefix that signifies that the number used is a constant as opposed to
memory location.
Example:
RPT #15 ; this syntax is using short immediate addressing. It will repeat the next
instruction 15+1 times.
LACC #60h ; this will load the accumulator with the
; Constant 60h
LACC 60h ; However, this instruction will load the
; Accumulator with the contents in the data
; Memory location 60h, not the constant #60h
We will now provide a few examples of using the instruction set. Example 2.1 performs a few
arithmetic functions with the DSP core and illustrates the nature of assembly programming.
Programming with the assembly instruction set is somewhat different than languages such as C.
In a high-level language, to add two numbers we might just code “c = a + b”. In assembly, the
user must be sure to code everything that needs to happen in order for a task to be executed. Take
the following example:
Example 2.1 - Add the two numbers “2” and “3”:
LDP #6h ; loads the proper DP for dma 300h
SPLK #2, 300h ; store the number “2” in memory address 300h
LACL #3 ; load the accumulator with the number “3”
ADD 300h ; adds contents of 300h (“2”) to the contents
; of the accumulator (“3”); accumulator = 5
Another way:
LDP #6h ; loads the proper DP for dma 300h
SPLK #2h, 300h ; store the number “2h” in memory address
; 300h
SPLK #3h, 301h ; stores the number “3h” into memory address
; 301h
23
LACL 300h ; load the accumulator with the contents in
; Memory location 300h
ADD 301h ; adds contents of memory address 301h (“3h”)
; To the contents of the accumulator (“2h”)
;accumulator = 5h
Looping algorithms are very common in all programming languages. In high-level languages, the
“For” and “While” loops can be used. However, in assembly, we need a slightly different
approach to perform a repeating algorithm. The following example is an algorithm that stores the
value “1” to memory locations 300h, 301h, 302h, 303h, and 304h.
24
CONTENTS
V 2
UNIT-V: FPGA
Introduction 2
Unit-V notes 2
Solved Problems
Part A Questions (2 marks) 38
Part B Questions (10 marks) 40
1
UNIT V
FPGA
5.1 Introduction to Field Programmable Gate Arrays – CPLD Vs FPGA – Types of FPGA –
Xilinx, XC3000 series - Configurable logic Blocks (CLB) – Input / Output Block (IOB) –
Programmable Interconnect Point (PIP) – Xilinx 4000 series – HDL programming –overview of
Spartan 3E and Virtex II pro FPGA boards- case study
It has been more than three decades since the introduction of FPGAs into the market and in this
long span, they have undergone a severe technological advancement and gained a continuously
growing popularity.
Before diving into the main topic, I want to briefly discuss the concept of Programmable Logic
Devices. So, what is a PLD. It is an IC containing a large number of Logic gates and Flip-flops
that can be configured by the user to implement a wide variety of functions.
The simplest of Programmable Logic Devices consists of an array of AND & OR gates and the
logic of these gates and their interconnections can be configured by a programming process.
2
PLDs are particularly useful when an engineer wants to implement a customized logic and is
restricted by the pre-configured integrated circuits. PLDs provide a way to implement a custom
digital circuit through the power of hardware configuration rather than implementing it using a
software.
A PLA consists of an AND gate plane with programmable interconnects and an OR gate plane
with programmable interconnects. The following is a simple four input – four output PLA with
3
Any input can be connected to any AND gate by connecting the horizontal and vertical
interconnect lines. The outputs from different AND gates can then be applied to any of the OR
4
Fig PLA circuits
5
Fig. PAL Circuits
6
Generic Array Logic (GAL)
Architecture wise, a GAL is similar to a PAL but the difference lies in programmable structure.
PALs use PROM, which is one-time programmable, while GAL uses EEPROM, which can be
reprogrammed.
5.2 CPLD Vs FPGA
CPLD is often used for simple logic applications. It contains only a few blocks of logic and
reaches up to 100. Having said that, CPLDs are considered as ‘coarse-grain’ type of
devices. CPLDs are cheap and it also offers a much faster input to output duration because
of its simpler, ‘coarse grain’ architecture.
FPGAs are cheaper per gate but expensive when it comes to package.
Working with FPGAs requires special procedures as it is RAM based. To program the
device, you have to first describe the ‘logic function’ with the use of computer, either by
drawing a schematic or simply describing the function on a text file.
Compilation of the ‘logic function’ usually requires a software. It creates a binary file to
be downloaded into the FPGA and then the chip will behave just what you have instructed
in the ‘logic function’.
1. FPGA contains up to 100,000 of tiny logic blocks while CPLD contains only a few blocks
of logic that reaches up to a few thousands.
2. In terms of architecture, FPGAs are considered as ‘fine-grain’ devices while CPLDs are
‘coarse-grain’.
3. FPGAs are great for more complex applications while CPLDs are better for simpler
ones.
4. FPGAs are made up of tiny logic blocks while CPLDs are made of larger blocks.
5. FPGA is a RAM-based digital logic chip while CPLD is EEPROM-based.
6. Normally, FPGAs are more expensive while CPLDs are much cheaper.
7. Delays are much more predictable in CPLDs than in FPGAs.
7
Complex Programmable Logic Devices (CPLD)
Moving up from SPLD devices, we get CPLD. It is developed on top of SPLD devices to create
mush larger and complex designs. A CPLD consists of a number logic blocks (or functional
blocks), which internally consists of either a Pal or a PAL along with a Macrocell.
Macrocell consists of any additional circuitry and signal polarity control to provide true signal or
its complement
8
Using an FPGA, you can implement any custom design by specifying the logic or function of
each logic block and setting the connection of each programmable switch. Since this process of
designing a custom circuit is done in the field rather than in a fab, the device is known as “Field
Programmable”.
The following image shows a typical internal structure of an FPGA in a very broad sense.
As you can see, the core of the FPGA is made up of configurable logic cells and programmable
interconnections. These are surrounded by a number of programmable IO blocks, which are used
to talk to the external world.
9
Components of an FPGA
Let us now take a closer look at the structure of an FPGA. Typically, an FPGA consists of
three basic components. They are:
Programmable Logic Cells (or Logic Blocks) – responsible for implementing the core
logic functions.
Programmable Routing – responsible for connecting the Logic Blocks.
IO Blocks – which are connected to the Logic Blocks through the routing and help to
make external connections
Logic Block
The Logic Block in Xilinx based FPGAs are called as Configurable Logic Blocks or CLB while
the similar structures in Altera based FPGAs are called Logic Array Blocks or LAB. Let us use
the term CLB for this discussion. A CLB is the basic component of an FPGA, which provides
both the logic and storage functionalities. The basic logic block can be anything like a transistor,
10
a NAND gate, Multiplexors, Look-up Table (LUT), a PAL like structure or even a processor.
Both Xilinx and Altera use Look-up Table (LUT) based logic blocks to implement the logic as
well as the storage functionalities.
A Logic Block can be made up of a single Basic Logic Element or a set of interconnected Basic
Logic Elements, where a Basic Logic Element is a combination of a Look-up table (which is in
turn made up of SRAM and Multiplexors) and a Flip-flop
A LUT with ‘n’ inputs consists of 2n configuration bits, which are implemented by SRAM Cells.
Using these 2n SRAM Bits, the LUT can be configured to implement any logical function.
11
Routing
If the computational functionality is provided by the Logic Blocks, then the programmable
routing network is responsible for interconnection these logic blocks. The Routing Network
provides interconnections between one logic block to other as well as between the logic block
and the IO Block to completely implement a custom circuit.
Basically, the routing network consists of connecting wires with programmable switches, which
can be configured using any of the programming technologies. There are basically two types of
routing architectures. They are:
Many logic blocks are confined to a local set of connections and hierarchical routing architecture
makes use of this feature by dividing the logic blocks into several groups or clusters. If the logic
blocks are residing in the same cluster, then the hierarchical routing connects them in a low level
of hierarchy.
12
5.3 Types of FPGA
We have talked about the reprogrammable architecture of FPGAs quite a bit but now let us see
some of the most commonly used programming techniques that is responsible for such
reconfigurable architecture.
The following are three of the well-known programming technologies used in FPGAs.
SRAM
EEPROM / Flash
Anti-Fuse
13
Other technologies include EPROM and Fusible Link but they are used in CPLDs and other
PLDs but not in FPGAs, Hence, let us keep the discussion limited to FPGA related programming
technologies.
SRAM
We know that there are two types of semiconductor RAM called the SRAM and DRAM. SRAM
is short for Static RAM while DRAM is short for Dynamic Ram. SRAM is designed using
transistors and the term static means that the value loaded on a basic SRAM Memory Cell will
remain the same until deliberately changed or when the power is removed.
A typical 6 transistor SRAM Cell to store 1 bit is shown in the following image.
This is in contrast to the DRAM, which consists of a combination of a transistor and a capacitor.
The term Dynamic refers to the fact that the value loaded in the basic DRAM Memory Cell is
14
valid until there is charge in the capacitor. As capacitor loses its charge over time, the memory
cell has to be periodically recharged to maintain the charge. This is also known as refreshing.
Many FPGA vendors implement Static Memory Cells in SRAM based FPGAs for programming.
SRAM based FPGAs are used to program both the logic cells and the interconnects and they
have become quite predominant due to their re-programmability and use of CMOS technology,
which is known for its low dynamic power consumption, high speed and tighter integration.
EEPROM / Flash
A close alternative to SRAM based programming technology is based on EEPROM or Flash
programming technologies. The main advantage of flash-based programming is its non-volatile
nature. Even though flash supports re-programmability, the number of times this can be done is
very small when compared to an SRAM technology.
15
Anti-Fuse
The anti-fuse programming technology is an old technique of producing one-time programmable
devices. They are implemented using a link called the antifuse, which in its unprogrammed state
has a very high resistance and can be considered an open circuit.
When programming, a high voltage and current is supplied to the input. As a result, the antifuse,
which is initially in the form of amorphous silicon (basically an insulator with very high
resistance) linking two metal tracks, comes to life by converting to a conducting polysilicon.
When compared to the other two technologies, the antifuse one occupies the least amount of
space but comes only as one-time programmable option.
Property OTP FPGA MTP FPGA
16
5.4 Xilinx
Xilinx is the inventor of the FPGA, programmable SoCs, and now, the
ACAP. Xilinx delivers the most dynamic processing technology in the industry.
Xilinx, Inc. (/ˈzɪlɪŋks/ ZEE-links) was an American technology and semiconductor company
that primarily supplied programmable logic devices. The company was known for
inventing the first commercially viable field-programmable gate array (FPGA) and
creating the first fabless manufacturing model,
Xilinx was co-founded by Ross Freeman, Bernard Vonderschmitt, and James V Barnett II
in 1984 and the company went public on the NASDAQ in 1989. AMD announced its
acquisition of Xilinx in October 2020 and the deal was completed on February 14, 2022
through an all-stock transaction worth an estimated $50 billion.
Before 2010, Xilinx offered two main FPGA families: the high-performance Virtex series
and the high-volume Spartan series, with a cheaper EasyPath option for ramping to
volume production. The company also provides two CPLD lines: the CoolRunner and the
9500 series. Each model series has been released in multiple generations since its launch.
With the introduction of its 28 nm FPGAs in June 2010, Xilinx replaced the high-volume
Spartan family with the Kintex family and the low-cost Artix family.
Features
Complete line of four related Field Programmable Gate Array product families - XC3000A,
XC3000L, XC3100A, XC3100L
• Ideal for a wide range of custom VLSI design tasks - Replaces TTL, MSI, and other PLD logic
- Integrates complete sub-systems into a single package - Avoids the NRE, time delay, and risk
of conventional masked gate arrays
• Extensive packaging options - Over 20 different packages - Plastic and ceramic surface-mount
and pin-gridarray packages - Thin and Very Thin Quad Flat Pack (TQFP and VQFP) options
• Ready for volume production - Standard, off-the-shelf product availability - 100% factory pre-
tested devices - Excellent reliability record
Complete Development System - Schematic capture, automatic place and route - Logic and
timing simulation - Interactive design editor for design optimization - Timing calculator -
Interfaces to popular design environments like Viewlogic, Cadence, Mentor Graphics, and others
CLBs contain smaller components, including flip-flops, look-up tables (LUTs), and multiplexers.
Flip-Flop—A circuit capable of two stable states that represents a single bit. A flip-flop
is the smallest storage resource on the FPGA. Each flip-flop in a CLB is a binary register
used to save logic states between clock cycles on an FPGA circuit.
Look-up Table (LUT)—A collection of gates hardwired on the FPGA. An LUT stores a
predefined list of outputs for every combination of inputs. LUTs provide a fast way to
retrieve the output of a logic operation because possible results are stored and then
referenced rather than calculated. The LUTs in a CLB can also implement FIFOs and
memory items in LabVIEW.
Multiplexer—A circuit that selects between two or more inputs and then returns the
selected input.
18
When you compile code to run on an FPGA target, LabVIEW implements much of the code
using flip-flops, LUTs, and multiplexers.
The input/output block (IOB) is used for communication between the problem program and the
system. It provides the addresses of other control blocks, and maintains information about the
channel program, such as the type of chaining and the progress of I/O operations. You must
define the IOB and specify its address as the only parameter of the EXCP or EXCPVR macro
instruction.
The input/output block (IOB) is not automatically constructed by a macro instruction; it must be
defined as a series of constants and be on a word boundary. For unit-record and tape devices, the
IOB is 32 bytes long. For direct access, teleprocessing, and graphic devices, 8 additional bytes
must be provided. Use the system mapping macro IEZIOB, which expands into a DSECT, to
help in constructing an IOB. IEZIOB fields that are not described here are not part of the
programming interface.
19
In Figure 1 the shaded areas indicate fields in which you must specify information. The other
fields are used by the system and must be defined as all zeros. You cannot place information into
these fields, but you can examine them.
You do not have to set the following IOB fields to any particular value before issuing EXCP
because the system itself sets them:
IOBSENS0
IOBSENS1
IOBECBCC
IOBCSW
IOBSIOCC
IOBCMD31
20
. Figure Input/Output Block (IOB) Format
IOBFLAG1 (1 byte)
Set bit positions 0, 1, 6, and 7. One-bits in positions 0 and 1 (IOBDATCH and
IOBCMDCH) indicate data chaining and command chaining, respectively. (If you
21
specify both data chaining and command chaining, the system does not use error
recovery routines except for the direct access and tape devices.) If an I/O error occurs
while your channel program executes, a failure to set the chaining bits in the IOB that
correspond to those in the CCW might make successful error recovery impossible. The
integrity of your data could be compromised.
A one-bit in position 6 (IOBUNREL) indicates that the channel program is not a related
request; that is, the channel program is not related to any other channel program. See bits
2 and 3 of IOBFLAG2 below.
If you intend to issue an EXCP or XDAP macro with a BSAM, QSAM, or BPAM DCB,
you should turn on bit 7 (IOBSPSVC) to prevent access-method appendages from
processing the I/O request.
IOBFLAG2 (1 byte)
If you set bit 6 in the IOBFLAG1 field to zero, bits 2 and 3 (IOBRRT3 and
IOBRRT2) in this field must then be set to one of the following:
00, if any channel program or appendage associated with a related request might
modify this IOB or channel program.
01, if the conditions requiring a 00 setting do not apply, but the CHE or ABE
appendage might retry this channel program if it completes normally or with the
unit-exception or wrong-length-record bits on in the CSW.
10 in all other cases.
The combinations of bits 2 and 3 represent related requests,known as type 1 (00), type 2
(01), and type 3 (10). The type you use determines how much the system can overlap the
processing of related requests. Type 3 allows the greatest overlap, normally making it
possible to quickly reuse a device after a channel-end interruption. (Related requests that
were executed on a pre-MVS system are executed as type-1 requests if not modified.)
22
IOBSENS0 and IOBSENS1 (2 bytes)
are set by the system when a unit check occurs. These are the first two sense bytes.
Occasionally, the system is unable to obtain any sense bytes because of unit checks
when sense commands are issued. In this case, the system simulates sense bytes by
moving X'10FE' to IOBSENS0 and IOBSENS1.
The first six of these 16 bits have these device-independent meanings:
The last ten of these 16 bits have device-dependent meanings. See appropriate hardware
documentation.
If you wish to retrieve more than two sense bytes, supply an IOBE and IEDB
OBECBCC (1 byte)
The first byte of the completion code for the channel program. The system places this
code in the high-order byte of the event control block when the channel program is
posted complete.
OBECBPT (3 bytes)
The address of the 4-byte event control block (ECB) you have provided.
IOBFLAG3 (1 byte) and IOBCSW (7 bytes)
The system stores status information in these eight bytes
IOBSIOCC (1 byte)
If the channel program uses format 0 CCWs, bits 2 and 3 contain the start subchannel
(SSCH) condition code for the instruction the system issues to start the channel
program.
23
If this is a format 1 CCW channel program or is a zHPF channel program, then field
IOBSIOCC is redefined as field IOBSTART, which contains the four byte starting
address of the channel program to be executed
IOBSTRTB (3 bytes)
If the channel program uses format 0 CCWs, the three byte starting address of the
channel program to be executed.
IOBFLAG4 (1 byte)
Set bit 3 (IOBCEF) to indicate whether you are supplying an IOB common extension
(IOBE). If this bit is 1, then register 0 contains the IOBE address
IOBDCBPT (3 bytes)
The address of the DCB of the data set to be read or written by the channel program.
Reserved (1 byte)
Used by the system.
IOBRESTR+1 (3 bytes)
If a related channel program is permanently in error, this field is used to chain together
IOBs that represent dependent channel programs.
IOBINCAM (2 bytes)
For magnetic tape, the amount by which the system increments the block count
(DCBBLKCT) field in the device-dependent portion of the DCB. You can alter these
bytes at any time. For forward operations, these bytes should contain a binary positive
integer (usually +1); for backward operations, they should contain a binary negative
integer.
IOBERRCT (2 bytes)
Used by the system.
IOBSEEK (first byte, M)
For direct access devices, the extent entry in the data extent block that is associated
with the channel program (0 indicates the first entry; 1 indicates the second, and so
forth).
IOBSEEK (last 7 bytes, BBCCHHR)
For direct access devices, the seek address for your channel program.
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5.8 Programmable Interconnect Point (PIP)
Programmable Interconnect Points (PIPs)
•Also known as Configurable Interconnect Points (CIPs)
Transmission gate connects to 2 wire segments–Controlled by configuration memory bit
•0 = wires disconnected
•1 = wires connected
PIPs
Break-point PIP–Connect or isolate 2 wire segments
25
Features
26
Backward Compatible with XC4000 Family
XACTstep Development System runs on ‘386/’486/ Pentium-type PC, Sun-4, and Hewlett-
Packard 700 series
Interfaces to popular design environments including VIEWlogic, Mentor Graphics and
OrCAD
Fully automatic partitioning, placement and routing
Interactive design editor for design optimization
Unified Libraries, including 288 soft macros and 34 Relationally Placed Macros (RPMs)
RAM/ROM compiler
The XC4000E family is supported by powerful and sophisticated software, covering every aspect
of design from schematic or behavioral entry, floor planning, simulation, automatic block
placement and routing of interconnects, to the creation, downloading, and read back of the
configura-tion bit stream.
The Xilinx XC4000E family includes three major configurable elements: configurable logic
blocks (CLBs), input/output blocks, and interconnects.
The CLBs provide the functional elements for constructing user's logic. The IOBs provide the
interface between the package pins and internal signal lines.
The programmable interconnect resources provide routing paths to connect the inputs and
outputs of the CLBs and IOBs onto the appropriate networks.
27
Specifications
Device XC4013E
Aproximate Gate Count 13,000
CLB Matrix 24 x 24
Number of CLBs 567
Number of Flip-Flops 1,536
Max. Decode Inputs per Side 72
Max. RAM Bits 18,432
Number of IOBs 192
Horizontal Longlines 48
TBUFs per Longlines 26
PROM Size (bits) 247,96
Features
28
Abundant flip-flops
Flexible function generators
Dedicated high-speed carry-propagation circuit
Wide edge decoders (four per edge)
Hierarchy of interconnect lines
Internal 3-state bus capability
8 global low-skew clock or signal distribution network
Flexible Array Architecture
Programmable logic blocks and I/O blocks
Programmable interconnects and wide decoders
Sub-micron CMOS Process
High-speed logic and Interconnect
Low power consumption
Systems-Oriented Features
IEEE 1149.1-compatible boundary scan logic support
Programmable output slew rate (2 modes)
Programmable input pull-up or pull-down resistors
12-mA sink current per output
24-mA sink current per output pair
The XC4000E family is supported by powerful and sophisticated software, covering every aspect
of design from schematic or behavioral entry, floorplanning, simulation, automatic block
placement and routing of interconnects, to the creation, downloading, and readback of the
29
configura-tion bit stream. The Xilinx XC4000E family includes three major configurable
elements: configurable logic blocks (CLBs), input/output blocks, and interconnects. The CLBs
provide the functional elements for constructing user's logic. The IOBs provide the interface
between the package pins and internal signal lines. The programmable interconnect resources
provide routing paths to connect the inputs and outputs of the CLBs and IOBs onto the
appropriate networks. Customized configuration is established by programming internal static
memory cells that determine the logic functions and internal connections implemented in the
FPGA.
Specifications
Device XC4013E
Aproximate Gate Count 13,000
CLB Matrix 24 x 24
Number of CLBs 567
Number of Flip-Flops 1,536
Max. Decode Inputs per Side 72
Max. RAM Bits 18,432
Number of IOBs 192
Horizontal Longlines 48
TBUFs per Longlines 26
PROM Size (bits) 247,960
The principle CLB elements are shown in Figure . Each CLB contains a pair of flip-flops and
two independent 4-input function generators. These function generators have a good deal of
flexabilty as most combinatorial logic functions need less than four inputs. Thirteen CLB inputs
and four CLB outputs provide access to the functional flip-flops. Configurable Logic Blocks
implement most of the logic in an FPGA. The principal CLB elements are shown in Figure 1.
Two 4-input function generators (F and G) offer unre-stricted versatility. Most combinatorial
logic functions need four or fewer inputs. However, a third function generator (H) is provided.
The H function generator has three inputs. One or both of these inputs can be the outputs of F
and G; the other input(s) are from outside the CLB. The CLB can therefore implement certain
functions of up to nine variables, like parity check or expandable-identity comparison of two sets
of four inputs.
30
Figure Block Diagram of XC4000 Families Configuration Logic Block (CLB)
Each CLB contains two flip-flops that can be used to store the function generator outputs.
However, the flip-flops and function generators can also be used independently. DIN can be used
as a direct input to either of the two flip-flops. H1 can drive the other flip-flop through the H
function gen-erator. Function generator outputs can also be accessed from outside the CLB,
using two outputs independent of the flip-flop outputs. This versatility increases logic density
and simplifies routing. Thirteen CLB inputs and four CLB outputs provide access to the function
generators and flip-flops. These inputs and outputs connect to the programmable interconnect
resources outside the block.
5. 10 HDL LANGUAGE
Advances in semiconductor technology continue to increase the power and complexity of digital
systems. To design such systems requires a strong knowledge of Application Specific Integrated
Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs), as well as the CAD tools
required. Hardware Description Language (HDL) is an essential CAD tool that offers designers
31
an efficient way for implementing and synthesizing the design on a chip. HDL Programming
Fundamentals: VHDL and Verilog teaches students the essentials of HDL and the functionality
of the digital components of a system. Unlike other texts, this book covers both IEEE
standardized HDL languages: VHDL and Verilog. Both of these languages are widely used in
industry and academia and have similar logic, but are different in style and syntax. By learning
both languages students will be able to adapt to either one, or implement mixed language
environments, which are gaining momentum as they combine the best features of the two
languages in the same project. The text starts with the basic concepts of HDL, and covers the key
topics such as data flow modeling, behavioral modeling, gate-level modeling, and advanced
programming. Several comprehensive projects are included to show HDL in practical
application, including examples of digital logic design, computer architecture, modern
bioengineering, and simulation.
Digital circuits consist primarily of interconnected transistors. We design and analyze these
circuits with the aid of a hierarchical structure: we could, in theory, interpret a central processing
unit (CPU) as a vast sea of transistors, but it is much easier to organize transistors into logic
gates, logic gates into adders or registers or timing modules, registers into memory banks, and so
forth.
To describe digital circuits, textual language is used that is specifically intended to clearly and
concisely capture the defining features of digital design.
Such languages are called hardware description languages (HDLs).
The most popular hardware description languages are Verilog and VHDL. They are widely used
in conjunction with FPGAs, which are digital devices that are specifically designed to facilitate
the creation of customized digital circuits.
Hardware description languages allow you to describe a circuit using words and symbols, and
then development software can convert that textual description into configuration data that is
loaded into the FPGA in order to implement the desired functionality.
entity Circuit_1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
out1 : out STD_LOGIC);
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end Circuit_1;
-----------------------------------------------------
architecture Behavioral of Circuit_1 is
begin
out1 <= ( a and b );
end Behavioral;
entity HALF_ADDER is
port (A, B: in BIT;
SUM, CARRY: out BIT);
end HALF_ADDER;
33
5.11 overview of Spartan 3E
The XA Spartan®-3E FPGA is the world’s lowest cost logic optimized full feature platform of
five devices with system gates ranging from 100K to 1.6M gates, and I/Os ranging from 66 to
376 I/Os, with density migration.
The Spartan®-3 Generation of FPGAs offers a choice of five platforms, each delivering a unique
cost-optimized balance of programmable logic, connectivity, and dedicated hard IP for your low-
cost applications.
o For applications where integrated DSP MACs and expanded memory are required
o Ideal for designs requiring low cost FPGAs for signal processing applications
such as military radio, surveillance cameras, medical imaging, etc.
Spartan-3AN – Non-volatile
34
o For applications where non-volatile, system integration, security, large user flash
are required
o For applications where I/O count and capabilities matter more than logic density
o For applications where logic densities matter more than I/O count
o Ideal for logic integration, DSP co-processing and embedded control, requiring
significant processing and narrow or few interfaces
o For applications where both high logic density and high I/O count are important
The target EHW is implemented as an OPB slave peripheral module – see Fig. 2. Interfacing
with the OPB bus has been simplified by the use of a Xilinx IP Interface core (IPIF). This
35
provides a simpler interface standard, the Xilinx IPIC, for the user module.Control and
configuration of this module are undertaken through register write operations. Genome values
are written to registers which are again connected to the configuration inputs of the functional
unit array. Registers are also
The functional unit array (FUA) is a general structure used for EHW. It is based on the principle
that the configuration of the FPGA itself is not changed, but a virtual circuit which is
implemented on top of it can be reconfigured. Hence the names ”Virtual FPGA” or ”Virtual
Reconfigurable Circuit
Our FUA consists of a fixed-size array of functional units. The array consists of C columns of R
units from input to output. Each unit has I inputs, each of which can be connected to any output
in the previous column. The unit’s output is a result of any of F functions. The function of each
unit and its inputs are configurable. They are determined by evolution, in the way that each
individual’s binary genome is sent to the FUA and mapped to the configuration lines. Fitness is
then calculated by feeding a number of input vectors on the inputs of the first column, and
reading the results from the outputs of the last column. The array is constructed in a pipelined
36
fashion, that is, registers are connected to the outputs of each layer. Currently, this is not
exploited for fitness evaluation. Only one input vector is evaluated at a time.
Table Functions used by units in the image recognition task. Inputs are A and B, ouput is O. C1
and C2 are constants available to each unit.
37
2 mark questions and answers.
1. What is FPGA?
Field Programmable Gate Arrays (FPGAs) are digital Integrated Circuit that enable the
hardware design engineer to program a customized Digital Logic as per requirements.
2. What is CPLD?
CPLD is an integrated circuit that helps to implement digital systems whereas FPGA is an
integrated circuit designed to be configured by a customer or a designer after manufacturing.
4. What is CLB ?
A configurable logic block (CLB) is the basic repeating logic resource on an FPGA.
When linked together by routing resources, the components in CLBs execute complex
logic functions, implement memory functions, and synchronize code on the FPGA.
5. What is PIP in FPGA?
Transmission Gates connects to two wire segments.
0- Wire disconnected
1- Wire connected
The Xilinx XC4000E family includes three major configurable elements: configurable
logic blocks (CLBs), input/output blocks, and interconnects. The CLBs provide the
functional elements for constructing user's logic. The IOBs provide the interface between the
package pins and internal signal lines.
7. What is HDL?
Digital circuits consist primarily of interconnected transistors. We design and analyze
these circuits with the aid of a hierarchical structure: we could, in theory, interpret a
central processing unit (CPU) as a vast sea of transistors, but it is much easier to organize
38
transistors into logic gates, logic gates into adders or registers or timing modules,
registers into memory banks, and so forth..
Another way to describe digital circuits is to use a textual language that is specifically intended
to clearly and concisely capture the defining features of digital design.
Such languages exist, and they are called hardware description languages (HDLs).
The most popular hardware description languages are Verilog and VHDL. They are
widely used in conjunction with FPGAs, which are digital devices that are specifically
designed to facilitate the creation of customized digital circuits.
The Spartan-3 Generation of FPGAs offers a choice of five platforms, each delivering a
unique cost-optimized balance of programmable logic, connectivity, and dedicated hard
IP for your low-cost applications.
1. VHLD, 2 Verilog
. Both of these languages are widely used in industry and academia and have similar
logic, but are different in style and syntax.
13. What is minimum and maximum frequency of dcm in spartan-3 series fpga?
Spartan series dcm’s have a minimum frequency of 24 MHZ and a maximum of 248.
The modes are Master Parallel, Slave Parallel, Master Serial, Slave Serial, and Boundary
Scan.
39
10 mark questions
1. Write about some of features of FPGA which are are currently used.
40