Automotive FET Driver For 3 Phase BLDC Motor: Features

L9907
Automotive FET driver for 3 phase BLDC motor
Datasheet - production data
Protection and diagnostic

 Gate to source output voltage limit
 Gate to source passive switch off
 FET driver supply UV diagnostic
 OV, UV diagnostic and protection on VB and
TQFP64 (exposed pad down) VCC
GAPGPS00129  External MOSFET overcurrent protection
 Over-temperature diagnostic and shutdown
Features
Applications
 AEC-Q100 qualified
 Electric power steering
 Supply voltage from 4.2 V to 54 V
 Electric brake booster
 The device can withstand -7 V to 90 V at the
 Generic brushless DC motor driving
FET high-side Driver pins
 Low standby current consumption
Description
 Compatible with 3.3 V and 5 V Logic Level
L9907 is a gate driver unit controlling 6 N-channel
 All logic pins withstand 35 V
FETs for brushless DC motors in automotive
 Boost regulator for full Rdson down to 6 V applications.
battery voltage
Each pre-driver channel can be controlled
 3 low-side + 3 high-side independent gate independently allowing the implementation of all
drivers kinds of electric motor control strategy.
 PWM operation up to 20 kHz
The base gate output current is set via an
 Adjustable gate driver controlled current up to external resistor, while via SPI it is possible to
600 mA select among 4 gate output current levels even
 2 programmable differential current sense when the application is running.
amplifiers L9907 is equipped with 2 current sense amplifiers
 8 MHz, 16-bit SPI interface with configurable mode, gain and offset to
 Programmable parameters: guarantee maximum flexibility for phase or
ground current sense strategy.
– Cross conduction dead time
– External MOSFET gate current level Full diagnostic is available through SPI.
– Current sense amplifier mode, offset and
gain Table 1. Device summary
– Input over voltage threshold Order code Package Packing
– Short circuit detection L9907 Tray
TQFP64
L9907TR (10x10x1.0 mm) Tape & reel
April 2021 DS11800 Rev 5 1/49

This is information on a product in full production. www.st.com
Contents L9907
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Power supply VB, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Voltage regulator VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 EN1 and EN2 pins (ENABLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.4.1 BstDis (boost disable) function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5 MOSFET drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.1 GCR pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.2 Shoot through protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.3 Drain source monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6 Current Sense Amplifier (CSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7 System clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.8 General SPI usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.9 Device and FET fault handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.9.1 SPI and PWM faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 Maximum operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Temperature ranges and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5.1 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5.2 Voltage regulator VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5.3 Logic input pins (PWM_H1 to 3, PWM_L1 to 3, SCK, CS, SDI, BST_DIS,
EN1 and EN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5.4 Logic output pins (FS_FLAG, SDO, TO3) . . . . . . . . . . . . . . . . . . . . . . . 22
3.5.5 Boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5.6 MOSFET drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/49 DS11800 Rev 5

L9907 Contents
3.5.7 Current sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4 SPI operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1 SPI bits mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.1 SDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1 12 V/24 V system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2 48 V system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.3 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.1 TQFP64 (10x10x1 mm exp. pad down) package mechanical data . . . . . 45
6.1.1 TQFP64 exposed pad dimensions for L9907 . . . . . . . . . . . . . . . . . . . . 47
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
DS11800 Rev 5 3/49

3
List of tables L9907
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Offset bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Gain bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. System clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Device and FET fault handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. SPI and PWM faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Maximum operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 11. Temperature ranges and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 12. Supply electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 13. Voltage regulator VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14. Logic I/O pins electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. Logic output pins (FS_FLAG, SDO, TO3) electrical characteristics . . . . . . . . . . . . . . . . . . 22
Table 16. Boost converter electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 17. MOSFET drivers electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 18. External MOSFET overcurrent drop voltage sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 19. Gate voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 20. Phase current sense amplifier (SPI select: Offx=1, where x=1,2) . . . . . . . . . . . . . . . . . . . 25
Table 21. Ground current sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 22. SPI timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 23. SDI bit map definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 24. SDI frame structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 25. Dead time parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 26. Turn on/off current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 27. Current sense amplifier 2 gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 28. Current sense amplifier 1 gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 29. Short circuit detection threshold for low-side external MOSFET . . . . . . . . . . . . . . . . . . . . 32
Table 30. Short circuit detection threshold for low-side external MOSFET . . . . . . . . . . . . . . . . . . . . 33
Table 31. VB over voltage threshold for single or double battery application . . . . . . . . . . . . . . . . . . . 33
Table 32. CMD1 SDI SPI bits vs. enabled fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 33. VCC over voltage threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 34. Current sense amplifier input offset calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 35. CMD4 SDI SPI bits vs. enabled fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 36. SDO bit map definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 37. Application circuit - BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 38. TQFP64 (10x10x1 mm exp. pad down) package mechanical data . . . . . . . . . . . . . . . . . . 46
Table 39. TQFP64 exposed pad dimensions for L9907 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 40. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4/49 DS11800 Rev 5

L9907 List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Pin connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. MOSFET drivers supply structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Case of T_BOOST_OFF < T_BOOST_OFF_MAX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Case of T_BOOST_OFF > T_BOOST_OFF_MAX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. CSA simplified circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Timing diagram for the SPI operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 8. Application circuit, 12 V/24 V system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 9. Application circuit, 48 V system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 10. TQFP64 (10x10x1 mm exp. pad down) package mechanical drawing. . . . . . . . . . . . . . . . 45
DS11800 Rev 5 5/49

5
Block diagram and pin description L9907
1 Block diagram and pin description
1.1 Block diagram

Figure 1. Block diagram
Vcc
(5V or 3.3V) VC BST_C BST_L
VB
3.3V Boost
VDH
Vdd Vreg regulator
(3.3V)
BGND
CBS1
PWM H1
PWM L1
GHS1
PWM H2
PWM L2
Logic SHS1
PWM H3
PWM L3
EN1
GLS1
EN2
BST_DIS
SLS1
Half bridge driver 1
CBS2
FS FLAG GHS2
H bridge driver 2
Half SHS2
GLS2
SDI SLS2
CBS3
CS SPI
GHS3
SCK Half bridge driver 3 SHS3
GLS3
SDO SLS3
Gat charge current set
Gate
GCR
TM 100 / 75 / 50 / 25%
TO3 Overvolt. IS1+

Undervolt.
IS1-
Overtemp.
IB1 IS2+
IB2 IS2-
AGND DGND SGND1 SGND2

GAPGPS00833
6/49 DS11800 Rev 5

L9907 Block diagram and pin description
1.2 Pin description

Figure 2. Pin connection diagram
BST_DI
BST_C
BST_L
DGND
BGND
VCAP
GCR
VDH
VDD
VCC
NC
NC
NC
NC
NC
VB
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
NC 1 48 SGND1
GLS_3 2 47 PWM_L3
SLS_3 3 46 PWM_L2
NC 4 45 PWM_L1
GLS_2 5 44 EN1
SLS_2 6 43 EN2
NC 7 42 TO3
GLS_1 8 41 SDO
SLS_1 9 40 SDI
AGND 10 39 SCK
IS1+ 11 38 CS
IS1- 12 37 FS_FLAG
NC 13 36 PWM_H3
IB1 14 35 PWM_H2
IB2 15 34 PWM_H1
SGND2 16 33 TM
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
17 IS2-
IS2+
NC
CBS_3
GHS_3
SHS_3
NC
CBS_2
GHS_2
SHS_2
NC
CBS_1
GHS_1
SHS_1
NC
NC GAPGPS00834
Table 2. Pin function

Pin # Pin name Description I/O Type
1 NC NC -
2 GLS_3 Gate connection for low-side MOSFET, phase 3 O
3 SLS_3 Source connection for low-side MOSFET, phase 3 I
4 NC NC -
7 NC NC -
10 AGND Analog ground GND
11 IS1+ Positive input for current sense amplifier 1 I
12 IS1- Negative input for current sense amplifier 1 I
13 NC NC -
14 IB1 Output for current sense amplifier 1 (Test mode digital output #1) O
15 IB2 Output for current sense amplifier 2 (Test mode digital output #2) O
16 SGND2 Substrate (and ESD_GND) connection 2 GND
DS11800 Rev 5 7/49

48
Block diagram and pin description L9907
Table 2. Pin function (continued)

17 IS2- Negative input for current sense amplifier 2 I

18 IS2+ Positive input for current sense amplifier 2 i
19 NC NC -
20 CBS_3 Bootstrap capacitor for high-side MOSFET, phase 3 I
21 GHS_3 Gate connection for high-side MOSFET, phase 3 O
22 SHS_3 Source connection for high-side MOSFET, phase 3 I
23 NC NC -
27 NC NC -
31 NC NC -
32 NC NC -
(1)
33 TM Test mode enable input I
34 PWM_H1 PWM command input for high-side phase 1 I
37 FS_FLAG Fault status flag output O
38 CS SPI chip select input I
39 SCK SPI serial clock input I
40 SDI SPI Serial data input I
41 SDO SPI serial data output O
42 TO3 Test output O
43 EN2 Enable Input 2 (ANDed with EN1 to enable any gate drive output). I
44 EN1 Enable Input 1 (ANDed with EN2 to enable any gate drive output). I
45 PWM_L1 PWM command input for low-side phase 1 I
48 SGND1 Substrate (and ESD_GND) connection 1 GND
49 Vcc 5 V / 3.3 V power supply input I
50 NC NC -
51 GCR Connection to resistor for current selection of gate driver O
8/49 DS11800 Rev 5

L9907 Block diagram and pin description
Table 2. Pin function (continued)

52 Vdd 3.3 V power supply output (for IC internal purpose only) O

53 DGND Digital ground GND
54 VB Protected battery monitor I
55 NC NC -
56 BST_L Boost regulator inductance connection O
57 BGND Boost ground GND
58 BST_DIS Boost disable I
59 NC NC -
60 BST_C Boost regulator capacitance connection I
61 NC NC -
62 VCAP Decoupling capacitor for power supply of low-side drivers I
63 NC NC -
64 VDH High-side drain voltage sense I
1. TM pin has to be connected to ground in the application.
DS11800 Rev 5 9/49

48
Functional description L9907
2 Functional description
2.1 Power supply VB, VCC

Voltage present at VB and VCC pins is monitored in order to inhibit driver and/or boost
functionality in case of under/over voltage detection. A VCC over voltage self test is
embedded for safety integrity check: VCC over voltage threshold can be reduced on
purpose to a level that is always triggered with nominal values on VCC rail. The device is
self protected in case of ground disconnections versus both SGNDx pins. SGND1 and
SGND2 pins are internally shorted and connected to substrate: at least one of these pins
must be connected to board ground. In case of AGND loss, a dedicated comparator will lead
to a POR state for logic, where boost regulator and MOSFET drivers are disabled. This fault
doesn't set any SPI error bit. In case of DGND loss the device is automatically disabled:
MOSFET drivers go in tri-state condition and external FETs are kept off using integrate
passive pull down. In case of BGND ground loss the boost regulator cannot work properly:
the effect is an undervoltage on HS and/or LS side gate voltage monitor.
The ground reference for all the voltages and thresholds available in the device is AGND.
The Exposed Pad (EP) is mainly used for thermal dissipation. It should be grounded and
connected together with SGNDx pins.
2.2 Voltage regulator VDD

The internal 3.3 V voltage regulator is used to supply the internal logic and all internal
blocks. For stability reasons a 100 nF capacitor has to be connected to VDD pin. This
regulator is to be intended for IC internal use only. Suggested limits for external capacitor
are min = 100 nF -20% ma x= 220 nF +20%. All tests are performed with a 100 nF capacitor,
unless otherwise specified.
2.3 EN1 and EN2 pins (ENABLE)

To enable the gate driver functionality EN1 and EN2 have to be pulled high. These pins are
by default internally logically ANDed. In case REGOFF_EN bit in CMD4 SPI frame is set to
1 (refer to SPI mapping,Table 23), EN1 and EN2 have different meanings: EN2 stays the
same as a gate driver functionality enabler, while EN1 will also become an enabler for all the
regulators supplying the pre-driver circuitries. In this way, EN1 becomes a safety control pin
that implements an additional switch-off path.
These pins are also used to enable the SPI write to CMD1 and CMD4. These registers
contain gate driver sensitive to failure management bits which just can be written when at
least one of the ENx pins is pulled low (gate driver disabled).
Nevertheless the pins are used as well to reactivate the gate driver in case of device internal
switch off. Therefore a low cycle of at least 3µs has to be applied after fault condition is
removed to one or both of the ENx pins.
On both pins internal pull down currents are implemented.
10/49 DS11800 Rev 5

L9907 Functional description
2.4 Boost converter

The purpose of the Boost converter is to generate a voltage around 10 V higher than the
one present at VDH monitor pin. This voltage is used to supply HS drivers (through
dedicated regulators) and LS drivers (through VCAP regulator). The regulated voltage is
present at BST_C pin. BST_L pin is the drain of an integrated NDMOS switch. VCAP
regulator is a current limited voltage regulator, fed by Boost and referred to SLS3 voltage,
used to supply LS drivers. Each HS driver has a current limited voltage regulator that is fed
by Boost, referred to SHSx pins and with regulated voltage present at CBSx pins. These
regulators limit VGS of the external FETs. Overvoltage at BST_C pin (e.g. due to low current
demand) is limited by skipping turn on pulses until over voltage condition is removed. A
fixed voltage threshold on BST_C is implemented, in order to avoid the boost voltage
exceeding a safety level in case of high voltage on VDH monitor pin. In case the user would
not need this over voltage protection (e.g. for applications where high voltage is present on
the VDH rail), L9907 provides a disabling bit in CMD3 SPI command (DIS_BSTov). The
Boost converter is disabled in case of validated Fault (see Table 6) and reactivated by fault
removal and cleared after SPI reading.
Figure 3. MOSFET drivers supply structure

VCAP BST_C
CBS1
V-reg V-reg
GHS1
SHS1
HS-Gate-Driver 1
GLS1
SLS1
LS-Gate-Driver 1
CBS2
V-reg
GHS2
SHS2
HS-Gate-Driver 2
GLS2
SLS2
LS-Gate-Driver 2
CBS3
V-reg
GHS3
SHS3
HS-Gate-Driver 3
GLS3
SLS3
LS-Gate-Driver 3
GAPGPS00835
DS11800 Rev 5 11/49

48
In case Boost converter is disabled, but voltage at BST_C pin is present, Current Sense
Amplifiers are active but with degraded performances at least in common mode dynamic
range. In order to improve EMC behaviour an external RC series snubber can be added
between BST_L and BGND pins. RC~1/(6.28*fSW_BST).
2.4.1 BstDis (boost disable) function

In case noise-free CSA measuring is needed, a special functionality that temporarily
disables Boost regulator is implemented, with the purpose to reduce PCB coupling between
CSA output and boost PCB metal stripes that can act as antennas. Once BST_DIS pin is
asserted, boost regulator is disabled starting from the next complete boost cycle (maximum
delay T_BOOST_OFF_FILT).
Boost is re-enabled in two ways:
 internal timer expired (T_BOOST_OFF_MAX time is reached)
 BstDis pin deasserted
In both cases boost starts working again from the beginning of the next complete boost
cycle.
T_BOOST_OFF_MAX = 6*TBOOST = 96*TCK
T_BOOST_OFF_FILT = 3*TCK min, 21*TCK max
Figure 4. Case of T_BOOST_OFF < T_BOOST_OFF_MAX

Internal boost control
signal generated by
logic and internal oscillator
BOOST DIS PIN
BOOST CLK MASK
BOOST CLK
21*TCK MAX =
5*TCK filter +
1BOOST period GAPGPS00836
Figure 5. Case of T_BOOST_OFF > T_BOOST_OFF_MAX
Internal sync signal
BOOST DIS PIN
BOOST CLK MASK
BOOST CLK
T_BOOST_OFF_MAX =
96*TCK = 6 BOOST periods
GAPGPS00837
12/49 DS11800 Rev 5

When BST_DIS_EN bit of CMD2 SPI frame is set to 1 (refer to SPI mapping, Table 23),
BST_DIS becomes a full-time control of the boost operation: the boost will be disabled as
long as the BST_DIS pin is high. This implements a boost permanent disabler that can be
used for different reasons, e.g. to allow more precise and less noisy measurements, to
decrease power dissipation or current load on battery in all conditions when the boost is not
strictly necessary.
2.5 MOSFET drivers

MOSFET drivers are programmable current mirrors used to limit gate charge/discharge
current without gate series resistors (which can be used anyway). Programmability has two
degrees of freedom: SPI programmability (25, 50, 75, 100% of max. available current IG) for
MOSFET gate current adjustment during running application and via external resistor at
GCR pin to adjust the gate current among different applications. External MOSFETs are
protected against over current in on-state monitoring their Vds voltage. Maximum Vgs of
external MOSFETs is limited using VCAP regulator for LS drivers and dedicated floating
regulators referred to sources for HS drivers.
2.5.1 GCR pin

At GCR pin a resistor has to be connected which defines in combination with the IGx SPI
bits the gate current for charge and discharge.
Minimum value for GCR resistor is GCR(min) = 1 kΩ- 10% (maximum allowable gate
current), maximum is GCR(max) = 22 kΩ +10% (minimum allowable gate current), but with
degraded precision performances with GCR > 6 kΩ+ 10%. Tested values are GCR = 1 kΩ
and GCR = 6 kΩ
GCR pin circuitry implements an open/short protection in case of a too high/low resistive
load connected to it. If one of the above conditions occurs, the device switches to an
internally generated current, equivalent to approximately 15 k. The current reference can
be switched to the internal reference by using the GCR_INT_I bit of CMD2 frame (refer to
SPI mapping, Table 23); this can be used when a reduced power dissipation is needed.
2.5.2 Shoot through protection

Shoot through protection's aim is to avoid destructive cross current conduction between
high-side and low-side FETs of the same phase in case of unwanted condition when
PWM_Hx and PWM_Lx signals are set to logic '1' at the same time (e.g. because of a
controller fault). With every activation of either PWM_Hx or PWM_Lx the cross current
protection time is activated and switches off the corresponding half bridge for the
programmed Dead time. The shoot through condition is validated via an up-down counter
which is proportional to the programmed dead time. With this feature, continuous activation
of HS and LS and also high frequency oscillations of the PWMx input signals (HS and LS)
are detected and the shoot through failure state is set. If the fault condition is validated, all
external FETs are switched OFF and FS_FLAG is asserted low. No SPI SDO diagnostic bit
is set, since the hypothesis is that the controller is not able to work properly. In case the
SHT_PH bit of CMD2 SPI frame would be set to 1 (refer to SPI mapping, Table 23), the
device allows the switching off of the only phase for which the shoot through occurred. The
phase that experienced the fault is reported on DIAG2 SPI frame (SDO bits B<2:0>). In
order to re-enable FET pre-drivers, at least one Enable signal EN1 or EN2 must be toggled.
DS11800 Rev 5 13/49

48
In order to unlatch also FS_FLAG status a SPI communication with diagnostic frame must
be performed.
2.5.3 Drain source monitoring

To monitor the external MOSFET a Drain Source monitoring for all HS and LS is
implemented. In case the drain source voltage exceeds a certain threshold (e.g. MOSFET
short) during gate ON mode, all drivers will be disabled and the fail will be reported via
FS_FLAG and SPI. In case the ShortPH bit of CMD2 SPI frame would be set to 1 (refer to
SPI mapping, Table 23), the device allows the switching off of the only phase for which the
drain-source short occurred.
2.6 Current Sense Amplifier (CSA)

L9907 is equipped with two SPI-programmable Current Sense Amplifiers to measure the
motor current by converting and amplifying the voltage drop across an external shunt
resistor. A simplified CSA circuit diagram is showed in Figure 6.
Figure 6. CSA simplified circuit diagram

100*RG SG4
50*R SG3
G
30*RG SG2
10*RG SG1
RG
ISx-
IBx
VIsx+-VIsx-
ISx+
RG
SG1 SG2 SG3 SG4
VCC
10*RG 30*RG 50*RG 100*RG
ROFS
SOFS1 SOFS2
0.25*ROFS ROFS
Each CSA can be used for phase (bidirectional) or ground (unidirectional) current
monitoring by properly selecting the output zero-current offset via dedicated bits in the SPI
register CMD0; Off1 for CSA1 and Off2 for CSA2.
14/49 DS11800 Rev 5

Table 3. Offset bit configuration

Offx SOFS1 SOFS2 Output Offset
0 Open Closed 20% VCC

1 Closed Open 50% VCC
The gain of each CSA can be independently configured selecting between four different
values via dedicated bits in the SPI register CMD0; G10, G11 for CSA1 and G20, G21 for
CSA2.
Table 4. Gain bit configuration

Gx1 Gx0 SG1 SG2 SG3 SG4 Gain
0 0 Closed Open Open Open 10

0 1 Closed Closed Open Open 30
1 0 Open Open Closed Open 50
1 1 Open Open Open Closed 100
Current Sense Amplifier is active if IC is active (VCC and VDD present and within spec
range), despite the EN status. In case Boost converter is disabled, but voltage at BST_C pin
is present, Current Sense Amplifiers work but with degraded performances at least in
common mode dynamic range.
2.7 System clock

Table 5. System clock frequency
Symbol Parameter Min Typ Max Unit
CLK_freq System Clock Frequency - 5.6 - MHz
2.8 General SPI usage

For device programmability a four-wire SPI is used. The device acts as SPI slave. Data will
be latched on the negative clock edge and shifted out on the positive edge (µC setting:
CPHA =1; CPOL = 0).
To perform an SPI write the WE bit has to be set and a correct ODD parity bit has to be
written.
A data read out is always performed on the following SPI frame (after power-up CMD0 is
read). That means sending data to a certain register will lead to shift out the content of the
addressed register in the following SPI frame. In case of wrong SPI communication (e.g.
due to stuck at 0 or at 1 of SDI) the current command is rejected and an error message
(0xB001) is presented as SDO response at the following SPI cycle.
DS11800 Rev 5 15/49

48
2.9 Device and FET fault handling

All internal fault events are filtered to achieve noise immunity. After filter-time they are
latched in the corresponding SPI register and the FS_FLAG (active low) becomes low. In
case the related driver-disable-bit (EN_x) is set, additionally the gate driver will be disabled
and actively discharged (see: Fault Effect enabling; Table 35 and 32). In case EN_x is
disabled the µC takes fully response to react on any errors immediately indicated by the
FS_FLAG. Neither the boost nor the FET drivers will be disabled on deselected faults.
Table 6. Device and FET fault handling

Device action when
Fault Diagnosis Exit from fault condition
EN_x enabled
– Remove fault => auto recovery

FS_FLAG = low; FET driver functionality
Overtemperature – SPI read clears the Fault Flags and
THSD SPI bit set disabled
sets FS_FLAG to high
– Remove fault => auto recovery of
FS_FLAG = low; Boost
VB or VCC over- or VBOV or VBUV or FET driver functionality – EN cycling toggle reactivates the FET
undervoltage VCCOV or VCCUV SPI and Boost disabled driver
bit set – SPI read clears the Fault Flags and
– Remove fault
FS_FLAG = low; – EN cycling toggle reactivates the FET
Boost HS or LS FET driver functionality
UV_HS or UV_LS SPI driver
undervoltage disabled
bit set – SPI read clears the Fault Flags and
– Remove fault
VSC_HSx FET driver functionality
driver
overcurrent VSC_HSx SPI bit set disabled
– SPI read clears the Fault Flags and
– Remove fault
VSC_LSx FET driver functionality
driver
overcurrent VSC_LSx SPI bit set disabled
– SPI read clears the Fault Flags and
16/49 DS11800 Rev 5

2.9.1 SPI and PWM faults
Table 7. SPI and PWM faults

Fault Diagnosis Device Action Exit from Fault Condition
SPI Error (wrong

address access; SPI_Error bit set and Faulty SPI frame is
-
parity error; SCK 0xB001 return frame ignored
count error)
– Remove fault
PWM_Hx and
FET driver functionality – EN cycling toggle reactivates the FET
PWM_Lx shoot FS_FLAG = low;
disabled driver
through protection
– SPI read sets FS_FLAG to high
DS11800 Rev 5 17/49

48
Electrical specifications L9907
3 Electrical specifications
3.1 Maximum operating ranges

The device may not operate properly if the maximum operating condition is exceeded.
Table 8. Maximum operating conditions

Symbol Parameter Value Unit
VB Protected battery monitor voltage 4.2 to 54(1) V

VCC 5 V / 3.3 V power supply 3 to 5.5 V
VDH High-side drain voltage sense 4.2 to 54(1) (2) V
(1) (3)
SHS_1 to 3 High-side source voltage -7 to 54 V
ISxx Current sense amplifier input pin voltage -2 to VDH +4(4) V
1. Maximum operating voltage is 75 V in dynamic conditions.
2. VDH maximum operating voltage range is limited by V(BST_C)-15 V.
3. SHS maximum operating voltage range is limited by V(CBSxmax)-15 V.
4. Maximum operating voltage is VDH +20 V in dynamic conditions.
3.2 Absolute maximum ratings

Maximum ratings are absolute ratings; exceeding any one of these values may cause
permanent damage to the integrated circuit.
Table 9. Absolute maximum ratings

Parameter Pin Min Max Unit
-0.3 75 V
Monitor supply pin VB
-10 +10 mA
-0.3 90 V
BST_C
-100 100 mA
-0.3 90 V
BST_L
-100 100 mA
-0.3 35 V
Power supply pins Vcc
-10 25 mA
-0.3 4.6 V
Vdd
-10 15 mA
-0.3 20 V
VCAP
-100 100 mA
Miscellaneous Analog/Digital input PWM_H1 to 3, PWM_L1 to 3, EN1, -0.3 35 V
pins EN2, BST_DIS,TM, CS, SCK, SDI -100 100 mA
Miscellaneous Analog/Digital output -0.3 35(1) V
IB1, IB2, FS_FLAG, SDO, TO3
pins -100 100 mA
18/49 DS11800 Rev 5

L9907 Electrical specifications
Table 9. Absolute maximum ratings (continued)

Parameter Pin Min Max Unit
-0.3 4.6 V
Gate current selection pin GCR
-10 +10 mA
-7 75 V
Current sense amplifier pins IS1+,IS1-,IS2+,IS2-
-10 10 mA
Differential voltage between ISx +/- Abs |ISx+ - ISx-| - 15 V
-4 75 V
High-side drain sense VDH
-10 10 mA
HS Bootstrap Cap pins: CBS_1 to 3 -0.3 90 V
Differential gate to source HS pins:
-0.3 20 V
FET-driver pins V(GHS_x) - V(SHS_x), x = 1 to 3(2)
Source HS pins: SHS_1 to 3 -7 75 V
Source LS pins: SLS_1 to 3 -7 10 V
Differential gate to source LS pins:
FET driver pins -0.3 20 V
V(GLS_x) - V(SLS_x), x = 1 to 3(2)
Current sense amplifier differential
BST_C-ISxx -0.3 90 V
voltage
BGND and DGND -0.3 4.6 V
GND pins
AGND and EP -0.3 0.3 V
1. In standard battery level application (12 V systems) the I/O pins and Vcc pin can stand a short to battery up
to 35 V. A short to 35 V battery on any output pin also forces the Vcc to approximately 35 V. Care must be
taken in order to avoid that under such conditions the Vcc pin is strongly pulled down to 5 V (or 3.3 V) with
a current exceeding the absolute maximum ratings level.
2. Negative AMR is -0.3 V or -20 mA.
3.3 ESD protection

Table 10. ESD protection
Parameter Condition Min Max Unit
Logic and power pins Human body model -2 2 kV

FET driver pins Human body model -2 2 kV
All pins but corner pins Charge device model -250 250 V
Corner pins Charge device model -750 750 V
HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114_A. HBM with all
unzapped pins grounded.
DS11800 Rev 5 19/49

48
3.4 Temperature ranges and thermal data

Table 11. Temperature ranges and thermal data
Symbol Parameter Min Max Unit
Operating junction temperature -40 150 °C

Tj
100 hours over lifetime temperature (1) - 175 °C
Tstg Storage temperature -55 150 °C
Tot Thermal shutdown temperature 175 205 °C
(2)
Thys Thermal shutdown temperature hysteresis 10 - °C
Rth j-amb Thermal resistance junction-to-ambient (3) - 23 °C/W
Rth j-case Thermal resistance junction-to-case - 3 °C/W
1. Functionality is guaranteed, the specified limits may be exceeded.
2. Guaranteed by design.
3. IC soldered on 2s2p PCB thermally enhanced.
3.5 Electrical characteristics

All voltages referred to ground (SGNDx ground) and currents are assumed to be positive
when current flows into the pin.
3.5.1 Supply
The device is operated in the specified operating range, unless otherwise specified
(VCC = 3.20 V to 5.25 V, VB = 4.2 V to 54 V, Tj = -40 °C to 150 °C).
Table 12. Supply electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit
VB Operating supply voltage range - 4.2 - 54 V
Overvoltage threshold for double

VB OV_1 VBOV2,VBOV1= 01 36 - 42 V
battery applications (L9907)
Overvoltage threshold for single

VB OV_2 VBOV2,VBOV1= 10 27.5 31 34.5 V
battery application
Overvoltage time delay for noise

Td VB (guaranteed through scan) 30 - 80 µs
rejection
VB UV Undervoltage disable threshold - 4.2 4.6 5 V
Undervoltage time delay for noise

Td UV (guaranteed through scan) 30 - 80 µs
rejection
VB= 13V, Vcc < 0.5 V, room

IVB(dis) Supply current - 1 10 µA
temperature
20/49 DS11800 Rev 5

Table 12. Supply electrical characteristics (continued)

VB= 13V, Vcc= 3.3V, open

IVB - - 10 mA
VB supply current outputs, fPWM =0
IBST_C VB = 13 V, drivers off, boost off - - 10 mA
VCC Operating supply voltage range - 3.20 - 5.25 V
VB= 13 V, Vcc = 3.3 V - - 20 mA

Icc Vcc DC supply current
VB= 13 V, Vcc = 5 V - - 25 mA
Vcc UV Vcc undervoltage monitor - 2.9 3.05 3.2 V
VCC OV Vcc overvoltage monitor for 3.3V VCCOV2,VCCOV1=10, 

3.4 3.55 3.7 V
3.3V supply system Default on 3.3V
VCC OV Vcc overvoltage monitor for 5V

VCCOV2,VCCOV1=01 5.45 5.75 6.0 V
5V supply system
VCC OV Vcc overvoltage monitor for safety

VOVTST = 1 (CMD2, B6) 2.6 2.8 3.0 V
test integrity check
Overvoltage and undervoltage time

Td Vcc (guaranteed through scan) 30 - 80 µs
delay for noise rejection
VDD undervoltage monitor and

VDD UV - 2.5 2.7 2.8 V
reset
AGNDloss AGND loss threshold Ramp AGND starting from 0 V 150 220 290 mV
3.5.2 Voltage regulator VDD

Table 13. Voltage regulator VDD

VDD - No external current load 3.0 3.3 3.6 V

Time from VCC to steady
Twuae Wake up time (design info) state to Vdd power on reset - - 100 µs
release (with 100 nF on Vdd)
DS11800 Rev 5 21/49

48
3.5.3 Logic input pins (PWM_H1 to 3, PWM_L1 to 3, SCK, CS, SDI, BST_DIS,
EN1 and EN2)
Table 14. Logic I/O pins electrical characteristics

Symbol Parameter Test condition Min Max Unit
Vin(HL) High level input voltage - 1.9 - V

Vin(LL) Low level input voltage - - 0.8 V
Vhin Input voltage hysteresis - 0.1 - V
Time from VCC to
steady state to Vdd
Twuae Wake up time (design info) power on reset - 100 µs
release (with 100 nF
on Vdd)
PWM_H1 to 3, PWM_L1 to 3, SDI,
Iin(PD)(1) Vin = 0.8 V 15 45 µA
BST_DIS, EN1 and EN2
Iin(PU)(1) Input pins pull up current at CS pin Vin = 2 V -45 -15 µA
Delay time from
EN=(EN1 AND EN2)
falling edge to gate
td_EN EN1, EN2 falling edge deglitch time 1.36 3 µs
drive switch off
(guaranteed through
scan)
1. No PU/PD current at SCK pin.
3.5.4 Logic output pins (FS_FLAG, SDO, TO3)

Table 15. Logic output pins (FS_FLAG, SDO, TO3) electrical characteristics
Symbol Parameter Test condition Min Max Unit
Vout(HL) High level output voltage Isink = -1 mA Vcc-300mV - mV

Vout(LL) Low level output voltage Isource = 1 mA - 300 mV
3.5.5 Boost converter

Table 16. Boost converter electrical characteristics

Vbst Boost regulator output voltage Ibst = 50 mA VDH+8.5 VDH+10 VDH+15 V

Ibst Boost regulator output current VB = 14 V - 50 70 mA
22/49 DS11800 Rev 5

Table 16. Boost converter electrical characteristics (continued)

ILIM Boost switch current limit - 250 - 500 mA

Lbst Boost regulator inductance - - 47 - µH
Cbst Boost regulator capacitance - - 2 - µF
fSW_BST Boost regulator switching frequency - 280 350 420 kHz
BST_HOV Boost over voltage threshold - 63 - 73 V
BST_HOV
Boost over voltage hysteresis - 8 - 10 V
_HYST
Tbst Boost regulator start-up time (design info) Cbst = 2 µF - 1 - ms
V(SLS3) V(SLS3)
VCAP Supply voltage for the LS gate driver ICAP = 25 mA - V
+8.5 +15
Output current for the voltage regulator
ICAP VB = 14 V -65 - -20 mA
for the LS
Bootstrap capacitor voltage V(SHSx) = 14 V,
VCBSX 8.5 - 15 V
V(CBSx)-V(SHSx) ICBSX = -6 mA
Bootstrap capacitor charge current at pin
ICBSX - 6 - 18 mA
CBSx
3.5.6 MOSFET drivers

Table 17. MOSFET drivers electrical characteristics

VGS(L) Low level output voltage VGx-VSx @ I= 50 mA - 100 250 mV

VGS(H) High level output voltage VGx-VSx @ I= -5 mA 7.5 - 15 V
IG_1,IG_0 = 11 100% Imax 450 600 750 mA
Turn-on/off current with GCR = 1 IG_1,IG_0 = 10 75% Imax 337 450 563 mA
IGxx_1
kΩ (1) IG_1,IG_0 = 01 50% Imax 225 300 375 mA
IG_1,IG_0 = 00 25% Imax 112 150 188 mA
IG_1,IG_0 = 11 100% Imax 75 100 125 mA
Turn-on/off current with GCR = 6 IG_1,IG_0 = 10 75% Imax 56 75 94 mA

IGxx_2
kΩ IG_1,IG_0 = 01 50% Imax 37 50 63 mA
IG_1,IG_0 = 00 25% Imax 18 25 32 mA
ISLSx (2)
Low-side driver SLS output current GCR = 1 kΩ, PWM signals low - - 3.3 mA
(2)
ISHSx High-side driver SHS output current GCR = 1 kΩ, PWM signals low - - 3.3 mA
GCR_STG Gate driver over current protection - - - 880 Ω
GCR_OL Gate driver under current protection - 22 - - kΩ
GCR = 1 kΩ, IG_1,IG_0=11, I =
RGxxON ON-resistance of SINK stage - - 5 Ω
25 mA injected into Gate pin
DS11800 Rev 5 23/49

48
Table 17. MOSFET drivers electrical characteristics (continued)

Gate source passive discharge

RGxx - 100 200 500 kΩ
resistance
tGHxlh Propagation delay time low to high VB = 13.5 V, Cg = 22 nF - - 300 ns
tGLxlh Propagation delay time low to high VB = 13.5 V, Cg = 22 nF - - 300 ns
tGHxhl Propagation delay time high to low VB = 13.5 V, Cg = 22 nF - - 300 ns
tGLxhl Propagation delay time high to low VB = 13.5 V, Cg = 22 nF - - 300 ns
fPWM PWM Switching frequency - - - 20 kHz
(3)
Q Drivable gate charge VGS = 10 V, 20 kHz 300 - 900 nC
DT1, DT0 = 00 (default) 100 - 200 ns
Dead time (adjustable in 4 steps via DT1, DT0 = 01 300 - 500 ns

tDT
2-bit SPI Register) DT1, DT0 = 10 700 - 1000 ns
DT1, DT0 = 11 1000 - 1500 ns
1. Only for turn-on currents with GCR = 1 kW: parameter is tested at hot temperature only; other temperatures are granted by
design.
2. I = 400 µA + 2.872/GCR.
3. Design information. The IC does not provide any active internal Gate Charge limit.
Table 18. External MOSFET overcurrent drop voltage sense

Symbol Parameter Test condition(1) Min Typ Max Unit
SC_LS1, SC_LS0 = 00
0.4 0.5 0.6 V
(default)
Short circuit detection threshold low-
VSC_LS side (adjustable in 4 steps via 2 bits SC_LS1, SC_LS0 = 01 0.7 0.8 0.9 V
SPI register) SC_LS1, SC_LS0 = 10 0.9 1 1.1 V
SC_LS1, SC_LS0 = 11 1.17 1.3 1.43 V
SC_HS1, SC_HS0 = 00
0.4 0.5 0.6 V
(default)
Short Circuit detection threshold high-
VSC_HS side (adjustable in 4 steps via 2 bits SC_HS1, SC_HS0 = 01 0.7 0.8 0.9 V
SPI register) SC_HS1, SC_HS0 = 10 0.9 1 1.1 V
SC_HS1, SC_HS0 = 11 1.17 1.3 1.43 V
Short Circuit shut down delay (the Masking time at switch

9 12 14(2) µs
circuit shuts down by short circuit ON
TSCoff
longer than TSCoff; guaranteed Filter Time in normal
through scan) 1 - 2 µs
operation
Test functions for short circuit detection
VSC TEST VSCTST=1 (CMD2, B7) -0.7 -0.5 -0.3 V
level (SCDL)(3)
1. The accuracy of SC detection thresholds for HS and LS is guaranteed for VB ≥ 6 V. In case VB < 6 V the accuracy for each
configuration, both for HS and LS, is 22.5%.
2. The PWM ON time must be longer than this Short Circuit shutdown delay, else the short circuit condition cannot be
detected.
3. Security Level test function. If this function is selected via SPI, the short circuit detection threshold is set to the specified
negative level. In this way a short circuit is detected even if the current in the external MOSFET is zero, that is Vds=0.
24/49 DS11800 Rev 5

Table 19. Gate voltage monitoring

Undervoltage threshold for

HS gate driver. It monitors the
VG UV HS voltage difference between V(BST_C)-V(VDH) 4.6 - 6.8 V
boost output pin BST_C and
HS FET drain connection
VDH
Undervoltage threshold for
LS gate driver. It monitors the
VG UV LS voltage difference between V(VCAP)-V(SLS3) 7.4 8.2 9.0 V
low-side gate driver supply
pin VCAP and LS FET 3
source connection SLS3
(guaranteed through
tUV VG Undervoltage filter time 3.5 5 7 µs
scan)
3.5.7 Current sense amplifier

Note: Table 20 is referred to bidirectional current measurement (shunt resistors on the phase of
the motor).
Table 20. Phase current sense amplifier (SPI select: Offx=1, where x=1,2)
Differential input offset

Vin_off - -5 - 5 mV
voltage
Calibration step of
Vio_step Differential input offset - 0.5 1 1.5 mV
voltage(1)
Common mode input Operating -2 - VB+4 V

VICM
voltage range Transient (t < 1 µs) -7 - VB+20 V
0.5*Vcc- 0.5*Vcc+
Vobias Output bias voltage V(Isx+) -V(Isx-) = 0 0.5*Vcc V
0.5(2) 0.5(3)
IOD Input offset drift (3) Vcc = 5V - 7 14 µV/°C
Input common mode
CMRR - 70 86 - dB
rejection ratio
Gain = 10 to 100, 
ISX+(4) Positive input pin current -200 - - µA
VCC = 5 V
Gain = 10 to 100, 
ISX-(4) Negative input pin current -1 - - mA
VCC = 5 V
Rejection ratio for Boost
V(BST_C) / V(IBx)
BST_C PSRR output power supply to 40(5) - - dB
f=350KHz
amplifier Input
DS11800 Rev 5 25/49

48
Table 20. Phase current sense amplifier (SPI select: Offx=1, where x=1,2) (continued)
Gx1,Gx0 = 11 (x = 1,2) -2% 100 +2% -

Gx1,Gx0 = 10 (x = 1,2) -2% 50 +2% -
Gain Gx1,Gx0 = 01 (x = 1,2) -2% 30 +2% -
Gain
Gx1,Gx0 = 00 (x = 1,2)
-2% 10 +2% -
(default)
ppm/
Gain temperature drift (3) - - - 100
°C
V(Isx+) -V(Isx-) > 500mV, Vcc -
- - -
IBx output voltage high Iout = 100 µA, VCC = 3.3 V 0.12V
Voh
level V(Isx+) -V(Isx-) > 500mV, Vcc -
- - -
Iout = 100 µA, VCC = 5V 0.15V
V(Isx+) -V(Isx-) <
Vol IBx output voltage low level - - 100 mV
-500mV, Iout = 100 µA
SRCSO CSO slew rate RL = 1 kOhm, CL = 20 pF 0.5 2 - V/µs
Gain = 10,30, 50 and 100,
tSETTLING Output settling time from 10% to 90% - - 5.0 µs
RL = 1 kOhm, CL = 20 pF
1. 30 calibration steps (15 for positive and 15 for negative direction) are available through SPI command for offset calibration.
2. Worst case, if gain = 100 is selected.
3. Guaranteed by design.
0.8  V CC
- + I  trim HI   --------------------------------------------
2 +  3  Phase  - + 10A
4. I SxHI = –  ---------------------------------- 
  2000  Gnom  8

 0.8  V CC
- + I  trim LO   2
I SxLO = –  ---------------------------------- --- + 10A + I  rail  
 2000  Gnom 8

Where:
ISxHI is current flowing out from ISxHI pin
ISxLO is current flowing out from ISxLO pin
Vcc = reference supply [5 V or 3.3 V]
Gnom = nominal programmed gain [10, 30, 50, 100]
I(trim,HI/LO) = offset trimming current (w.c. ±8 µA see expression below)
Phase = programmed phase configuration [1 if selected, otherwise 0]
I(rail) = current from auxiliary rail (used for floating OpAmp) [typ ~145 µA±35% T+Models]

 weight
trimming bit -------------------
 Vbg 2  2 +  3  Phase  
I  trim HI  =  -----------  ----------------------------------------------------------------------  --------------------------------------------- 
 15 10300   5 +  3  Ground  8

 weight
trimming bit -------------------
 Vbg 2 2
I  trim LO  =  -----------  ----------------------------------------------------------------------  --- 
 15 10300   5 +  3  Ground  8

Where:
Vbg = band gap reference (1.2371 V nominal)
Ground = programmed ground configuration [1 if selected, otherwise 0]
Trimming bit weight= how many mV offset trimming are programmed.
The ± depends on offset trim direction (+: bit7=1, -: bit7=0)
5. A 350 kHz, 100 mVpp, ripple at the boost regulator output, generates 1 mVpp noise at the amplifier input. It represents a 2
App current noise on a 0.5 mΩ current sense resistor.
26/49 DS11800 Rev 5

Note: Table 21 is referred to current sense amplifier configuration for unidirectional current
measurement (shunt resistors to ground). SPI select: Offx=0 (Power up default), where
x=1,2 in CMD0 command frame.
Table 21. Ground current sense amplifier

Differential input offset

Vin_off - -5 - 5 mV
voltage
Calibration step of
Vio_step differential input offset - - 1 - mV
voltage(1)
Common Mode Input Operating -2 - +2 V

VICM
Voltage Range Transient (t<1s) -7 - +7 V
0.2*Vcc- 0.2*Vcc+
Vobias Output bias voltage V(Isx+) -V(Isx-) = 0 0.2*Vcc V
0.5(2) 0.5(3)
IOD Input offset drift(3) Vcc = 5V - 7 14 µV/°C
Input common mode
CMRR - 70 86 - dB
rejection ratio
Gain = 10 to 100, 
ISX+(4) Positive input pin current -200 - - µA
VCC = 5 V
Negative input pin Gain = 10 to 100, 
ISX-(4) -1 - - mA
current VCC = 5 V
Rejection ratio for Boost
V(BST_C) / V(IBx)
BST_C PSRR output power supply to 40(5) - - dB
f=350KHz
Amplifier Input
Gx1,Gx0 = 11 (x=1,2) -2% 100 +2% -
Gx1,Gx0 = 10 (x=1,2) -2% 50 +2% -
Gain Gx1,Gx0 = 01 (x=1,2) -2% 30 +2% -
Gain
Gx1,Gx0 = 00 (x=1,2)
-2% 10 +2% -
(default)
ppm/
Gain temperature drift(3) - - - 100
°C
V(Isx+) -V(Isx-) > 500 mV, Vcc -
- -
IBx output voltage high Iout = 100 µA, VCC = 3.3 V 0.12V
Voh Voh
level V(Isx+) -V(Isx-) > 500 mV, Vcc -
- -
Iout = 100 µA, VCC = 5 V 0.15V
IBx output voltage low V(Isx+) -V(Isx-) < -500 mV,
Vol - - 100 mV
level Iout = 100 µA
SRCSO CSO slew rate RL = 1 kΩ, CL = 20 pF 1 2 - V/µs
Gain = 10,30, 50 and 100,
tSETTLING Output settling time from 10% to 90% - - 5 µs
RL = 1 kΩ, CL = 20 pF
1. 30 calibration steps (15 for positive and 15 for negative direction) are available through SPI command for offset calibration.
2. Worst case, if gain=100 is selected.
DS11800 Rev 5 27/49

48
3. Guaranteed by design.
0.8  V CC
- + I  trim HI   --------------------------------------------
2 +  3  Phase  - + 10A
4. I SxHI = –  ---------------------------------- 
 2000  Gnom 8

 0.8  V CC
- + I  trim LO   2
I SxLO = –  ---------------------------------- --- + 10A + I  rail  
  2000  Gnom  8

Where:
ISxHI is current flowing out from ISxHI pin
ISxLO is current flowing out from ISxLO pin
Vcc = reference supply [5 V or 3.3 V]
Gnom = nominal programmed gain [10, 30, 50, 100]
I(trim,HI/LO) = offset trimming current (w.c. ± 8 µA see expression below)
Phase = programmed phase configuration [1 if selected, otherwise 0]
I(rail) = current from auxiliary rail (used for floating OpAmp) [typ ~145 µA±35% T+Models]

 weight
trimming bit -------------------
 Vbg 2  2 +  3  Phase  
I  trim HI  =  -----------  ----------------------------------------------------------------------  ---------------------------------------------
 15 10300   5 +  3  Ground   8

 weight
trimming bit -------------------
 Vbg 2 2
I  trim LO  =  -----------  ----------------------------------------------------------------------  --- 
 15 10300   5 +  3  Ground   8

Where:
Vbg = band gap reference (1.2371 V nominal)
Ground = programmed ground configuration [1 if selected, otherwise 0]
Trimming bit weight= how many mV offset trimming are programmed.
The ± depends on offset trim direction (+: bit7=1, -: bit7=0)
5. A 350 kHz, 100 mVpp, ripple at the boost regulator output, generates 1 mVpp noise at the amplifier input. It represents a 2
App current noise on a 0.5 m current sense resistor.
28/49 DS11800 Rev 5

L9907 SPI operation
4 SPI operation
The L9907 SPI is a standard 16-bit, four wire interface. By means of the SPI most device
parameters can be internally set and the fault diagnostic can be read.
The timing diagram for the SPI operation is reported in Figure 7 below. The IC reads the
input data at SDI pin on the falling edge of the SPI clock (SCK). The IC outputs the SPI data
at SDO pin on the rising edge of the SPI clock (SCK).
Figure 7. Timing diagram for the SPI operation.

9
8
CS
10
2 1
3
SCK
1a 1b
11 4
7
SDO SPI error Bi t ( 15) MS B Bi t(14:1) Bit(0) LSB
5 6
SDI MSB IN Bi t(14:1) LSB I N

GAPGPS00838
The SPI protocol integrates an internal check to add robustness to the communication: a
writing attempt of a not allowed register, an incorrect parity frame or a wrong number of bits
(different than 16) results in a "SPI error bit", that is available at SDO immediately after
asserting CS the next time and before starting the SCK toggling.
If the current SPI cycle is affected by a communication error, the current SDI command is
rejected and a SPI error message (0xB001) is presented as SDO response at the following
SPI cycle.
Table 22. SPI timing specifications

# Parameter Condition Min. Typ. Max. Unit
1 SCK Frequency (fSCK) 1 - - 8 MHz

2 SCK High/low time (tSCK-high, t-SCK-low) 1a, 1b 60 - - ns
3 Enable lead time (tlead) 2 740 - - ns
4 Enable lag time (tlag) 3 200 - - ns
4
5 Data valid time (tvalid) Cload<60pF - - 50 ns
@ fSCK=8MHz
Data set up time (tSI-set) 5 30
6 - - ns
Data hold time (tSI-hold) 6 30
7 Disable time (tdisable) 7 120 ns
8 SCK, SI rise/fall time (trise, tfall) - - 5 - ns
DS11800 Rev 5 29/49

48
SPI operation L9907
Table 22. SPI timing specifications (continued)

# Parameter Condition Min. Typ. Max. Unit
Cload < 60 pF
9 SDO rise/fall time (tSDO-rise, tSDO-fall) - 35 - ns
@ fSCK =8 MHz
CS
tCS-select 8 50 ns
10 - -
tCS-access 9 3.58 µs
tCS-negated 10 640 ns
11 SDO Access Time (ta) 11 - - 80 ns
4.1 SPI bits mapping

The L9907 provides the instructions to decide which kind of strategy to adopt for faults
managing: the strategy can be selected by toggling the enable fault flags available in CMD4
and CMD1 registers.
When a fault has been validated, the corresponding diagnostic flag is set and FS_FLAG is
asserted low. The device can perform shut-off or take no action depending on the value of
the enable fault flag.
In the case where shut-off for a fault is disabled, micro becomes fully responsible for the
shut-off management for the disabled fault.
As default value, all the enable fault flags are asserted high, so the device will take the
actions described in the section related to each of them.
Table 23. SDI bit map definition

AND (EN1,
Item B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
EN2)
CMD0 0 0 0 - Par WE DT1 DT0 IG_1 IG_0 G21 G20 Off2 G11 G10 Off1 -
EN_THSD
BST_DIS_EN(1) EN_VBov
EN_VBuv
SC_HS0
SC_LS1
SC_LS0
VccOV2
VccOV1
VBOV2
VBOV1
SC_HS
CMD1 0 0 1 Par WE 0
GCR_INT_I(1)
SHT_PH(1)
ShortPH(1)
VOVTST
VSCTST
CMD2 0 1 0 Par WE - - - - - -
REGOFF_EN DIS_BSTov(1)
TRIM24
TRIM23
TRIM22
TRIM21
TRIM20
TRIM14
TRIM13
TRIM12
TRIM10
TRIM11
CMD3 0 1 1 Par WE -
EN_VSCHS1
EN_VSCHS2
EN_VSCHS3
EN_VSCLS1
EN_VSCLS2
EN_VSCLS3
EN_UV_HS
EN_UV_LS
EN_Vccov
EN_Vccuv
CMD4 1 0 0 Par WE 0
DIAG 1 1 0 - Par - - - - - - - - - - - -
DIAG2 1 1 1 - Par - - - - - - - - - - - -
1. Writable only if AND(EN1,EN2) low else command ignored.
30/49 DS11800 Rev 5

L9907 SPI operation
Table 24. SDI frame structure

Bit position Description
B(15:13) SDI command selection bits, used to select the SPI operation to be implemented
B11 (Par) odd parity bit
Write Enable bit.

A SPI cycle with WE=1 transfers the SDI data to the addressed CMDx register.
B10 (WE)
A SPI cycle with WE=0 transfers the content of the addressed CMDx register to the SDO data of
the following SPI cycle.
B(9:0) the SDI setting bits to be internally stored for device operation in case of writing SPI cycle
1. CMD0 register - Driver settings: B(15:13) = 000

a) DT1 and DT0 (B9,B8) are used to select dead time (tDT) parameter: ('00' default
condition at Power-On Reset)
Table 25. Dead time parameter

Dead time B9 = DT1 B8 = DT0
100-200ns 0 0
300-500 ns 0 1
700-1000 ns 1 0
1000-1500 ns 1 1
b) IG_1 and IG_0 (B7,B6) are used to select turn on/off current value: ('00' default
condition at Power-On Reset)
Table 26. Turn on/off current

Percentage B7 = IG_1 B6 = IG_0
25% 0 0
50% 0 1
75% 1 0
100% 1 1
c) G21 and G20 (B5,B4) are used to select current sense amplifier 2 gain: ('00'
default condition at power on reset)
Table 27. Current sense amplifier 2 gain

B5= B4=
Gain
G21 G20
10 0 0
30 0 1
50 1 0
100 1 1
DS11800 Rev 5 31/49

48
SPI operation L9907
d) Off2 (B3) is used to select current sense amplifier 2 offset (for ground or phase
connection): '0' (default value) means ground, '1' means phase.
e) G11 and G10 (B2,B1) are used to select Current sense amplifier 1 Gain:('00'
default condition at Power-On Reset)
Table 28. Current sense amplifier 1 gain

Gain B2 = G11 B1 = G10
10 0 0
30 0 1
50 1 0
100 1 1
f) Off1 (B0) is used to select current sense amplifier 1 offset (for ground or phase
connection): '0' (default value) means ground, '1' means phase.
2. CMD1 register - Diagnostic settings: B(15:13) = 001

In order to avoid unsafe change of diagnostic settings, it is not possible to write the CMD1
register during normal Output Gate Drive operation. For this reason at least one Enable
signal EN1 or EN2 must be deasserted in order to update the CMD1 register. If EN1 and
EN2 are both asserted while a SPI cycle CMD1 with WE=1 is ongoing, then a SPI
communication error is generated and the corresponding SPI command is ignored.
Since the Enable signals EN1 and EN2 also affect the output gate drives, a deglitch filter is
implemented on both of them. This filter is active on either falling edge of EN1 or EN2
signal.
In order to avoid unsafe change of fault management settings, as for the CMD1 register, it is
not possible to write CMD4 register during normal Output Gate Drive operation. For this
reason at least one Enable signal EN1 or EN2 must be deasserted in order to update the
register.
If EN1 and EN2 are both asserted while a SPI cycle CMD4 or CMD1 with WE=1 is ongoing,
then a SPI communication error is generated and the corresponding SPI command is
ignored.
a) SC_LS1 and SC_LS0 (B7,B6) are used to select short circuit detection threshold
for low-side external MOSFET ('00' default condition at power up):
Table 29. Short circuit detection threshold for low-side external MOSFET
VSC_LS B7 = SC_LS1 B6 = SC_LS0
0.4 – 0.6 V 0 0
0.7 – 0.9 V 0 1
0.9 – 1.1 V 1 0
1.17 – 1.43 V 1 1
Note: The accuracy in ranges in Table 29 is valid for VB > 6 V. For VB < 6 V the accuracy is 22.5%
for each configuration.
32/49 DS11800 Rev 5

L9907 SPI operation
b) SC_HS1 and SC_HS0 (B5-B4) are used to select short circuit detection threshold
for high-side external MOSFET ('00' default condition at Power Up):
Table 30. Short circuit detection threshold for low-side external MOSFET
VSC_HS B5 = SC_HS1 B4 = SC_HS0
0.4 – 0.6 V 0 0
0.7 – 0.9 V 0 1
0.9 – 1.1 V 1 0
1.17 – 1.43 V 1 1
Note: The accuracy in ranges in Table 30 is valid for VB > 6 V. For VB < 6 V the accuracy is 22.5%
for each configuration.
c) VBOV2 and VBOV1 (B3-B2) are used to select over voltage threshold for single or
double battery application
Table 31. VB over voltage threshold for single or double battery application
VBOV B3 = VBOV2 B2 = VBOV1 (1)
27.5 – 34.5 V 1 0
36 – 42 V (Default) 0 1
Not Allowed 0 0
Not Allowed 1 1
1. For power supply configuration in 48 V domain, please refer to AN5124.
The power-up default value for this parameter is "01", corresponding to double battery
applications.
A SPI command attempting to set a not allowed VBOV configuration does not return any SPI
error, and the VBOV configuration register retains its previous value.
d) EN_THSD, EN_VBOV EN_VBUV (B12,B9,B8) are used to enable/disable effect
of Thermal Shut Down, VB overvoltage, VB Under Voltage faults respectively.
Default value is '1' for all of them, that means "fault effect is enabled".
Table 32. CMD1 SDI SPI bits vs. enabled fault

CMD1 SDI SPI BIT Name Description (Default value=’1’)
B12 EN_THSD It enables Thermal shut down fault effect in case of THSD fault detection
B9 EN_VBOV It enables VBOV fault effect in case of VBOV fault detection
B8 EN_VBUV It enables VBUV fault effect in case of VBUV fault detection
e) VCCOV2 and VCCOV1 (B1-B0) are used to select the VCC over voltage thresholds:
Table 33. VCC over voltage threshold

VCCOV B1 = VCCOV2 B0 = VCCOV1
3.3 V (default) 1 0
5.0 V 0 1
DS11800 Rev 5 33/49

48
SPI operation L9907
Table 33. VCC over voltage threshold (continued)

VCCOV B1 = VCCOV2 B0 = VCCOV1
Not Allowed 0 0
Not Allowed 1 1
The Power Up default value for this parameter is "10", corresponding to Vcc = 3.3 V
applications.
A SPI command attempting to set a not allowed VCCOV configuration does not return any
SPI error, and the VCCOV configuration register retains its previous value.
3. CMD2 register - Test Mode Selections: B(15:13) = 010

a) SDI bit B12: GCR_INT_I
This bit is accessible for writing only if AND(EN1,EN2)='0': trying to write it without
lowering AND(EN1,EN2) will not generate any SPI error but command will be
simply ignored for the specific bit.
Once written, CMD2 B12 changes the status of the output GCR_INT_I (refer to
Section 2.5.1).
b) SDI bit B9: BstDisEN
Once written, CMD2 B9 determines how to behave in case of activation of
BST_DIS pin. In case this bit is set and activating BST_DIS pin brings the device
to switch-off BST_CLK till BST_DIS pin becomes low (refer to Section 2.4.1).
c) SDI bit B8: SHT_PH
Once written, CMD2 B8 determines how to behave in case of shoot-through
detected. In case this bit is not set (default) a shoot-through in any phase will
prevent the actuation of all commands, only the involved phase is inhibited
otherwise (refer to Section 2.5.2).
d) VSCTST (B7) = '1' activates Test Function for short circuit level ('0' is the default
value).
e) VOVTST (B6) = '1' activates Test Function for VCC over-voltage level ('0' is the
default value).
f) SDI bit B5: Short_PH
Once written, CMD2 B5 determines how to behave in case of external FET (both
HS and LS) short detected. In case this bit is not set (default) a short in any phase
will prevent the actuation of all commands, only the involved phase is inhibited
otherwise (refer to Section 2.5.3).
34/49 DS11800 Rev 5

L9907 SPI operation
4. CMD3 register - Current Sense amplifier offset calibration: B(15:13) = 011

a) SDI bit DIS_BSTov (B12)
This bit is accessible for writing only if AND(EN1,EN2) = '0': trying to write it
without lowering AND(EN1,EN2) will not generate any SPI error but command will
be simply ignored for the specific bit. Once set to '1', CMD3 B12 disables the over
voltage protection on the boost regulator BST_C pin. This bit defaults to '0'.
b) SDI bits TRIM24 to TRIM10 (B9 to B0)
The input offset of both current sense amplifiers can be calibrated separately by
properly setting the bits of the CMD3 SPI Register. Such a register can be
accessed through SDI bits B(9:0). Bits B(9:5) are dedicated to offset calibration of
Current Sense amplifier 2, while bits B(4:0) are dedicated to current sense
amplifier 1. The encoded value is a signed representation, and the values "10000"
and "00000", both correspond to 0 mV calibration.
Table 34. Current sense amplifier input offset calibration

B9(B4)= B8(B3)= B7(B2)= B6(B1)= B5(B0)=
Current sense amplifier 2(1)
Trim24 Trim23 Trim22 Trim21 Trim20
calibration input offset
(Trim14) (Trim13) (Trim12) (Trim11) (Trim10)
-15 mV 0 1111
-14 mV 0 1110
-13 mV 0 1101
... 0 ...
-3 mV 0 0011
-2 mV 0 0010
-1 mV 0 0001
0 mV 0 0000
0 mV 1 0000 (0000 = Default)
+1 mV 1 0001
+2 mV 1 0010
+2 mV 1 0011
... 1 ...
+13 mV 1 1101
+14 mV 1 1110
+15 mV 1 1111
5. CMD4 register - Fault effect enabling B(15:13)=100

In order to avoid unsafe change of fault management settings, as for the CMD1 register, it is
not possible to write CMD4 register during normal Output Gate Drive operation. For this
reason at least one Enable signal EN1 or EN2 must be deasserted in order to update the
register.
Since the Enable signals EN1 and EN2 also affect the output gate drives, a deglitch filter is
implemented on both of them. This filter is active on the falling edges of EN1 or EN2 signal.
DS11800 Rev 5 35/49

48
SPI operation L9907
If EN1 and EN2 are both asserted while a SPI cycle CMD4 or CMD1 with WE=1 is ongoing,
then a SPI communication error is generated and the corresponding SPI command is
ignored.
The effect of any fault (except Shoot Through) can be selectively masked from Micro
Controller setting at '0' proper register. FS_FLAG status and SDO report are not affected
since fault detection always acts in the same way. Default value for these bits is '1' (fault
effect enabled). Once the fault effect is re-enabled with SPI communication the IC reacts to
fault as described in the specific paragraph if the fault is still present.
Table 35. CMD4 SDI SPI bits vs. enabled fault

CMD4 SDI SPI BIT Name Description (Default value=’1’)
B9 EN_VccOV It enables VCCOV fault effect in case of VCCOV fault detection

B8 EN_VccUV It enables VCCUV fault effect in case of VCCUV fault detection
B7 EN_UV_HS It enables UV_HS fault effect in case of UV_HS fault detection
B6 EN_UV_LS It enables UV_LS fault effect in case of UV_LS fault detection
B5 EN_VSCHS1 It enables VSCHS1 fault effect in case of VSCHS1 fault detection
B2 EN_VSCLS1 It enables VSCLS1 fault effect in case of VSCLS1 fault detection
6. CMD4 SPI command register

SDI bit B12: REGOFF_EN
lowering AND(EN1,EN2) will generate SPI error.
Once written, CMD4 B12 determines if the REG_OFF procedure is active or not
(default: not active).
7. REG_OFF procedure (active only if CMD4 B12 is set; refer also to Section 2.3)
Lowering EN1 external pin triggers the procedure to switch off regulators that supply
the HS and LS FET drivers: filter time, active only on the falling edge of the EN1 signal,
is implemented: 8*tosc  TFILT  16*tosc.
Once the procedure has been triggered, the device behaves as follows:
REG_OFF = '1', EN_PWM = "000", FS_FLAG = '0', DIAG2 bit B6 set
In order to re-engage, the correct procedure is to toggle AND(EN1,EN2) then read the
DIAG2 SPI register (to verify that bit B6 is set).
Toggling of AND(EN1,EN2) will re-engage the output commands (EN_PWM = "111")
while subsequent reading of DIAG2 register will re-engage HS/LS drivers supply
(REG_OFF = '0') and release FS_FLAG.
In order to avoid activating output commands while regulators that supply the HS and
LS FET drivers are in power-up phase (this could generate current shape distortion)
36/49 DS11800 Rev 5

L9907 SPI operation
microprocessor must guarantee a dis-overlap between reading of DIAG2 register and

PWM commands toggling.
4.1.1 SDO
Table 36. SDO bit map definition

Item B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CMD0 0 0 0 0 - - DT1 DT0 IG_1 IG_0 G21 G20 Off2 G11 G10 Off1
BST_DIS_EN EN_VBOV
EN_VBUV
EN_THSD
SC_HS1
SC_HS0
SC_LS1
SC_LS0
VccOV2
VccOV1
VBOV2
VBOV1
CMD1 0 0 1 - -
GCR_INT_I
Undefined
Undefined
Undefined
Undefined
VOVTST
SHT_PH
VSCTST
ShortPH
CMD2 0 1 0 - - -
REGOFF_EN DIS_BSTov
TRIM24
TRIM23
TRIM22
TRIM21
TRIM20
TRIM14
TRIM13
TRIM12
TRIM10
TRIM11
CMD3 0 1 1 - -
VSCHS1 EN_VSCHS1
VSCHS2 EN_VSCHS2
VSCHS3 EN_VSCHS3
VSCLS1 EN_VSCLS1
VSCLS2 EN_VSCLS2
VSCLS3 EN_VSCLS3
EN_UV_HS
EN_UV_LS
EN_VccOV
EN_VccUV
CMD4 1 0 0 - -
AND(EN1_EN2)_RB UV_HS
UV_LS
THSD
DIAG 1 1 0 VBOV VBUV VccOV VccUV

BSTDIS_RB(1)
REGOFF_RB
BST_C_OV
GCR_STG
GCR_OL
EN1_RB
DIAG2 1 1 1 - - - SHT3 SHT2 SHT1
1. Not cleared after read.
1. SDO CMD1 to CMD4 registers - Response to SDI commands: B(15:13)=000 till 100
SDO responds in the current SPI cycle with the content of the command register CMDn
(n=1 to 4) that is being addressed in the previous SPI cycle. In such a way the controller
may verify the command data being stored in the proper register (WE=1 in the previous SPI
cycle), or simply verify the correct IC data retention of initially programmed commands
(WE=0).
2. SDO DIAG register - Diagnostic read cycle: B(15:13) = 110

During its operation the IC detects diagnostic data that is made available at SDO SPI output
pin. Such diagnostic data is mainly related to output gate drivers, in order to check for
example under voltage condition on high-side or low-side (UV_HS and UV_LS) together
with over current information due to a short circuit fault on each external high and low-side
FET (VSCHS1-2-3 and VSCLS1-2-3). Additionally the device diagnostic allows also to
check Thermal Shutdown Fault (THSD), under and over voltage condition on VB line (VBUV
and VBOV) and VCC line (VccOV, VccUV).
DS11800 Rev 5 37/49

48
SPI operation L9907
Effects described in the following sections take into account that the corresponding Fault
Enable bit is set to '1'.
a) TH_SD (B12). Thermal shutdown.

Once Thermal shutdown threshold temperature is reached, all the FET drivers are
disabled and a cumulative fault information is available at FS_FLAG pin and
through SPI reading cycle, together with FET status (enable/disable). After cooling
down the FET drivers are automatically re-enabled once the temperature
becomes lower than (Tot -Thys: see Table 11) and the information about FET status
(enable/disable) is available at SDO pin through an SPI reading cycle. After
cooling down the SPI diagnostic bit remains set, and the pin FS_FLAG remains
asserted low. A SPI diagnostic read cycle clears the THSD bit and deactivates
high the FS_FLAG pin.
The filter time applied to this fault works on both edges of the input signal.
b) VB_OV (B11) and VB_UV (B10). VB over-voltage and under-voltage

When the device is active and an under or over-voltage condition on VB line is
present for a time longer than Td_VB, the fault is detected and internally latched.
Upon detection of under or over-voltage of VB, the FET drivers and the BOOST
regulator are disabled, the proper SPI bit is set and the FS_FLAG is asserted low.
After removal of the fault condition (VB returns inside its normal range), the
BOOST is automatically re-enabled, the FET drivers instead are restarted by
cycling EN signal (internal AND of EN1 and EN2 pins) from high to low to high. A
SPI diagnostic read cycle clears the SPI diagnostic flag releases the FS_FLAG pin
to high.
c) Vcc_OV (B9) and Vcc_UV (B8). VCC over-voltage and under-voltage

When an over-voltage condition appears on the VCC line for a time longer than
Td_Vcc, the fault is detected and internally latched, the device is then disabled.
In case of detected under or over-voltage of VCC, the FET drivers and the BOOST
regulator are disabled, the proper SPI bit is set and the FS_FLAG is asserted low.
After removal of the fault condition (Vcc returns inside its normal range), the
BOOST is automatically re-enabled, the FET drivers are restarted by cycling EN
signal (internal AND of EN1 and EN2 pins) from high to low to high. A SPI
diagnostic read cycle clears the SPI diagnostic flag and releases the FS_FLAG
pin to high.
d) UV_HS (B7). High-side FET drivers supply under-voltage

The voltage difference between boost output pin and high-side Drain connection is
monitored and, if it falls down below VG_UV_HS threshold for a time longer than
tUV_UG, a high-side under-voltage fault is detected and internally latched. All the
FET drivers are disabled and fault information is available at FS_FLAG pin and at
SDO pin through an SPI reading cycle.
The fault flag for the high-side FET drivers supply under-voltage is related to a
BOOST regulator under - voltage.
In case of detected fault, the FET drivers are disabled, the proper SPI bit is set
and the FS_FLAG is asserted low. After removal of the fault condition, the FET
38/49 DS11800 Rev 5

L9907 SPI operation
drivers are restarted by cycling EN signal (internal AND of EN1 and EN2 pins)
from high to low to high. A SPI diagnostic read cycle clears the SPI diagnostic flag
and releases the FS_FLAG pin to high.
e) UV_LS (B6). Low-side FET drivers supply under-voltage

The voltage difference between the low-side gate driver supply pin VCAP and
each of the low-side FET sources are monitored. In case VCAP is lower than
VG_UV_LS threshold for a time longer than tUV_UG, then a low-side under-
voltage fault is detected and internally latched. The low-side FET drivers supply
under-voltage is active if the fault condition is present at least on one of the three
channels.
In case of detected fault, the FET drivers are disabled, the proper SPI bit is set
and the FS_FLAG is asserted low. After removal of the fault condition, the FET
drivers are restarted by cycling EN signal (internal AND of EN1 and EN2 pins)
from high to low to high. A SPI diagnostic read cycle clears the SPI diagnostic flag
and releases the FS_FLAG pin to high.
f) VSC_HS1 to VSC_HS3 (B5 to B3). High-side external MOSFET over-current

The voltage difference between the high-side external power drain (VDH) and the
source (SHS1-2-3) is monitored and, if it exceeds VSC_HS threshold for a time
longer than TSCoff, then a high-side short circuit fault is detected and internally
latched.
In case of detected fault, all FET drivers are disabled, the proper SPI bit is set and
the FS_FLAG is asserted low. After removal of the fault condition, the FET drivers
are restarted by cycling EN signal (internal AND of EN1 and EN2 pins) from high
to low to high. A SPI diagnostic read cycle clears the SPI diagnostic flag and
releases the FS_FLAG pin to high.
g) VSC_LS1 to VSC_LS3 (B2 to B0). Low-side external MOSFET over-current

The voltage difference between low-side external power drain (SHS1-2-3) and
source (SLS1-2-3) is monitored and, if it exceeds the VSC_LS threshold for a time
longer than TSCoff, then a low-side short circuit fault is detected and internally
latched.
In case of detected fault, all FET drivers are disabled, the proper SPI bit is set and
the FS_FLAG is asserted low. After removal of the fault condition, the FET drivers
are restarted by cycling the EN signal (internal AND of EN1 and EN2 pins) from
high to low to high. A SPI diagnostic read cycle clears the SPI diagnostic flag and
releases the FS_FLAG pin to high.
DS11800 Rev 5 39/49

48
SPI operation L9907
3. SDO DIAG2 register - Diagnostic read cycle: B(15:13) = 111

Below, it is described the meaning of each diagnostic bit in case of DIAG2 active.
a) SDO bit B9: BST_DIS_RB
BST_DIS_RB informs about the status of that a BST_DIS pin (not cleared after
read).
b) SDO bit B8: EN1_RB
EN1_RB informs about the status of EN1 filtered input (not cleared after read).
c) SDO bit B7: AND(EN1,EN2)_RB
AND(EN1,EN2)_RB informs about the status of AND(EN1,EN2) signal (not
cleared after read).
d) SDO bit B6: REGOFF_RB
e) REGOFF_RB informs that a REG_OFF procedure has been triggered by EN1
lowering. Reading back this bit will re-engage FS_FLAG and cause
REG_OFF='0'.
f) SDO bit B5: BST_C_OV
BST_C_OV informs about the status of boost over voltage level.
Filter time duration: 16*tosc ≤ TFILT ≤ 20*tosc (active on both directions)
effect when validated: BST_CLK = 0, BST_EN = 1,
BST_HYST = 1, FS_FLAG = 0; EN_PWM[3:1] no change
re-engagement: BST_CLK self re-engagement when fault disappears
FS_FLAG re-engaged after DIAG2 reading and fault cleared
g) SDO bit B4: GCR_OL
GCR_OL informs about the status of the GCR pin open load condition (i.e. too
high resistive value).
effect when validated:GCR_INT_I = 1
re-engagement: GCR_INT_I = 0 self re-engagement when fault disappears
h) SDO bit B3: GCR_STG
GCR_STG informs about the status of the GCR pin short to ground condition (i.e.
too low resistive value).
effect when validated:GCR_INT_I = 1
re-engagement: GCR_INT_I = 0 self re-engagement when fault disappears
i) SDO bit B<2:0>: SHT<X>
Shoot Through on specific phase has occurred: FS_FLAG remains low till the fault
is cleared by a read back of DIAG2 frame.
40/49 DS11800 Rev 5

L9907 Application circuit
5 Application circuit
5.1 12 V/24 V system

Figure 8. Application circuit, 12 V/24 V system
Reverse battery protection
RRB1 C
RB1 R
RB3
Keep this loop D2
RRB2 TRB2
area small
D1 CBST2
D3
C LBST TRB1
BST1
D4
C
IN
BST_C BGND BST_L
_ D5
VB BATTERY
Power
VCC
VDH
C CHB
VCC
Supply
CBS1 T THS2 T
HS1 HS3
CBS1
R RGHS12 R
GHS11 GHS13
VDD GHS1
SHS1 RGHS21 RGHS22 RGHS23
CVDD
CBS2
CBS2
PWM H1
GHS2 RSHUNT1 BLDC
SHS2
PWM L1
PWM H2 CBS3
RSHUNT2 Motor
L9907
CBS3
PWM L2
PWM H3
GHS3
PWM L3
SHS3
TLS1 T TLS3
LS2
EN1
MCU
R RGLS12 R
EN2 GLS11 GLS13
GLS1
BST_DIS
SLS1
RGLS21 RGLS22 RGLS23
FS FLAG
SDI
GLS2
CS SLS2
SCK
GLS3
SDO
SLS3
VCAP
TM CLSD
TO3 IS1+
R
IB1 IS1-
IB1
RIB2
IB2 IS2+
C CIB1 DGND DGND SGND2 SGND1 GCR IS2-

IB2
CIS1+ C C CIS2-
IS1- IS2+
RGCR
DS11800 Rev 5 41/49

48
Application circuit L9907
5.2 48 V system
Figure 9. Application circuit, 48 V system
Reverse battery protection
RRB1 C
R RB1 RRB3
BP1
Keep this loop CBP D
2 R T
area small RB2 RB2
D CBST2
1 CIN R D
CBST1 L T BP2 3
BST BP T
RB1
BST_C BGND BST_L

_
VB BATTERY
Power
VCC
VDH
CVCC C
HB
Supply
CBS1 THS1 T THS3
HS2
C
BS1
RGHS11 RGHS12 RGHS13
VDD GHS1
SHS1
C RGHS21 RGHS22 RGHS23
VDD
CBS2
CBS2
PWM H1
GHS2 RSHUNT1 BLDC
SHS2
PWM L1
PWM H2 CBS3
R
SHUNT2
Motor
L9907
C
PWM L2 BS3
PWM H3
GHS3
PWM L3
SHS3
TLS1 T T
LS2 LS3
EN1
MCU
R RGLS12 R
EN2 GLS11 GLS13
GLS1
BST_DIS
SLS1
RGLS21 RGLS22 RGLS23
FS FLAG
SDI
GLS2
CS SLS2
SCK
GLS3
SDO
SLS3
VCAP
TM CLSD
TO3 IS1+
R
IB1 IS1-
IB1
RIB2
IB2 IS2+
C C DGND DGND SGND2 SGND1 GCR IS2-

IB2 IB1
CIS1+ CIS1- CIS2+ C
IS2-
R
GCR
5.3 Bill of materials

The following table summarizes the suggested BOM for both systems shown in the Figure 8
and Figure 9.
Table 37. Application circuit - BOM

Recommended Voltage/
Part Number
Component # Min Typ Max Unit Comment
12 V 24 V 48 V
system system system
CIN 1 - 100 - μF 50 V 100 V -

CRB1 - 390 - nF 50 V 100 V -
CBST1 - 100 - nF 50 V 100 V -
CBST2 - 1 - μF 25 V -
CBP - 100 - nF - 50 V -
42/49 DS11800 Rev 5

L9907 Application circuit
Table 37. Application circuit - BOM (continued)

Part Number
12 V 24 V 48 V
CHB 1 - 220 - μF 50 V 100 V -

CBSx 3 - 1 - μF 25 V X = 1, 2, 3
Place near
CLSD 1 - 1 - μF 16 V LSx
ground
CISx+ 2 - 22 - nF 6.3 V X = 1, 2
CISx- 2 - 22 - nF 6.3 V X = 1, 2
X = 1, 2
CIBx 2 - 220 - pF 6.3 V
optional
CVCC 1 - 100 - nF 6.3 V Place near
device
CVDD 1 100-20% 100 100+20% nF 6.3 V pins
RRB1 1 - 39 - kΩ - -
RRB2 1 - 1 - kΩ - -
RRB3 1 - 22 - kΩ - -
RBP1 1 - 22 - kΩ - optional
RBP2 1 - 22 - kΩ - optional
X = 1, 2, 3
RGHS1x 3 - 22 - Ω -
optional
X = 1, 2, 3
RGHS2x 3 - 100 - kΩ -
optional
X = 1, 2, 3
RGLS1x 3 - 22 - Ω -
optional
X = 1, 2, 3
RGLS2x 3 - 100 kΩ -
optional
X = 1, 2,
RIBx 2 - 1 - kΩ -
optional
RSHUNTx 2 - 4 - mΩ WSL10204L000FEA X = 1, 2
RGCR 1 1-10% 1 22+10% kΩ - -
LBST 1 - 47 - μH - -
D1 1 - - - - STPS2H100ZFY -
D2 1 - - - - STPS0520Z -
D3 1 - - - - STPS3L60 -
D4 1 - - - - SMA6T39AY SMA6T56AY - -
D5 1 - - - - Short SMA6T6V7AY - -
DS11800 Rev 5 43/49

48
Application circuit L9907
Table 37. Application circuit - BOM (continued)

Part Number
12 V 24 V 48 V
STL225N6F7
TRB1 STD105N10F7AG(1) -
AG(1)
TRB2 BCP56-16 -
TBP - BCP56-16 -
STL225N6F7
THSx STD105N10F7AG(1) X = 1, 2, 3
AG(1)
STL225N6F7
TLSx STD105N10F7AG(1) X = 1, 2, 3
AG(1)
1. Actual part number must be carefully selected according to the application current consumption estimation.
44/49 DS11800 Rev 5

L9907 Package information
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
6.1 TQFP64 (10x10x1 mm exp. pad down) package mechanical data

Figure 10. TQFP64 (10x10x1 mm exp. pad down) package mechanical drawing
BOTTOM VIEW
D2
E2
D1/4
E1/4
4x N/4 TIPS
SECTION A-A
aaa C A-B D ș ș
bbb H A-B D 4x
(N-4) x e
R1
C
A H R2
A2 A1 b ccc C
ddd M A D
ņ 0.05 GAUGE PLANE
0.25
D S ș
D1 L
ș
D (L1)
SECTION B-B
1
E1/4 (b)
2
3
WITH PLATING
A B
D1/4 c c1
E1 E
b1 BASE METAL
A A
(see SECTION A-A)
TOP VIEW
7278840_G_9I GAPGPS03451
DS11800 Rev 5 45/49

48
Package information L9907
Table 38. TQFP64 (10x10x1 mm exp. pad down) package mechanical data
Dimensions
Ref Millimeters Inches(1)
Min. Typ. Max. Min. Typ. Max.
Ө 0° 3.5° 6° 0° 3.5° 6°
Ө1 0° - - 0° - -
Ө2 11° 12° 13° 11° 12° 13°
Ө3 11° 12° 13° 11° 12° 13°
A - - 1.20 - - 0.0472
A1 0.05 - 0.15 0.002 - 0.0059
A2 0.95 1.0 1.05 0.0374 0.0394 0.0413
b 0.17 0.22 0.27 0.0067 0.0079 0.0091
b1 0.17 0.20 0.23 0.0067 0.0079 0.0091
c 0.9 - 0.20 0.0354 - 0.0079
c1 0.9 - 0.16 0.0354 - 0.0063
D - 12.00 BSC - - 0.4724 BSC -
(2)
D1 - 10.00 BSC - - 0.3937 BSC -
D2 VARIATION
e - 0.50 BSC - - 0.0197 BSC -
E - 12.00 BSC - - 0.4724 BSC -
(2)
E1 - 10.00 BSC - - 0.3937 BSC -
E2 VARIATION
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 - 1.00 REF - - 0.0394 REF -
N - 64.00 - - 2.5197 -
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
TOLERANCE OF FORM AND POSITION
aaa - 0.20 - - 0.0079 -
bbb - 0.20 - - 0.0079 -
ccc - 0.08 - - 0.0031 -
ddd - 0.07 - - 0.0028 -
VARIATIONS
Option A
D2 - 4.50 - - 0.1772 -
46/49 DS11800 Rev 5

L9907 Package information
Table 38. TQFP64 (10x10x1 mm exp. pad down) package mechanical data (continued)
Dimensions
Ref Millimeters Inches(1)
E2 - 4.50 - - 0.1772 -
Option B
D2 - 6.0 - - 0.2362 -
E2 - 6.0 - - 0.2362 -
1. Values in mm are converted into inches and rounded to 4 decimal digits.
2. Dimensions D1 and E1 do not include mold flash or protrusions.
Allowable mold flash or protrusion is “0.25 mm” per side.
6.1.1 TQFP64 exposed pad dimensions for L9907
Table 39. TQFP64 exposed pad dimensions for L9907

Millimeters Inches(1)
Ref
D2 5.85 6.0 6.15 0.2303 0.2362 0.2421

E2 5.85 6.0 6.15 0.2303 0.2362 0.2421
1. Values in mm are converted into inches and rounded to 4 decimal digits.
DS11800 Rev 5 47/49

48
Revision history L9907
7 Revision history
Table 40. Document revision history

Date Revision Changes
30-Mar-2017 1 Initial release

Corrected limits (LSL = 1 µs) for TSCoff digital filter time (short circuit
shutdown delay) in Table 18 on page 24.
Updated:
– Operating VB range, extension to 4.2 V;
– ISxx range: VDH+4 V in Table 8 on page 18
29-Jun-2018 2 – Inserted note (2) for differential driver stage in Table 9: Absolute
maximum ratings;
– Corrected in Table 16 on page 22, VCAP range, with LSL limit to
7.5 V;
– Corrected B8 description in Table 32 on page 33;
– Added note in Table 31 reference regarding power supply
configuration for 48 V boardnet.
Updated:
07-Aug-2019 3 – High level digital input LSL from 2 V to 1.9 V in Table 14;
– LSL of overdrive for VBST, VCAP and VCBS set to 8.5 V in Table 16.
20-Jul-2020 4 Typing error.
Added:
– Section 2.7: System clock.
Updated:
– Section : Features;
– Section : Description;
– Section 2.6: Current Sense Amplifier (CSA);
27-Apr-2021 5
– Section 5: Application circuit;
– Table 9: Absolute maximum ratings;
– Table 12: Supply electrical characteristics.
Minor text changes in:
– Section 4.1: SPI bits mapping;
– Section 4.1.1: SDO.
48/49 DS11800 Rev 5

L9907
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS11800 Rev 5 49/49

49

Automotive FET Driver For 3 Phase BLDC Motor: Features

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Automotive FET Driver For 3 Phase BLDC Motor: Features

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L9907

Automotive FET driver for 3 phase BLDC motor

Datasheet - production data

Protection and diagnostic

April 2021 DS11800 Rev 5 1/49

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2/49 DS11800 Rev 5

3.5.7 Current sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

DS11800 Rev 5 3/49

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4/49 DS11800 Rev 5

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DS11800 Rev 5 5/49

1 Block diagram and pin description

1.1 Block diagram

TO3 Overvolt. IS1+

AGND DGND SGND1 SGND2

6/49 DS11800 Rev 5

1.2 Pin description

Table 2. Pin function

DS11800 Rev 5 7/49

Table 2. Pin function (continued)

17 IS2- Negative input for current sense amplifier 2 I

8/49 DS11800 Rev 5

Table 2. Pin function (continued)

52 Vdd 3.3 V power supply output (for IC internal purpose only) O

DS11800 Rev 5 9/49

2.1 Power supply VB, VCC

2.2 Voltage regulator VDD

2.3 EN1 and EN2 pins (ENABLE)

10/49 DS11800 Rev 5

2.4 Boost converter

Figure 3. MOSFET drivers supply structure

DS11800 Rev 5 11/49

2.4.1 BstDis (boost disable) function

Figure 4. Case of T_BOOST_OFF < T_BOOST_OFF_MAX

BOOST DIS PIN

BOOST CLK MASK

Figure 5. Case of T_BOOST_OFF > T_BOOST_OFF_MAX

Internal sync signal

BOOST DIS PIN

BOOST CLK MASK

12/49 DS11800 Rev 5

2.5 MOSFET drivers

2.5.1 GCR pin

2.5.2 Shoot through protection

DS11800 Rev 5 13/49

2.5.3 Drain source monitoring

2.6 Current Sense Amplifier (CSA)

Figure 6. CSA simplified circuit diagram

SG1 SG2 SG3 SG4

14/49 DS11800 Rev 5

Table 3. Offset bit configuration

0 Open Closed 20% VCC

Table 4. Gain bit configuration

0 0 Closed Open Open Open 10

2.7 System clock

CLK_freq System Clock Frequency - 5.6 - MHz

2.8 General SPI usage

DS11800 Rev 5 15/49

2.9 Device and FET fault handling

Table 6. Device and FET fault handling

– Remove fault => auto recovery