Sequential Circuit

Moore Type Problem

❖The output z is equal to 1 if during two immediately preceding clock cycles the
input w was equal to 1. Otherwise, the value of z is equal to 0.
Forming State Diagram
Forming State Table
Forming State Assigned Table
Synthesis using K-map
Circuit
Timing Diagram
 Summary of Steps

State
State State Timing
Assigned Synthesis Circuit
Diagram Table Diagram
Table
 Mealy Type
❖ the output z should be equal to 1 in the same clock cycle when the second
occurrence of w = 1 is detected.

Mealy

Moore
Forming State Diagram
Forming State Table
Forming State Assigned Table
Synthesis using K-map
Circuit
Timing Diagram
Verilog Coding
 Sequence Detector (1)
❖The output z is equal to 1 when the previous two values of w were 00 or 11.
Otherwise, the value of z is equal to 0.
State Diagram
Solution
Verilog Code
 Sequence Detector (2)
❖The output z is equal to 1 when the two values of w were 00 or 11 in the current
cycle. Otherwise, the value of z is equal to 0.
Solution
Verilog Code
 3 Consecutive 1’s
❖The output z is equal to 1 if during three immediately preceding clock cycles the
input w was equal to 1. Otherwise, the value of z is equal to 0.
Solution
 Parity Generator
❖The output z is equal to 1 when the number of 1’s in all previous cycles is odd and
z is equal to 0 when the number of 1’s in all previous cycles is even.
Solution
Summary

❖ Sequence Detector
❖ Parity Generator
Serial Adder
Mealy Type State Diagram
Solution
Circuit
Moore Type State Diagram
Solution
Circuit
 Summary

❖ Serial adder with Moore and Mealy type

divide-by-3 counter FSM
gives a 1 every third count
𝟎 → 𝟎 → 𝟏 → 0…
state next output
state
00 01 0
01 10 0
10 00 1

draw a state diagram for a 3 bit counter

and write its SystemVerilog Code

Look up how to draw state

diagrams from DLD course

© 2021, ORCHI HASSAN

divide-by-3 counter FSM
gives a 1 every third count
𝟎 → 𝟎 → 𝟏 → 0…
state next output
state
00 01 0
01 10 0
10 00 1

draw a state diagram for a 3 bit counter

and write its SystemVerilog Code

Look up how to draw state

diagrams from DLD course

© 2021, ORCHI HASSAN

3-bit Right Shift Register
Serial-Input, Parallel Output

current state: OUT1 OUT2 OUT3 C

next state: IN OUT1 OUT2 N
S0 state: IN OUT1 OUT2
S1
S2
S3
S4
S5
S6
S7
S0
S1
S2
S3
S4
S5
S6
S7

© 2021, ORCHI HASSAN

 module shifter3fsm(input logic clk
3-bit Right Shift Register input logic x
Serial-Input, Parallel Output output logic [2:0]out)
typedef enum logic [2:0]{S0, S1, S2, S3,
S4, S5, S6, S7} statetype;
statetype state, nextstate;
S0 S0
S1 S0 // State Register
S2 S1 always_ff @(posedge clk)
S3 S1 state<= nextstate
S4 S2
S5 S2
S6
// Next State Logic
S3
S7 S3 always_comb
S0 S4 case(state)
S1 S4 S0: if(x) nextstate=S4 Mealy Machine
S2 S5 else nextstate=S0
S3 S5
S4
S1: if(x) nextstate=S4
S6
S5 S6 else nextstate=S0
S6 S7 :
S7 S7 endcase Moore Machine

// Output Logic
assign out=state
endmodule

© 2021, ORCHI HASSAN

 HistoryFSM
input a, and output x and y

x=1 when input is same as previous cycle

Y=1 when input has been the same for last two cycles

next state output xy

state
a=0 a=1 a=0 a=1
S0 S1 S3 00 00
S1 S2 S3 10 00
S2 S2 S3 11 00
S3 S1 S4 00 10
S4 S1 S4 00 11
* reset sets state to S0

© 2021, ORCHI HASSAN

* reset sets state to S0

© 2021, ORCHI HASSAN

Mealy Machine Moore Machine

• Output Logic Dependencies

• Synchronous-Asynchronous
• State Diagram
• Number of States
• General Circuit Complexity

© 2021, ORCHI HASSAN

DESIGN OF A MODULO-8 COUNTER : STATE MACHINE DESIGN

w= 0 w= 0 w= 0 w= 0

w= 1 w= 1 w= 1
A/0 B/1 C/2 D/3

w= 1 w= 1

H/7 G/6 F/5 E/4

w= 1 w= 1 w= 1

w= 0 w= 0 w= 0 w= 0

Figure 8.60. State diagram for the counter.

 STATE TABLE OF THE COUNTER

w=0 w=0 w=0 w=0 Next state

Present Output
state w= 0 w= 1
w=1 w=1 w=1
A/0 B/1 C/2 D/3
A A B 0
B B C 1
w=1 w=1
C C D 2
D D E 3
H/7 G/6 F/5 E/4 E E F 4
w=1 w=1 w=1
F F G 5
G G H 6
w=0 w=0 w=0 w=0
H H A 7

Figure 8.61. State table for the counter.

 Next state
Present
Count
state w= 0 w= 1
y2 y1 y0 z2z1z0
Y 2 Y 1Y 0 Y 2Y 1Y 0
A 000 000 001 000
B 001 001 010 001
C 010 010 011 010
D 011 011 100 011
E 100 100 101 100
F 101 101 110 101
G 110 110 111 110
H 111 111 000 111

Figure 8.62. State-assigned table for the counter.

 y1y0
Implementation using D-FF y1y0
wy2 wy2
00 01 11 10 00 01 11 10
00 0 1 1 0 00 0 0 1 1

01 0 1 1 0 01 0 0 1 1

11 1 0 0 1 11 0 1 0 1

10 1 0 0 1 10 0 1 0 1

Y0 = wy0 + wy0 Y1 = wy1 + y1y0 + wy0y1

y1y0
wy2
00 01 11 10
00 0 0 0 0

01 1 1 1 1

11 1 1 0 1

10 0 0 1 0

Y2 = wy2 + y0y2 + y1y2 + wy0y1y2

Figure 8.63. Karnaugh maps for D flip-flops for the counter.

 Implementation using D-FF
w Y0
Y0 = wy0 + wy0 D Q y

Y1
D Q y1
Y1 = wy1 + y1y0 + wy0y1
Q

Y2
Y2 = wy2 + y0y2 + y1y2 + wy0y1y2 D Q y2

Clock
Resetn

Figure 8.64. Circuit diagram for the counter implemented with D flip-flops.
 A counter that counts 0,4,2,6,1,5,3,7,0,4, and so on

Present Next Output

A counter that display counts in the state state z2z1z0
sequence
0,4,2,6,1,5,3,7,0,4, and so on A B 000
B C 100
C D 010
D E 110
E F 001
F G 101
G H 011
H A 111

Figure 8.69. State table for the counterlike example.

 Present Next Output
state state
y2 y1 y0 Y2Y 1Y 0 z 2z 1z 0
000 1 00 0 00
100 0 10 1 00
010 1 10 0 10
110 0 01 1 10
001 1 01 0 01
101 0 11 1 01
011 1 11 0 11
111 0 00 1 11

Figure 8.70. State-assigned table for Figure 8.69.

 D Q z2

D2=Y2=y2 Q
D1=Y1=y1Åy2
D0=Y0=y0Åy1y2

D Q z1

D Q z0

w Q

Figure 8.71. Circuit for Figure 8.70.

FSM OF AN ARBITER CIRCUIT
Reset 000

Idle

0xx 1xx

gnt1 g1 = 1

x0x 1xx 01x

gnt2 g2 = 1

xx0 x1x 001

gnt3 g3 = 1

xx1
FSM OF AN ARBITER CIRCUIT r 1r 2 r 3
Reset

Idle

r1 r1

gnt1 g1 = 1

r2 r1 r 1r 2

gnt2 g2 = 1

r3 r2 r 1r 2 r 3

gnt3 g3 = 1

r3

Figure 8.73. Alternative style of state diagram for the arbiter.

Verilog Code for the arbiter

endmodule