MT2503D SOC Processor Data Sheet v1.0

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MT2503D SOC Processor Data Sheet

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Version: 1.0
Release date: 2015-12-14
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Specifications are subject to change without notice.
© 2015 MediaTek Inc.

This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
[email protected],time=2016-03-29 15:29:32,ip=183.37.111.14,doctitle=MT2503D SOC Processor Data Sheet v1.0.pdf,company=SAC-Wearable_WCX

MT2503D
SOC Processor Data Sheet
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Document Revision History
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Revision Date Author Description
0.1 2015-10-08 Sharon Chu Initial draft
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1.0 2015-12-14 Sharon Chu
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MediaTek Confidential © 2015 MediaTek Inc. Page 2 of 491


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Table of Contents
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Document Revision History ......................................................................................................................... 2
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Table of Contents ....................................................................................................................................... 3
1 System Overview ........................................................................................................................ 12
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1.1 Platform Features ............................................................................................................... 16
1.2 MODEM Features ............................................................................................................... 18
1.3
1.4
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GSM/GPRS RF Features ................................................................................................... 19
Multimedia Features ........................................................................................................... 20

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1.5 Bluetooth Features ............................................................................................................. 22
1.6 FM Features ....................................................................................................................... 23

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1.7 GPS feature ........................................................................................................................ 24
1.8 General Descriptions .......................................................................................................... 26

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2 Product Descriptions ................................................................................................................. 28

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2.1 Pin Description.................................................................................................................... 28
2.1.1
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Ball Diagram ....................................................................................................... 28
2.1.2 Pin Coordination ................................................................................................. 28
2.1.3 Detailed Pin Description ..................................................................................... 31

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2.1.4 Pin Multiplexing, Capability and Settings ........................................................... 45
2.2 Electrical Characteristics .................................................................................................... 52

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2.2.1 Absolute Maximum Ratings ............................................................................... 52
2.2.2 Recommended Operating Conditions ................................................................ 53

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2.2.3 Electrical Characteristics under Recommended Operating Conditions ............. 54
2.3 System Configuration ......................................................................................................... 61
2.3.1 Strapping Resistors ............................................................................................ 61
2.3.2 Mode Selection ................................................................................................... 61
2.4 Power-on Sequence and Protection Logic ......................................................................... 61


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2.5 Analog Baseband ............................................................................................................... 65
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2.5.1 APC-DAC ........................................................................................................... 65
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2.5.2 Auxiliary ADC ..................................................................................................... 66
2.5.3 Audio Mixed-Signal Blocks ................................................................................. 67
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2.6 Power Management Unit Blocks ........................................................................................ 69
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2.6.1 LDO .................................................................................................................... 70
2.6.2 BOOST ............................................................................................................... 74
2.6.3 ISINK and KPLED Switches ............................................................................... 74
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2.6.4
2.6.5
STRUP ............................................................................................................... 76
PCHR ................................................................................................................. 76
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2.7 GSM/GPRS RF................................................................................................................... 82
2.7.1 General Description............................................................................................ 82

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2.7.2 Functional Block Diagram .................................................................................. 83
2.7.3 Electrical Characteristics .................................................................................... 83

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2.8 Bluetooth............................................................................................................................. 87
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2.8.1 Block Description................................................................................................ 87
2.8.2 Functional Specifications ................................................................................... 88

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2.9 FM RF ................................................................................................................................. 90
2.9.1 Block Description ................................................................................................ 90

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2.9.2 Functional Specifications ................................................................................... 91
2.10 Package Information ........................................................................................................... 92

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2.10.1 Package Outlines ............................................................................................... 92
2.10.2 Thermal Operating Specifications ...................................................................... 95
2.10.3 Lead-free Packaging .......................................................................................... 95

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2.11 Ordering Information ........................................................................................................... 95
2.11.1 Top Marking Definition ....................................................................................... 95
3 Micro-Controller Unit Peripherals ............................................................................................. 96
3.1 Pulse-Width Modulation Outputs (2 Channel) .................................................................... 96


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3.1.1 General Description............................................................................................ 96
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3.1.2 Register Definition .............................................................................................. 97
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3.2 SIM Interface .................................................................................................................... 101
3.2.1 Register Definition ............................................................................................ 103
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3.2.2 SIM Card Insertion and Removal ..................................................................... 118
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3.2.3 Card activation and Deactivation ..................................................................... 118
3.2.4 Answering to Reset Sequence ......................................................................... 118
3.2.5 SIM Data Transfer ............................................................................................ 119
3.3
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Keypad Scanner ............................................................................................................... 122
3.3.1 General Description.......................................................................................... 122

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3.3.2 Register Definitions .......................................................................................... 125
3.4 General Purpose Inputs/Outputs ...................................................................................... 132

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3.5 General-purpose Timer .................................................................................................... 269

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3.5.1 General Descriptions ........................................................................................ 269

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3.5.3 Application Note ............................................................................................... 273
3.6 MCU OSTIMER ................................................................................................................ 274

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3.6.1 Overview .......................................................................................................... 274
3.6.2 Terminology...................................................................................................... 274

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3.6.3 Introduction to Wakeup Source ........................................................................ 274
3.7 UART1 .............................................................................................................................. 286

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3.8 UART2 .............................................................................................................................. 301


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3.9 UART3 .............................................................................................................................. 318
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3.10 I2C/SCCB Controller ........................................................................................................ 332
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3.10.2 Programming Examples ................................................................................... 334
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3.11 I2C/SCCB Controller (I2C_SCCB_Controller_V18) ......................................................... 345

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3.11.2 Programming Examples ................................................................................... 347

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3.12 Real Time Clock ............................................................................................................... 358
3.12.1 General Descriptions ........................................................................................ 358

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3.13 Auxiliary ADC Unit ............................................................................................................ 373

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3.13.2 General Programming Guide ........................................................................... 384
3.13.3 Usage Programming Guide .............................................................................. 384

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3.13.4 Performance Programming Guide ................................................................... 384
3.13.5 AUXADC PDN .................................................................................................. 385

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3.13.6 Notice ............................................................................................................... 385
3.14 USB Device Controller ...................................................................................................... 385

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3.14.2 Terminology...................................................................................................... 386
3.14.4 System Integration Guide ................................................................................. 402
3.15 Accessory Detector .......................................................................................................... 403


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3.15.2 Pulse Width Modulation ................................................................................... 405
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3.16 SD Memory Card Controller (MSDC0) ............................................................................. 415
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3.16.1 Introduction ....................................................................................................... 415
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3.16.2 Overview .......................................................................................................... 415
3.17 SD Memory Card Controller (MSDC1) ............................................................................. 441
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3.17.1
3.17.2
Introduction ....................................................................................................... 441
Overview .......................................................................................................... 442

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3.18 BTIF .................................................................................................................................. 468

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4 GPS ............................................................................................................................................ 475

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4.1 RF Part ............................................................................................................................. 475

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4.1.1 LNA/Mixer ......................................................................................................... 475
4.1.2 VCO/Synthesizer .............................................................................................. 475
4.1.3 LPF ................................................................................................................... 475

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4.1.4 ADC .................................................................................................................. 475
4.2 Digital Part ........................................................................................................................ 476

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4.2.1 ARM7EJ-S ........................................................................................................ 476
4.2.2 Cache ............................................................................................................... 476

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4.2.3 Boot ROM ......................................................................................................... 476
4.2.4 Real Time Clock (RTC) .................................................................................... 476
4.2.5 SMPS ............................................................................................................... 477
4.2.6 Timer function ................................................................................................... 477
4.2.7 GPIO in RTC domain ....................................................................................... 477


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4.2.8 Low power detection ........................................................................................ 477
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4.2.9 Clock module .................................................................................................... 477
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4.2.10 Reset controller ................................................................................................ 478
4.2.11 Host interface ................................................................................................... 479
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4.2.12 Interrupt control unit ......................................................................................... 479
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4.2.13 Flash ................................................................................................................. 479
4.2.14 GPIO unit .......................................................................................................... 480
4.2.15 PPS .................................................................................................................. 480
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4.2.16
4.2.17
ECLK ................................................................................................................ 480
SYNC ............................................................................................................... 480

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4.2.18 Power scheme.................................................................................................. 481
4.3 Electrical Characteristics .................................................................................................. 483

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4.3.1 DC characteristics ............................................................................................ 483
4.3.2 Analog related characteristics .......................................................................... 486

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4.3.3 RF related characteristics ................................................................................ 487

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4.4 Interface Characteristics ................................................................................................... 488
4.4.1 JTAG interface timing ....................................................................................... 488

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4.4.2 RS-232 interface timing .................................................................................... 489
4.4.3 SPI interface timing .......................................................................................... 490

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4.4.4 I2C interface timing .......................................................................................... 490

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Lists of Tables and Figures
Table 1. Pin coordinates ........................................................................................................................ 28

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Table 2. Acronym for pin types .............................................................................................................. 31

Table 3. PIN function description and power domain ............................................................................ 31
Table 4. Acronym for state of pins ......................................................................................................... 41
Table 5. State of pins ............................................................................................................................. 41
Table 6. Acronym for pull-up and pull-down types ................................................................................ 45
Table 7. Capability of PU/PD, driving and Schmitt trigger ..................................................................... 45
Table 8. Absolute maximum ratings for power supply ........................................................................... 52
Table 9. Absolute maximum ratings for voltage input ........................................................................... 53
Table 10. Absolute maximum ratings for storage temperature ............................................................. 53


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Table 11. Recommended operating conditions for power supply ......................................................... 53
Table 12. Recommended operating conditions for voltage input .......................................................... 53
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Table 13. Recommended operating conditions for operating temperature ........................................... 54
Table 14. Electrical characteristics ........................................................................................................ 54
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Table 15. Strapping table ...................................................................................................................... 61
Table 16. Mode selection of chip ........................................................................................................... 61
Table 17. APC-DAC specifications ........................................................................................................ 65
Table 18. Functional specifications of auxiliary ADC ............................................................................ 66
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Table 19. Functional specifications of analog voice blocks ................................................................... 68
Table 20. Functional specifications of analog audio blocks .................................................................. 69
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Table 21. LDO types and brief specifications ........................................................................................ 72
Table 22. Analog LDO specifications .................................................................................................... 73
Table 23. Digital LDO specifications ..................................................................................................... 73
Table 24. RTC LDO specification .......................................................................................................... 74
Table 25. RTC LDO specification. ......................................................................................................... 74
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Table 26. ISINKs and KPLED Switches Specification. ......................................................................... 75
Table 27. Charger detection specifications ........................................................................................... 80
Table 28. Pre-charge specifications ...................................................................................................... 80
Table 29. Constant current specifications ............................................................................................. 80
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Table 30. Constant voltage and over-voltage protection specifications ................................................ 81
Table 31. BC1.1 specifications .............................................................................................................. 81
Table 32. DC characteristics (TA = 25oC, VDD = 2.8V unless otherwise stated) ................................. 83
Table 33. Rx AC characteristics (TA = 25oC, VDD = 2.8V unless otherwise stated) ............................ 84
Table 34. Tx GMSK AC characteristics (TA = 25oC, VDD = 2.8V unless otherwise stated) ................. 85
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Table 35. SX AC characteristics (TA = 25oC, VDD = 2.8V unless otherwise stated) ........................... 86
Table 36. DCXO AC characteristics (TA = 25oC, VDD = 2.8V unless otherwise stated) ...................... 86
Table 37. Basic data rate – receiver specifications ............................................................................... 88
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Table 38. Basic data rate – transmitter specification ............................................................................ 88

Table 39. Enhanced data rate – receiver specifications ....................................................................... 89
Table 40. Enhanced data rate – transmitter specifications ................................................................... 89
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Table 41. FM receiver DC characteristics (TA=25°C, VDD=2.8V unless otherwise stated) ................. 91
Table 42. FM receiver AC characteristics .............................................................................................. 91
Table 43. Time-out condition for answering to reset sequence ........................................................... 119
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Table 44. 5*5 double KEY’s order number in COL/ROW matrix ......................................................... 132
Table 45. 5*5 triple KEY’s order number in COL/ROW matrix ............................................................ 132
Table 46. Abbreviations ....................................................................................................................... 274
Table 47. Wakeup sources .................................................................................................................. 275
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Table 48. Characteristics of wakeup sources ...................................................................................... 275

Table 49. Relationship between commands and touch panel control signals .................................... 375
Table 50. Sharing of pins for SD memory card controller ................................................................... 415
Table 51. Sharing of pins for SD memory card controller ................................................................... 442
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Table 52. IIR[5:0] codes associated with the possible interrupts ........................................................ 470
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Figure 1. Typical application of MT2503D ............................................................................................. 15
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Figure 2. MT2503D block diagram ........................................................................................................ 27
Figure 3. Ball diagram and top view ...................................................................................................... 28
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Figure 4. IO types in state of pins ......................................................................................................... 44
Figure 5. Power-on/off control sequence by pressing PWRKEY and XOSC32_ENB = 0 .................... 62
Figure 6. Power-on/off control sequence by pressing PWRKEY and XOSC32_ENB = 1 .................... 63
Figure 7. Block diagram of audio mixed-signal blocks .......................................................................... 68
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Figure 8. PMU system block diagram ................................................................................................... 70
Figure 9. Power domain ........................................................................................................................ 71
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Figure 10. LDO block diagram .............................................................................................................. 72
Figure 11. ISINKs and KPLED switches bock diagram......................................................................... 75
Figure 12. PCHR block diagram. .......................................................................................................... 77
Figure 13. Charging states diagram ...................................................................................................... 78
Figure 14. Diagram of MT2503D 2G RFSYS........................................................................................ 83
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Figure 15. System diagram of Bluetooth RF transceiver ...................................................................... 87
Figure 16. Block diagram of hardware top-level architecture ............................................................... 91
Figure 17. Outlines and dimension of VFBGA 8.4mm*6.2mm, 215-ball, 0.4 mm pitch package ......... 94
Figure 18. Mass production top marking of MT2503D .......................................................................... 95
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Figure 19. PWM waveform .................................................................................................................... 96
Figure 20. PWM waveform with register values.................................................................................... 97
Figure 21. Block diagram of SIM interface .......................................................................................... 101
Figure 22. Timing diagram of SIM interface ........................................................................................ 103
Figure 23. Answering to reset sequence ............................................................................................. 119
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Figure 24. 5x5 double keypad matrix (50 keys) .................................................................................. 123
Figure 25. 5x5 triple keypad matrix (75 keys) ..................................................................................... 124
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Figure 26. 5*5 double keypad scan waveform .................................................................................... 124

Figure 27. One key pressed with de-bounce mechanism denoted .................................................... 125
Figure 28. (a) Two keys pressed, case 1; (b) Two keys pressed, case 2 ........................................... 125
Figure 29. kp timing register................................................................................................................ 131
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Figure 30. GPIO block diagram .......................................................................................................... 133

Figure 31. OS timer system view ........................................................................................................ 274
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Figure 32. Wakeup event and Irq_b integration diagram .................................................................... 276
Figure 33. Pause command complete and pause request state ........................................................ 280
Figure 34. Debug wakeup events ....................................................................................................... 286
Figure 35. Block Diagram of UART1 ................................................................................................... 287
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Figure 38. AUXADC architecture ........................................................................................................ 373
Figure 39. Touch panel circuit structure .............................................................................................. 374
Figure 40. Touch panel sampling waveform ....................................................................................... 375
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Figure 41. Suggested Accessory Detection Circuit. ............................................................................ 404

Figure 42. The Sate machine between Microphone and Hook-Switch plug-in/out change. ............... 405
Figure 43. PWM waveform.................................................................................................................. 405
Figure 44. PWM waveform with register value present ...................................................................... 408
Figure 45. Card detection for SD memory card .................................................................................. 416
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Figure 46. Card detection for SD memory card .................................................................................. 443

Figure 47. Card detection for SD memory card (Scheme 2) .............................................................. 443
Figure 48. Interface connection between BT and baseband system .................................................. 468
Figure 49. RTC with internal RTC LDO application circuit 1 ............................................................... 476
Figure 50. RTC with internal RTC LDO application circuit 2 ............................................................... 477
Figure 51. Power on reset diagram ..................................................................................................... 478
Figure 52. Power on/off reset behavior ............................................................................................... 478
Figure 53. Flow diagram of SYNC function ......................................................................................... 480


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Figure 54. Power supply connection (low power) ............................................................................... 481
Figure 55. Power supply connection (low cost) .................................................................................. 482
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Figure 56. Power supply connection (external LDO) .......................................................................... 482
Figure 57. Power on/off sequence for external LDO mode ................................................................ 483
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Figure 58. Timing diagram of JTAG interface ..................................................................................... 489
Figure 59. Timing diagram of RS-232 interface .................................................................................. 489
Figure 60. Timing diagram of SPI interface......................................................................................... 490
Figure 61.Timing diagram of HOST I2C interface ............................................................................... 491
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1 System Overview
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MT2503D is a monolithic chip integrating security digital rights management for copyright
leading edge power management unit, analog protection. For further safeguard and to protect
baseband and radio circuitry based on the low- the manufacturer’s development investment,
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power CMOS process. hardware flash content protection is provided to
prevent unauthorized porting of the software
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MT2503D is a feature-rich and extremely load.
powerful single-chip solution for high-end
GSM/GPRS capability. Based on the 32-bit Memory
TM
ARM7EJ-S
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RISC processor, MT2503D’s
superb processing power, along with high
bandwidth architecture and dedicated hardware
support, provides a platform for high-
MT2503D supports serial flash interface with
various operating frequencies.
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Multimedia
performance GPRS Class 12 MODEM
The MT2503D multimedia subsystem provides
application and leading-edge multimedia
serial interface for CMOS sensors. The camera
applications.
resolution is up to VGA size. The software-
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based codec can be used to process various

MT2503D also features:
video types. To take advantage of the high MCU
 A highly integrated Bluetooth transceiver
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performance, GIF and PNG decoders are

which is fully compliant with Bluetooth
implemented by the software.
specification v3.0.
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 A FM receiver supporting both audio In addition, MT2503D is implemented with a

broadcast de-modulation and RDS/RBDS high-performance audio synthesis technology,
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data decoding. as well as a high-quality audio amplifier to

provide superior audio experiences.
Typical application diagram is shown in Figure 1.
Connectivity and storage
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Platform MT2503D supports UART, USB 1.1 FS/LS ,

MT2503D is capable of running the ARM7EJ- SDIO and SD storage systems. These
TM
S RISC processor, which provides the best interfaces provide MT2503D users with the
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trade-off between system performance and highest level of flexibility in implementing high-
power consumption. end solutions.
For large amounts of data transfer, high- To achieve a complete user interface, MT2503D
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performance DMA (Direct Memory Access) with also brings together all the necessary peripheral
hardware flow control is implemented, which blocks for a multimedia GSM/GPRS phone. The
greatly enhances the data movement speed peripheral blocks include the keypad scanner
while reducing the MCU processing load. with the capability to detect multiple key presses,
SIM controller, real-time clock, PWM, serial LCD
Targeted as a media-rich platform for mobile
applications, MT2503D also provides hardware


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controller and general-purpose programmable reduction. In addition, the minimum component
I/Os. count is guaranteed by realizing a highly
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integrated transmitter, low-spur frequency
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Audio synthesizer and a Digitally-Controlled Crystal
Using a highly integrated mixed-signal audio Oscillator (DCXO).
front-end, the MT2503D architecture provides
easy audio interfacing with direct connection to
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GPS
the audio transducers. The audio interface
A high-performance single-chip multi-GNSS
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integrates A/D converters for voice band, as well
solution which includes on-chip CMOS RF,
as high-resolution stereo D/A converters for both
digital baseband, ARM7 CPU and an embedded
audio and voice band.
NOR flash. It is able to achieve the industry’s
highest level of sensitivity, accuracy and Time-
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MT2503D supports AMR codec to adaptively
optimize the quality of speech and audio.
Moreover, HE-AAC codec is implemented to
to-First-Fix (TTFF) with the lowest power
consumption in a small-footprint lead-free
package. Its small footprint and minimal BOM
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deliver CD-quality audio at low bit rates.
requirement provide significant reductions in the
design, manufacturing and testing resource
In addition, an 1.2W audio amplifier is also required for portable applications.
embedded to save the BOM cost of adopting
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With built-in LNA to reach total receiver chain

external amplifiers.
NF to 2.2 dB, you can eliminate antenna
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requirement and do not need external LNA. It

GSM/GPRS radio also up to 12 multi-tone active interference
MT2503D integrates a mixed-signal baseband cancellers (ISSCC2011 award) offer you more
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front-end in order to provide a well-organized flexibility in system design.

radio interface with flexibility for efficient
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customization. The front-end contains gain and

MT2503D acquires and tracks satellites in the
offset calibration mechanisms and filters with
shortest time even at indoor signal levels. In
programmable coefficients for comprehensive
addition, MT2503D supports various location
compatibility control on RF modules. MT2503D
and navigation applications, including
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achieves outstanding MODEM performance by

autonomous GPS, GLONASS, GALILEO,
utilizing a highly dynamic range ADC in the RF
BEIDOU(after ICD released), SBAS ranging
downlink path.
(WAAS, EGNOS, GAGAN, and MSAS), QZSS,
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DGPS (RTCM) and AGPS.

MT2503D embeds a high-performance and
completely integrated single-ended SAW-less
Bluetooth radio
RF transceiver for multi-band GSM cellular
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MT2503D offers a highly integrated Bluetooth

system. In this RF transceiver, a quad-band
radio and baseband processor. Only a minimum
receiving feature with high sensitivity is
of external components are required. MT2503D
supported utilizing one RF receiver and a fully
provides superior sensitivity and class 1 output
integrated channel filter. With ultra-high dynamic
power and thus ensures the quality of the
range, the off-chip balun and SAW filters on the
receiving path can be removed for BOM cost


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connection with a wide range of Bluetooth The JTAG interface enables in-circuit debugging
TM
devices. of the software program with the ARM7EJ-S
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core. With this standardized debugging interface,
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MT2503D is fully compliant with Bluetooth v3.0 MT2503D provides developers with a wide set
and offers enhanced data rates of up to 3Mbps. of options in choosing ARM development kits
It also provides the coexistence protocol with from different third party vendors.
802.11 system.
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Power management
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MT2503D supports rich Bluetooth profiles, A power management is embedded in MT2503D
enabling diversified applications that are widely to provide rich features a high-end feature
used on the handset with excellent phone supports, including Li-ion battery charger,
interoperability. high performance and low quiescent current
FM radio
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The FM radio subsystem provides a completely
LDOs, and drivers for LED and backlight.
MT2503D offers various low-power features to

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integrated FM Rx receiver supporting 65 ~ help reduce the system power consumption.
108MHz FM bands with 50kHz tuning step. In MT2503D is also fabricated in an advanced low-
addition to receiving FM audio broadcasting, the power CMOS process, hence providing an
digital RDS/RBDS data system is supported as overall ultra-low leakage solution.
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well. The integrated FM transceiver utilizes

state-of-the-art digital demodulation/modulation Package
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techniques to achieve excellent performance. The MT2503D device is offered in a

8.4mm×6.2mm, 215-ball, 0.4mm pitch, VFBGA
In order to achieve high SINAD, good sensitivity package.
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and excellent noise suppression, the FM

receiver adopts adaptive demodulation scheme
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to optimize Rx system performance in all ranges

of signal quality by reference of a very
sophisticated channel quality index (CQI). When
the received signal quality is poor, the design
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not only enhances the ACI rejection capability

but also uses a very ingenious skill to soft mute
annoying noise so as to provide good
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perception quality.
The FM radio subsystem supports both long

antenna, which is usually an earphone, and
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auto-calibrated short antenna, which is usually a

FPC short antenna or shared antenna with GSM
for different application scenarios.
Debugging function


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SD SIM2 SIM1 USB 1.1 F/S
SDIO USIM USIM DEVICE
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1 2 3
4 5 6 KEYPAD RF
7 8 9 LCD
INTERFACE
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* 0 #
APC
PA SW
SPEECH/AUDIO
BPI
OUTPUT (PCM
INTERFACE)
SUPPLY
MT2503D VOLTAGES
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LCD
POWER
MANAGEMENT
CIRCUITRY
CHARGER
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CHIP RID
PWM
LCD
AUXADC
SPEECH/AUDIO
INPUT
FM STEREO
SDIO INTERFACE
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RADIO INPUT
I2S I2C CAM HIFI STEREO

INTERFACE INTERFACE UART JTAG OUTPUT
WI FI
5931
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AUDIO
4-SIM CMOS DEBUGGER

DAC
6306 SENSOR
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Figure 1. Typical application of MT2503D

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1.1 Platform Features
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General
 Integrated voice-band, audio-band and Connectivity
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base-band analog front-end  3 UARTs with hardware flow control and
 Integrated full-featured power management supports baud rate up to 921,600 bps
unit  FS/LS USB 1.1 device controller
 Multimedia card, secure digital Memory
MCU subsystem


ARM7EJ-S .co ID
TM
32-bit RISC processor
Java hardware acceleration for fast Java- 
Card, host controller with flexible I/O voltage
power
Supports 4-bit SDIO interface for SDIO
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based games and applets peripherals as well as WIFI connectivity
 High-performance multi-layer AHB bus  DAI/PCM and I2S interface for audio
 Dedicated DMA bus with 16 DMA channels applications
 
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On-chip boot ROM for factory flash I2C master interface for peripheral
programming management including image sensors
 Watchdog timer for system crash recovery  SPI master/slave interface for peripheral
u@ C
 3 sets of general-purpose timers management.

 Division coprocessor
.Li K
Power management
User interfaces  Li-ion battery charger

no TE
 5-row x 5-column keypad controller with 13 LDOs for the power supply of memory
hardware scanner card, camera, Bluetooth, RF, SIM card and
 Supports multiple key presses for gaming other diversified usage
 Dual SIM/USIM controller with hardware T =  1 open-drain output switches to
Ar IA
0/T = 1 protocol control supply/control the LED

 Real-time clock (RTC) operating with a low-  LDO type vibrator
quiescent-current power supply  One NMOS switch to control keypad LED
R ED
 General-purpose I/Os (GPIOs) available for  Thermal overload protection

auxiliary applications  Under-voltage lock-out protection
 2 sets of Pulse Width Modulation (PWM)  Over-voltage protection
output  Different levels of power-down modes with
FO M
 24 external interrupt lines sophisticated software control enables

 1 external channel auxiliary 10-bit A/D excellent power saving performance.
converter
Test and debugging
Security  Built-in digital and analog loop back modes
 Supports security key and chip random ID for both audio and baseband front-end


MT2503D
Y
Confidential A
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 DAI port complies with GSM Rec.11.10.

US IAL
JTAG port for debugging embedded MCU
EO
hk T
m. EN
.co ID
sac NF
O
u@ C
.Li K
no TE
Ar IA
R ED
FO M


MT2503D
Y
Confidential A
NL
US IAL
EO
1.2 MODEM Features
hk T
Radio interface and baseband front-end  Supports SAIC (single antenna interference
 Digital PM data path with baseband front- cancellation) technology
m. EN
end  Supports VAMOS(Voice services over
 High dynamic range delta-sigma ADC Adaptive Multi-user channels on One Slot)
converts the downlink analog I and Q technology in R9 spec.
signals to digital baseband.


.co ID
10-bit D/A converter for Automatic Power
Control (APC)
Programmable radio Rx filter with adaptive
Voice interface and voice front-end
 Microphone input has one low-noise
amplifier with programmable gain and
sac NF
gain control Automatic Gain Control (AGC) mechanisms
 Dedicated Rx filter for FB acquisition  Voice power amplifier with programmable
 6-pin Baseband Parallel Interface (BPI) with gain

nd
O
programmable driving strength 2 order Sigma-Delta A/D converter for

 Supports multi-band voice uplink path
 Shares D/A converter with audio playback
u@ C
Voice and modem CODEC path

 Dial tone generation  Supports full-duplex hands-free operation
.Li K
 Voice memo  Compliant with GSM 03.50

 Noise reduction
no TE
 Echo suppression
 Advanced sidetone oscillation reduction
 Digital sidetone generator with
programmable gain
Ar IA
 Two programmable acoustic compensation

filters
 Supports GSM/GPRS modem
R ED
 GSM quad vocoders for adaptive multirate

(AMR), enhanced full rate (EFR), full rate
(FR) and half rate (HR)
 GSM channel coding, equalization and A5/1,
FO M
A5/2 and A5/3 ciphering

 GPRS GEA1, GEA2 and GEA3 ciphering
 GPRS packet switched data with
CS1/CS2/CS3/CS4 coding schemes
 GPRS Class 12


MT2503D
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Confidential A
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EO
1.3 GSM/GPRS RF Features
hk T
Receiver
 Dual single-ended LNAs support Quad
m. EN
bandQuadrature RF mixer
 Fully integrated channel filter
 High dynamic range ADC
 12dB PGA gain with 6dB gain step
Transmitter

.co ID
Transmitter outputs support quad bands.
sac NF
 Highly precise and low noise RF transmitter
for GSM/GPRS applications
O
Frequency synthesizer
 Programmable fractional-N synthesizer
 Integrated wide range RFVCO
u@ C
 Integrated loop filter

 Fast settling time suitable for multi-slot
.Li K
GPRS applications
no TE
Digitally-Controlled Crystal Oscillator (DCXO)

 Two-pin 26MHz crystal oscillator
 On-chip programmable capacitor array for
coarse-tuning
Ar IA
 On-chip programmable capacitor array for

fine-tuning
 Low power mode supports 32K crystal
R ED
removal
FO M


MT2503D
Y
Confidential A
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US IAL
EO
1.4 Multimedia Features
hk T
LCD controller  High throughput hardware scaler. Capable
 Supports simultaneous connection to seral 2 of tailoring an image to an arbitrary size.
m. EN
lane LCD modules  Horizontal scaling with bilinear interpolation
 LCM formats supported: RGB565, RGB666,  Vertical scaling with bilinear interpolation
RGB888  YUV and RGB color space conversion
 Supports LCD module with maximum  RGB/YCbCr format thumbnail output


.co ID
resolution up to 320x240
Per pixel alpha channel
True color engine
MPEG-4/H.263 CODEC
 Software-based MPEG4 encoder
sac NF
 Supports hardware display rotation  Software-based MPEG4 decoder
 Capable of combining display memories  ISO/IEC 14496-2 simple profile:
with up to 4 blending layers  Decode spec: 480x320@25fps
O
 Encode spec: QVGA@15fps

Camera interface  ISO/IEC 14496-2 advanced simple profile:
 YUV422 format image input  Decode @ level 0/1/2/3
u@ C
 Capable of processing image of size up to  ITU-T H.263 profile 0 @ level 40

VGA (Mediatek serial interface)  Supports visual tools for decoder: I-VOP, P-
.Li K
VOP, B-VOP, AC/DC prediction, 4-MV,

JPEG decoder unrestricted MV, error resilience, short

no TE
Baseline JPEG decoding header, global motion compensation,

 Supports various YUV formats, DC/AC method 1/2 quantization, quarter-pel motion
Huffman tables and quantization tables
compensation.
JPEG encoder  Error resilience for decoder: Slice
Ar IA
 ISO/IEC 10918-1 JPEG baseline mode resynchronization, data partitioning,

 ISO/IEC 10918-2 compliance reversible VLC
 Supports YUV420 and grayscale formats  Supports visual tools for encoder: I-VOP, P-
R ED
 Supports EXIF/JFIF VOP, Half-Pel, DC prediction, unrestricted

 Standard DC and AC Huffman tables
MV, short header
 Provides 5 levels of encode quality
 Supports zeros shutter delay
H.264
FO M
 ISO/IEC 14496-10 baseline profile

MJPEG  Decode spec: QCIF@30fps
 Decode spec: CIF@30fps
 Encode spec: QVGA@15fps 2D accelerator
 Supports 32-bpp ARGB8888, 24-bpp
Image data processing RGB888, 16-bpp RGB565, 24-bpp
 Supports 4x digital zoom ARGB6666.


MT2503D
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 4 layers overlay with individual color format,
window size, source key, constant alpha and
US IAL
rotation
EO
 Rectangle fill with constant
 BitBlt: Capable with 7 rotation types
 Alpha blending with 7 rotation types, per-
hk T
pixel alpha and pre-multiplied alpha
 Font drawing: Normal font and anti-aliasing
m. EN
font
Audio CODEC
 Supports AAC codec decoding

 .co ID
Wavetable synthesis with up to 64 tones
Advanced wavetable synthesizer capable of
generating simulated stereo
sac NF
 Wavetable including GM full set of 128
instruments and 47 sets of percussions
 PCM playback and record
 Digital audio playback
O
Audio interface and audio front-end

u@ C
 Supports I2S interface

 High-resolution D/A converters for stereo
.Li K
audio playback
 Voice band A/D converter support
 Stereo to mono conversion
no TE
Ar IA
R ED
FO M


MT2503D
Y
Confidential A
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US IAL
EO
1.5 Bluetooth Features
hk T
Radio features  Channel quality driven data rate adaptation
 Fully compliant with Bluetooth specification  Channel assessment for AFH
m. EN
3.0
 Low out-of-band spurious emissions support Platform features
simultaneous operation with GPS and  Embedded processor for Bluetooth protocol
GSM/GPRS worldwide radio systems stack with built-in memory system


.co ID
Low-IF architecture with high degree of
linearity and high order channel filter
Integrated T/R switch and Balun
 Fully verified ROM based system with code
patch for feature enhancement
sac NF
 Fully integrated PA provides 7.5dBm output
power
 -95dBm sensitivity with excellent
O
interference rejection performance

 Hardware AGC dynamically adjusts receiver
performance in changing environments
u@ C
Baseband features
.Li K
 Up to 4 simultaneous active ACL links

 Up to 1 simultaneous SCO or eSCO link
no TE
with CVSD coding

 Supports eSCO
 Scatternet support: Up to 4 piconets
simultaneously with background
Ar IA
inquiry/page scan
 Supports sniff mode
 AFH and PTA collaborative support for
R ED
WLAN/BT coexistence
 Idle mode and sleep mode enables ultra-low
power consumption.
 Supports PCM interface and built-in
FO M
programmable transcoders for linear voice

with re-transmission
 Built-in hardware modem engine for access
code correlation, header error correction,
forward error correction, CRC, whitening
and encryption


MT2503D
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Confidential A
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US IAL
EO
1.6 FM Features
hk T
 65-108MHz worldwide FM bands with
50KHz tuning step
m. EN
 Supports RDS/RBDS radio data system
 Digital stereo demodulator
 Adaptive FM demodulator for both high- and
low-quality scenarios


Low
.co ID
sensitivity
interference rejection
Programmable
level with superior
de-emphasis
sac NF
 Stereophonic multiplex signal (MPX) signal
detection and demodulation

O
Superior stereo noise reduction and soft

mute volume control

u@ C
Audio dynamic range control

 Mono/stereo blending
 Audio sensitivity3dBµVemf (SINAD=26dB)
.Li K
 Audio SINAD≥60dB
 Supports Anti-jamming algorithm
no TE
 Supports short antenna

Ar IA
R ED
FO M


MT2503D
Confidential A
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NL
US IAL
EO
1.7 GPS feature
Specifications
hk T
ARM7EJ-S CPU
 GPS/GLONASS/GALILEO/BEIDOU(after
 Up to 158 MHz processor clock
m. EN
ICD released) receiver
 Dynamic clock rate control
 Supports multi-GNSS incl. QZSS, SBAS
ranging
Pulse-per-second (PPS) GPS time
 Supports WAAS/EGNOS/MSAS/GAGAN
reference


.co ID
12 multi-tone active interference cancellers
(ISSCC2011 award)
RTCM ready


Adjustable duty cycle
Typical accuracy: ±10 ns
sac NF
 Indoor and outdoor multi-path detection
Power scheme
and compensation
 A 1.8 volts SMPS build-in SOC
 Supports FCC E911 compliance and A-
 Direct lithium battery connection (2.8 ~ 4.3
GPS
O
volts)
 Max. fixed update rate up to 10 Hz
 Self build 1.1 volts RTC LDO, 1.1 volts
u@ C
core LDO, and 2.8 volts TCXO LDO

Advanced software features
 AlwaysLocateTM advanced location
Build-in reset controller
awareness technology
.Li K
 Does not need external reset control IC

 EPOTM/HotStillTM orbit prediction
 EASYTM self-generated orbit prediction
no TE
Internal real-time clock (RTC)

 Supports logger function
 32.768 KHz ± 20 ppm crystal
 Supports time service application which
 1.1 volts RTC clock output
can be achieved by PPS VS. NMEA
 Supports external pin to wake up
Ar IA
feature.
Backup mode
Reference oscillator
 A Force_On pin to ease backup mode

R ED
TCXO
application circuit
Frequency: 16.368 MHz, 12.6 ~ 40.0 MHz
Frequency variation: ±2.5 ppm
Serial interface
 Crystal
 3 UARTs
FO M
Frequency: 26 MHz, 12.6 ~ 40.0 MHz

 SPI, I2C
Frequency accuracy: ±10 ppm
 GPIO interface (up to 16 pins)
RF configuration
NMEA
 SoC, integrated in single chip with CMOS
 NMEA 0183 standard V4.1 and backward
process
compliance
 Supports 219 different data


MT2503D
Confidential A
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Superior sensitivities
 Acq.: -148 dBm (cold) / -163 dBm (hot)
US IAL
 Tracking: -165 dBm
EO
Ultra-low power consumption
(GPS+GLONASS)
 Acquisition: 37 mW
hk T
 Tracking: 27 mW
 AlwaysLocateTM: 3.0 mW
m. EN
hardware design
 9 passive external components

.co ID
Single RF Front-End
frequency bands
for Multi-GNSS
sac NF
O
u@ C
.Li K
no TE
Ar IA
R ED
FO M


MT2503D
Y
Confidential A
NL
US IAL
EO
1.8 General Descriptions
hk T
Figure 2 is the block diagram of MT2503D.  Audio front-end: Data path for converting
Based on a multi-processor architecture, stereo audio from an audio source
m. EN
TM
MT2503D integrates an ARM7EJ-S core, the  Baseband front-end: Data path for
main processor running high-level GSM protocol converting a digital signal to and from an
software as well as multimedia applications, analog signal from the RF modules
single digital signal processor core, which  Timing generator: Generates the control
.co ID
manages the low-level MODEM and advanced
audio functions, an embedded processor
running Bluetooth baseband and link control

signals related to the TDMA frame timing
Power, reset and clock subsystem: Manage
the power, reset and clock distribution
sac NF
protocol and the Bluetooth radio control. inside MT2503D.
 Bluetooth subsystem: Includes an
MT2503D consists of the following subsystems: embedded processor with embedded
 Microcontroller Unit (MCU) subsystem:
O
ROM/RAM system, baseband processor,

TM
Includes an ARM7EJ-S RISC processor and a high-performance radio block
and its accompanying memory  Power management unit: Self-contained
u@ C
management and interrupt handling logics power supply source which also controls
 Digital Signal Processor (DSP) subsystem: the charging and system startup circuitry.
Includes a DSP and its accompanying
.Li K
memory, memory controller and interrupt Details of the individual subsystems and blocks
controller are described in the following chapters.
no TE
 MCU/DSP interface: Junction at which the

MCU and the DSP exchange hardware and
software information

Ar IA
Microcontroller peripherals: Include all user

interface modules and RF control interface
modules

R ED
Microcontroller coprocessors: Run

computing-intensive processes in place of
the microcontroller
 DSP peripherals: Hardware accelerators for
FO M
GSM/GPRS channel codec

 Multimedia subsystem: Integrates several
advanced accelerators to support
multimedia applications
 Voice front-end: Data path for converting
analog speech to and from digital speech


MT2503D
Confidential A
Y
NL
US IAL
EO
hk T
m. EN
.co ID
sac NF
O
5x5 Qwerty SD/SDIO

GPS UART USB1.1 I2C
Keypad Card
u@ C
MT2503D
UART UART USB11 I2C Keypad SD/SDIO SIM1 SIM Card

Peripherals
MCU SIM2 SIM Card

.Li K
DSP JTAG
ICE
PMU
Internal ARM7EJS
no TE
Internal Memory
DMA
Memory
Speaker GPIO
DMA GPIO
AFE Interrupt
Voice in Analog Baseband VFE Controller
Interrupt Boot
Touch GPTimer
Panel BFE
DS Controller ROM
P
Ar IA
Multimedia JPEG LCD QVGA

PA/ASW RF CODEC Control LCD
Scaler
BLUESY Internal memory
R ED
BT RF S Image
DMA
Camer 2D
FM RF FMSYS a INT
FO M
VGA
Camera
Figure 2. MT2503D block diagram


MT2503D
Confidential A
Y
NL
2 Product Descriptions
US IAL
EO
2.1 Pin Description
2.1.1 Ball Diagram
hk T
For MT2503D, an VFBGA 8.4mm*6.2mm, 215-ball, 0.4mm pitch package is offered. Pin-outs and the
top view are illustrated in Figure 3 for this package.
m. EN
.co ID
sac NF
O
u@ C
.Li K
no TE
Ar IA
Figure 3. Ball diagram and top view

R ED
2.1.2 Pin Coordination

Table 1. Pin coordinates
FO M
Pin# Net name Pin# Net name Pin# Net name

A1 RXLB E12 GPIO_7 K9 MCDA1
A2 AVSS_2GHF E17 GPS_DVDD28_SF K10 MCCK
A3 SRCLKENAI E18 GPS_TX1 K16 GPS_RX0
A5 AVSS_2GHF E19 GPS_AVDD28_TLDO K17 GPS_RX2
A6 BT_LNA E20 GPS_AVDD28_CLDO K19 GPS_T1P


MT2503D
Confidential A
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A8 VIO28 F2 FM_ANT_P K20 GPS_T1N
US IAL
A10 BPI_BUS2 F4 PWRKEY L1 AVSS44_BOOST
EO
A12 SCL28 F5 GND L2 AVSS44_BOOST
A13 CMRST F6 GND L3 AU_HPL
A15 CMMCLK F13 GPS_DVSS11_CORE L4 ACCDET
hk T
A16 CMCSD0 F14 GPS_DVSS11_CORE L5 LSCE_B
A17 GPS_XIN F15 GPS_DVSS28_SF L6 TESTMODE_D
m. EN
A18 GPS_XOUT F17 GPS_JCK L7 RESETB
A19 GPS_AVDD43_RTC F19 GPS_AVDD_TCXO_SW L8 LPTE
A20 GPS_AVDD43_DCV G1 VREF L10 MCDA0
B1
B2
B3
.co ID RXHB
TX_LB
AVSS_2GHF
G2
G3
G4
AVSS_FM
CHRLDO
BATON
L11
L12
L13
MCDA3
VMC
VSIM2
sac NF
B4 XTAL1 G5 GND L14 GPS_JRST_
B5 XTAL2 G6 GND L17 GPS_JDI
B6 AVSS_2GHF G7 GND L18 GPS_DVDD28_IO2
O
B7 AVDD15_BTRF G8 GND L19 GPS_HRST_B

B8 BPI_BUS1 G9 GND M1 AVDD_SPK
u@ C
B10 BPI_BUS0 G10 GND M2 AU_HPR

B11 VDDK G13 GPS_DVSS11_CORE M3 AVSS28_ABB
B12 SDA28 G14 GPS_DVSS11_CORE M4 AU_VIN0_P
.Li K
B13 GPIO_3 G15 GPS_DVSS11_CORE M5 AU_VIN0_N

B14 GPIO_2 G16 GPS_DVSS11_CORE M7 LSA0
no TE
B15 CMCSD1 G17 GPS_TX2 M8 LSDA

B16 CMCSK G18 GPS_RX1 M11 MCDA2
B18 GPS_DVSS11_CORE G19 GPS_AVDD43_VBAT M13 SIM2_SCLK
Ar IA
B19 GPS_DCV_FB G20 GPS_AVSS43_MISC M14 SIM2_SRST

B20 GPS_AVSS11_CLDO H1 BATSNS M16 GPS_TX0
C2 TX_HB H2 ISENSE M17 GPS_JRCK
R ED
C3 EINT H3 VCDT M18 GPS_SCS1_

C5 FREF H4 KPLED M19 GPS_XTEST
C8 KCOL1 H5 GND M20 GPS_AVSS_RF
FO M
C9 KROW1 H6 GND N1 SPK_OUTN

C10 KROW2 H7 GND N2 AVSS_SPK
C13 GPIO_0 H8 GND N3 AU_HSP
C15 CMPDN H9 GND N4 AU_HSN
C16 GPS_DVDD11_CORE1 H10 GND N5 AU_VIN1_N
C17 GPS_FORCE_ON H11 GND N6 AU_MICBIAS0


MT2503D
Confidential A
Y
NL
C19 GPS_DCV H13 GPS_DVSS11_CORE N7 APC
US IAL
C20 GPS_AVSS43_DCV H14 GPS_DVSS11_CORE N8 AVSS44_DLDO
EO
D1 VRF H15 GPS_DVSS11_CORE N9 VIBR
D2 AVSS_2GHF H16 GPS_DVSS11_CORE N10 VUSB
D3 GPIO_10 H17 GPS_DVSS28_IO N11 VIO18
hk T
D4 GPIO_11 H18 GPS_DVDD28_IO1 N12 VIO18
D5 EXT_CLK_SEL H19 GPS_VREF N13 SIM2_SIO
m. EN
D7 KROW0 J2 DRV N14 SIM1_SIO
D8 KROW3 J4 AUXIN4 N15 SIM1_SRST
D9 KCOL3 J5 GND N16 GPS_JDO
D11
D12
D13
.co ID KCOL4
GPIO_4
GPIO_5
J6
J7
J8
GND
GND
GND
N17
N18
N19
GPS_EINT0
GPS_EINT1
GPS_AVSS_RF
sac NF
D14 GPIO_1 J9 GND N20 GPS_RFIN
D15 GPIO_6 J10 GND P1 SPK_OUTP
D16 GPS_32K_OUT J11 GND P2 AVSS_SPK
O
D17 GPS_AVDD11_RTC J12 VSF P3 VA

D19 GPS_AVDD11_CLDO J13 GPS_DVSS11_CORE P5 AU_VIN1_P
u@ C
E1 VBAT_VA J14 GPS_DVSS11_CORE P7 VRTC

E2 AVSS44_ALDO J16 GPS_SCK1 P8 VCORE
E3 VCAMA J17 GPS_DVDD11_CORE2 P10 VBAT_DIGITAL
.Li K
E4 TESTMODE J19 GPS_AVDD18_CM P12 USB11_DP

E5 KCOL0 J20 GPS_OSC P13 USB11_DM
no TE
E6 KCOL2 K2 ISINK P15 VSIM1

E7 UTXD1 K3 AVSS44_PMU P16 SIM1_SCLK
E8 URXD1 K4 AVSS44_PMU P17 GPS_JMS
Ar IA
E9 KROW4 K5 GND P19 GPS_AVDD18_RXFE

E10 GPIO_9 K7 LSCK P20 GPS_AVSS_RF
E11 GPIO_8 K8 MCCM0
R ED
FO M


MT2503D
Confidential A
Y
NL
2.1.3 Detailed Pin Description
US IAL
Table 2. Acronym for pin types
Abbreviation Description
EO
AI Analog input
AO Analog output
AIO Analog bi-direction
hk T
DI Digital input
m. EN
DO Digital output
DIO Digital bi-direction
P Power
G Ground
.co ID Table 3. PIN function description and power domain

sac NF
Pin name Type Description Power domain
System
RESETB DIO System reset DVDD18_EMI
SRCLKENAI DIO 26MHz clock request by external devices VRF
O
EINT DIO External Interrupt VRF

TESTMODE_D DIO Digital Test Mode DVDD18_EMI
u@ C
GPIO_0 DIO General purpose input /output 0 DVDD28

.Li K

no TE

Ar IA

R ED
FO M


MT2503D
Confidential A
Y
NL
General purpose input /output 10,
US IAL
with analog output function, please be
notified that this GPIO may temporarily
EO
output high signal after VRF power-on then
output low once RF circuit reset done
hk T
GPIO_10 DIO VRF
m. EN
.co ID General purpose input /output 11,
sac NF
with analog output function, please be
notified that this GPIO temporarily output
high signal after VRF power-on then output
low once RF circuit reset done
O
GPIO_11 DIO VRF

u@ C
.Li K
no TE
RF control circuitro
BPI_BUS0 DIO RF hard-wire control bus bit 0 DVDD28
Ar IA

UART interface
R ED
URXD1 DIO UART1 receive data DVDD28

UTXD1 DIO UART1 transmit data DVDD28
Keypad interface
KCOL0 DIO Keypad column 0 DVDD28
FO M

KROW0 DIO Keypad row 0 DVDD28


MT2503D
Confidential A
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NL
US IAL
Camera interface
EO
CMRST DIO CMOS sensor reset signal output DVDD28
CMPDN DIO CMOS sensor power down control DVDD28
CMCSD0 DIO CMOS sensor data input 0 DVDD28
hk T
CMCSD1 DIO CMOS sensor data input 1 DVDD28
CMMCLK DIO CMOS sensor pixel clock input DVDD28
m. EN
CMCSK DIO CMOS sensor pixel clock output DVDD28
MS/SD card interface
SD serial data IO 0/memory stick serial data
MCDA0 DIO DVDD33_MSDC
IO
MCDA1
MCDA2
.co ID DIO
DIO
IO
DVDD33_MSDC
DVDD33_MSDC
sac NF
IO
MCDA3 DIO DVDD33_MSDC
IO
MCCK DIO SD serial clock/memory stick serial clock DVDD33_MSDC
O
SD command output/memory stick bus

MCCM0 DIO DVDD33_MSDC
state output
SIM card interface
u@ C
SIM1_SIO DIO SIM1 data input/outputs VSIM1

SIM1_SRST DIO SIM1 card reset output VSIM1
.Li K
SIM1_SCLK DIO SIM1 card clock output VSIM1

SIM2_SIO DIO SIM2 data input/outputs VSIM2
no TE
SIM2_SRST DIO SIM2 card reset output VSIM2

SIM2_SCLK DIO SIM2 card clock output VSIM2
I2C interface
SCL28 DIO I2C clock 2.8v power domain DVDD28
Ar IA
SDA28 DIO I2C data 2.8v power domain DVDD28

LCD interface
LSCE_B DIO Serial display interface chip select output DVDD18_EMI
R ED
LSCK DIO Serial display interface clock DVDD18_EMI

LSDA DIO Serial display interface data DVDD18_EMI
LSA0 DIO Serial display interface address DVDD18_EMI
LPTE DIO Serial display tearing signal DVDD18_EMI
FO M
FM
FM_ANT_P AI FM input from antenna VCAMA
Bluetooth
BT_LNA AIO Bluetooth RF single-ended input DVDD28
2G RF
RXHB AI RF input for highband Rx (DCS/PCS) VRF


MT2503D
Confidential A
Y
NL
RF input for lowband Rx
US IAL
RXLB AI VRF
(GSM900/GSM850)
TX_HB AO RF output for highband Tx (DCS/PCS) VRF
EO
RF output pin for lowband Tx
TX_LB AO VRF
(GSM900/GSM850)
FREF AO DCXO reference clock output VRF
hk T
XTAL1 AIO Input 1 for DCXO crystal VRF
XTAL2 AIO Input 2 for DCXO crystal VRF
m. EN
EXT_CLK_SEL AIO DCXO mode selection VRF
USB
USB11_DM AIO D- data input/output -
USB11_DP AIO D+ data input/output -
GPS
GPS_RFIN .co ID RF signal
Analog
LNA RF Input pin
sac NF
GPS_XIN RTC 32KHz XTAL input
input
Analog
GPS_XOUT RTC 32KHz XTAL output
output
Analog
O
GPS_AVDD43_RTC RTC LDO input

power
GPS_AVDD43_DCV SMPS SMPS input pin.
u@ C
Digital
GPS_DVSS11_CORE Digital 1.1V core ground
ground
GPS_DCV_FB SMPS
.Li K
SMPS feedback pin

Analog
GPS_AVSS11_CLDO GND pin for core LDO
ground
no TE
Digital
GPS_DVDD11_CORE1 Digital 1.1V core power input
power
1.2V
LVTTL
Ar IA
Logic high to force power on this chip.

input
Default: pull-up
PPU,PPD,
GPS_FORCE_ON SMT
R ED
GPS_DCV SMPS SMPS output pin

GPS_AVSS43_DCV SMPS SMPS GND pin
1.2V
LVTTL
FO M
I/O
RTC domain GPIO pin, can be
PPU, PPD, programmed to 32KHz clock output or
SMT DR wake-up signal input
4mA, Default: pull-down
8mA,
Default: 16mA driving
12mA,
16mA
GPS_32K_OUT PDR


MT2503D
Confidential A
Y
NL
Analog
US IAL
GPS_AVDD11_RTC RTC LDO output
power
Analog
EO
Core LDO output pin
GPS_AVDD11_CLDO power
Digital
GPS_DVDD28_SF Digital 2.8V serial flash power input
power
hk T
2.8V,
LVTTL
m. EN
I/O
PPU, PPD, Serial output for UART 1
SMT
Default: pull-up
4mA,
8mA,
GPS_TX1
.co ID 12mA,
16mA
PDR
sac NF
Analog
GPS_AVDD28_TLDO TCXO LDO output pin
power
Analog Core LDO input pin. Always powered
GPS_AVDD28_CLDO power by external source or SMPS
O
Digital
GPS_DVSS28_SF Digital 2.8V serial flash ground
ground
u@ C
2.8V,
LVTTL
I/O
.Li K
PPU, PPD, Serial input for UART 1

SMT
Default: pull-up
4mA,
no TE

8mA,
12mA,
16mA
GPS_JCK PDR
Ar IA
Analog
GPS_AVDD_TCXO_SW TCXO power switch output pin
power
2.8V,
LVTTL
R ED
I/O Serial output for UART 2

PPU, PPD, Default: pull-up
SMT Default: 8mA driving
4mA, Strap pin tcxo_sw_sel
FO M
8mA, 1’b0: AVDD_TCXO_SW output 1.8V

16mA
GPS_TX2 PDR


MT2503D
Confidential A
Y
NL
2.8V,
US IAL
LVTTL
I/O
EO
SMT
Default: pull-up
4mA,
8mA,
hk T
12mA,
16mA
m. EN
GPS_RX1 PDR
TCXO LDO input pin. Always be
Analog powered by external source. UVLO
power will detect this PIN to check power
GPS_AVDD43_VBAT
.co ID
GPS_AVSS43_MISC
Analog
ground
Digital
status.
GND pin for buck controller, TCXO
LDO and start-up block
sac NF
GPS_DVSS28_IO Digital 1.8/2.8V IO ground
ground
Digital
GPS_DVDD28_IO1 Digital 1.8/2.8V IO power input
power
O
Bandgap output pin. Must add 1uF

GPS_VREF Analog
decoupling cap on EVB.
2.8V, SPI clock output
u@ C
LVTTL Default: pull-up

I/O Default: 8mA driving
PPU, PPD,
.Li K
Strap pin clk_sel[0]

SMT
Clk_sel[1:0] Mode
4mA,
2’b00: XTAL mode
8mA,
no TE
12mA, 2’b01: External clock mode

16mA 2’b10: TCXO mode
GPS_SCK1 PDR 2’b11: 16.368MHz TCXO mode
Digital
Ar IA
GPS_DVDD11_CORE2 Digital 1.1V core power input

power
1.8V supply for XTAL OSC, bandgap,
RF power
GPS_AVDD18_CM thermal sensor and level shifter
R ED
Analog
GPS_OSC Input for crystal oscillator or TCXO
signal
2.8V,
LVTTL
FO M
I/O
SMT
Default: pull-up
4mA,
8mA,
12mA,
16mA
GPS_RX0 PDR


MT2503D
Confidential A
Y
NL
2.8V,
US IAL
LVTTL
I/O
EO
SMT
Default: pull-up
4mA,
8mA,
hk T
12mA,
16mA
m. EN
GPS_RX2 PDR
GPS_T1P Analog
RF testing signal
signal
Analog
GPS_T1N
.co ID signal
2.8V,
LVTTL
I/O
RF testing signal
sac NF
PPU, PPD, SPI slave selection 1
SMT Default: pull-up
4mA, Default: 8mA driving
8mA, Strap pin clk_sel[1]
O
12mA,
16mA
GPS_JRST_ PDR
u@ C
2.8V,
LVTTL
I/O
.Li K
PPU, PPD, JTAG interface data input.

SMT
no TE
Default: pull-down
4mA,
8mA,
12mA,
16mA
GPS_JDI
Ar IA
PDR
Digital
GPS_DVDD28_IO2 Digital 1.8/2.8V IO power input
power
2.8V
R ED
LVTTL System reset. Active low

input Default: pull-up
GPS_HRST_B SMT
FO M


MT2503D
Confidential A
Y
NL
2.8V,
US IAL
LVTTL
I/O
EO
SMT
Default: pull-up
4mA,
8mA,
hk T
12mA,
16mA
m. EN
GPS_TX0 PDR
2.8V, SPI clock output
LVTTL Default: pull-up
I/O Default: 8mA driving
.co ID PPU, PPD,

SMT
4mA,
8mA,
Strap pin clk_sel[0]
Clk_sel[1:0] Mode
2’b00: XTAL mode
sac NF
12mA, 2’b01: External clock mode
16mA 2’b10: TCXO mode
GPS_JRCK PDR 2’b11: 16.368MHz TCXO mode
2.8V,
O
LVTTL
I/O
PPU, PPD, SPI slave selection 1
u@ C
SMT Default: pull-up

4mA, Default: 8mA driving
8mA, Strap pin clk_sel[1]
.Li K
12mA,
16mA
GPS_SCS1_ PDR
no TE
2.8V
Test mode. Must keep low in normal
LVTTL
mode.
input
GPS_XTEST Default: pull-down
SMT
Ar IA
GPS_AVSS_RF RF
RF ground pins
ground
2.8V,
R ED
LVTTL
I/O Serial output for UART 2
PPU, PPD, Default: pull-up
SMT Default: 8mA driving
FO M
4mA, Strap pin tcxo_sw_sel

16mA
GPS_JDO PDR


MT2503D
Confidential A
Y
NL
2.8V,
US IAL
LVTTL
I/O
EO
PPU, PPD, External interrupt 0
SMT
Default: pull-down
4mA,
8mA,
hk T
12mA,
16mA
m. EN
GPS_EINT0 PDR
2.8V,
LVTTL
I/O
.co ID PPU, PPD,

SMT
4mA,
8mA,
External interrupt 1
Default: pull-down
sac NF
12mA,
16mA
GPS_EINT1 PDR
RF
RF ground pins
O
GPS_AVSS_RF ground
GPS_JMS SMPS SMPS GND pin
u@ C
2.8V,
LVTTL
I/O
.Li K

SMT
Default: pull-up
4mA,
no TE

8mA,
12mA,
16mA
GPS_AVDD18_RXFE PDR
Ar IA
Analog baseband
AU_HPR AIO Audio head phone output (R channel) AVDD28_ABB
R ED
AU_HPL AIO Audio head phone output (L channel) AVDD28_ABB

AU_HSP AIO Voice handset output (positive) AVDD28_ABB
AU_HSN AIO Voice handset output (negative) AVDD28_ABB
AU_VIN0_P AIO Microphone 0 input (positive) AVDD28_ABB
FO M
AU_VIN0_N AIO Microphone 0 input (negative) AVDD28_ABB

AU_VIN1_P AIO Microphone 1 input (positive) AVDD28_ABB
AU_VIN1_N AIO Microphone 1 input (negative) AVDD28_ABB
AUX_IN4 AIO Auxiliary ADC input AVDD28_ABB
SPK_OUTP AIO Speaker positive output VBAT_SPK
SPK_OUTN AIO Speaker negative output VBAT_SPK


MT2503D
Confidential A
Y
NL
APC AIO Automatic power control DAC output AVDD28_ABB
US IAL
AU_MICBIAS0 AIO Microphone bias source 0 AVDD28_ABB
ACCDET AIO Accessory detection
EO
AVDD28_ABB
Power management unit
VA AIO LDO output for ABB - VA VBAT_ANALOG
VCAMA AIO LDO output for sensor – VCAMA VBAT_VA
hk T
VIBR AIO LDO output for vibrator - VIBR VBAT_DIGITAL
VIO18 AIO LDO output for 1.8V power - VIO18 VBAT_DIGITAL
m. EN
VIO28 AIO LDO output for 2.8V power - VIO28 VBAT_DIGITAL
VMC AIO LDO output for memory card - VMC VBAT_DIGITAL
VSF AIO LDO output - VSF VBAT_DIGITAL
VRF
VRTC
VSIM1
.co ID AIO
AIO
AIO
LDO output for GSMRF - VRF
LDO output for RTC - VRTC
st
LDO output for 1 SIM - VSIM
nd
VBAT_VA
VBAT_DIGITAL
VBAT_DIGITAL
sac NF
VSIM2 AIO LDO output for 2 SIM - VSIM2 VBAT_DIGITAL
VUSB AIO LDO output for USB - VUSB VBAT_DIGITAL
VCORE AIO LDO output for core circuit - Vcore VBAT_DIGITAL
VREF AIO Band gap reference BATSNS
O
VCDT AIO Charger-In level sense pin BATSNS

DRV AIO IDAC current output open-drain pin BATSNS
u@ C
BATON AIO Battery Pack, NTC connected pin BATSNS

Top node of current sensing 0.2ohm
ISENSE AIO BATSNS
Rsense resistor
.Li K
CHRLDO AIO 2.8V shunt-regulator output BATSNS

BATDET AIO Battery detection pin BATSNS
no TE
ISINK0 AIO Backlight driver channel 0 VBAT_VA

KPLED AIO Keypad led driver VBAT_VA
TESTMODE AIO Test mode BATSNS
PWRKEY AIO PWR key BATSNS
Ar IA
AVDD25_V2P5 AIO Reference voltage for ABT -

Analog power
AVDD15_BTRF P BTRF power input -
R ED
VBAT_DIGITAL P Digital LDOs used battery voltage input -

VBAT_VA P Analog LDOs used battery voltage input -
AVDD_SPK P Input for loud speaker driver -
BATSNS P Battery node of battery pack -
FO M
AVDD15_BTRF P BTRF power input -

Analog ground
AVSS28_ABB G ABB 2.8V ground -
AVSS_BT G BT ground -
AVSS_2G G 2G RF ground -
AVSS_FM G FM ground -


MT2503D
Confidential A
Y
NL
AVSS44_PMU G PMU ground -
US IAL
AVSS44_ALDO G ALDO ground -
AVSS44_DLDO G DLDO ground
EO
-
AVSS_SPK G SPK ground -
AGND G GND for VREF -
AVSS44_BOOST G Audio boost GND -
hk T
Digital power
VDDK P Core power -
m. EN
Digital ground
GND G Ground -
.co ID Table 4. Acronym for state of pins
sac NF
I Input
LO Low output
HO High output
LO Low output
O
PU Pull-up
PD Pull-down
u@ C
- No PU/PD
0~N Aux. function number
X Delicate function pin
.Li K
no TE
Table 5. State of pins
Reset Termination
Name 1 2 3 Output drivability IO type
State Aux PU/PD when not used
Ar IA
System
RESETB HO 1 - DIOH3/DIOL3 No need IO Type 3
SRCLKENAI I 0 PD DIOH1/DIOL1 No need IO Type 1
R ED
EINT I 0 PD DIOH1/DIOL1 No need IO Type 1

FO M
1 The column “State” of “Reset” shows the pin state during reset. (Input, High Output, Low Output, etc)
2 The column “Aux” for “Reset” means the default aux function number, shown in the table “Pin Multiplexing, Capability and
Settings”.
3 The column “PU/PD” for “Reset” means if there is internal pull-up or pull-down when the pin is input in the reset state.


MT2503D
Confidential A
Y
NL
Reset Termination
US IAL
GPIO_0 I 0 PD DIOH1/DIOL1 No need IO Type 1
EO
hk T
GPIO_5 LO 0 PD DIOH2/DIOL2 No need IO Type 2
m. EN
GPIO_10
GPIO_11
.co ID
RF control circuitry
BPI_BUS0
I
I
LO
0
0
1
PD
PD
PD
DIOH1/DIOL1
DIOH1/DIOL1
DIOH2/DIOL2
No need
No need
No need
IO Type 1
IO Type 1
IO Type 2
sac NF
BPI_BUS1 I 1 PD DIOH2/DIOL2 No need IO Type 2
BPI_BUS2 I 1 PD DIOH2/DIOL2 No need IO Type 2
UART interface
O
URXD1 I 1 PU DIOH3/DIOL3 No need IO Type 3

UTXD1 HO 1 PU DIOH2/DIOL2 No need IO Type 2
u@ C
Keypad Interface
KCOL0 I 0 PU DIOH4/DIOL4 No need IO Type 4
.Li K

no TE

KROW0 I 0 PD DIOH5/DIOL5 No need IO Type 5
Ar IA

Camera interface
R ED
CMRST I 0 PD DIOH2/DIOL2 No need IO Type 2

CMPDN HO 0 - DIOH3/DIOL3 No need IO Type 3
CMCSD0 I 0 PU DIOH3/DIOL3 No need IO Type 3
CMCSD1 I 0 PD DIOH3/DIOL3 No need IO Type 3
FO M
CMMCLK I 0 PD DIOH3/DIOL3 No need IO Type 3

CMCSK I 0 PD DIOH2/DIOL2 No need IO Type 2
MS/SD card interface
MCDA0 I 0 PD DIOH3/DIOL3 No need IO Type 3


MT2503D
Confidential A
Y
NL
Reset Termination
US IAL
MCCK I 0 PU DIOH3/DIOL3 No need IO Type 3
EO
MCCM0 I 0 PU DIOH3/DIOL3 No need IO Type 3
SIM card interface
SIM1_SIO I 1 PD DIOH6/DIOL6 No need IO Type 6
SIM1_SRST I 1 PD DIOH6/DIOL6 No need IO Type 6
hk T
SIM1_SCLK I 1 PD DIOH6/DIOL6 No need IO Type 6
SIM2_SIO I 1 PD DIOH6/DIOL6 No need IO Type 6
m. EN
SIM2_SRST I 1 PD DIOH6/DIOL6 No need IO Type 6
SIM2_SCLK I 1 PD DIOH6/DIOL6 No need IO Type 6
I2C interface
I
SCL28
SDA28
LCD interface
LSCE_B
.co ID HO
I
0
0
1
PD
PD
-
DIOH2/DIOL2
DIOH2/DIOL2
DIOH3/DIOL3
No need
No need
No need
IO Type 2
IO Type 2
IO Type 3
sac NF
LSCK I 0 PD DIOH3/DIOL3 No need IO Type 3
LSDA I 0 PD DIOH3/DIOL3 No need IO Type 3
LSA0 I 0 PD DIOH3/DIOL3 No need IO Type 3
O
LPTE I 0 PD DIOH3/DIOL3 No need IO Type 3

u@ C
DVDIO DVDIO
.Li K
DVO DVO
no TE
PAD PAD
Output Output
Enable Enable
Input Input
DVDIO GNDIO DVDIO GNDIO
Enable Enable
PU PU
Ar IA
VIN VIN
PD PD
GNDIO GNDIO
R ED
IO type1 IO type2
FO M


MT2503D
Confidential A
Y
NL
US IAL
DVDIO
DVDIO
EO
DVO
DVO
PAD
PAD
Output
Output
Enable
hk T
Enable
DVDIO GNDIO
DVDIO GNDIO
m. EN
PU
PU
VIN
VIN
PD
PD
GNDIO
GNDIO
.co ID IO type3 IO type4

sac NF
O
u@ C
DVDIO
DVDIO
DVO
DVO
.Li K
PAD
PAD
Output
Output
Enable
Enable
no TE
DVDIO GNDIO
DVDIO GNDIO
PU
PU
VIN
VIN
PD
PD
Ar IA
GNDIO
GNDIO
IO type5 IO type6
R ED
FO M
Figure 4. IO types in state of pins


MT2503D
Confidential A
Y
NL
2.1.4 Pin Multiplexing, Capability and Settings
US IAL
Table 6. Acronym for pull-up and pull-down types
EO
PU Pull-up, not controllable
PD Pull-down, not controllable
hk T
CU Pull-up, controllable
CD Pull-down, controllable
m. EN
X Cannot pull-up or pull-down
Table 7. Capability of PU/PD, driving and Schmitt trigger
Name .co IDAux.

function
Aux. name
Aux.
type
PU/PD/
CU/CD
Driving SMT
sac NF
GPIO_0 0 GPIO0 IO CU, CD 4, 8, 12, 16mA 0
1 EINT0 I CU, CD 4, 8, 12, 16mA 0
2 XP AIO - 4, 8, 12, 16mA 0
3 U3RXD I CU, CD 4, 8, 12, 16mA 0
O
4 CMCSD2 I CU, CD 4, 8, 12, 16mA 0

u@ C
5 CMCSK I CU, CD 4, 8, 12, 16mA 0

6 EDIDO O CU, CD 4, 8, 12, 16mA 0
7 JTDI I PU 4, 8, 12, 16mA 0
.Li K
8 BTJTDI I CU, CD 4, 8, 12, 16mA 0

no TE
9 FMJTDI I CU, CD 4, 8, 12, 16mA 0

1 EINT1 I CU, CD 4, 8, 12, 16mA 0
Ar IA
2 XM AIO - 4, 8, 12, 16mA 0

3 U3TXD O CU, CD 4, 8, 12, 16mA 0
4 U1CTS I CU, CD 4, 8, 12, 16mA 0
R ED
5 CMMCLK O CU, CD 4, 8, 12, 16mA 0

6 EDIDI I CU, CD 4, 8, 12, 16mA 0
7 JTMS I PU 4, 8, 12, 16mA 0
FO M
8 BTJTMS I CU, CD 4, 8, 12, 16mA 0

9 FMJTMS I CU, CD 4, 8, 12, 16mA 0
1 EINT2 O CU, CD 4, 8, 12, 16mA 0
2 YP AIO - 4, 8, 12, 16mA 0
3 GPSFSYNC O CU, CD 4, 8, 12, 16mA 0


MT2503D
Confidential A
Y
NL
Aux. Aux. PU/PD/
Name Aux. name Driving SMT
function type CU/CD
US IAL
4 PWM0 O CU, CD 4, 8, 12, 16mA 0
EO
5 CMCSD0 I CU, CD 4, 8, 12, 16mA 0
6 EDIWS O CU, CD 4, 8, 12, 16mA 0
7 JTRST_B I PD 4, 8, 12, 16mA 0
hk T
8 BTJTRSTB I CU, CD 4, 8, 12, 16mA 0
m. EN
9 FMJTRSTB I CU, CD 4, 8, 12, 16mA 0
1 MCINS I CU, CD 4, 8, 12, 16mA 0
.co ID 2
4
5
YM
PWM1
CMCSD1
AIO
O
I
-
CU, CD
CU, CD
4, 8, 12, 16mA
4, 8, 12, 16mA
4, 8, 12, 16mA
0
0
0
sac NF
6 EDICK O CU, CD 4, 8, 12, 16mA 0
7 JTDO O CU, CD 4, 8, 12, 16mA 0
8 BTJTDO O CU, CD 4, 8, 12, 16mA 0
O
9 FMJTDO O CU, CD 4, 8, 12, 16mA 0

u@ C
1 EINT3 I CU, CD 4, 8, 12, 16mA 0

4 U1RTS O CU, CD 4, 8, 12, 16mA 0
.Li K

1 EINT4 I CU, CD 4, 8, 12, 16mA 0
no TE
3 BPI_BUS3 O CU, CD 4, 8, 12, 16mA 0

1 EINT5 I CU, CD 4, 8, 12, 16mA 0
Ar IA
2 MCINS I CU, CD 4, 8, 12, 16mA 0

3 BPI_BUS4 O CU, CD 4, 8, 12, 16mA 0
R ED

1 EINT6 I CU, CD 4, 8, 12, 16mA 0
3 BPI_BUS5 O CU, CD 4, 8, 12, 16mA 0
FO M
1 EINT7 I CU, CD 4, 8, 12, 16mA 0

2 SCL IO CU, CD 4, 8, 12, 16mA 0
1 EINT8 I CU, CD 4, 8, 12, 16mA 0
2 SDA IO CU, CD 4, 8, 12, 16mA 0


MT2503D
Confidential A
Y
NL
Aux. Aux. PU/PD/
function type CU/CD
US IAL
URXD1 0 GPIO10 IO CU, CD 4, 8, 12, 16mA 0
EO
1 U1RXD I PU 4, 8, 12, 16mA 0
2 CMRST O CU, CD 4, 8, 12, 16mA 0
3 EINT9 I CU, CD 4, 8, 12, 16mA 0
hk T
4 MCINS I CU, CD 4, 8, 12, 16mA 0
m. EN
UTXD1 0 GPIO11 IO CU, CD 4, 8, 12, 16mA 0
1 U1TXD O CU, CD 4, 8, 12, 16mA 0
2 CMPDN O CU, CD 4, 8, 12, 16mA 0
KCOL4 .co ID 3
0
1
EINT10
GPIO12
KCOL4
I
IO
IO
CU, CD
CU, CD
-
4, 8, 12, 16mA
4, 8, 12, 16mA
4, 8, 12, 16mA
0
0
0
sac NF
2 U2RXD I CU, CD 4, 8, 12, 16mA 0
3 EDIDI I CU, CD 4, 8, 12, 16mA 0
4 FMJTDI I CU, CD 4, 8, 12, 16mA 0
O
5 JTDI I PU 4, 8, 12, 16mA 0

6 BTJTDI I CU, CD 4, 8, 12, 16mA 0
u@ C
KCOL3 0 GPIO13 IO CU, CD 4, 8, 12, 16mA 0

1 KCOL3 IO - 4, 8, 12, 16mA 0
.Li K
2 EINT11 I CU, CD 4, 8, 12, 16mA 0

3 PWM0 O CU, CD 4, 8, 12, 16mA 0
no TE
4 FMJTMS I CU, CD 4, 8, 12, 16mA 0

5 JTMS I PU 4, 8, 12, 16mA 0
6 BTJTMS I CU, CD 4, 8, 12, 16mA 0
Ar IA

1 KCOL2 IO - 4, 8, 12, 16mA 0
R ED
2 EINT12 I CU, CD 4, 8, 12, 16mA 0

3 U1RTS I CU, CD 4, 8, 12, 16mA 0
1 KCOL1 IO - 4, 8, 12, 16mA 0
FO M
2 GPSFSYNC O CU, CD 4, 8, 12, 16mA 0

3 U1CTS I CU, CD 4, 8, 12, 16mA 0
4 FMJTCK I CU, CD 4, 8, 12, 16mA 0
5 JTCK I PU 4, 8, 12, 16mA 0
6 BTJTCK I CU, CD 4, 8, 12, 16mA 0


MT2503D
Confidential A
Y
NL
Aux. Aux. PU/PD/
function type CU/CD
US IAL
EO
1 KCOL0 IO - 4, 8, 12, 16mA 0
KROW4 0 GPIO17 IO CU, CD 4, 8, 12, 16mA 0
1 KROW4 IO - 4, 8, 12, 16mA 0
hk T
2 U2TXD O CU, CD 4, 8, 12, 16mA 0
m. EN
3 EDICK O CU, CD 4, 8, 12, 16mA 0
1 KROW3 IO - 4, 8, 12, 16mA 0
.co ID 2
3
4
EINT13
CLKO0
FMJTRSTB
O
I
I
CU, CD
CU, CD
CU, CD
4, 8, 12, 16mA
4, 8, 12, 16mA
4, 8, 12, 16mA
0
0
0
sac NF
5 JTRST_B I PD 4, 8, 12, 16mA 0
6 BTJTRSTB I CU, CD 4, 8, 12, 16mA 0
O
1 KROW2 IO - 4, 8, 12, 16mA 0

2 PWM1 O CU, CD 4, 8, 12, 16mA 0
u@ C
3 EDIWS O CU, CD 4, 8, 12, 16mA 0

4 FMJTDO O CU, CD 4, 8, 12, 16mA 0
.Li K
5 JTDO O CU, CD 4, 8, 12, 16mA 0

6 BTJTDO O CU, CD 4, 8, 12, 16mA 0
no TE

1 KROW1 IO - 4, 8, 12, 16mA 0
2 EINT14 I CU, CD 4, 8, 12, 16mA 0
Ar IA
3 EDIDO O CU, CD 4, 8, 12, 16mA 0

4 BTPRI IO CU, CD 4, 8, 12, 16mA 0
R ED
5 JTRCK O CU, CD 4, 8, 12, 16mA 0

6 BTDBGACKN O CU, CD 4, 8, 12, 16mA 0
1 KROW0 IO - 4, 8, 12, 16mA 0
FO M
5 MCINS I CU, CD 4, 8, 12, 16mA 0

6 BTDBGIN I CU, CD 4, 8, 12, 16mA 0
BPI_BUS2 0 GPIO22 IO CU, CD 4, 8, 12, 16mA 0
1 BPI_BUS2 O CU, CD 4, 8, 12, 16mA 0


MT2503D
Confidential A
Y
NL
Aux. Aux. PU/PD/
function type CU/CD
US IAL
1 BPI_BUS1 O CU, CD 4, 8, 12, 16mA 0
EO
1 BPI_BUS0 IO CU, CD 4, 8, 12, 16mA 0
CMRST 0 GPIO25 IO CU, CD 4, 8, 12, 16mA 0
hk T
1 CMRST O CU, CD 4, 8, 12, 16mA 0
m. EN
2 TESTMODE_D O CU, CD 4, 8, 12, 16mA 0
3 CLKO1 O CU, CD 4, 8, 12, 16mA 0
4 EINT15 I CU, CD 4, 8, 12, 16mA 0
CMPDN
.co ID 5
6
0
FMJTDI
JTDI
GPIO26
I
I
IO
CU, CD
PU
CU, CD
4, 8, 12, 16mA
4, 8, 12, 16mA
4, 8, 12, 16mA
0
0
0
sac NF
1 CMPDN O CU, CD 4, 8, 12, 16mA 0
2 LSCK1 O CU, CD 4, 8, 12, 16mA 0
3 DAICLK O CU, CD 4, 8, 12, 16mA 0
O
4 SPICS IO CU, CD 4, 8, 12, 16mA 0

5 FMJTMS I CU, CD 4, 8, 12, 16mA 0
u@ C
6 JTMS I PU 4, 8, 12, 16mA 0

CMCSD0 0 GPIO27 IO CU, CD 4, 8, 12, 16mA 0
.Li K
1 CMCSD0 I CU, CD 4, 8, 12, 16mA 0

2 LSCE_B1 O CU, CD 4, 8, 12, 16mA 0
no TE
3 DAIPCMIN I CU, CD 4, 8, 12, 16mA 0

4 SPISCK IO CU, CD 4, 8, 12, 16mA 0
5 FMJTCK I CU, CD 4, 8, 12, 16mA 0
Ar IA
6 JTCK I PU 4, 8, 12, 16mA 0

8 MC2CM0 O - 4, 8, 12, 16mA 0
R ED
CMCSD1 0 GPIO28 IO CU, CD 4, 8, 12, 16mA 0

1 CMCSD1 I CU, CD 4, 8, 12, 16mA 0
2 LSDA1 IO CU, CD 4, 8, 12, 16mA 0
3 DAIPCMOUT O CU, CD 4, 8, 12, 16mA 0
FO M
4 SPIMOSI IO CU, CD 4, 8, 12, 16mA 0

5 FMJTRSTB I CU, CD 4, 8, 12, 16mA 0
6 JTRST_B I PD 4, 8, 12, 16mA 0
8 MC2CK O - 4, 8, 12, 16mA 0
CMMCLK 0 GPIO29 IO CU, CD 4, 8, 12, 16mA 0


MT2503D
Confidential A
Y
NL
Aux. Aux. PU/PD/
function type CU/CD
US IAL
1 CMMCLK O CU, CD 4, 8, 12, 16mA 0
EO
2 LSA0DA1 O CU, CD 4, 8, 12, 16mA 0
3 DAISYNC O CU, CD 4, 8, 12, 16mA 0
4 SPIMISO IO CU, CD 4, 8, 12, 16mA 0
hk T
5 FMJTDO O CU, CD 4, 8, 12, 16mA 0
m. EN
6 JTDO O CU, CD 4, 8, 12, 16mA 0
8 MC2DA0 IO - 4, 8, 12, 16mA 0
CMCSK 0 GPIO30 IO CU, CD 4, 8, 12, 16mA 0
.co ID 1
2
3
CMCSK
LPTE
CMCSD2
I
I
I
CU, CD
CU, CD
CU, CD
4, 8, 12, 16mA
4, 8, 12, 16mA
4, 8, 12, 16mA
0
0
0
sac NF
4 EINT16 I CU, CD 4, 8, 12, 16mA 0
6 JTRCK O CU, CD 4, 8, 12, 16mA 0
MCCK 0 GPIO31 IO CU, CD 4, 8, 12, 16mA 0
O
1 MCCK O - 4, 8, 12, 16mA 0

4 U2RXD I CU, CD 4, 8, 12, 16mA 0
u@ C
MCCM0 0 GPIO32 IO CU, CD 4, 8, 12, 16mA 0

1 MCCM0 IO - 4, 8, 12, 16mA 0
.Li K
4 U2TXD O CU, CD 4, 8, 12, 16mA 0

MCDA0 0 GPIO33 IO CU, CD 4, 8, 12, 16mA 0
no TE
1 MCDA0 IO - 4, 8, 12, 16mA 0

4 DAISYNC O CU, CD 4, 8, 12, 16mA 0
Ar IA
1 MCDA1 IO - 4, 8, 12, 16mA 0

2 EINT17 I CU, CD 4, 8, 12, 16mA 0
R ED
4 DAIPCMIN I CU, CD 4, 8, 12, 16mA 0

1 MCDA2 IO - 4, 8, 12, 16mA 0
2 EINT18 I CU, CD 4, 8, 12, 16mA 0
FO M
4 DAICLK O CU, CD 4, 8, 12, 16mA 0

1 MCDA3 IO - 4, 8, 12, 16mA 0
2 EINT19 I CU, CD 4, 8, 12, 16mA 0
3 CLKO2 O CU, CD 4, 8, 12, 16mA 0


MT2503D
Confidential A
Y
NL
Aux. Aux. PU/PD/
function type CU/CD
US IAL
4 DAIPCMOUT O CU, CD 4, 8, 12, 16mA 0
EO
SIM1_SIO 0 GPIO37 IO CU, CD 2, 4, 6, 8mA 0
1 SIM1_SIO IO - 2, 4, 6, 8mA 0
SIM1_SRST 0 GPIO38 IO CU, CD 2, 4, 6, 8mA 0
hk T
1 SIM1_SRST IO - 2, 4, 6, 8mA 0
m. EN
SIM1_SCLK 0 GPIO39 IO CU, CD 2, 4, 6, 8mA 0
1 SIM1_SCLK IO - 2, 4, 6, 8mA 0
SIM2_SIO 0 GPIO40 IO CU, CD 2, 4, 6, 8mA 0
SIM2_SRST
.co ID 1
3
0
SIM2_SIO
U2RTS
GPIO41
IO
O
IO
-
CU, CD
CU, CD
2, 4, 6, 8mA
2, 4, 6, 8mA
2, 4, 6, 8mA
0
0
0
sac NF
1 SIM2_SRST IO - 2, 4, 6, 8mA 0
2 CLKO3 O CU, CD 2, 4, 6, 8mA 0
3 U2CTS I CU, CD 2, 4, 6, 8mA 0
O
4 SCL18 IO CU, CD 4, 8, 12, 16mA 0

SIM2_SCLK 0 GPIO42 IO CU, CD 2, 4, 6, 8mA 0
u@ C
1 SIM2_SCLK IO - 2, 4, 6, 8mA 0
2 LSCE1_B1 O CU, CD 2, 4, 6, 8mA 0
.Li K
4 SDA18 IO CU, CD 4, 8, 12, 16mA 0

SCL 0 GPIO43 IO CU, CD 4, 8, 12, 16mA 0
no TE
1 SCL IO CU, CD 4, 8, 12, 16mA 0

SDA 0 GPIO44 IO CU, CD 4, 8, 12, 16mA 0
1 SDA IO CU, CD 4, 8, 12, 16mA 0
Ar IA
TESTMODE_D 0 GPIO45 IO CU, CD 4, 8, 12, 16mA 0

1 TESTMODE_D O CU, CD 4, 8, 12, 16mA 0
R ED
3 CMRST O CU, CD 4, 8, 12, 16mA 0

LSCE_B0 0 GPIO46 IO CU, CD 4, 8, 12, 16mA 0
1 LSCE_B0 O CU, CD 4, 8, 12, 16mA 0
2 EINT20 I CU, CD 4, 8, 12, 16mA 0
FO M
3 CMCSD0 I CU, CD 4, 8, 12, 16mA 0

4 CLKO4 O CU, CD 4, 8, 12, 16mA 0
LSCK0 0 GPIO47 IO CU, CD 4, 8, 12, 16mA 0
1 LSCK0 O CU, CD 4, 8, 12, 16mA 0
3 CMPDN O CU, CD 4, 8, 12, 16mA 0


MT2503D
Confidential A
Y
NL
Aux. Aux. PU/PD/
function type CU/CD
US IAL
LSDA0 0 GPIO48 IO CU, CD 4, 8, 12, 16mA 0
EO
1 LSDA0 IO - 4, 8, 12, 16mA 0
2 EINT21 I CU, CD 4, 8, 12, 16mA 0
3 CMCSD1 I CU, CD 4, 8, 12, 16mA 0
hk T
4 WIFITOBT I CU, CD 4, 8, 12, 16mA 0
m. EN
LSA0 0 GPIO49 IO CU, CD 4, 8, 12, 16mA 0
1 LSA0DA0 O - 4, 8, 12, 16mA 0
2 LSCE1_B0 O CU, CD 4, 8, 12, 16mA 0
LPTE .co ID 3
0
1
CMMCLK
GPIO50
LPTE
O
IO
I
CU, CD
CU, CD
CU, CD
4, 8, 12, 16mA
4, 8, 12, 16mA
4, 8, 12, 16mA
0
0
0
sac NF
2 EINT22 I CU, CD 4, 8, 12, 16mA 0
3 CMCSK I CU, CD 4, 8, 12, 16mA 0
4 CMCSD2 I CU, CD 4, 8, 12, 16mA 0
O
6 MCINS I CU, CD 4, 8, 12, 16mA 0

9 CLKO5 O CU, CD 4, 8, 12, 16mA 0
u@ C
RESETB 0 GPIO51 IO CU, CD 4, 8, 12, 16mA 0

1 RESETB IO CU, CD 4, 8, 12, 16mA 0
.Li K
EINT 0 AGPI52 I CU, CD 8mA 0

2 EINT23 I CU, CD 8mA 0
no TE
SRCLKENAI 0 AGPI53 I CU, CD 8mA 0

1 SRCLKENAI I CU, CD 8mA 0
2 EINT24 I - 8mA 0
Ar IA
GPIO_10 0 AGPIO54 IO CU, CD 8mA 0

GPIO_11 0 AGPIO55 IO CU, CD 8mA 0
R ED
2.2 Electrical Characteristics

FO M
2.2.1 Absolute Maximum Ratings

Table 8. Absolute maximum ratings for power supply
Symbol or pin name Description Min. Max. Unit

VBAT_DIGITAL Digital used battery voltage input -0.3 +4.4 V
VBAT_VA Analog used battery voltage input -0.3 +4.4 V


MT2503D
Confidential A
Y
NL
AVDD_SPK VBAT input for loud speaker driver -0.3 +5.5 V
US IAL
VDDK 1.3v core power -0.3 +1.43 V
EO
Table 9. Absolute maximum ratings for voltage input
hk T
VIN1 Digital input voltage for IO Type 1 -0.3 3.08 V
m. EN
VIN6
VIN7
.co ID Digital input voltage for IO Type 6
Digital input voltage for IO Type 7
-0.3
-0.3
3.08
3.63
V
V
sac NF
Table 10. Absolute maximum ratings for storage temperature

o
Tstg Storage temperature -55 125 C
O
u@ C
2.2.2 Recommended Operating Conditions

Table 11. Recommended operating conditions for power supply
.Li K
Symbol or pin name Description Min. Typ. Max. Unit

VBAT_DIGITAL Digital used battery voltage input 3.4 3.8 4.2 V
no TE
VBAT_VA Analog used battery voltage input 3.4 3.8 4.2 V

AVDD_SPK VBAT input for loud speaker driver 3.4 3.8 4.2 V
VDDK 1.2v core power 1.17 1.3 1.43 V
Ar IA
Table 12. Recommended operating conditions for voltage input
Symbol or pin name Description Min. Typ. Max. Unit

R ED
VIN1 Digital input voltage for IO Type 1 -0.3 - DVDIO+0.3 V

FO M



MT2503D
Confidential A
Y
NL
Table 13. Recommended operating conditions for operating temperature
US IAL
Symbol or pin name Description Min. Typ Max. Unit
o
Tc Operating temperature -20 - 85 C
EO
2.2.3 Electrical Characteristics under Recommended Operating Conditions
hk T
Table 14. Electrical characteristics
m. EN
Symbol Description Condition Min. Typ. Max. Unit
PU/PD disabled,
DVDIO = 2.8V, -5 - 5
2.1 < VIN1 < 3.1
DIIH1
.co ID
Digital high input current
for IO Type 1
PU enabled,
DVDIO = 2.8V,
2.1 < VIN1 < 3.1
PD enabled,
-22.5 - 12.5 μA
sac NF
DVDIO = 2.8V, 6.1 - 82.5
2.1<VIN1<3.1
PU/PD disabled,
DVDIO = 2.8V, -5 - 5
O
-0.3 < VIN1 < 0.7

PU enabled,
Digital low input current
u@ C
DIIL1 DVDIO = 2.8V, -82.5 - -6.1 μA

for IO Type 1
-0.3 < VIN1 < 0.7
PD enabled,
.Li K
DVDIO = 2.8V, -12.5 - 22.5

-0.3 < VIN1 < 0.7
DVOH > 2.38V,
no TE
Digital high output current

DIOH1 -16 - - mA
for IO Type 1 DVDIO = 2.8V
Digital low output current DVOL < 0.42V,
DIOL1 - - 16 mA
Digital I/O pull-up
Ar IA
DRPU1 DVDIO = 2.8V 40 85 190 kΩ

resistance for IO Type 1
Digital I/O pull-down
DRPD1 DVDIO = 2.8V 40 85 190 kΩ
resistance for IO Type 1
R ED
Digital output high

DVOH1 DVDIO = 2.8V 2.38 V
voltage for IO Type 1
Digital output low voltage
DVOL1 DVDIO = 2.8V 0.42 V
for IO Type 1
FO M
PU/PD disabled,
DVDIO = 2.8V, -5 - 5
Digital high input current 2.1 < VIN1 < 3.1
DIIH2 μA
for IO Type 2 PU enabled,
DVDIO = 2.8V, -22.5 - 12.5
2.1 < VIN1 < 3.1


MT2503D
Confidential A
Y
NL
PD enabled,
US IAL
DVDIO = 2.8V, 6.1 - 82.5
2.1<VIN1<3.1
EO
PU/PD disabled,
DVDIO = 1.8V, -5 - 5
1.35 < VIN1 < 2.1
hk T
PU enabled,
DVDIO = 1.8V, -11.4 - 9.3 μA
m. EN
1.35 < VIN1 < 2.1
PD enabled,
DVDIO = 1.8V, -0.8 - 35
1.35 < VIN1 < 2.1
PU/PD disabled,
.co ID DVDIO = 2.8V,

-0.3 < VIN2 < 0.7
PU enabled,
-5 - 5
sac NF
DVDIO = 2.8V, -82.5 - -6.1 μA
-0.3 < VIN2 < 0.7
PD enabled,
DVDIO = 2.8V, -12.5 - 22.5
O
Digital low input current -0.3 < VIN2 < 0.7

DIIL2
for IO Type 2 PU/PD disabled,
DVDIO = 1.8V, -5 - 5
u@ C
-0.3 < VIN1 < 0.45

PU enabled,
DVDIO = 1.8V, -35 - 0.8 μA
.Li K
-0.3 < VIN1 < 0.45

PD enabled,
no TE
DVDIO = 1.8V, -9.3 - 11.4

-0.3 < VIN1 < 0.45
DVOH > 2.38V,
-16 - - mA
Digital high output current DVDIO = 2.8V
DIOH2
Ar IA
for IO Type 2 DVOH > 1.53V,

-12 - - mA
DVDIO = 1.8V
DVOL < 0.42V,
- - 16 mA
R ED
Digital low output current DVDIO = 2.8V

DIOL2
for IO Type 2 DVOL < 0.27V,
- - 12 mA
DVDIO = 1.8V
Digital I/O pull-up DVDIO = 2.8V 40 85 190 kΩ
DRPU2
FO M
resistance for IO Type 2 DVDIO = 1.8V 70 150 320 kΩ

Digital I/O pull-down DVDIO = 2.8V 40 85 190 kΩ
DRPD2
Digital output high DVDIO = 2.8V 2.38 V
DVOH2
voltage for IO Type 2 DVDIO = 1.8V 1.53 V
Digital output low voltage DVDIO = 2.8V 0.42 V
DVOL2
for IO Type 2 DVDIO = 1.8V 0.27 V


MT2503D
Confidential A
Y
NL
PU/PD disabled,
US IAL
DVDIO = 2.8V, -5 - 5
2.1 < VIN3 < 3.1
EO
PU enabled,
DVDIO = 2.8V, -22.5 - 12.5 μA
2.1 < VIN3 < 3.1
hk T
PD enabled,
DVDIO = 2.8V, 6.1 - 82.5
m. EN
Digital high input current 2.1 < VIN3 < 3.1
DIIH3
DVDIO = 1.8V, -5 - 5
1.35 < VIN3 < 2.1
PU enabled,

1.35 < VIN3 < 2.1
PD enabled,
-11.4 - 9.3 μA
sac NF
DVDIO = 1.8V, -0.8 - 35
1.35 < VIN3 < 2.1
PU/PD disabled,
DVDIO = 2.8V, -5 - 5
O
-0.3 < VIN3 < 0.7

PU enabled,
DVDIO = 2.8V, -82.5 - -6.1 μA
u@ C
-0.3 < VIN3 < 0.7

PD enabled,
DVDIO = 2.8V, -12.5 - 22.5
.Li K

DIIL3
no TE
DVDIO = 1.8V, -5 - 5
-0.3 < VIN3 < 0.45
PU enabled,
DVDIO = 1.8V, -35 - 0.8 μA
Ar IA
-0.3 < VIN3 < 0.45

PD enabled,
DVDIO = 1.8V, -9.3 - 11.4
-0.3 < VIN3 < 0.45
R ED
DVOH > 2.38V,

-16 - - mA
DIOH3
-12 - - mA
DVDIO = 1.8V
FO M
DVOL < 0.42V,

- - 16 mA
DIOL3
- - 12 mA
DVDIO = 1.8V
DRPU3
DRPD3 Digital I/O pull-down DVDIO = 1.8V 10 47 100 kΩ


MT2503D
Confidential A
Y
NL
US IAL
DVOH3
EO
DVDIO = 1.8V 1.53 V
DVOL3
PU/PD disabled,
hk T
DVDIO = 2.8V, -5 - 5
2.1 < VIN4 < 3.1
m. EN
PU enabled,
DIIH4 DVDIO = 2.8V, -22.5 - 12.5 μA
for IO Type 4
2.1 < VIN4 < 3.1
PD enabled,

2.1 < VIN4 < 3.1
PU/PD disabled,
6.1 - 82.5
sac NF
DVDIO = 2.8V, -5 - 5
-0.3 < VIN4 < 0.7
PU enabled,
Digital low input current
DIIL4 DVDIO = 2.8V, -82.5 - -6.1 μA
for IO Type 4
-0.3 < VIN4 < 0.7
O
PD enabled,
DVDIO = 2.8V, -12.5 - 22.5
u@ C
-0.3 < VIN4 < 0.7

Digital high output current DVOH > 2.38V,
DIOH4 -16 - - mA
.Li K

DIOL4 - - 16 mA
no TE
Digital I/O pull-up

DRPU4 resistance for IO Type 4 DVDIO = 2.8V 15 36 55 kΩ
(GPIO mode)
DRPD4 resistance for IO Type 4 DVDIO = 2.8V 15 36 55 kΩ
Ar IA
(GPIO mode)
DRPU4 Digital I/O pull-up

resistance for IO Type 4 DVDIO = 2.8V 1200 - - kΩ
1200K (Key PAD mode)
R ED
DRPD4 Digital I/O pull-down

1200K (Key PAD mode)
Digital output high
FO M

for IO Type 4
PU/PD disabled,
DIIH5 DVDIO = 2.8V, -5 - 5 μA
for IO Type 5
2.1 < VIN5 < 3.1


MT2503D
Confidential A
Y
NL
PU enabled,
US IAL
DVDIO = 2.8V, -22.5 - 12.5
2.1 < VIN5 < 3.1
EO
PD enabled,
DVDIO = 2.8V, 6.1 - 82.5
2.1 < VIN5 < 3.1
hk T
PU/PD disabled,
DVDIO = 2.8V, -5 - 5
m. EN
-0.3 < VIN5 < 0.7
Digital low input current PU enabled, DVDIO =
DIIL5 -82.5 - -6.1 μA
for IO Type 5 2.8V, -0.3 < VIN5 < 0.7
PD enabled,
DVDIO = 2.8V, -12.5 - 22.5
DIOH5
.co ID
for IO Type 5
-0.3 < VIN5 < 0.7
DVOH > 2.38V,
DVDIO = 2.8V
-16 - - mA
sac NF
DIOL5 - - 16 mA
Digital I/O pull-up
DRPU5 resistance for IO Type 5 DVDIO = 2.8V 15 36 55 kΩ
O
(GPIO mode)
DRPD5 resistance for IO Type 5 DVDIO = 2.8V 15 36 55 kΩ
u@ C
(GPIO mode)
DRPU5 Digital I/O pull-up

1K
.Li K
(Key PAD mode)
DRPD5 Digital I/O pull-down

no TE
1K (Key PAD mode)

Digital output high
Ar IA
for IO Type 5
PU/PD disabled, DVDIO
= 2.8V, -5 - 5
2.1 < VIN6 < 3.1
R ED
PU enabled,
DVDIO = 2.8V, -22.5 - 12.5 μA
2.1 < VIN6 < 3.1
PD enabled,
FO M
Digital high input current DVDIO = 2.8V, 6.1 - 82.5

DIIH6
for IO Type 6
2.1 < VIN6 < 3.1
PU/PD disabled,
DVDIO = 1.8V, -5 - 5
1.35 < VIN6 < 2.1
μA
PU enabled,
DVDIO = 1.8V, -11.4 - 9.3
1.35 < VIN6 < 2.1


MT2503D
Confidential A
Y
NL
PD enabled,
US IAL
DVDIO = 1.8V, -0.8 - 35
1.35 < VIN6 < 2.1
EO
PU/PD disabled,
DVDIO = 2.8V, -5 - 5
-0.3 < VIN6 < 0.7
hk T
PU enabled,
DVDIO = 2.8V, -82.5 - -6.1 μA
m. EN
-0.3 < VIN6 < 0.7
PD enabled,
DVDIO = 2.8V, -12.5 - 22.5
DIIL6

-0.3 < VIN6 < 0.45
PU enabled,
-5 - 5
sac NF
DVDIO = 1.8V, -35 - 0.8 μA
-0.3 < VIN6 < 0.45
PD enabled,
DVDIO = 1.8V, -9.3 - 11.4
O
-0.3 < VIN6 < 0.45

DVOH > 2.38V,
-8 - - mA
DVDIO = 2.8V
u@ C

DIOH6
-6 - - mA
DVDIO = 1.8V
.Li K
DVOL < 0.42V,

- - 8 mA
DIOL6
no TE
- - 6 mA
DVDIO = 1.8V
DRPU6
kΩ
Ar IA
Digital I/O pull-down DVDIO = 2.8V 40 85 190

DRPD6
DVOH6
R ED
DVDIO = 1.8V 1.53 V

DVOL6
PU/PD disabled,
FO M
DVDIO = 2.8V, -5 - 5
2.1 < VIN7 < 3.1
PU enabled,
DIIH7 DVDIO = 2.8V, -22.5 - 12.5 μA
for IO Type 7
2.1 < VIN7 < 3.1
PD enabled,
DVDIO = 2.8V, 6.1 - 82.5
2.1<VIN7<3.1


MT2503D
Confidential A
Y
NL
PU/PD disabled,
US IAL
DVDIO = 1.8V, -5 - 5
1.35 < VIN7 < 2.1
EO
PU enabled,
DVDIO = 1.8V, -11.4 - 9.3 μA
1.35 < VIN7 < 2.1
hk T
PD enabled,
DVDIO = 1.8V, -0.8 - 35
m. EN
1.35 < VIN7 < 2.1
PU/PD disabled,
DVDIO = 2.8V, -5 - 5
-0.3 < VIN7 < 0.7
PU enabled,

-0.3 < VIN7 < 0.7
PD enabled,
-82.5 - -6.1 μA
sac NF
DVDIO = 2.8V, -12.5 - 22.5
DIIL7
DVDIO = 1.8V, -5 - 5
O
-0.3 < VIN7 < 0.45

PU enabled,
DVDIO = 1.8V, -35 - 0.8 μA
u@ C
-0.3 < VIN7 < 0.45

PD enabled,
DVDIO = 1.8V, -5 - 5
.Li K
-0.3 < VIN7 < 0.45

DVOH > 2.38V,
no TE
-16 - - mA
DIOH7
-12 - - mA
DVDIO = 1.8V
Ar IA
DIOL7 - - 16 mA
DVOL < 0.27V,
- - 12 mA
DVDIO = 1.8V
R ED

DRPU7
Digital I/O pull-down DVDIO = 2.8V 40 85 190 kΩ
DRPD7
FO M

DVOH7
voltage for IO Type 7 DVDIO = 1.8V 1.53 V
DVOL7


MT2503D
Confidential A
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2.3 System Configuration
US IAL
2.3.1 Strapping Resistors
EO
Table 15. Strapping table
Pin name Description Trapping condition

Pull-up with 10K resister(Default internal pull-
LSA0 Power-on reset
hk T
down with 47K resister)
Pull-up with 10K resister (Default internal pull-
BPI_BUS1 Power-on reset
m. EN
Pull-up with 10K resister (Default internal pull-
BPI_BUS2 Power-on reset
2.3.2
.co ID
Mode Selection
Table 16. Mode selection of chip
sac NF
Pin name Description
GND: Uses DCXO as 26M clock source
EXT_CLK_SEL
VRF: Uses external clock as 26M clock source
GND: Uses 1.8V serial flash device
O
LSA0
DVDD18_EMI: Uses 3.3V serial flash device
GND: Boots ROM to enter USB download mode
KCOL0
u@ C
DVDD28: Normal boot-up mode

{GND, GND}: No JTAG
{BPI_BUS1,BPI_BU {GND, DVDD28}: JTAG at keypad pins
.Li K
S2} {DVDD28, GND}: JTAG at GPIO pins

{DVDD28, DVDD28}: JTAG at camera pins
no TE
2.4 Power-on Sequence and Protection Logic

Ar IA
MT2503D provides 32K crystal removal feature. The XOSC32_ENB state tells if MT2503D provides
this feature or not. VRF will be turned on at the same time with VRTC when XOSC32_ENB = 1. The
power-on/off sequence controlled by “Control” and “Reset Generator” is shown as the figure below.
R ED
FO M


MT2503D
Confidential A
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<=100ms
US IAL
VBAT
EO
DDLO
XOSC32
_ENB=0
hk T
VRTC
m. EN
UVLO
PWRKEY
PWRBB
.co ID De-bounce
time = 50ms
sac NF
1.7ms
VCORE
1.7ms
VIO18
O
1.7ms
VIO28
u@ C
1.7ms
VSF
1.7mms
.Li K
VA
1.7ms
no TE
VUSB
1.7ms
VRF
Ar IA
1.7ms
RESETB
200ms
R ED
Figure 5. Power-on/off control sequence by pressing PWRKEY and XOSC32_ENB = 0

FO M


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Confidential A
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<=100ms
US IAL
VBAT
EO
DDLO
XOSC32
_ENB=1
hk T
VRTC/
m. EN
VRF
UVLO
PWRKEY
.co ID De-bounce
time = 50ms
sac NF
PWRBB
1.7ms
VCORE
1.7ms
O
VIO18
1.7ms
u@ C
VIO28
1.7ms
.Li K
VSF
1.7mms
no TE
VA
1.7ms
VUSB
Ar IA
1.7ms
1.7ms
R ED
RESETB
200ms
Figure 6. Power-on/off control sequence by pressing PWRKEY and XOSC32_ENB = 1

FO M
Note that each of the above figures only shows one power-on/off condition when XOSC32_ENB = 0
or XOSC32_ENB = 1. MT2503D handles the power-on and off of the handset. The following three
methods can switch on the handset (when leaving UVLO): XOSC32_ENB = 0
1. Push PWRKEY (Pull the PWRKEY pin to the low level.)


MT2503D
Confidential A
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Pulling PWRKEY low is the typical way to turn on the handset. The turn-on sequence is
VCORE  VIO18  VIO28  VSF  VA  VUSB  VRF.
US IAL
The supplies for the baseband are ready, and the system reset ends at the moment when the
EO
above LDOs are fully turned on to ensure correct timing and function. After that, the baseband will
send the PWRBB signal back to the PMU for acknowledgement. To successfully power on the
handset, PWRKEY should be kept low until PMU receives PWRBB from the baseband.
hk T
2. RTC module generates PWRBB to wake up the system.
m. EN
If the RTC module is scheduled to wake up the handset at a certain time, the PWRBB signal will
be directly sent to the PMU. In this case, PWRBB will become high at specific moment and allow
the PMU to be powered on as the sequence described above. This is called the RTC alarm.
.co ID
3. Valid charger plug-in (CHRIN voltage is within the valid range.)
sac NF
The charger plug-in will also turn on the handset if the charger is valid (no OVP takes place).
However, if the battery voltage is too low to power on the handset (UVLO state), the system will
not be turned on by any of the three methods. In this case, the charger will charge the battery first
O
and the handset will be powered on automatically as long as the battery voltage is high enough.
Under-voltage lockout (UVLO)

u@ C
The UVLO state in the PMU prevents startup if the initial voltage of the main battery is below the 3.2V
threshold. It ensures that the handset is powered on with the battery in good condition. The UVLO
.Li K
function is performed by a hysteretic comparator which ensures a smooth power-on sequence. In

addition, when the battery voltage is getting lower, it will enter the UVLO state, and the PMU will be
no TE
turned off by itself, except for VRTC LDO, to prevent further discharging. Once the PMU enters the
UVLO state, it will draw low quiescent current. The RTC LDO will still be working until the DDLO
disables it.
Ar IA
Deep discharge lockout (DDLO)

The PMU will enter the deep discharge lockout (DDLO) state when the battery voltage drops below
2.5V. In this state, the VRTC LDO will be shut down. Otherwise, it will draw very low quiescent current
R ED
to prevent further discharging or damage to the cells.
Reset
The PMU contains a reset control circuit which takes effect at both power-up and power-down. The
FO M
RESETB pin is held low in the beginning of power-up and returns to high after the pre-determined
delay time. The delay time is controlled by a large counter which uses the clock from internal ring-
oscillator. At power-off, the RESETB pin will return to low immediately without any delay.
Over-temperature protection


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If the die temperature of PMU exceeds 150°C, the PMU will automatically disable all the LDOs except
for VRTC. Once the over-temperature state is resolved, a new power-on sequence will be required to
US IAL
enable the LDOs.
EO
2.5 Analog Baseband
hk T
To communicate with analog blocks, a common control interface for all analog blocks is implemented.
In addition, there are some dedicated interfaces for data transfer. The common control interface
m. EN
translates the APB bus write and read cycle for specific addresses related to analog front-end control.
During the writing or reading of any of these control registers, there is a latency associated with the
transfer of data to or from the analog front-end. Dedicated data interface of each analog block is
implemented in the corresponding digital block. An analog block includes the following analog
1.
.co ID
functions for the complete GSM/GPRS baseband signal processing:
RF control: DAC for automatic power control (APC) is included, and its output is provided to
sac NF
external RF power amplifier respectively.
2. Auxiliary ADC: Provides an ADC for the battery and other auxiliary analog functions monitoring
O
3. Audio mixed-signal block: Provides complete analog voice signal processing including
u@ C
microphone amplification, A/D conversion, D/A conversion, earphone driver, etc. Dedicated
stereo D/A conversion and amplification for audio signals are also included.
.Li K
4. Clock generation: Includes a clock squarer for shaping the system clock, and PLL providing
no TE
clock signals to DSP, MCU and USB unit

Ar IA
2.5.1 APC-DAC
2.5.1.1 Block Description
R ED
APC-DAC is a 10-bit DAC with output buffer aiming at automatic power control. See the tables below
for its analog pin assignment and functional specifications. It is an event-driven scheme for power
saving purpose.
FO M
2.5.1.2 Functional Specifications

Table 17. APC-DAC specifications
Symbol Parameter Min. Typ. Max. Unit

N Resolution 10 Bit
FS Sampling rate 1.0833 MSPS


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SINAD Signal to noise and distortion ratio 47 dB
US IAL
(10-kHz sine with 1.0V swing & 100-kHz BW)
99% settling time (full swing on maximal 5 μS
EO
capacitance)
Output swing 0 AVDD V
Output capacitance 200 2200 pF
hk T
Output resistance 0.47 10 KΩ
DNL Differential nonlinearity for code 20 to 970 ±1 LSB
m. EN
INL Integral nonlinearity for code 20 to 970 ±1 LSB
DVDD Digital power supply 1.1 1.2 1.3 V
AVDD Analog power supply 2.6 2.8 3.0 V
T Operating temperature -20 80 °C
.co ID
Current consumption
Power-up
Power-down
400
1
μA
μA
sac NF
2.5.2 Auxiliary ADC
O
The auxiliary ADC includes the following functional blocks:

u@ C
1. Analog multiplexer: Selects signal from one of the seven auxiliary input pins. Real-world
messages to be monitored, e.g. temperature, should be transferred to the voltage domain.

.Li K
2. 10-bit A/D converter: Converts the multiplexed input signal to 10-bit digital data.
no TE
Channel Application Input range [V]

0 BATSNS 3.2 ~ 4.2
1 ISENSE 3.2 ~ 4.2
Ar IA
2 VCDT Decided by application circuit

3 BATON 0 ~ AVDD28
R ED
4 AUXIN4 0 ~ AVDD28
others Internal use N/A
FO M

The functional specifications of the auxiliary ADC are listed in the following table.
Table 18. Functional specifications of auxiliary ADC


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N Resolution 10 Bit
US IAL
FC Clock rate 1.08 MHz
FS Sampling rate @ N-Bit 1.08/(N+1)
EO
MSPS
Input swing 0 AVDD V
CIN Input capacitance
Unselected channel 50 fF
hk T
Selected channel 4 pF
RIN Input resistance
m. EN
Unselected channel 400 MΩ
Selected channel 1 MΩ
Clock latency N+1 1/FC
DNL Differential nonlinearity ±1 LSB
INL
OE
FSE
.co ID
Integral nonlinearity
Offset error
Full swing error
±1
± 10
± 10
LSB
mV
mV
sac NF
SINAD Signal to noise and distortion ratio (10-kHz full
50 dB
swing input & 1.0833-MHz clock rate)
O

Current consumption
u@ C
Power-up 280 μA
Power-down 1 μA
.Li K
2.5.3 Audio Mixed-Signal Blocks

no TE

Audio mixed-signal blocks (AMB) integrate complete voice uplink/downlink and audio playback
functions. As shown in the figure below, it includes three parts. The first consists of stereo audio DACs
and audio amplifiers for audio playback. The second part is the voice downlink path, including voice-
Ar IA
band DACs (left channel audio DAC) and voice amplifier, which produces voice signals to earphones
or other auxiliary output devices. Moreover, a ClassK amplifier is embedded to support continuous
>1W output power with an on-chip boost. The last part is the voice uplink path, which is the interface
R ED
between the microphone (or other auxiliary input device) input and MT2503D DSP. A set of bias
voltage is provided for the external electric microphone.
FO M


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Confidential A
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PGA Class-K AU_SPKP
US IAL
AU_SPKN
EO
Audio Amp-R
Voice Signal AU_HPR
Audio
Stereo or Mono RCHDAC
Audio Signal
Audio Amp-L
hk T
Voice Signal AU_HPL
Audio
Stereo or Mono LCHDAC
Audio Signal
m. EN
AU_HSP
AU_HSN
.co ID Voice Amp
AU_VIN1_P
sac NF
PGA
Voice Signal AU_VIN1_N
M U X
Voice
ADC AU_VIN0_P
O
AU_VIN0_N
u@ C
Figure 7. Block diagram of audio mixed-signal blocks

.Li K

no TE
See the table below for the functional specifications of voice-band uplink/downlink blocks.
Table 19. Functional specifications of analog voice blocks

Ar IA
FS Sampling rate 6,500 kHz

R ED

VMIC Microphone biasing voltage 1.9 2.2 V
IMIC Current draw from microphone bias pins 2 mA
4
Uplink path
FO M
IDC Current consumption for one channel 1.5 mA

Signal to noise and distortion ratio
SINAD
Input level: -40 dbm0 29 dB
4
For uplink-path, not all gain settings of VUPG meet the specifications listed in the table, especially for several the lowest gains.
The minimum gain that meets the specifications is to be determined.


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Input level: 0 dbm0 69 dB
US IAL
RIN Input impedance (differential) 13 20 27 KΩ
ICN Idle channel noise -67 dBm0
EO
Downlink path
IDC Current consumption 4 mA
Signal to noise and distortion ratio
hk T
SINAD Input level: -40 dBm0 29 dB
Input level: 0 dBm0 69 dB
m. EN
RLOAD Output resistor load (differential) 16 32 Ω
CLOAD Output capacitor load 250 pF
ICN Idle channel noise of transmit path -64 dBPa
XT Crosstalk level on transmit path -66 dBm0
.co ID
See the table below for the functional specifications of audio blocks.
Table 20. Functional specifications of analog audio blocks

sac NF
FCK Clock frequency 6.5 MHz
Fs Sampling rate 32 44.1 48 kHz
O
AVDD Power supply 2.6 2.8 3.0 V

u@ C
IDC Current consumption 4 mA

PSNR Peak signal to noise ratio 88 dB
.Li K
DR Dynamic range 88 dB
Output swing for 0dBFS input level @ -1dB
VOUT 0.707 Vrms
headphone gain
no TE
VOUTMAX Maximum output swing 2.0 Vpp

Total harmonic distortion
THD
10mW at 64Ω load -70 dB
RLOAD Output resistor load (single-ended) 64 Ω
Ar IA
CLOAD Output capacitor load 250 pF

XT L-R channel cross talk 70 dB
R ED
2.6 Power Management Unit Blocks

The power management unit (PMU) manages the power supply of the entire chip, such as baseband,
FO M
processor, memory, SIM cards, camera, vibrator, etc. The digital part of PMU is integrated into the
analog part (see the figure below). PMU includes the following analog functions for signal processing:
 LDO: Regulates battery voltage to lower voltage level

 BOOST: Boosts battery voltage to target voltage for Class-AB audio amplifier
 Keypad LED driver (KPLED) and current sink (ISINK) switches: Sink current for keypad LED and
LCM module


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 Start-up (STRUP): Generates power-on/off control sequence of start-up circuits
 Pulse charger (PCHR): Controls battery charging
US IAL
Backup Battery
EO
VCORE
LCM
Current Sink
Module Essential LDOs
VCORE
VRTC Base Band
hk T
VRTC VA Processor
VA VIO18
VIO18 VIO28
1 2 3
m. EN
4 5 6
KP LED Driver VIO28
7 8 9 (Open Drain) VMC
VSF
0 # VSIM1 Serial Flash
VSIM2 VMC
VSF Memory card
Class-AB
VSIM1
Audio Amplifier
SIM1
.co ID BOOST
Control
Reset
Generator Basic Feature
LDOs
VSIM2
VUSB
SIM2
sac NF
VIBR Extra LDOs VUSB SDIO Device
M Vibrator VCAMA
VCAMA
Camera sensor
(AF)
SIM
Charger BJT Pulse-Charger Blue Tooth
Level Shifter
O
In +Rsense Controller (on chip)
MT2503D 2G Transceiver
LDOs
VRF
2G RF Transceiver
(on chip)
PMU VRF
u@ C
Figure 8. PMU system block diagram

.Li K
no TE
2.6.1 LDO
PMU integrates 13 general low dropout regulators (LDO) optimized for their given functions by
balancing the quiescent current, dropout voltage, line/load regulation, ripple rejection and output noise.
Ar IA
R ED
FO M


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PCHR STARTUP
CHRIN BATSNS
US IAL
7.5k
AVDD28_CHRLDO
Backlight and
EO
BATSNS
KPLED
C=1uF CHR CHR CHR 1.2V
PWR_SEL
LDO28 ANACKT LDO12
(max 4.3V) LDO IGEN
PWRKEY ISINK,
V12 VGEN KPLED
CHR controller
CTRL V33
LIMT STARTU
(2.5~3.3V) AVDD33/XVDD33/DVDD33
hk T
P
BGR PNP BGR CHRLDO

DDLO UVLO
BIAS BGR OSC DET
m. EN
LDO-Group1 VBAT1 LDO-Group2 Class AB
VBAT2 VBAT_BOOST and BOOST
VSIM1 VMC VSIM2 VCORE VA

BOOST BOOST
VIO28 VCAMA VRF
Cotroller Driver
VIO18
.co ID
VUSB VIBR
VIO18 VRTC
VBOOST
ClassAB
Cotroller
ClassAB
Driver
sac NF
Figure 9. Power domain
O
2.6.1.1 LDO
u@ C
A low-dropout regulator (LDO) is capable of maintaining its specified output voltage over a wide range
of load current and input voltage, down to a very small difference between input and output voltages.
.Li K
There are several features in the design of LDO, including discharge control, soft start and current
limit. Before LDO is enabled, the output pin of LDO should be discharged first to avoid voltage
no TE
accumulation on the capacitance. The soft-start limits inrush current and controls output-voltage rising
time during the power-up. The current limit is the current protection to limit the LDO’s output current
and power dissipation.
Ar IA
There are three types of LDOs in PMU of MT2503D PMU. The analog LDO is optimized for low-
frequency ripple rejection in order to reject the ripples coming from the burst of RF power amplifier.
The digital IO LDO is a linear regulator optimized for very low quiescent current. The single-step RTC
R ED
LDO is a linear regulator that can charge up a capacitor-type backup coin cell, which also supplies the
RTC module even at the absence of the main battery. The single-step LDO features reverse current
protection and is optimized for ultra-low quiescent current while sustaining the RTC function as long
as possible.
FO M


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2.6.1.1.1 Block Description
US IAL
AVDD43_VXX
EO
Current
Limit
VREF
hk T
VOUT VOUT
m. EN
R1
VOUT
Discharge
R2 Control
.co ID
sac NF
GND
Figure 10. LDO block diagram

O
2.6.1.1.2 LDO Types

u@ C
Table 21. LDO types and brief specifications
Type LDO name Vout (Volt) Imax(mA) Description

.Li K
RF chip and 26MHz

ALDO VRF 2.8 150
reference clock
no TE
ALDO VA 2.8 150 Analog baseband

ALDO VCAMA 2.8 70 Camera sensor
DLDO VIO28 2.8 100 Digital IO and Blue tooth
Ar IA
DLDO VSIM1 1.8/3.0 30 SIM card

DLDO VSIM2 1.8/3.0 30 SIM card
DLDO VUSB 3.3 50 USB
R ED
DLDO VIO18 1.8 100 Digital IO

DLDO VCORE 0.75~1.35 150 Digital baseband
DLDO VIBR 1.8/2.8/3.0 100 Vibrator
DLDO VMC 1.8/2.8/3.0/3.3 100 Memory card
FO M
DLDO VSF 1.86/2.8/3.0/3.3 50 Serial flash

RTCLDO VRTC 2.8/3.3 2 Real-time clock


MT2503D
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2.6.1.1.3 Functional Specifications
US IAL
Table 22. Analog LDO specifications
EO
Load capacitor 1 μF
Current limit 1.2*Imax 5*Imax mA
hk T
Includes load
regulation, line Max. (-5%, Max. (+5%,
Vout V
regulation, and -0.1V) +0.1V)
m. EN
temperature coefficient
Max. (-5%, Max. (+5%,
Transient response Slew: 15mA/us V
-0.1V) +0.1V)
Temperature
.co ID
coefficient
PSRR
Iout < 0.5*Imax
10 < f < 3 kHz
65
100 ppm/C
dB
sac NF
Iout < 0.5*Imax
45 dB
3K < f< 30 kHz
Output noise With A-weighted filter 90 uVrms
Quiescent current Iout = 0 55 μA
O
Max.
Turn-on overshoot Iout = 0 (+10%, V
u@ C
+0.1V)
Turn-on settling
Iout = 0 240 μsec
time
.Li K
Table 23. Digital LDO specifications

no TE

5
Ar IA
Current limit 1.2*Imax 5*Imax mA

Includes load
Max.
regulation, line Max. (-
Vout (+5%, V
regulation, and 5%, -0.1V)
R ED
+0.1V)
Max.
Max. (-
Transient response Slew: 15mA/us (+5%, V
5%, -0.1V)
+0.1V)
FO M
Temperature
100 ppm/C
coefficient
5 VCORE loading capacitor typical value is 2.2uF. Other LDOs are 1uF.


MT2503D
Confidential A
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Max.
US IAL
Turn-on overshoot Iout = 0 (+10%, V
+0.1V)
EO
Turn-on settling
Iout = 0 240 μs
time
hk T
Table 24. RTC LDO specification
m. EN
Includes load regulation,
Vout line regulation, and 2 2.8 3 V
.co ID
Temperature
coefficient
100 ppm/C
sac NF
2.6.2 BOOST
O

u@ C
Table 25. RTC LDO specification.

.Li K
Cin 2.2uF
μF
Cout 4.7uF
no TE
L Rdcr,max<80mOhm 0.68 uH
Vout 5.3 V
Ripple
Vin=3.4V/3.8V/4.2V,
Ar IA
Cin=2.2uF & Cout=4.7uF,

L= 0.68uH 100 mV
(Rdcr,max<80mOhm)
R ED
650mA , switching Freq

2MHz
Switching
2 MHz
frequency
FO M
Quiescent current Iout = 0 4 6 mA
2.6.3 ISINK and KPLED Switches
One built-in open-drain output switch drives the keypad LED (KPLED) in the handset. The switch is
controlled by the baseband with enabling registers. The switch of keypad LED can sink as much as


MT2503D
Confidential A
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60mA current, and the output is high impedance when disabled. The value of the sink current decides
the brightness of the LED.
US IAL
The current controlled open drain drivers are also implemented to drive the LCM backlight module,
EO
and provides currentfrom 4mA to 96mA.
hk T
m. EN
AVDD43
ISINK
.co ID
NI_ISINKS_CH_EN ISINK_EN
sac NF
RG_ISINKS_CH0_STEP[2:0]
Step[2:0]
O
PAD_KPLED
NI_KPLED_EN
u@ C
A2D signals
NI_ISINK0_STATUS
KPLED_EN
.Li K
NI_ISINK1_STATUS
NI_ISINK2_STATUS
NI_ISINK3_STATUS AVSS43_DRV
NI_KPLED_STATUS
no TE
Figure 11. ISINKs and KPLED switches bock diagram.

Ar IA

R ED
Table 26. ISINKs and KPLED Switches Specification.

Sink current of keypad Von > 0.5V, 100% dimming
60 mA
LED driver duty
FO M
1 ch Sink current of Von > 0.15V, 100%

ISINK without current dimming duty, 4 mA
double option ISINKS_CHx_STEP = 000
1 ch Sink current of Von > 0.15V, 100% 12 mA


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ISINK without current dimming duty,
US IAL
EO
hk T
m. EN
Von > 0.15V, 100%
Current mismatch -5 5 %
dimming duty
2.6.4
.co ID
STRUP
sac NF
PMU handles the power-on and off of the handset. If the battery voltage is neither in the UVLO state
(VBAT ≥ 3.4V) nor in the thermal condition, there are three methods to power on the handset system:
pulling PWRKEY low (the user pushes PWRKEY), pulling PWRBB high (baseband BB_WakeUp) or
O
valid charger plug-in.

u@ C
According to different battery voltage (VBAT) and phone states, control signals and regulators will
have different responses.
.Li K
2.6.5 PCHR
no TE
The charger controller senses the charger input voltage from either a standard AC-DC adaptor or an
USB charger. When the charger input voltage is within a pre-determined range, the charging process
will be activated. This detector can resist higher input voltage than other parts of the PMU.
Ar IA
R ED
FO M


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Confidential A
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US IAL
EO
hk T
m. EN
.co ID
sac NF
O
u@ C
.Li K
Figure 12. PCHR block diagram.

no TE
2.6.5.1.1 Charger Detection

Ar IA
Whenever an invalid charging source is detected (> 7.0 V), the charger detector stops the charging
process immediately to avoid burning out the chip or even the phone. In addition, if the charger-in
level is not high enough (< 4.3V), the charger will also be disabled to avoid improper charging
R ED
behavior.
2.6.5.1.2 Charging Control

FO M
When the charger is active, the charger controller manages the charging phase according to the
battery status. During the charging period, the battery voltage is constantly monitored. The battery
charger supports pre-charge mode (VBAT < 3.2V, PMU power-off state), CC mode (constant current
mode or fast charging mode at the range 3.2V < VBAT < 4.2V) and CV mode (constant voltage mode)
to optimize the charging procedure for Li-ion battery. The charging states diagram is shown in the
figure below.


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US IAL
NON- CHARGING
EO
Dead Battery
VBAT <2.2V YES
5 min timeout
hk T
NO
m. EN
CHRIN >4. 3V
CHRIN DET
YES
.co ID VBAT >3.3V

YES
sac NF
NO CC Mode
YES VBAT< 3 .3V

Charger OFF 35 min timeout
O
VBAT>4.1V NO
NO
u@ C
PreCC
CV Mode
.Li K
YES
FULL
no TE
NO
VBAT=4.2V
Ar IA
YES
Reduce ICHG
by step
R ED
NO
ICHG < I TERM
YES
FO M
Charger OFF
YES VBAT<4.05V NO
Re- Charge
Figure 13. Charging states diagram


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Confidential A
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Pre-charge mode
US IAL
When the battery voltage is in the UVLO state, the charger operates in the pre-charge mode. There
are two steps in this mode. When the battery voltage is deeply discharged below 2.2V, PRECC1
EO
trickle charging current will be applied to the battery.
The PRECC1 trickle charging current is about 550ms pulse 70mA current when VBAT is under 2.2V.
hk T
When the battery voltage exceeds 2.2V, called the PRECC2 stage, the closed-loop pre-charge is
m. EN
enabled. The voltage drop across the external RSENSE is kept around 40mV (AC charger) or 14mV
(USB host). The closed-loop pre-charge current can be calculated:
VSENSE 40mV
IPRECC2, AC adapter  
.co ID
IPRECC2,USBHOST
Rsense Rsense
V
 SENSE 
14mV
Rsense Rsense
sac NF
Constant current mode
As the battery is charged up and over 3.4V, it can switch to the CC mode. (CHR_EN should be high)
O
In the CC mode, several charging currents can be set by programming registers or the external
RSENSE resistor. The charging current can be determined by CS_VTH/RSENSE, where CS_VTH is
programmed by registers. For example, if RSENSE is selected as 0.2ohm, the CC mode charging
u@ C
current can be set from 70 to 800mA. It can accommodate the battery charger to various charger
inputs with different current capabilities.
.Li K
Constant voltage mode and over-voltage protection (OV)

While the battery voltage reaches about 4.2V, a constant voltage is used for charging. This is called
no TE
the full-voltage charging mode or constant-voltage charging mode in correspondence to a linear

charger. While the battery voltage actually reaches 4.2V, the charging current is gradually decreased
step-by-step, the end-of-charging process starts. It may prolong the charging and detecting period for
Ar IA
acquiring optimized full charging volume. The charging process is completed once the current
reaches zero automatically and this mechanism is optimized for different battery
R ED
BC1.1 Dead-Battery Support of China Standard

MT2503D supports dead-battery condition from China standard (called BC1.1). The specification
protects dead-battery charging by timer and trickle current. Once the battery voltage is below 2.2V, a
period (TUNIT) of trickle current (IUNIT) will be applied to the battery.
FO M
If the battery voltage is still below 2.2V after applying trickle current, the charger will be disabled. On
the other hand, if the battery voltage is raised to above 2.2V, the charger will enter the PRECC2 stage,
and the charging current will be 70mA or 200mA depending on the type of charging port.
Under the condition of battery voltage from 2.2V to 3.3V, the charger will charge the battery with the
PRECC2 current.


MT2503D
Confidential A
Y
NL
A dedicated 5mins (T1) timer will be timed out and disable the charger if the battery voltage is always
US IAL
below 2.7V under charging. Another 35mins (T2) timer will also be timed out and disable the charger if
the battery voltage is always kept between 2.7V and 3.3V under charging.
EO
The trickle current (IUNIT) and two dedicated timers protect the charging action if the battery is dead.
hk T
m. EN
Table 27. Charger detection specifications

Charger detect-on
.co ID
range
Table 28. Pre-charge specifications

4.3 7 V
sac NF
IUNIT with 500ms
VBAT < 2.2V 20 48 100 mA
pulse
O
VBAT < 2.2V (500ms

20 48 100 mA
pulse)
u@ C
VBAT ≥ 2.2V (USB

7/Rsense 14/Rsense 20/Rsense mA
host)
Pre-charging current
VBAT ≥ 2.2V (AC
.Li K

adapter < 7V)
VBAT ≥ 2.2V (AC
no TE
adapter > 7V)

Pre-charging off
CHR_EN = L 3.3 V
threshold
Ar IA
Pre-charging off
0.4 V
hysteresis
R ED
Table 29. Constant current specifications

CS_VTH [3:0] = 0000 320/Rsense mA
FO M
CS_VTH [3:0] = 0001 300/Rsense mA

CS_VTH [3:0] = 0010 280/Rsense mA
CC mode charging
CS_VTH [3:0] = 0011 260/Rsense mA
current ( CS_VTH )
CS_VTH [3:0] = 0100 240/Rsense mA
CS_VTH [3:0] = 0101 220/Rsense mA
CS_VTH [3:0] = 0110 200/Rsense mA


MT2503D
Confidential A
Y
NL
CS_VTH [3:0] = 0111 180/Rsense mA
US IAL
CS_VTH [3:0] = 1000 160/Rsense
EO
CS_VTH [3:0] = 1001 140/Rsense
CS_VTH [3:0] = 1010 130/Rsense
CS_VTH [3:0] = 1011 110/Rsense
hk T
CS_VTH [3:0] = 1100 90/Rsense
CS_VTH [3:0] = 1101 60/Rsense
m. EN
CS_VTH [3:0] = 1110 40/Rsense
CS_VTH [3:0] = 1111 14/Rsense
Current sensing
RSENSE 0.2 ohm
resistor
.co ID
Table 30. Constant voltage and over-voltage protection specifications
sac NF
Charging complete
4.15 4.2 4.25 V
threshold
O
Battery over-voltage
protection threshold 4.3 V
(OV)
u@ C
Table 31. BC1.1 specifications

.Li K

IUNIT BC1.1 trickle current VBAT < 2.2V 50 100 mA
no TE
IPRECC2
(USB PRECC2 current 2.2 < VBAT < 3.3V 70 100 mA
host)
IPRECC2
Ar IA
(AC PRECC2 current 2.2 < VBAT < 3.3V 200 250 mA
adapter)
5 minute dedicated
T1 2.2 < VBAT < 2.7V 5 6.5 min.
R ED
timer
35 minute dedicated
T2 2.7 < VBAT < 3.3V 35 38.5 min.
timer
BC1.1 trickle current
TUNIT 550 770 ms.
FO M
period


MT2503D
Confidential A
Y
NL
2.7 GSM/GPRS RF
US IAL
2.7.1 General Description
EO
2G RFSYS which is built in MT2503D SOC is a highly integrated RF transceiver for multi-band GSM
and GPRS cellular systems.
hk T
The features include:
m. EN
Receiver
 Single-end saw-less Rx
 Quadrature RF mixer
.co ID
 Fully integrated channel filter
sac NF
 High dynamic range ADC
 12dB PGA gain with 6dB gain step

O
u@ C
Transmitter
 High accurate transmitter modulator for GSM/GPRS application
.Li K
 Built-in calibration of SX loop filter and loop gain

no TE
Frequency synthesizer
 Programmable fractional-N synthesizer
Ar IA
 Integrated wide range RFVCO

R ED
 Integrated loop filter
 Fast settling time suitable for multi-slot GSM/GPRS applications

FO M
Digitally-Controlled Crystal Oscillator (DCXO)

 Two-pin 26 MHz crystal oscillator
 On-chip programmable capacitor array for coarse-tuning
 On-chip programmable capacitor array for fine-tuning


MT2503D
Confidential A
Y
NL
 Supports 32K XTAL-less operation
US IAL
EO
2.7.2 Functional Block Diagram
hk T
RXHB
2GRXIP
2GRXIN
2GRXQP
m. EN
2GRXQN
RXLB DIV2/ SDM

DMD
DIV4 MASH111
TXO_HB .co ID DIV2

RFVCO
VCO Sub Band

Calibration
Predistortion
Gaussian
Filter
sac NF
TXO_LB DIV4 Loop XTAL1
CP PFD DCXO
Filter XTAL2
TP1
TP2
TP3
TP4
O
VRF
u@ C
2G RFDIG
GND_RF
DBB_CLK
OUT_32KB
OUT_32K
.Li K
FREF
no TE
Figure 14. Diagram of MT2503D 2G RFSYS

Ar IA
2.7.3 Electrical Characteristics

Table 32. DC characteristics (TA = 25oC, VDD = 2.8V unless otherwise stated)
R ED
RFSYS mode VRF AVDD28_2GAFE RFSYS total Unit

BCM_Deep sleep (DCXO is off) 17 1 18 uA
BCM_Sleep (DCXO is on) 1.2 0.26 1.5 mA
FO M
Low power mode 60 1 61 uA

Full power mode 1.2 0.26 1.5 mA
RX (GSM850/EGSM) 62 5 67 mA
RX (DCS/PCS) 66 5 71 mA
TX (GSM850/EGSM) 41 2 43 mA
TX (DCS/PCS) 36 2 38 mA


MT2503D
Confidential A
Y
NL
Table 33. Rx AC characteristics (TA = 25oC, VDD = 2.8V unless otherwise stated)
US IAL
Item Symbol Band Test condition Min. Typ. Max. Unit
GSM850 869 894 MHz
EO
GSM900 925 960 MHz
Input frequency FRX
DCS1800 1,805 1,880 MHz
PCS1900 1,930 1,990 MHz
hk T
1
GSM850 LNA = High gain 52 55 dB
2
GSM900 PGA = High gain 52 55 dB
Voltage gain 1 G1
m. EN
3
DCS1800 LNA = High gain 52 55 dB
4
PCS1900 PGA = High gain 52 55 dB
GSM850 LNA = Middle gain 46 dB
GSM900 PGA = High gain 46 dB
Voltage gain 2
.co ID G2
DCS1800
PCS1900
GSM850
LNA = Middle gain
PGA = High gain
LNA = Low gain
45
45
26
dB
dB
dB
sac NF
GSM900 PGA = High gain 26 dB
Voltage gain 3 G3
DCS1800 LNA = Low gain 26 dB
PCS1900 PGA = High gain 26 dB
1
O
GSM850 3 5 dB
2
GSM900 3 5 dB
Noise figure at 25°C NF25 G1 3
u@ C
DCS1800 3 5 dB
4
PCS1900 3 5 dB
GSM850 4.5 dB
.Li K
GSM900 4.5 dB
Noise figure at 85°C NF85 G1
DCS1800 4.5 dB
no TE
PCS1900 4.5 dB
1
GSM850 31 43 dBm
nd 2
2 -order input GSM900 31 43 dBm
IIP2 G2 3
intercept point DCS1800 31 43 dBm
Ar IA
4
PCS1900 31 43 dBm
1
GSM850 -14 -3 dBm
rd 2
3 -order input GSM900 -14 -3 dBm
R ED
IIP3 G2 3
intercept point DCS1800 -14 -3 dBm
4
PCS1900 -14 -3 dBm
GSM850 -5 dBm
rd
3 -order input
FO M
GSM900 -5 dBm
intercept point @ - IIP3-20 G2
20°C DCS1800 -5 dBm
PCS1900 -5 dBm
1
GSM850 G2 8 12 dB
2
Receiver S/N with GSM900 Blocker = -23dBm 8 12 dB
SN3M 3
3MHz blocker DCS1800 G2 8 12 dB
4
PCS1900 Blocker = -26dBm 8 12 dB


MT2503D
Confidential A
Y
NL
5
GSM850 G2 6 8 dB
US IAL
Blocker = 2dBm, 5
GSM900 offset +/-20MHz 6 8 dB
Receiver S/N with
EO
SNOOB 5
OBB DCS1800 G2 6 8 dB
Blocker = -10/2dBm, 5
PCS1900 offset +/-80/-100MHz 6 8 dB
1,2,3,4
Image rejection ratio IRR ALL G2 32 40 dB
hk T
Receiver channel @3MHz offset 20 dB
ALL
response attenuation
m. EN
@6MHz offset 35 dB
Receiver filtering 3-
ALL For all gain settings 900 kHz
dB bandwidth
5
INL 0.2 1 dBΩ
PGA gain linearity ALL 5
dBΩ
PGA gain step
.co ID
PGA dynamic range
ALL
ALL
DNL 0.1
6
12
0.5
dBΩ
dBΩ
sac NF
I/Q common-mode 5 5
ALL G1 1.1 1.2 1.3 V
output voltage
Output static dc offset ALL G1 100 200 mV
O
Table 34. Tx GMSK AC characteristics (TA = 25oC, VDD = 2.8V unless otherwise stated)

u@ C
GSM850 824 849 MHz

GSM900 880 915 MHz
Frequency FTX
.Li K
DCS1800 1,710 1,785 MHz

PCS1900 1,850 1,910 MHz
no TE
GSM850 1,2
1.5 2.5 degree
GSM900
RMS phase error PErms
DCS1800 3,4
1.5 2.5 degree
PCS1900
Ar IA
GSM850 1,2
400kHz offset -66 -64 dBc
GSM900
(RBW = 30kHz
DCS1800 bandwidth) 3,4
-66 -64 dBc
PCS1900
R ED
Output modulation
ORFS
spectrum GSM850 5
1.8MHz offset -75 dBc
GSM900
(RBW = 30kHz
DCS1800 bandwidth) 5
-75 dBc
PCS1900
FO M
5
20MHz offset -165 -163 dBc/Hz
GSM850 5
5
Tx noise in Rx band GSM900 5
5
DCS1800 20MHz offset -160 -156 dBc/Hz
5
PCS1900 20MHz offset -160 -156 dBc/Hz


MT2503D
Confidential A
Y
NL
GSM850 1,2 1,2
US IAL
1 3 6 dBm
GSM900 PA driver amplifier
Output power level Pout
DCS1800 Rload = 50Ω
EO
3,4 3,4
1 3 6 dBm
PCS1900
rd
Output 3 harmonics ALL PA driver amplifier -10 dBc
hk T
Table 35. SX AC characteristics (TA = 25oC, VDD = 2.8V unless otherwise stated)
m. EN
Item Symbol Test condition Min. Typ. Max. Unit
Frequency range Frange 3,296 3,980 MHz
Reference frequency Fref 26 MHz
Frequency step resolution Fres 3 Hz
Phase noise
.co ID PN10k
PN400k
PN3M
@ 10kHz offset
@ 400kHz offset
@ 3MHz offset
-83
-114
-136
dBc/Hz
dBc/Hz
dBc/Hz
sac NF
Frequency error < ± 5
Lock time of Rx burst Tlock_rx 150 200 us
0.1ppm
Frequency error < ± 5
Lock time of Tx burst Tlock_tx 200 300 us
0.1ppm
O
Pushing figure With internal RFVCO LDO 400 kHz/V

u@ C
Table 36. DCXO AC characteristics (TA = 25oC, VDD = 2.8V unless otherwise stated)
Item Symbol Test condition Min. Typ. Max. Unit

.Li K
Operating frequency Fref 26 MHz

Crystal C load CL 7.5 pF
no TE
Crystal tuning sensitivity TS 27.5 32.3 ppm/pF

Static range SR CDAC from 0 to 255 ± 22 ± 50 ppm
Dynamic range DR CAFC from 0 to 8191 36 50 ppm
Ar IA
AFC tuning step Fres-AFC 0.008 ppm/DAC

CAFC from 0 to 8191
5
AFC settling time TAFC CAFC from 8191 to 0 100 200 us
Frequency error < 0.1ppm
R ED
Frequency error < 1ppm 5

Start-up time TDCXO 4 ms
Amplitude > 90 %
Pushing figure 0.2 ppm/V
5
Fref buffer output level VFref Max. loading = 19pF 0.8 Vp-p
FO M
Fref buffer output phase

10kHz offset Jitter noise -135 dBc/Hz
noise
1, 2
: Tested at E-GSM Tx channel 0 and GSM850 Rx channel 190.
3, 4
: Tested at PCS Tx channel 601 and DCS Rx channel 636.
5
: Not subject to production test – verified by characterization and design.


MT2503D
Confidential A
Y
NL
2.8 Bluetooth
US IAL
2.8.1 Block Description
EO
hk T
m. EN
.co ID
sac NF
O
u@ C
.Li K
no TE
Figure 15. System diagram of Bluetooth RF transceiver

Ar IA
The Bluetooth RF subsystem contains a fully integrated transceiver.

R ED
For TX path, the baseband transmit data are digitally modulated in the baseband processor then up-
converted to 2.4GHz RF channels through DA converter, filter, IQ up-converter and power amplifier.
The power amplifier is capable of transmitting 7.5dBm power for class-1 operation.
FO M
For RX path, MT2503D is a low IF receiver architecture. An image-reject mixer down-converts the RF
signal to the IF with LO from the synthesizer, which supports different clock frequencies as the
reference clock. The mixer output is then converted to digital signal and down-converted to baseband
for demodulation. A fast AGC enables effective discovery of device within dynamic range of the
receiver.


MT2503D
Confidential A
Y
NL
MT2503D features self calibration schemes to compensate the process and temperature variation to
US IAL
maintain high performance. Those calibrations are performed automatically right after system boot-up.
EO
2.8.2 Functional Specifications
2.8.2.1 Basic Data Rate – Receiver Specifications
hk T
Table 37. Basic data rate – receiver specifications
m. EN
Frequency range 2,402 - 2,480 MHz
Receiver sensitivity BER < 0.1% - -95 - dBm
.co ID
Max. detectable input power
C/I co-channel selectivity
C/I 1 MHz adj. channel
BER < 0.1%
BER < 0.1%
BER < 0.1%
-
-
-
0
4
-12
-
-
-
dBm
dB
dB
sac NF
selectivity
C/I 2 MHz adj. channel
BER < 0.1% - -42.5 - dB
selectivity
C/I  3 MHz adj. channel
BER < 0.1% - -46 - dB
O
selectivity
C/I image channel selectivity BER < 0.1% - -24 - dB
u@ C
C/I image 1 MHz adj.

BER < 0.1% - -45 - dB
channel selectivity
30 to 2,000 MHz - -4 - dBm
.Li K
2,000 to 2,399 MHz - -18 - dBm

Out-of-band blocking
2,498 to 3,000 MHz - -18 - dBm
no TE
3,000 MHz to 12.75 GHz - 1 - dBm

Intermodulation - -22 - dBm
Ar IA
2.8.2.2 Basic Data Rate – Transmitter Specification

Table 38. Basic data rate – transmitter specification
R ED

Maximum transmit power - 7.5 - dBm
Gain step - 4 - dB
FO M
Δf1avg (00001111) 140 158 175 kHz

Δf2max (10101010) 115 130 - kHz
Δf1avg/Δf2avg 0.8 0.9 - kHz
Initial carrier frequency drift -75 5 75 kHz
DH1 -25 9 25 kHz
Frequency drift
DH3 -40 10 40 kHz


MT2503D
Confidential A
Y
NL
DH5 -40 10 40 kHz
US IAL
Max. drift rate - 100 400 Hz/μs
EO
BW 20dB of Tx output spectrum - 920 1,000 kHz
±2 MHz offset - -38 - dBm
In-band spurious emission ±3 MHz offset - -43 - dBm
hk T
> ±3 MHz offset - -43 - dBm
Out-of-band spurious
30 MHz to 1 GHz - -36 - dBm
m. EN
emission
1 to 12.75 GHz - -30 - dBm
1.8 to 1.9 GHz - -47 - dBm
5.15 to 5.3 GHz - -47 - dBm
2.8.2.3
.co ID
Enhanced Data Rate – Receiver Specifications
sac NF
Table 39. Enhanced data rate – receiver specifications

O

π/4 DQPSK, BER < 0.01% - -95 - dBm
Receiver sensitivity
u@ C
8PSK, BER < 0.01% - -88 - dBm

Max. detectable input π/4 DQPSK, BER < 0.01% - -4.5 - dBm
power 8PSK, BER < 0.01% - -4.5 - dBm
.Li K
π/4 DQPSK, BER < 0.01% - 8 - dB

C/I co-channel selectivity
8PSK, BER < 0.01% - 14.5 - dB
no TE
C/I 1MHz adj. channel π/4 DQPSK, BER < 0.01% - -13 - dB
selectivity 8PSK, BER < 0.01% - -7 - dB
C/I 2MHz adj. channel π/4 DQPSK, BER < 0.01% - -42 - dB
Ar IA
selectivity 8PSK, BER < 0.01% - --41.5 - dB

C/I  3MHz adj. channel π/4 DQPSK, BER < 0.01% - -48 - dB
selectivity 8PSK, BER < 0.01% - -44.5 - dB
R ED
C/I image channel π/4 DQPSK, BER < 0.01% - -30 - dB

selectivity 8PSK, BER < 0.01% - -23 - dB
C/I image 1 MHz adj. π/4 DQPSK, BER < 0.01% - -47.5 - dB
channel selectivity 8PSK, BER < 0.01% - -44.5 - dB
FO M
2.8.2.4 Enhanced Data Rate – Transmitter Specifications

Table 40. Enhanced data rate – transmitter specifications


MT2503D
Confidential A
Y
NL
US IAL
π/4 DQPSK - 4.5 - dBm
Max. transmit power
EO
8PSK - 4.5 - dBm
π/4 DQPSK - -1.7 - dB
Relative transmit power
8PSK - -1.7 - dB
hk T
π/4 DQPSK - 1.5 - kHz
Freq. stability ω0
8PSK - 1.5 - kHz
m. EN
π/4 DQPSK - 3 - kHz
Freq. stability ω1
8PSK - 3 - kHz
π/4 DQPSK - 2.8 - kHz
| ω0+ω1|
.co ID
RMS DEVM
8PSK
π/4 DQPSK
8PSK
-
-
-
2.8
7
6
-
-
-
kHz
%
%
sac NF
π/4 DQPSK - 11 - %
99% DEVM
8PSK - 11 - %
π/4 DQPSK - 18 - %
Peak DEVM
8PSK - 18 - %
O
π/4 DQPSK, ±1 MHz offset - -28 - dBm

8PSK, ±1 MHz offset - -28 - dBm
u@ C
In-band spurious π/4 DQPSK, ±2 MHz offset - -25 - dBm

emission 8PSK, ±2 MHz offset - -25 - dBm
.Li K
π/4 DQPSK, ±3 MHz offset - -40.5 - dBm

8PSK, ±3 MHz offset - -40.5 - dBm
no TE
Note: To meet the specifications, use a front-end band-pass filter.

Ar IA
2.9 FM RF
2.9.1 Block Description

R ED
The connection between internal modules, as well as external interfaces, are as shown in Figure 16.
The FM receiver section incorporates the complete receiving path with wide tuning range. The FM
baseband signal processor incorporates the digital demodulator and audio processing function which
FO M
provides superior audio quality.

FM contains completely integrated FM audio receiver functions (RDS/RBDS may also be supported
depending on the model number). The integrated receiver enables superior sensitivity, ACI
performance and FM audio performances with minimum external BOM.
The FM subsystem supports either high performance stereo analog line out or digital audio output
(I2S).
For models supporting RDS/RBDS, large dedicated internal data buffers are allocated to reduce the
frequency of the interrupt to the host, so that the receiving host can enter low power states efficiently.


MT2503D
Confidential A
Y
NL
US IAL
sysrst_b FM RX FM_RF
fspi_core_rstb
EO
FM_CLKCON FM_MAINCON
fspi_rgf_rstb
hk T
I2S Interface FM FMX FM RX AFE
FM Modem RF MACRO
m. EN
Front End Interface
interrupts
FM RX RF
FM RDS FM SCRG
.co ID
FSPI host Interface
FM HCI
(SPI slave)
FM RGF
RF
Control
FM_RGF
_RF
sac NF
Figure 16. Block diagram of hardware top-level architecture
O
2.9.2 Functional Specifications

Table 41. FM receiver DC characteristics (TA=25°C, VDD=2.8V unless otherwise stated)
u@ C
Operating mode Current consumption Unit

Idle 5 μA
.Li K
FM receiver 12 mA
no TE
Unless otherwise stated, all receiver characteristics are applicable to both long and short antenna
ports when operated under the recommended operating conditions. Typical specifications are for
channel 98.7MHz, default register settings and under recommended operating conditions. The
minimum and maximum specifications are for extreme operating voltage and temperature conditions,
Ar IA
unless otherwise stated.

R ED
Table 42. FM receiver AC characteristics

Input frequency range 65 108 MHz
SINAD = 26dB, unmatched 3 dBVemf
FO M
Sensitivity (long
1,3
antenna) SINAD = 26dB, matched 2 dBVemf
RDS sensitivity (long f=2kHz, BLER < 5%,
18 dBVemf
antenna) unmatched
Sensitivity (short
1,3 SINAD = 26dB, unmatched 3 dBVemf
antenna)
RDS sensitivity (short f = 2kHz, BLER < 5%,
18 dBVemf
antenna) unmatched


MT2503D
Confidential A
Y
NL
4
LNA input resistance Antenna port 2.4k Ohm
US IAL
4
LNA input capacitance Antenna port 8 pF
1,4
AM suppression M = 0.3 58
EO
dB
Adjacent channel
1,4 200kHz 53 dB
selectivity
Alternate channel
400kHz 65 dB
hk T
1,4
selectivity
Spurious response
4 In-band 55 dB
m. EN
rejection
Maximum input level 117 dBVemf
Audio mono
1,3,4 60 dB
(S+N+D)/(N+D)
.co ID
Audio stereo
(S+N+D)/(N+D)
Audio stereo
separation
4
2,3,4
f = 75kHz
52
45
dB
dB
sac NF
Audio output load Single-ended at AFR/AFL
10k Ohm
resistance outputs
Audio output load Single-ended at AFR/AFL
12.5 pF
capacitance outputs
O
1,4
Audio output voltage At AFR/AFL outputs 80 mVrms
1,4
Audio output THD 0.05 0.1 %
u@ C
Audio output frequency

3dB corner frequency 30 15k Hz
range
f = 22.5kHz, fm = 1kHz, 50s de-emphasis, mono, L = R

1
.Li K
f = 22.5kHz, fm = 1kHz, 50us de-emphasis, stereo

2
3
A-weighting, BW = 300 Hz to 15 kHz
no TE
4
Vin = 60dBVemf
5
Reference clock accuracy assumes ideal FM source. If the input FM source has less frequency error, it is
recommended to use a reference clock of accuracy within 100ppm so as not to affect the channel scan
quality.
Ar IA
2.10 Package Information

R ED
2.10.1 Package Outlines

FO M


MT2503D
Confidential A
Y
NL
US IAL
EO
hk T
m. EN
.co ID
sac NF
O
u@ C
.Li K
no TE
Ar IA
R ED
FO M


MT2503D
Confidential A
Y
NL
US IAL
EO
hk T
m. EN
.co ID
sac NF
O
u@ C
.Li K
no TE
Ar IA
R ED
FO M
Figure 17. Outlines and dimension of VFBGA 8.4mm*6.2mm, 215-ball, 0.4 mm pitch package


MT2503D
Confidential A
Y
NL
2.10.2 Thermal Operating Specifications
US IAL
Symbol Description Value Unit Notes
Thermal resistance from device junction to package case 48 C/W
EO
Maximum package temperature 65 Deg C
Maximum power dissipation 1.28 W
hk T
2.10.3 Lead-free Packaging
MT2503D is provided in a lead-free package and meets RoHS requirements
m. EN
2.11 Ordering Information
2.11.1
.co ID
Top Marking Definition
sac NF
MEDIATEK
ARM
O
MTXXXXXX Product No.
MT2503DV
DDDD: Date Code
#####: Subcontractor Code
u@ C
DDDD - #####
LLLLLL: Die Lot No.
LLLLLL
.Li K
no TE
Figure 18. Mass production top marking of MT2503D
Part number Package Description

Ar IA
8.4mm*6.2mm, 215-ball, 0.4 mm pitch package, non-

MT2503DV/B VFBGA
security version
R ED
FO M


MT2503D
Confidential A
Y
NL
3 Micro-Controller Unit Peripherals
US IAL
EO
3.1 Pulse-Width Modulation Outputs (2 Channel)
hk T
2 generic pulse-width modulators are implemented to generate pulse sequences with programmable
frequency and duty cycles for LCD backlight. As long as the internal counter value is bigger than or
m. EN
equal to the threshold value, the duration of the PWM output signal is LOW. The waveform is shown
in Figure 19.
.co ID
Internal counter
Threshold
sac NF
PWM Signal
Figure 19. PWM waveform

O
The frequency and volume of the PWM output signal are determined by PWM1_COUNT,
u@ C
PWM1_THRES and PWM1_CON. The POWERDOWN (pdn1_pwm) signal is applied to power-down

the PWM_1ch module. When PWM_1ch is deactivated (pwm1_pdn=1), the output is in the LOW state.
.Li K
The output PWM frequency is determined by:

CLK
CLK  13000000 when CLKSEL  0, CLK  32000whenCLKSEL  1
no TE
CLOCK _ DIV  ( PWM _ COUNT  1)
CLOCK_DIV = 1, when CLK[1:0] = 00b

Ar IA

R ED
The output PWM duty cycle is determined by: PWM _ THRES

PWM _ COUNT  1
Note: PWM_THRES should be less than the PWM_COUNT. If this condition is not satisfied, the
FO M
output pulse of the PWM will always be HIGH.
Figure 20 shows the PWM waveform with the indicated register values.


MT2503D
Confidential A
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13MHz
US IAL
PWM_COUNT = 5
PWM_THRES = 1
PWM_CON = 0b
EO
Figure 20. PWM waveform with register values
hk T
3.1.2 Register Definition
m. EN
Module name: Pulse Width Modulation base address: (+A00E0000h)
Address Name Width Register function
A00E0000 PWM1_CTRL_ADDR 16 PWM1 control register
A00E0004
A00E0008 .co ID
PWM1_COUNT_ADDR
PWM1_THRESH_ADDR
16
16
PWM1 max counter value register
PWM1 threshold value register
sac NF
A00E0000 PWM1_CTRL_ADDR PWM1 Control Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM1
O
PWM1_CLK_
Name _CLK_
DIV
SEL
Type RW RW
u@ C
Reset 0 0 0
Bit(s) Mnemonic Name Description

.Li K
2 PWM1_CLK CLK_SEL Selects source clock frequency of PWM1

_SEL 0: CLK = 13MHz
1: CLK = 32kHz
no TE
1:0 PWM1_CLK CLK_DIV Selects clock prescaler scale of PWM1

_DIV 2'b00: f = fclk
2'b01: f = fclk/2
2'b10: f = fclk/4
Ar IA
2'b11: f = fclk/8
R ED
A00E0004 PWM1_COUNT_ADDR PWM1 Max. Counter Value Register 1FFF

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PWM1_COUNT
Type RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1
FO M

PWM1 maximum counter value
This value is the initial value of the internal counter. Regardless of
PWM1_COU the operation mode, if PWM1_COUNT is written while the internal
12:0 PWM1_COUNT
NT counter is counting backwards, the new initial value will not take
effect until the internal counter counts down to 0, i.e. a complete
period.


MT2503D
Confidential A
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US IAL
A00E0008 PWM1_THRESH_ADDR PWM1 Threshold Value Register 0000
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PWM1_THRES
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
hk T
m. EN
PWM1 threshold value
PWM1_THR When the internal counter value is bigger than or equal to
12:0 PWM1_THRES PWM1_THRES, the PWM1 output signal will be "0". When the
ES
internal counter is less than PWM1_THRES, the PWM1 output
signal will be "1".
.co ID
Module name: Pulse Width Modulation base address: (+A0280000h)
sac NF
A0280000 PMW4_CTRL_ADDR 16 PMW4 control register
A0280004 PMW4_COUNT_ADDR 16 PMW4 max counter value register
A0280008 PMW4_THRESH_ADDR 16 PMW4 threshold value register
O
u@ C
A0280000 PMW4_CTRL_ADDR PMW4 Control Register 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.Li K
PMW4
PMW4_CLK_
Name _CLK_
DIV
SEL
no TE
Type RW RW
Reset 0 0 0

Ar IA
2 PMW4_CLK CLK_SEL Selects source clock frequency of PMW4

_SEL 0: CLK = 13MHz
1: CLK = 32kHz
1:0 PMW4_CLK CLK_DIV Selects clock prescaler scale of PMW4
R ED
_DIV 2'b00: f = fclk

2'b01: f = fclk/2
2'b10: f = fclk/4
2'b11: f = fclk/8
FO M
A0280004 PMW4_COUNT_ADDR PMW4 Max. Counter Value Register 1FFF

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PMW4_COUNT
Type RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1


MT2503D
Confidential A
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PMW4 maximum counter value
US IAL
This value is the initial value of the internal counter. Regardless of
PMW4_COU the operation mode, if PMW4_COUNT is written while the internal
12:0 PMW4_COUNT
EO
NT counter is counting backwards, the new initial value will not take
effect until the internal counter counts down to 0, i.e. a complete
period.
hk T
A0280008 PMW4_THRESH_ADDR PMW4 Threshold Value Register 0000
m. EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PMW4_THRES
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
.co ID
PMW4 threshold value
When the internal counter value is bigger than or equal to
sac NF
PMW4_THR
12:0 PMW4_THRES PMW4_THRES, the PMW4 output signal will be "0". When the
ES
internal counter is less than PMW4_THRES, the PMW4 output
signal will be "1".
O
Module name: PWM_2CH base address: (+A0740000h)

Address Name Width Register Function
u@ C
PWM2 control register

A074000C PWM2_CTRL 16
Selects CLK SRC and prescaler scale.
PWM2 threshold value register
.Li K
A0740014 PWM2_THRES 16
Controls the duty of waveform
PWM3 control register
no TE
A0740018 PWM3_CTRL 16
Select CLK SRC and prescaler scale.
PWM3 max counter value register
A074001C PWM3_COUNT 16
Configures internal counter's max. value
A0740020 PWM3_THRES 16 PWM3 threshold value register
Ar IA
R ED
A074000C PWM2_CTRL PWM2 Control Register 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM2
Name _CLK_
SEL
FO M
Type RW
Reset 1
Bit(s) Name Description

Selects PWM2 CLK
2 PWM2_CLK_SEL 0: CLK = 13M CLK
1: CLK = 32k CLK


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A0740014 PWM2_THRES PWM2 Threshold Value Register 0000
US IAL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM2_THRE
EO
Name S
Type RW
Reset 0 0
hk T
m. EN
1:0 PWM2_THRES 0: Duty = 0%
1: Duty = 50%
2: Duty = 100%
A0740018
Bit 15
.co ID
PWM3_CTRL
14 13 12
PWM3 Control Register
11 10 9 8 7 6 5 4 3 2 1
0000
0
sac NF
PWM3
PWM3
_ALW PWM3_CLK_
Name _CLK_
AYS_ DIV
SEL
HIGH
Type RW RW RW
Reset 0 0 0 0
O

u@ C
3 PWM3_ALWAYS_HIG When pwm3_thresh is set to be bigger than pwm3_width, which means

H the PWM output is always high, the driver should set this register to 1.
It is specially used by ISINK.
.Li K
0: Duty! = 100%
1: Duty = 100%
2 PWM3_CLK_SEL Selects PWM3 CLK
no TE
0: CLK = 13M CLK

1: CLK = 32k CLK
1:0 PWM3_CLK_DIV PWM3 CLK division
2'b0: f = fclk
Ar IA
2'b1: f = fclk/2
2'b2: f = fclk/4
2'b3: f = fclk/8
R ED
A074001C PWM3_COUNT PWM3 Max Counter Value Register 1FFF

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PWM3_COUNT
FO M
Type RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1

PWM3 maximum counter value
12:0 PWM3_COUNT This value is the initial value of the internal counter. Regardless of the
operation mode, if PWM3_COUNT is written while the internal counter is
counting backwards, the new initial value will not take effect until the internal


MT2503D
Confidential A
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NL
counter counts down to 0, i.e. a complete period.
US IAL
EO
A0740020 PWM3_THRES PWM3 Threshold Value Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PWM3_THRES
hk T
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
m. EN
12:0 PWM3_THRES When the internal counter value is bigger than or equal to PWM3_THRES, the
PWM3 output signal will be 0. When the internal counter is less than
.co ID PWM3_THRES, the PWM3 output signal will be 1.

sac NF
3.2 SIM Interface
MT2503D contains two dedicated smart card interfaces to allow the MCU to access two SIM cards.
Each interface can operate via 5 terminals. See Figure 21, SIMVCC, SIMSEL, SIMRST, SIMCLK and
O
SIMDATA are for one SIM interface, and SIM2VCC, SIM2SEL, SIM2RST, SIM2CLK and SIM2DATA
are for the other SIM interface.
u@ C
13MHz
.Li K
VCC1 SIMVCC
SIMSEL
1st
no TE
RST1 SIMRST 1st

SIM
SIM I/F
CARD CLK1 SIMCLK
DATA1 SIMDATA APB
Bridge
Ar IA
Level
Shift SIM2VCC
SIM2SEL
R ED
VCC2
SIM2RST 2nd
SIM I/F
2nd SIM2CLK SIMIRQ
RST2
SIM SIM2DATA IRQ Ctrl
CARD CLK2 SIM2IRQ
FO M
DATA2
13MHz
Figure 21. Block diagram of SIM interface


MT2503D
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The functions of the two SIM interfaces are identical; therefore, only the first SIM interface will be
described in this document. SIMVCC is used to control the external voltage supply to the SIM card,
US IAL
and SIMSEL determines the regulated smart card supply voltage. SIMRST is used as the SIM card
reset signal. Besides, SIMDATA and SIMCLK are used for data exchange.
EO
The SIM interface is a half duplex asynchronous communication port, and its data format is composed
of ten consecutive bits: a start bit in state “low”, eight information bits and a tenth bit used for parity
hk T
checking. The data format can be divided into two modes as follows:
m. EN
 Direct convention mode (ODD = SDIR = SINV = 0)
SB D0 D1 D2 D3 D4 D5 D6 D7 PB
SB: Start bit (in state “low”)
.co ID
Dx: Data byte (LSB is the first and logic level ONE is in state “high”)
PB: Even parity check bit
sac NF
 Inverse convention mode (ODD = SDIR = SINV = 1)
SB N7 N6 N5 N4 N3 N2 N1 N0 PB
SB: Start bit (in state “low”)
O
Nx: Data byte (MSB is the first and logic level ONE is in state “low”)
PB: Odd parity check bit
u@ C
If the receiver obtains a wrong parity bit, it will respond by pulling the SIMDATA “low” to inform the
.Li K
transmitter, and the transmitter will retransmit the character.
If the receiver is an SIM card, the error response will start 0.5 bit after the PB and may last for 1 ~ 2-
no TE
bit period. If the receiver is an SIM interface, the error response will start 0.5 bit after the PB and last
for 1.5-bit period.
Ar IA
If the SIM interface is a transmitter, it will take total 14 bits guard period wherever the error response
appears. If the receiver shows the error response, the SIM interface will retransmit the previous
character again, or it will transmit the next character.
R ED
FO M


MT2503D
Confidential A
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NL
US IAL
EO
hk T
m. EN
.co ID
sac NF
O
Figure 22. Timing diagram of SIM interface

u@ C

.Li K
When the MCU controls two SIM card interfaces, all registers will be duplicated to two copies but with
st nd
different base address. n = “0” is for the 1 SIM card interface; n=1 is for the 2 SIM card interface.
no TE
For example, address SIMIF0+0000h is mapped to the SIMIF0_SIM_CTRL register while address
SIMIF1+0000h is mapped to the SIMIF1_SIM_CTRL register.
Ar IA
3.2.1.1 Register Overview
MCU register
Acronym Description
address (hex)
R ED
st
1 SIM card interface
SIMIF0+0000h SIMIF0_SIM_CTRL Control register
SIMIF0+0004h SIMIF0_SIM_CONF Configuration register
FO M
SIMIF0+0008h SIMIF0_SIM_BRR Baudrate register

SIMIF0+0010h SIMIF0_SIM_IRQEN Interrupt enabling register
SIMIF0+0014h SIMIF0_SIM_STS Status register
SIMIF0+0018h SIMIF0_SIM_CLR_STA SIM clear status
SIMIF0+0020h SIMIF0_SIM_RETRY Retry limit register
SIMIF0+0024h SIMIF0_SIM_TIDE FIFO tide mark register
SIMIF0+0030h SIMIF0_SIM_DATA TX/RX data register


MT2503D
Confidential A
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MCU register
Acronym Description
address (hex)
US IAL
SIMIF0+0034h SIMIF0_SIM_COUNT FIFO count register
SIMIF0+0040h SIMIF0_SIM_ATIME Activation time register
EO
SIMIF0+0044h SIMIF0_SIM_DTIME Deactivation time register
SIMIF0+0048h SIMIF0_SIM_TOUT Character to character waiting time register
SIMIF0+004Ch SIMIF0_SIM_GTIME Block to block guard time register
hk T
SIMIF0+0050h SIMIF0_SIM_ETIME Block to error signal time register
SIMIF0+0054h SIMIF0_SIM_EXT_TIME Extend data I/O state switch time register
m. EN
SIMIF0+0058h SIMIF0_SIM_CGTIME Character to character guard time register
SIMIF0+0060h SIMIF0_SIM_INS Command header register : INS
SIMIF0+0064h SIMIF0_SIM_IMP3 Command header register : P3
.co ID
SIMIF0+0068h
SIMIF0+006Ch
SIMIF0+0070h
SIMIF0+0074h
SIMIF0_SIM_SW1
SIMIF0_SIM_SW2
SIMIF0_SIM_ATRSTA
SIMIF0_SIM_STATUS
Procedure byte register : SW1
Procedure byte register : SW2
ATR state register
Protocol state register
sac NF
SIMIF0+0080h SIMIF0_SIM_DMADATA TX/RX data register for DMA
SIMIF0+0090h SIMIF0_SIM_DBG Debug register
SIMIF0+0094h SIMIF0_SIM_DBGDATA FIFO data debug register
O
SIMIF0+00A0h SIMIF0_SIM_SCLK SCLK PAD control register

SIMIF0+00A4h SIMIF0_SIM_SRST SRST PAD control register
u@ C
SIMIF0+00A8h SIMIF0_SIM_SIO SIO PAD control register

SIMIF0+00ACh SIMIF0_SIM_MON PAD monitor register
SIMIF0+00B0h SIMIF0_SIM_SEL Testing output select
.Li K
nd
2 SIM card interface
SIMIF1+0000h SIMIF1_SIM_CTRL Control register
no TE
SIMIF1+0004h SIMIF1_SIM_CONF Configuration register

SIMIF1+0008h SIMIF1_SIM_BRR Baudrate register
SIMIF1+0010h SIMIF1_SIM_IRQEN Interrupt enabling register
SIMIF1+0014h SIMIF1_SIM_STS Status register
Ar IA
SIMIF1+0018h SIMIF1_SIM_CLR_STA Sim clear status

SIMIF1+0020h SIMIF1_SIM_RETRY Retry limit register
SIMIF1+0024h SIMIF1_SIM_TIDE FIFO tide mark register
R ED
SIMIF1+0030h SIMIF1_SIM_DATA TX/RX data register

SIMIF1+0034h SIMIF1_SIM_COUNT FIFO count register
SIMIF1+0040h SIMIF1_SIM_ATIME Activation time register
SIMIF1+0044h SIMIF1_SIM_DTIME Deactivation time register
FO M
SIMIF1+0048h SIMIF1_SIM_TOUT Character to character waiting time register

SIMIF1+004Ch SIMIF1_SIM_GTIME Block to block guard time register
SIMIF1+0050h SIMIF1_SIM_ETIME Block to error signal time register
SIMIF1+0054h SIMIF1_SIM_EXT_TIME Extend data I/O state switch time register
SIMIF1+0058h SIMIF1_SIM_CGTIME Character to character guard time register
SIMIF1+0060h SIMIF1_SIM_INS Command header register : INS


MT2503D
Confidential A
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MCU register
Acronym Description
address (hex)
US IAL
SIMIF1+0064h SIMIF1_SIM_IMP3 Command header register : P3
SIMIF1+0068h SIMIF1_SIM_SW1 Procedure byte register : SW1
EO
SIMIF1+006Ch SIMIF1_SIM_SW2 Procedure byte register : SW2
SIMIF1+0070h SIMIF1_SIM_ATRSTA ATR state register
SIMIF1+0074h SIMIF1_SIM_STATUS Protocol state register
hk T
SIMIF1+0080h SIMIF1_SIM_DMADATA TX/RX data register for DMA
SIMIF1+0090h SIMIF1_SIM_DBGD Debug register
m. EN
SIMIF1+0094h SIMIF1_SIM_DBGDATA FIFO data debug register
SIMIF1+00A0h SIMIF1_SIM_SCLK SCLK PAD control register
SIMIF1+00A4h SIMIF1_SIM_SRST SRST PAD control register
.co ID
SIMIF1+00A8h
SIMIF1+00ACh
SIMIF1+00B0h
SIMIF1_SIM_SIO
SIMIF1_SIM_MON
SIMIF1_SIM_SEL
SIO PAD control register
PAD monitor register
Testing output select
sac NF
3.2.1.2 Register Description
O
SIMn+0000h SIM Module Control Register SIMIFN_SIM_CTRL

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
u@ C
VCCC VCCL RSTC RSTL CSTO SIMO

Name WRST
TRL V TRL V P N
Type R/W R/W R/W R/W W R/W R/W
Reset 0 0 0 0 0 0 0
.Li K
SIMON Conrols SIM card power-up/power-down

0 1-to-0 change will start the card deactivation sequence.
no TE
1 0-to-1 change will start the card activation sequence.

CSTOP Enables clock stop mode. Together with CPOL in the SIM_CONF register, it determines
the polarity of SIMCLK in this mode.
Ar IA
0 Enable SIMCLK output

1 Disable SIMCLK outpu
WRST Controls SIM card warm reset
RSTLV Controls SIMRST parking level in SIMRST direct control mode
R ED
RSTCTRL Enables SIMRST direct control mode

VCCLV Controls SIMVCC parking level in SIMVCC direct control mode
VCCCTRL Enables SIMVCC direct control mode
FO M
SIMn+0004h SIM Module Configuration Register SIMIFN_SIM_CONF

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T1TX2 TXRDI RXRDI SIMSE TXAC RXAC
Name HFEN T0EN T1EN TOUT ODD SDIR SINV CPOL
RXEN S S L K K
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0


MT2503D
Confidential A
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NL
RXACK Handshaking control of SIM card reception error
US IAL
0 Disable character receipt handshaking
1 Enable character receipt handshaking
EO
TXACK Handshaking control of SIM card transmission error
0 Disable character transmission handshaking
1 Enable character transmission handshaking
hk T
CPOL SIMCLK polarity control in clock stop mode
0 Make SIMCLK stop in “low” level
m. EN
1 Make SIMCLK stop in “high” level
SINV Data inversion mode
0 Does not invert the transmitted and received data; data logic ONE is in “high” state
1 Invert the transmitted and received data; data logic ONE is in “low” state
SDIR
.co ID
Direction of data transfer
0 LSB is transmitted and received first.
1 MSB is transmitted and received first.
sac NF
ODD Selecting odd or even parity
0 Even parity
1 Odd parity
SIMSEL Selects SIM card supply voltage (also configure SIMSEL in PMU register)
O
0 SIMSEL pin is set to “low” level, 1.8V

1 SIMSEL pin is set to “high” level, 3V
u@ C
TOUT Controls SIM work waiting time counter

0 Disable time-out counter
1 Enable time-out counter
.Li K
T1EN Controls T = 1 protocol controller

0 Disable T = 1 protocol controller
no TE
1 Enable T = 1 protocol controller

T0EN Controls T = 0 protocol controller
0 Disable T = 0 protocol controller
1 Enable T = 0 protocol controller
Ar IA
HFEN Controls hardware flow

0 Disable hardware flow control
1 Enable hardware flow control
R ED
RXRDIS Disables RX DMA request

0 Enable RX DMA request (default)
RXRDIS must be set to 0 for protocol T = 1
1 Disable RX DMA request
FO M
During TX transmission and not protocol T = 1, the recommended setting of RXRDIS

is 1
TXRDIS Disables TX DMA request disable
0 Enable TX DMA request (default)
TXRDIS must be set to 0 for protocol T = 1
1 Disable TX DMA request


MT2503D
Confidential A
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NL
During RX transmission and not protocol T = 1, the recommended setting of TXRDIS
is 1.
US IAL
T1TX2RXEN Enables DMA type auto switch for protocol T = 1 (this function is not supported in
MT6260)
EO
0 Disable DMA type auto switch function
If the current block is TX transmission and the next block is also TX
transmission, disabling this bit is recommended
hk T
1 Enable DMA type auto switch function
If the current block is TX transmission and the next block is RX transmission,
m. EN
enabling this bit is recommended to improve transmission quality
SIMn +0008h
bit
Name
Type
15 .co ID
14
SIM Baudrate Register
13 12 11 10 9 8 7 6
ETU[8:0]
R/W
5 4 3
SIMIFN_SIM_BRR
2 1
SIMCLK[1:0]
R/W
0
sac NF
Reset 372d 01
SIMCLK Sets up SIMCLK frequency

00 Reserved
O
01 13/4 MHz
10 13/8 MHz
u@ C
11 13/12 MHz
ETU Determines duration of elementary time unit in SIMCLK unit
The minimum valid setting of ETU is 8
.Li K
no TE
SIMn +0010h SIM Interrupt Enable Register SIMIFN_SIM_IRQEN

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRU EDCE T1EN RXER T0EN SIMO ATRER TXER TOU OVRU RXTID TXTID
Name
N RR D R D FF R R T N E E
Ar IA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0
For all the bits

R ED
0 Disable interrupt
1 Enable interrupt
FO M
SIMn +0014h SIM Module Status Register SIMIFN_SIM_STS

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRU EDCE T1EN RXER T0EN SIMO ATRER TXER TOU OVRU RXTID TXTID
Name
N RR D R D FF R R T N E E
Type R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R R
Reset - - - - - - - - - - - - -


MT2503D
Confidential A
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NL
TXTIDE The interrupt occurs when the number of transmitted data in the FIFO is less than the
transmitted tide.
US IAL
RXTIDE The interrupt occurs when the number of received data in the FIFO is less than the
received tide.
EO
OVRUN Receiving FIFO overflow interrupt occurrs.
TOUT Between characters time-out interrupt occurs.
TXERR Character transmission error interrupt occurs.
hk T
ATRERR ATR start time-out interrupt occurrs.
SIMOFF Card deactivation completed interrupt occurs.
m. EN
T0END Data transfer handled by T = 0 controller completed interrupt occurs.
RXERR Character reception error interrupt occurrs.
T1END Data transfer handled by T = 1 controller completed interrupt occurs.
EDCERR T = 1 controller CRC error occurs.
UDRUN
.co ID
FIFO underflow interrupt occurs (still reading FIFO when FIFO is empty).
sac NF
SIMIFN_SIM_CLR_ST
SIMn +0018h SIM Clear Status Register
A
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
O
CLR_
Name
STA
Type RO
u@ C
Reset 0
CLA_STA 1: Clear SIMIF. Do not write to SIMIF; 0: SIMIF clear finished or not in clear status, you
.Li K
can write data to SIMIF.

no TE
SIMn +0020h SIM Retry Limit Register SIMIFN_SIM_RETRY

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ar IA
Name TXRETRY[2:0] RXRETRY[2:0]

Type R/W R/W
Reset 3h 3h
RXRETRY Specifies maximum number of receive retries allowed when parity error occurrs.
R ED
TXRETRY Specifies maximum number of transmit retries allowed when parity error occurrs.
FO M
SIMn +0024h SIM FIFO Tide Mark Register SIMIFN_SIM_TIDE

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TXTIDE[3:0] RXTIDE[3:0]
Type R/W R/W
Reset 0h 0h
RXTIDE Trigger point of RXTIDE interrupt

TXTIDE Trigger point of TXTIDE interrupt


MT2503D
Confidential A
Y
NL
US IAL
SIMn +0030h Data Register Used As Tx/Rx Data Register SIMIFN_SIM_DATA
EO
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DATA[7:0]
Type R/W
Reset -
hk T
DATA Eight data digits, corresponding to the character being read or written
m. EN
SIMn +0034h SIM FIFO Count Register SIMIFN_SIM_COUNT
bit
Name
Type
Reset
15
.co ID
14 13 12 11 10 9 8 7 6 5 4 3 2
COUNT[4:0]
R/W
0h
1 0
sac NF
COUNT Number of characters in the SIM FIFO when read and flushes when written.
O
SIMn +0040h SIM Activation Time Register SIMIFN_SIM_ATIME

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
u@ C
Name ATIME[9:0]
Type R/W
Reset 2BEh
.Li K
ATIME Defines the duration, in 64 SIM clock cycles, of the time taken for each of the three
stages of the card activation process, from SIMON transiting to “high” to turning on VCC,
no TE
from turning on VCC to pull data “high” and then from pulling data “high” to turning on
CLK.
Ar IA
SIMn +0044h SIM Deactivation Time Register SIMIFN_SIM_DTIME

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ED
Name DTIME[5:0]
Type R/W
Reset Fh
DTIME Defines the duration, in 64 13 MHz clock cycles, of the time taken for each of the three
FO M
stages of the card deactivation sequence, from pulling RST “low” to turning off CLK, from
turning off CLK to pulling data “low”, from pulling data “low” to turning off VCC.
SIMn +0048h Character to Character Waiting Time Register SIMIFN_SIM_TOUT

bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name WTIME[21:0]


MT2503D
Confidential A
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NL
Type R/W
Reset 260h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US IAL
Name WTIME[21:0]
Type R/W
EO
Reset 260h
WTIME Maximum interval between the leading edge of two consecutive characters in 16 ETU
units
hk T
m. EN
SIMn +004Ch Block to Block Guard Time Register SIMIFN_SIM_GTIME
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GTIME[3:0]
Type
Reset
GTIME
.co ID
Minimum interval between the leading edge of two consecutive characters sent in
R/W
10d
sac NF
opposite directions in ETU unit
O
SIMn +0050h Block to Error Signal Time Register SIMN_SIM_ETIME

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
u@ C
Name ETIME[5:0]
Type R/W
Reset 15d
.Li K
ETIME Defines the interval, in 1/16 ETU unit, between the end of the transmitted parity bit and
the time to check the parity error signal sent from SIM card.
no TE
SIMIFN_SIM_EXT_TIM
SIMn +0054h Active High Period Control Register
Ar IA
E
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name EXT_TIME[3:0]
Type R/W
R ED
Reset 1d
EXT_TIME Defines the interval, in 1/16 ETU unit, between the end of the transmitted parity bit and
the time to switch SIO to input mode. This value should be smaller than ETIME.
FO M
SIMn +0058h Character to Character Guard Time Register SIMIFN_SIM_CGTIME

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CGTIME[7:0]
Type R/W
Reset 2h


MT2503D
Confidential A
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CGTIME Defines the minimum interval between the leading edges of two consecutive characters
in ETU unit.
US IAL
In the same transmission direction, the minimum interval is (12 + CGTIME) ETU. In
opposite transmission direction, the minimum interval is (12 + CGTIME + GTIME) ETU.
EO
hk T
SIMn +0060h SIM Command Header Register: INS SIMIFN_SIM_INS
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. EN
Name INSD SIMINS[7:0]
Type R/W R/W
Reset 0h 0h
SIMINS This field should be identical to the INS instruction code. When writing to this register, the
INSD .co ID
T = 0 controller will be activated and data transfer initiated.
Instruction direction
0 T = 0 controller receives data from the SIM card.
sac NF
1 T = 0 controller sends data to the SIM card.
SIMIFN_SIM_IMP3
O
SIMn +0064h SIM Command Header Register: P3

(ICC_LEN)
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
u@ C
SIMP3
Name SIMP3[7:0]
[8]
Type R R/W
Reset 0h 0h
.Li K
SIMP3 This field should be identical to the P3 instruction code. It should be written prior to the
no TE
SIM_INS register. When the data transfer is being conducted, this field will show the
number of the remaining data to be sent or to be received.
Ar IA
SIMIFN_SIM_SW1
SIMn +0068h SIM Procedure Byte Register: SW1
(ICC_LEN)
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ED
Name SIMSW1[7:0]
Type R
Reset 0h
SIMSW1 This field holds the last received procedure byte for debugging. When the T0END
FO M
interrupt occurrs, it will keep the SW1 procedure byte.
SIMIFN_SIM_SW2
SIMn +006Ch SIM Procedure Byte Register: SW2
(ICC_EDC)
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SIMSW2[7:0]


MT2503D
Confidential A
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NL
Type R
Reset 0h
US IAL
SIMSW2 This field holds the SW2 procedure byte
EO
SIMIFN_SIM_ATRST
SIMn +0070h SIM ATR State Register
hk T
A
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name AL IR OFF
m. EN
Type R R R
Reset 0h 0h 1h
The SIM card is initially turned off. After configuring SIMON of SIMn_SIM_CTRL and ATR procedure,
SIMn_SIM_ATRSTA will set IR or AL to 1 to indicate the card’s feature.
OFF
IR
.co ID
Indicates On/Off of the SIM card
SIM card is IR (internal reset) card
sac NF
AL SIM card is AL (active low reset) card
O
SIMn +0074h SIM Protocol State Register SIMIFN_SIM_STATUS

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
u@ C
Name ALL ONE IDLE

Type R R R
Reset 0h 0h 1h
.Li K
T0 or T1 protocol of the SIM card is initially turned off. When T0 or T1 protocol is turned on,
SIMn_SIM_T0STA will transit between ONE or ALL according to the procedure byte of the SIM card.
no TE
IDLE SIM card’s T0 or T1 protocol is active or idle.

ONE SIM card will send the next byte
ALL SIM card will send all the remaining bytes.
Ar IA
R ED
SIMn +0080h Data Register Used As Tx/Rx Data Register SIMIFN_SIM_DMADATA

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DATA[7:0]
Type R/W
FO M
Reset -
DATA Eight data digits, corresponding to the character being read or written
SIMn +0090h SIM Module Debug Register SIMIFN_SIM_DBG

bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


MT2503D
Confidential A
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Name DBG7 DBG6 DBG5 DBG4 DBG3[4:0]
Type R R R R R
Reset 0h 0h 0h 0h 0h
US IAL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DBG2[4:0] DBG1[4:0]
EO
Type R R
Reset 0h 0h
DBG1 Debugging register 1
hk T
m. EN
.co ID
sac NF
SIMn +0094h SIM FIFO Data Debug Register SIMIFN_SIM_DBGDATA
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DBGRPTR[3:0] DBGDATA[7:0]
Type R R
O
Reset 0h -
DBGDATA FIFO data debugging register

u@ C
There is no impact on data transmission when this register is read.

DBGRPTR FIFO read pointer related to DBGDATA
Automatically increases by 1 after this register is read.
.Li K
no TE
SIMn +00A0h SIM SCLK PAD Control Register SIMIFN_SIM_SCLK

bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACD_
DEBU
Ar IA
Name FUN
G
C
Type R/W R/W
Reset 0h 0h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ED
IES_ IES_L
Name TDSEL[1:0] RDSEL[1:0] R1 R0 PUPD SMT E4 E2 SR[1:0]
CTRL V
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0h 0h 0h 0h 0h 0h 0h 1h 0h 1h 3h
FO M
SR Output slew rate control

High asserted. SR = 1, slower slew. SR = 0, no slew rate control.
For SIM card mode, SR[1:0] = [1 1] is the recommended setting to eliminate
overshooting/undershooting. For non-SIM card mode, SR[1:0] = [0 0] is set for best speed.
E2 TX driving strength control
For SIM card mode, E2 = [1] is the recommended setting for SCLK/SRST/SIO. (SIO/SRST
can use [0])


MT2503D
Confidential A
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For SIM card mode, E4 = [0] is the recommended setting for SCLK/SRST/SIO.
US IAL
SMT RX input buffer schmit trigger hysteresis control enable
High asserted. SMT = 1, schmit trigger enable.
EO
For SIM card mode, SMT = [1] is the recommended setting.
PUPD Weak pull-up/pull-down control
0 Pull-up
hk T
1 Pull-down
R0 Weak pull-up/pull-down resistance select
m. EN
Check the table in register “R1”.
Check the following table.
.co ID E
0
0
PUPD
0
0
R1
0
0
R0
0
1
R Value
High – Z
PU – 20k
sac NF
0 0 1 0 PU – 5k
0 0 1 1 PU – 4k
0 1 0 0 High – Z
O
0 1 0 1 PD – 75k
0 1 1 0 PD – 75k
PD – 37.5k
u@ C
0 1 1 1
1 x x x High - Z
.Li K
RDSEL Selects RX duty

RDSEL[0]: Input buffer duty high when asserted. (high pulse width adjustment)
no TE
RDSEL[1]: Input buffer duty low when asserted. (low pulse width adjustment)
For SIM card mode, RDSEL = [0 0] is the recommended setting.
TDSEL Selects TX duty
TDSEL[0]: Output level shifter duty high when asserted. (high pulse width adjustment)
Ar IA
TDSEL[1]: Output level shifter duty low when asserted. (low pulse width adjustment)
For SIM card mode, TDSEL = [0 0] is the recommended setting.
IES_LV Controls IES (RX input buffer enable) parking level in IES direct control mode
R ED
High asserted. Datapath: From IO to O. IES = 0, O = 0.

In quiescent mode, IES = 0 is suggested for power saving.
IES_CTRL Enables IES direct control mode
ACD_FUNC ACD function mode for analog designer
FO M
DEBUG Output PAD related signals for monitoring

0 Disable
1 Enable


MT2503D
Confidential A
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SIMn +00A4h SIM SRST PAD Control Register SIMIFN_SIM_SRST
US IAL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IES_ IES_L
EO
CTRL V
SR Output slew rate control
hk T
m. EN
can use [0])
E4
.co ID
TX driving strength control
sac NF
O
0 Pull-up
1 Pull-down
u@ C

.Li K

no TE
E PUPD R1 R0 R Value
0 0 0 0 High – Z
0 0 0 1 PU – 20k
0 0 1 0 PU – 5k
Ar IA
0 0 1 1 PU – 4k
0 1 0 0 High – Z
0 1 0 1 PD – 75k
R ED
0 1 1 0 PD – 75k
0 1 1 1 PD – 37.5k
1 x x x High - Z
FO M



MT2503D
Confidential A
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IES_LV Controls IES (RX input buffer enable) parking level in IES direct control mode
US IAL
EO
IES_CTRL Enables IES direct control mode
hk T
SIMn +00A8h SIM SIO PAD Control Register SIMIFN_SIM_SIO
m. EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IES_ IES_L
CTRL V
SR
.co ID
Output slew rate control
sac NF
O
can use [0])

u@ C
.Li K

no TE
0 Pull-up
1 Pull-down
Ar IA

For SIO, [R1 R0] = [1 0] is the recommended setting for 5k weak pull-up. In 4 SIM application
R ED
and SIO is connected to external SIM switch, please disable pull-up resistance. ([R1 R0] = [0
0])
FO M
0 0 0 0 High – Z
0 0 0 1 PU – 20k
0 0 1 0 PU – 5k
0 0 1 1 PU – 4k
0 1 0 0 High – Z
0 1 0 1 PD – 75k
0 1 1 0 PD – 75k


MT2503D
Confidential A
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0 1 1 1 PD – 37.5k
US IAL
1 x x x High - Z
EO
hk T
m. EN
IES_LV Controlling IES (RX input buffer enable) parking level in IES direct control mode
IES_CTRL
.co ID
Enables IES direct control mode
sac NF
SIMn +00ACh SIM Monitor Register SIMIFN_SIM_MON

O
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MON1 MON1 MON1
Name MON9 MON8 MON7 MON6 MON5 MON4 MON3 MON2 MON1
u@ C
2 1 0
Type R R R R R R R R R R R R
Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h
.Li K
MON1 Monitor signal 1

no TE

Ar IA

R ED

FO M
SIMn+00B0h SIM Test Select SIMIFN_SIM_SEL

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SIMSEL
Type R/W
Reset 3’b001


MT2503D
Confidential A
Y
NL
SIMSEL Selects monitor SIMRST, SIMCLK, SIMIO input signal
001 SIMRST input is monitored.
US IAL
010 SIMCLK input is monitored.
100 SIMSIO input is monitored.
EO
Others No meaning
hk T
3.2.2 SIM Card Insertion and Removal
m. EN
The detection of physical connection to the SIM card and card removal can be done by the external
interrupt controller or by GPIO.
3.2.3 .co ID
Card activation and Deactivation
The card activation and deactivation sequence are both controlled by H/W. The MCU initiates the
sac NF
activation sequence by writing “1” to bit 0 of the SIM_CTRL register, and then the interface performs
the following activation sequence:
 Assert SIMRST ”low”
 Set SIMVCC at “high” level and SIMDATA in the reception mode
O
 Enable SIMCLK clock

 De-assert SIMRST “high” (required if it belongs to active low reset SIM card)
u@ C
The final step in a typical card session is contacting deactivation in case the card will be electrically
.Li K
damaged. The deactivation sequence is initiated by writing “0” to bit 0 of the SIM_CTRL register, and
the interface will perform the following deactivation sequence:
no TE
 Assert SIMRST ”low”

 Set SCIMCLK at “low” level
 Set SIMDATA at “low” level
 Set SIMVCC at “low” level
Ar IA
3.2.4 Answering to Reset Sequence

R ED
After the card is activated, a reset operation will result in an answer from the card consisting of the
initial character TS, followed by maximum 32 characters. The initial character TS provides a bit
synchronization sequence and defines the conventions to interpret data bytes in all subsequent
FO M
characters.
On reception of the first character, TS, the MCU should read this character, establish the respective
required convention and re-program the related registers. These processes should be completed prior
to the completion of reception of the next character. Next, the remainder of the ATR sequence will be
received, read via the SIM_DATA in the selected convention and interpreted by the S/W.


MT2503D
Confidential A
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NL
The timing requirement and procedures for ATR sequence are handled by H/W and shall meet the
requirement of ISO 7816-3, as shown in Figure 23.
US IAL
EO
hk T
m. EN
.co ID Figure 23. Answering to reset sequence
sac NF
Table 43. Time-out condition for answering to reset sequence
Time Value Comment

T1 > 400 SIMCLK SIMCLK start to ATR appears
O
T2 < 200 SIMCLK SIMCLK start to SIMDATA in reception mode

T3 > 40,000 SIMCLK SIMCLK start to SIMRST ”high”
u@ C
T4 - SIMVCC “high” to SIMCLK start

T5 - SIMRST “low” to SIMCLK stop
T6 - SIMCLK stop to SIMDATA ”low”
.Li K
T7 - SIMDATA “low” to SIMVCC ”low”

no TE
3.2.5 SIM Data Transfer

There are two transfer modes provided, in software controlled byte by byte fashion or in a block
Ar IA
fashion using T=0 controller and DMA controller. In both modes, the time-out counter can be enabled
to monitor the elapsed time between two consecutive bytes.
R ED
3.2.5.1 Byte Transfer Mode

This mode is used during ATR and PPS procedure. In this mode, the SIM interface only ensures error
free character transmission and reception.
FO M
Receiving characters
Upon detection of the start-bit sent by SIM card, the interface transforms into reception mode and the
following bits are shifted into an internal register. If no parity error is detected or the character-
received handshaking is disabled, the received-character will be written into the SIM FIFO and the
SIM_COUNT register increased by one. Otherwise, the SIMDATA line will be held “low” at 0.5 etu after
detecting the parity error for 1.5 etus, and the character will be re-received. If a character fails to be


MT2503D
Confidential A
Y
NL
received correctly for the RXRETRY times, the receive-handshaking will be aborted, the last-received
character written into the SIM FIFO, the SIM_COUNT increased by one and the RXERR interrupt
US IAL
generated.
EO
When the number of characters held in the received FIFO exceeds the level defined in the SIM_TIDE
register, a RXTIDE interrupt will be generated. The number of characters held in the SIM FIFO can be
hk T
determined by reading the SIM_COUNT register, and writing to this register will flush the SIM FIFO.
m. EN
Sending characters
Characters that are to be sent to the card are first written into the SIM FIFO and then automatically
transmitted to the card at timed intervals. If character-transmitted handshaking is enabled, the
SIMDATA line will be sampled at 1 etu after the parity bit. If the card indicates that it does not receive
.co ID
the character correctly, the character will be re-transmitted for maximum of TXRETRY times before a
TXERR interrupt is generated and the transmission is aborted. Otherwise, the succeeding byte in the
SIM FIFO will be transmitted.
sac NF
If a character fails to be transmitted and a TXERR interrupt is generated, the interface will need to be
reset by flushing the SIM FIFO before any subsequent transmission or reception operation.
O
When the number of characters held in the SIM FIFO falls below the level defined in the SIM_TIDE
register, a TXTIDE interrupt will be generated. The number of characters held in the SIM FIFO can be
u@ C
determined by reading the SIM_COUNT register, and writing to this register will flush the SIM FIFO.
.Li K
3.2.5.2 Block Transfer Mode

no TE
Basically the SIM interface is designed to work in conjunction with the T=0 protocol controller and the
DMA controller during non-ATR and non-PPS phase, though it is still possible for software to service
the data transfer manually as in the byte transfer mode if necessary. Thus the T=0 protocol should be
controlled by software.
Ar IA
The T=0 controller can be accessed via four registers representing the instruction header bytes INS
and P3, and the procedure bytes SW1 and SW2. The registers are:
R ED
 SIM_INS, SIM_P3
 SIM_SW1, SIM_SW2
FO M
During the character transfer, SIM_P3 holds the number of characters to be sent or to be received,
and SIM_SW1 holds the last received procedure byte including NULL, ACK, NACK and SW1 for
debugging.
Data receiving instruction

Data receiving instructions receive data from the SIM card. See the following instantiated procedure.


MT2503D
Confidential A
Y
NL
1. Enable the T=0 protocol controller by setting the T0EN bit to 1 in the SIM_CONF register.
2. Program the SIM_TIDE register to 0x0000 (TXTIDE = 0, RXTIDE = 0).
US IAL
3. Program the SIM_IRQEN to 0x019C (enable RXERR, TXERR, T0END, TOUT and OVRUN
interrupts).
EO
4. Write CLA, INS, P1, P2 and P3 into SIM FIFO.
5. Program the DMA controller:
- DMAn_MSBSRC and DMAn_LSBSRC: Address of the SIM_DATA register
hk T
- DMAn_MSBDST and DMAn_LSBDST: Memory address reserved to store the received
characters
m. EN
- DMAn_COUNT: Identical to P3 or 256 (if P3 = 0)
- DMAn_CON: 0x0078
6. Write P3 into the SIM_P3 register and then INS into SIM_INS register. (Data transfer is initiated
now.)
.co ID
7. Enable the time-out counter by setting the TOUT bit to 1 in the SIM_CONF register.
8. Start the DMA controller by writing 0x8000 into the DMAn_START register.
sac NF
Upon completion of the data receiving instruction, T0END interrupt will be generated and the time-out
counter should be disabled by setting the TOUT bit to 0 in the SIM_CONF register.
If error occurs during the data transfer (RXERR, TXERR, OVRUN or TOUT interrupt is generated), the
O
SIM card should be deactivated first and then activate the prior subsequent operations.
u@ C
Data sending instruction

Data sending instructions send data to the SIM card. See the following instantiated procedure.
.Li K
1. Enable the T=0 protocol controller by setting the T0EN bit to 1 in the SIM_CONF register.
2. Program the SIM_TIDE register to 0x0100 (TXTIDE = 1, RXTIDE = 0)
no TE
3. Program the SIM_IRQEN to 0x019C (enable RXERR, TXERR, T0END, TOUT and OVRUN
interrupts)
4. Write CLA, INS, P1, P2 and P3 into SIM FIFO
Ar IA
5. Program the DMA controller:

 DMAn_MSBSRC and DMAn_LSBSRC: Memory address reserved to store the transmitted
characters

R ED
DMAn_MSBDST and DMAn_LSBDST: Address of the SIM_DATA register

 DMAn_COUNT: Identical to P3
 DMAn_CON: 0x0074
6. Write P3 into the SIM_P3 register and then (0x0100 | INS) into SIM_INS register. (Data transfer is
FO M
initiated now.)
7. Enable the time-out counter by setting the TOUT bit to 1 in the SIM_CONF register.
8. Start the DMA controller by writing 0x8000 into the DMAn_START register.
Upon completion of the data sending instruction, T0END interrupt will be generated and the time-out
counter should be disabled by setting the TOUT bit back to 0 in the SIM_CONF register.


MT2503D
Confidential A
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NL
If error occurs during the data transfer (RXERR, TXERR, OVRUN or TOUT interrupt is generated), the
SIM card should be deactivated first and then activate the prior subsequent operations.
US IAL
EO
3.3 Keypad Scanner
hk T
The keypad supports two types of keypads: 5*5 double keypad and 5*5 triple keypad.
m. EN
The 5*5 keypad can be divided into two parts: 1) The keypad interface including 5 columns and 5
rows (see Figure 24 and Figure 25); 2) The key detection block providing key pressed, key released
and de-bounce mechanisms.
.co ID
Each time the key is pressed or released, i.e. something different in the 5*5 matrix, the key detection
block senses the change and recognizes if a key has been pressed or released. Whenever the key
sac NF
status changes and is stable, a KEYPAD IRQ will be issued. The MCU can then read the key(s)
pressed directly in the KP_MEM1, KP_MEM2, KP_MEM3, KP_MEM4 and KP_MEM5 registers. To
ensure the key pressed information is not missed, the status register in keypad is not read-cleared by
the APB read command. The status register can only be changed by the key-pressed detection FSM.
O
This keypad can detect one or two keys pressed simultaneously. Figure 27 shows the one key
u@ C
pressed condition. Figure 28(a) and Figure 28(b) illustrate the two keys pressed cases. Since the key
pressed detection depends on the HIGH or LOW level of the external keypad interface, if the keys are
pressed at the same time and there exists a key that is on the same column and the same row with
.Li K
other keys, the pressed key cannot be correctly decoded. For example, if there are three key pressed:
key1 = (x1, y1), key2 = (x2, y2), and key3 = (x1, y2), then both key3 and key4 = (x2, y1) will be
no TE
detected, and therefore they cannot be distinguished correctly. Hence, the keypad can detect only one
or two keys pressed simultaneously at any combination. More than two keys pressed simultaneously
in a specific pattern will retrieve the wrong information.
Ar IA
The 5*5 double keypad (Figure 24) supports a 5*5*2 = 50 keys matrix. The 50 keys are divided into
25 sub groups and each group consists of 2 keys and a off-chip resistor. 5*5 double keypad has
another limitation, which is it cannot detect two keys pressed simultaneously when the two keys are in
R ED
one group, i.e. the 5*5 keypad cannot detect key0 and key1 pressed simultaneously or key15 and
key16 pressed simultaneously.
The 5*5 triple keypad (Figure 25) supports a 5*5*3 = 75 keys matrix. The 75 keys are divided into 25
FO M
sub groups and each group consists of 3 keys and two off-chip resistors. 5*5 triple keypad has
another limitation, which is it cannot detect three keys pressed simultaneously when the three keys
are in one group, i.e. 5*5 keypad cannot detect key0, key1 and key2 pressed simultaneously or key15,
key16 and key17 pressed simultaneously.


MT2503D
Confidential A
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NL
KCOL0 KCOL1 KCOL2 KCOL3 KCOL4
US IAL
KROW0 0 3 6 9 12
EO
1 4 7 10 13
KROW1
15 18 21 24 27
hk T
16 19 22 25 28
m. EN
KROW2 30 33 36 39 42
31 34 37 40 43
KROW3 48 54
45 51 57
.co ID
KROW4
46 49 52 55 58
sac NF
60 63 66 69 72
61 64 67 70 73
Baseband
O
u@ C
Figure 24. 5x5 double keypad matrix (50 keys)

.Li K
no TE
Ar IA
R ED
FO M


MT2503D
Confidential A
Y
NL
KCOL0 KCOL1 KCOL2 KCOL3 KCOL4
US IAL
KROW0
0 3 6 9 12
EO
1 4 7 10 13
2 5 8 11 14
KROW1
15 18 21 24 27
hk T
16 19 22 25 28
17 20 23 26 29
KROW2
m. EN
30 33 36 39 42
31 34 37 40 43
32 35 38 41 44
KROW3
.co ID
45 48 51 54 57
46 49 52 55 58
47 50 53 56 59
KROW4
sac NF
60 63 66 69 72
61 64 67 70 73
62 65 68 71 74
O
Baseband
u@ C
Figure 25. 5x5 triple keypad matrix (75 keys)

.Li K
no TE
Ar IA
R ED
FO M
Figure 26. 5*5 double keypad scan waveform


MT2503D
Confidential A
Y
NL
US IAL
Key Pressed
De-bounce time De-bounce time
EO
Key-pressed Status
KP_IRQ
hk T
KEY_PRESS_IRQ KEY_RELEASE_IRQ
m. EN
Figure 27. One key pressed with de-bounce mechanism denoted
.co ID
Key1 pressed
Key2 pressed
Status
sac NF
IRQ
Key1 pressed Key2 pressed Key1 released Key2 released
(a)
Key1 pressed
O
Key2 pressed
u@ C
Status
IRQ
Key1 pressed Key2 pressed Key2 released Key1 released

.Li K
(b)
Figure 28. (a) Two keys pressed, case 1; (b) Two keys pressed, case 2
no TE
3.3.2 Register Definitions

Ar IA
Module name: KP Base address: (+A00D0000)

R ED
A00D0000 KP_STA 16 Keypad Status

Keypad Scanning Output Register
A00D0004 KP_MEM1 16 Shows the key-pressed status of key 0 (LSB) ~ key 15.
Refer to Table 1 and Table 2.
FO M
A00D000C KP_MEM3 16 Shows the key-pressed status of key 32 (LSB) ~ key 47.


MT2503D
Confidential A
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US IAL
EO
De-bounce Period Setting
Defines the waiting period before key pressing or release
events are considered stable. If the de-bounce setting is
A00D0018 KP_DEBOUNCE 16 too small, the keypad will be too sensitive and detect too
hk T
many unexpected key presses. The suitable de-bounce
time setting must be adjusted according to the user's
habit.
m. EN
Keypad Scan Timing Adjustment Register
Sets up the keypad scan timing.
Note: ROW_SCAN_DIV > ROW_INTERVAL_DIV and
A00D001C KP_SCAN_TIMING 16 COL_SCAN_DIV > COL_INTERVAL_DIV.
.co ID ROW_INTERVAL_DIV/COL_INTERVAL_DIV are used to

lower the power consumption for it decreases the actual
scan number during the de-bounce time.
Keypad Selection Register
sac NF
A00D0020 KP_SEL 16 Selects:
1: Use the double keypad or triple keypad
2: Which cols and rows are used
Keypad Enable Register
A00D0024 KP_EN 16
Enables/Disables keypad.
O
u@ C
A00D0000 KP_STA Keypad Status 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name STA
Type RO
.Li K
Reset 0
no TE

Indicates the keypad status
The register is not cleared by the read operation.
0 STA STA
0: No key pressed
Ar IA
1: Key pressed
R ED
A00D0004 KP_MEM1 Keypad Scanning Output Register FFFF

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name KEY1
KEY14 KEY13 KEY12 KEY11 KEY10 KEY9 KEY8 KEY7 KEY6 KEY5 KEY4 KEY3 KEY2 KEY1 KEY0
5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
FO M
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Overview: Shows the key-pressed status of key 0 (LSB) ~ key 15. Refer to Table 1 and Table 2.

15 KEY15 KEY15
14 KEY14 KEY14


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13 KEY13 KEY13
US IAL
12 KEY12 KEY12
11 KEY11 KEY11
EO
10 KEY10 KEY10
9 KEY9 KEY9
8 KEY8 KEY8
hk T
7 KEY7 KEY7
6 KEY6 KEY6
m. EN
5 KEY5 KEY5
4 KEY4 KEY4
3 KEY3 KEY3
2 KEY2 KEY2
1
0
KEY1
KEY0
.co ID KEY1
KEY0
sac NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
O
Name KEY3 KEY1

KEY30 KEY29 KEY28 KEY27 KEY26 KEY25 KEY24 KEY23 KEY22 KEY21 KEY20 KEY19 KEY18 KEY17
1 6
Reset
u@ C
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
.Li K

15 KEY31 KEY31
no TE
14 KEY30 KEY30
13 KEY29 KEY29
12 KEY28 KEY28
Ar IA
11 KEY27 KEY27
10 KEY26 KEY26
9 KEY25 KEY25
R ED
8 KEY24 KEY24
7 KEY23 KEY23
6 KEY22 KEY22
5 KEY21 KEY21
FO M
4 KEY20 KEY20
3 KEY19 KEY19
2 KEY18 KEY18
1 KEY17 KEY17
0 KEY16 KEY16


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A00D000C KP_MEM3 Keypad Scanning Output Register FFFF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US IAL
Name KEY4 KEY3
KEY46 KEY45 KEY44 KEY43 KEY42 KEY41 KEY40 KEY39 KEY38 KEY37 KEY36 KEY35 KEY34 KEY33
7 2
EO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
hk T
m. EN
15 KEY47 KEY47
14 KEY46 KEY46
13 KEY45 KEY45
12 KEY44 KEY44
11
10
9
KEY43
KEY42
KEY41
.co ID KEY43
KEY42
KEY41
sac NF
8 KEY40 KEY40
7 KEY39 KEY39
6 KEY38 KEY38
5 KEY37 KEY37
O
4 KEY36 KEY36
3 KEY35 KEY35
u@ C
2 KEY34 KEY34
1 KEY33 KEY33
0 KEY32 KEY32
.Li K
no TE

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name KEY6 KEY62 KEY61 KEY60 KEY59 KEY58 KEY57 KEY56 KEY55 KEY54 KEY53 KEY52 KEY51 KEY50 KEY49 KEY4
3 8
Ar IA
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R ED

15 KEY63 KEY63
14 KEY62 KEY62
FO M
13 KEY61 KEY61
12 KEY60 KEY60
11 KEY59 KEY59
10 KEY58 KEY58
9 KEY57 KEY57
8 KEY56 KEY56
7 KEY55 KEY55


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6 KEY54 KEY54
US IAL
5 KEY53 KEY53
4 KEY52 KEY52
EO
3 KEY51 KEY51
2 KEY50 KEY50
1 KEY49 KEY49
hk T
0 KEY48 KEY48
m. EN
A00D0014 KP_MEM5 Keypad Scanning Output Register 07FF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
.co ID KEY74 KEY73 KEY72 KEY71 KEY70 KEY69 KEY68 KEY67 KEY66 KEY65
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
KEY6
4
RO
1
sac NF
O

10 KEY74 KEY74
u@ C
9 KEY73 KEY73
8 KEY72 KEY72
7 KEY71 KEY71
.Li K
6 KEY70 KEY70
5 KEY69 KEY69
no TE
4 KEY68 KEY68
3 KEY67 KEY67
2 KEY66 KEY66
1 KEY65 KEY65
Ar IA
0 KEY64 KEY64
The five registers list the status of 75 keys on the keypad. For 5*5 keypad, KP_MEM1~4 registers list the status
R ED
of 75 keys on the keypad. When the MCU receives KEYPAD IRQ, both two registers must be read. If any key is
pressed, the relative bit will be set to 0.
FO M
In order to work normally, the corresponding pull-up/down setting must be programmed correctly. If some keys
can be used because their COL or ROW is used as GPIO, these corresponding enabling bit should be set.
KEYS Status list of the 75 keys.
A00D0018 KP_DEBOUNCE De-bounce Period Setting 0400

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


MT2503D
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Name DEBOUNCE
Type RW
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0
US IAL
Overview: Defines the waiting period before key pressing or release events are considered stable. If the de-
EO
bounce setting is too small, the keypad will be too sensitive and detect too many unexpected key presses. The
suitable de-bounce time setting must be adjusted according to the user's habit.
hk T
13:0 DEBOUNCE DEBOUNCE De-bounce time = KP_DEBOUNCE/32ms.
m. EN
KP_SCAN_TIMI
A00D001C Keypad Scan Timing Adjustment Register 0011
NG
Bit
Name
Type
Reset
15
0
.co ID
0
14
COL_INTERVAL_DIV
RW
0 0
13 12 11
0 0
10
ROW_INTERVAL_DIV
RW
0 0
9 8 7
0 0
RW
6
COL_SCAN_DIV
0 1
5 4 3
0
2
ROW_SCAN_DIV
0
RW
0
1
1
0
sac NF
Overview: Sets up the keypad scan timing. Note: ROW_SCAN_DIV > ROW_INTERVAL_DIV and
COL_SCAN_DIV > COL_INTERVAL_DIV. ROW_INTERVAL_DIV/COL_INTERVAL_DIV are used to lower the
power consumption for it decreases the actual scan number during the de-bounce time.
O

15:12 COL_INTER COL_INTERVAL_D Sets up the COL SCAN interval cycle, i.e. cycles between two
u@ C
VAL_DIV IV scans
Default 0 means there is 1 cycle between two high scan pulses.
11:8 ROW_INTERROW_INTERVAL_ Sets up the ROW SCAN interval cycle, i.e. cycles between two
.Li K
VAL_DIV DIV scans

Default 0 means there is 1 cycle between two high scan pulses.
7:4 COL_SCAN COL_SCAN_DIV Sets up the COL SCAN cycle which includes
no TE
_DIV COL_INTERVAL_DIV and the high pulse period

Default 1 means there are 2 cycles for each scan, including 1 cycle
high pulse and 1 cycle interval.
3:0 ROW_SCAN ROW_SCAN_DIV Sets up the ROW SCAN cycle which includes
Ar IA
_DIV ROW_INTERVAL_DIV and the high pulse period

Default 1 means there are 2 cycles for each scan, including 1 cycle
high pulse and 1 cycle interval.
R ED
FO M


MT2503D
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f32k_ck
US IAL
EO
Row0_scan
hk T
Row1_scan
m. EN
row_interval_div
= 4'h0
row_scan_div
= 4'h1
.co ID Figure 29. kp timing register

sac NF
A00D0020 KP_SEL Keypad Selection Register FFC0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KP_S
Name KP1_COL_SEL SAMPLE_DELAY
EL
O
Type RW RW RW
Reset 1 1 1 1 1 0 0 0 0 0 0
u@ C
Overview: Selects 1: Use the double keypad or triple keypad; 2: Which cols and rows are used.

.Li K
15:11 KP1_COL_S KP1_COL_SEL Selects to use which col

EL 0: Disable corresponding column
no TE
1: Enable corresponding column

5:1 SAMPLE_D SAMPLE_DELAY Sets up delay cycles to sample col
ELAY 0: No delay
n: n*31.25ns delay to sample col
Ar IA
0 KP_SEL KP_SEL Selects to use double keypad or triple keypad

0: Use triple keypad
1: Use double keypad
R ED
A00D0024 KP_EN Keypad Enable Register 0001

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KP_E
FO M
Name
N
Type RW
Reset 1
Overview: Enables/Disables keypad.

0 KP_EN KP_EN 0: Disable keypad (Both double and triple keypads will not work.)


MT2503D
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1: Enable keypad (Only either of double or triple keypads can work.)
US IAL
EO
Table 44. 5*5 double KEY’s order number in COL/ROW matrix
COL0 COL1 COL2 COL3 COL4

ROW4 60/61 63/64 66/67 69/70 72/73
hk T
ROW3 45/46 48/49 51/52 54/55 57/58
m. EN
ROW2 30/31 33/34 36/37 39/40 42/43
ROW1 15/16 18/19 21/22 24/25 27/28
ROW0 0/1 3/4 6/7 9/10 12/13
.co ID Table 45. 5*5 triple KEY’s order number in COL/ROW matrix
COL0 COL1 COL2 COL3 COL4

sac NF
ROW4 60/61/62 63/64/65 66/67/68 69/70/71 72/73/74
ROW3 45/46/47 48/49/50 51/52/53 54/55/56 57/58/59
ROW2 30/31/32 33/34/35 36/37/38 39/40/41 42/43/44
ROW1 15/16/17 18/19/20 21/22/23 24/25/26 27/28/29
O
ROW0 0/1/2 3/4/5 6/7/8 9/10/11 12/13/14

u@ C
3.4 General Purpose Inputs/Outputs

.Li K

no TE
MT2503D offers 56 general purpose I/O pins. By setting up the control registers, the MCU software
can control the direction, the output value, and read the input values on these pins. These GPIOs and
GPOs are multiplexed with other functions to reduce the pin count. In addition, all GPO pins are
removed. To facilitate application use, the software can configure which clock to send outside the chip.
Ar IA
There are 6 clock-out ports embedded in 56 GPIO pins, and each clock-out can be programmed to
output appropriate clock source. Besides, when 2 GPIO function for the same peripheral IP, the
smaller GPIO serial numbers have higher priority than larger numbers.
R ED
FO M


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Figure 30. GPIO block diagram
US IAL
3.4.2
EO
Register Definitions
Module name: gpio_reg Base address: (+A0020000h)
hk T
GPIO Direction Control
A0020000 GPIO_DIR0 32
Configures GPIO direction
m. EN
A0020004 GPIO_DIR0_SET 32
For bitwise access of GPIO_DIR0
A0020008 GPIO_DIR0_CLR 32
A0020010
A0020014 .co ID
GPIO_DIR1
GPIO_DIR1_SET
32
32
Configures GPIO direction
sac NF
A0020018 GPIO_DIR1_CLR 32
GPIO Pull-up/down Enable Control
A0020100 GPIO_PULLEN0 32
Configures GPIO pull enabling
GPIO_PULLEN0_ GPIO Pull-up/down Enable Control
O
A0020104 SET 32
For bitwise access of GPIO_PULLEN0
A0020108 CLR 32
u@ C
For bitwise access of GPIO_PULLEN0

A0020110 GPIO_PULLEN1 32
Configures GPIO pull enabling
.Li K
A0020114 GPIO_PULLEN1_ 32
SET For bitwise access of GPIO_PULLEN1
A0020118 32
no TE
CLR For bitwise access of GPIO_PULLEN1

GPIO Data Inversion Control
A0020200 GPIO_DINV0 32
Configures GPIO inversion enabling
GPIO_DINV0_SE GPIO Data Inversion Control
A0020204 T 32
For bitwise access of GPIO_DINV0
Ar IA
GPIO_DINV0_CL GPIO Data Inversion Control

A0020208 R 32
GPIO Data Inversion Control
A0020210 GPIO_DINV1 32
R ED
Configures GPIO inversion enabling

GPIO_DINV1_SE GPIO Data Inversion Control
A0020214 T 32
GPIO_DINV1_CL GPIO Data Inversion Control
A0020218 32
R For bitwise access of GPIO_DINV1
FO M
GPIO Output Data Control

A0020300 GPIO_DOUT0 32
Configures GPIO output value
GPIO_DOUT0_SE GPIO Output Data Control
A0020304 T 32
GPIO_DOUT0_CL GPIO Output Data Control
A0020308 R 32
GPIO Output Data Control
A0020310 GPIO_DOUT1 32
Configures GPIO output value


MT2503D
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GPIO_DOUT1_SE GPIO Output Data Control
A0020314 32
US IAL
T For bitwise access of GPIO_DIR1
GPIO_DOUT1_CL GPIO Output Data Control
A0020318 32
EO
R For bitwise access of GPIO_DIR1
GPIO Input Data Value
A0020400 GPIO_DIN0 32
Reads GPIO input value
GPIO Input Data Value
hk T
A0020410 GPIO_DIN1 32
Reads GPIO input value
GPIO Pullsel Control
A0020500 GPIO_PULLSEL0 32
m. EN
Configures GPIO PUPD selection
GPIO_PULLSEL0 GPIO Pullsel Control
A0020504 _SET 32
For bitwise access of GPIO_PULLSEL0
A0020508 _CLR 32
A0020510
A0020514
.co ID
GPIO_PULLSEL1
GPIO_PULLSEL1
32
32
Configures GPIO PUPD selection
sac NF
_SET For bitwise access of GPIO_PULLSEL1
A0020518 _CLR 32
GPIO SMT Control
A0020600 GPIO_SMT0 32
Configures GPIO Schmit trigger control
O
GPIO SMT Control

A0020604 GPIO_SMT0_SET 32
For bitwise access of GPIO_SMT0
u@ C
GPIO SMT Control

A0020608 GPIO_SMT0_CLR 32
GPIO SMT Control
A0020610 GPIO_SMT1 32
Configures GPIO Schmit trigger control
.Li K
GPIO SMT Control

A0020614 GPIO_SMT1_SET 32
no TE
GPIO SMT Control

A0020618 GPIO_SMT1_CLR 32
GPIO SR Control
A0020700 GPIO_SR0 32
Configures GPIO slew rate control
Ar IA
GPIO SR Control
A0020704 GPIO_SR0_SET 32
For bitwise access of GPIO_SR0
GPIO SR Control
A0020708 GPIO_SR0_CLR 32
R ED
GPIO SR Control
A0020710 GPIO_SR1 32
Configures GPIO slew rate control
GPIO SR Control
A0020714 GPIO_SR1_SET 32
GPIO SR Control
FO M
A0020718 GPIO_SR1_CLR 32
GPIO SIM SR Control
A0020720 GPIO_SIM_SR 32
Configures GPIO slew rate control for SIM IO
GPIO_SIM_SR_S GPIO SIM SR Control
A0020724 ET 32
For bitwise access of GPIO_SIM_SR
GPIO_SIM_SR_C GPIO SIM SR Control
A0020728 LR 32
For bitwise access of GPIO_SIM_SR
A0020800 GPIO_DRV0 32 GPIO DRV Control


MT2503D
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Configures GPIO driving control
US IAL
GPIO DRV Control
A0020804 GPIO_DRV0_SET 32
For bitwise access of GPIO_DRV0
EO
GPIO DRV Control
A0020808 GPIO_DRV0_CLR 32
GPIO DRV Control
A0020810 GPIO_DRV1 32
Configures GPIO driving control
hk T
GPIO DRV Control
A0020814 GPIO_DRV1_SET 32
m. EN
GPIO DRV Control
A0020818 GPIO_DRV1_CLR 32
GPIO IES Control
A0020900 GPIO_IES0 32
Configures GPIO input enabling control
GPIO IES Control
A0020904
A0020908 .co ID
GPIO_IES0_SET
GPIO_IES0_CLR
32
32
For bitwise access of GPIO_IES0
GPIO IES Control
sac NF
GPIO IES Control
A0020910 GPIO_IES1 32
Configures GPIO input enabling control
GPIO IES Control
A0020914 GPIO_IES1_SET 32
GPIO IES Control
O
A0020918 GPIO_IES1_CLR 32
GPIO PUPD Control
A0020A00 GPIO_PUPD0 32
u@ C
Configures GPIO PUPD control

GPIO_PUPD0_SE GPIO PUPD Control
A0020A04 T 32
For bitwise access of GPIO_PUPD0
.Li K
GPIO_PUPD0_CL GPIO PUPD Control

A0020A08 R 32
GPIO PUPD Control
A0020A10 GPIO_PUPD1 32
no TE
Configures GPIO PUPD control

GPIO_PUPD1_SE GPIO PUPD Control
A0020A14 32
T For bitwise access of GPIO_PUPD1
GPIO_PUPD1_CL GPIO PUPD Control
A0020A18 R 32
Ar IA
GPIO R0 Control
A0020B00 GPIO_RESEN0_0 32
Configures GPIO R0 control
GPIO_RESEN0_0 GPIO R0 Control
A0020B04 32
R ED
_SET For bitwise access of GPIO_RESEN0_0

A0020B08 _CLR 32
For bitwise access of GPIO_RESEN0_0
GPIO R0 Control
FO M

A0020B14 32
A0020B18 _CLR 32
GPIO R1 Control
A0020B24 _SET 32


MT2503D
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A0020B28 32
US IAL
_CLR For bitwise access of GPIO_RESEN1_0
GPIO R1 Control
EO
A0020B34 32
hk T
A0020B38 _CLR 32
GPIO Mode Control
A0020C00 GPIO_MODE0 32
m. EN
Configures GPIO aux. mode
GPIO_MODE0_S GPIO Mode Control
A0020C04 ET 32
For bitwise access of GPIO_MODE0
GPIO_MODE0_C GPIO Mode Control
A0020C08 LR 32
A0020C10
A0020C14
.co ID
GPIO_MODE1
GPIO_MODE1_S
32
32
GPIO Mode Control
GPIO Mode Control
sac NF
ET For bitwise access of GPIO_MODE1
A0020C18 LR 32
GPIO Mode Control
O

A0020C24 ET 32
u@ C

A0020C28 LR 32
GPIO Mode Control
.Li K

A0020C34 32
no TE

A0020C38 LR 32
GPIO Mode Control
Ar IA

A0020C44 ET 32
A0020C48 LR 32
R ED
GPIO Mode Control

A0020C54 32
GPIO Mode Control
FO M
GPIO_MODE5_C
A0020C58 LR 32
GPIO Mode Control
A0020C64 ET 32
A0020C68 LR 32
A0020D10 GPIO_TDSEL 32 GPIO TDSEL Control


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GPIO TX duty control register
US IAL
GPIO_TDSEL_SE GPIO TDSEL Control
A0020D14 T 32
For bitwise access of GPIO_TDSEL
EO
GPIO_TDSEL_CL GPIO TDSEL Control
A0020D18 R 32
For bitwise access of GPIO_TDSEL
CLK Out Selection Control
A0020E00 CLK_OUT0 32
CLK OUT0 Setting
hk T
CLK OUT1 Setting
m. EN
CLK OUT2 Setting
CLK OUT3 Setting
A0020E40
A0020E50 .co ID
CLK_OUT4
CLK_OUT5
32
32
CLK OUT4 Setting
CLK OUT5 Setting
sac NF
A0020000 GPIO_DIR0 GPIO Direction Control 040008E0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
O
GPIO3 GPIO3 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO1 GPIO1 GPIO1 GPIO1
Mne 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
u@ C
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1
Mne GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
5 4 3 2 1 0
.Li K
Reset 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0
no TE
Overview: Configures GPIO direction

Ar IA
31 GPIO31 GPIO31_DIR GPIO31 direction control

0: GPIO as input
1: GPIO as output
R ED
0: GPIO as input
1: GPIO as output
0: GPIO as input
1: GPIO as output
FO M

0: GPIO as input
1: GPIO as output
0: GPIO as input
1: GPIO as output
0: GPIO as input


MT2503D
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1: GPIO as output
US IAL
0: GPIO as input
EO
1: GPIO as output
0: GPIO as input
1: GPIO as output
hk T
0: GPIO as input
m. EN
1: GPIO as output
0: GPIO as input
1: GPIO as output
20 GPIO20
.co ID GPIO20_DIR
0:
1: GPIO as output
GPIO
GPIO20 direction control

as input
sac NF
0: GPIO as input
1: GPIO as output
0: GPIO as input
1: GPIO as output
O

0: GPIO as input
1: GPIO as output
u@ C

0: GPIO as input
1: GPIO as output
.Li K

0: GPIO as input
1: GPIO as output
no TE

0: GPIO as input
1: GPIO as output
Ar IA
0: GPIO as input
1: GPIO as output
0: GPIO as input
R ED
1: GPIO as output
0: GPIO as input
1: GPIO as output
FO M

0: GPIO as input
1: GPIO as output
0: GPIO as input
1: GPIO as output
0: GPIO as input
1: GPIO as output


MT2503D
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US IAL
0: GPIO as input
1: GPIO as output
EO
0: GPIO as input
1: GPIO as output
hk T
0: GPIO as input
1: GPIO as output
m. EN
0: GPIO as input
1: GPIO as output
0: GPIO as input
3 GPIO3 .co ID GPIO3_DIR

1: GPIO as output
0:
1: GPIO as output
GPIO as input
sac NF
0: GPIO as input
1: GPIO as output
O
0: GPIO as input
1: GPIO as output
u@ C
0: GPIO as input
1: GPIO as output
.Li K
GPIO_DIR0_SE
no TE
A0020004 GPIO Direction Control 00000000

T
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
Ar IA
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
5 4 3 2 1 0
R ED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Overview: For bitwise access of GPIO_DIR0

FO M

31 GPIO31 GPIO31_DIR Bitwise SET operation of GPIO31 direction
0: Keep
1: SET bits
0: Keep
1: SET bits


MT2503D
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US IAL
0: Keep
1: SET bits
EO
0: Keep
1: SET bits
hk T
0: Keep
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
24 GPIO24.co ID GPIO24_DIR
1: SET bits
Bitwise SET operation of GPIO24 direction
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
O
0: Keep
1: SET bits
u@ C
0: Keep
1: SET bits
.Li K
0: Keep
1: SET bits
no TE

0: Keep
1: SET bits
0: Keep
Ar IA
1: SET bits
0: Keep
1: SET bits
R ED

0: Keep
1: SET bits
FO M
0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits


MT2503D
Confidential A
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0: Keep
US IAL
1: SET bits
EO
0: Keep
1: SET bits
0: Keep
hk T
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
1: SET bits
7
6
GPIO7
GPIO6
.co ID GPIO7_DIR
GPIO6_DIR
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
0: Keep
O
1: SET bits
0: Keep
u@ C
1: SET bits
0: Keep
.Li K
1: SET bits
0: Keep
no TE
1: SET bits
0: Keep
1: SET bits
Ar IA

0: Keep
1: SET bits
R ED
GPIO_DIR0_CL
R
FO M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


MT2503D
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US IAL
31 GPIO31 GPIO31_DIR Bitwise CLR operation of GPIO31 direction
EO
0: Keep
1: CLR bits
0: Keep
hk T
1: CLR bits
m. EN
0: Keep
1: CLR bits
0: Keep
1: CLR bits
27 GPIO27
.co ID GPIO27_DIR Bitwise CLR operation of GPIO27 direction
0:
1: CLR bits
Keep
sac NF
0: Keep
1: CLR bits
0: Keep
O
1: CLR bits
u@ C
0: Keep
1: CLR bits
0: Keep
.Li K
1: CLR bits
no TE
0: Keep
1: CLR bits
0: Keep
1: CLR bits
Ar IA

0: Keep
1: CLR bits
R ED

0: Keep
1: CLR bits
0: Keep
FO M
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep


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1: CLR bits
US IAL
0: Keep
EO
1: CLR bits
0: Keep
1: CLR bits
hk T
0: Keep
m. EN
1: CLR bits
0: Keep
1: CLR bits
9 GPIO9
.co ID GPIO9_DIR
0:
1: CLR bits
Bitwise CLR operation of GPIO9 direction
Keep
sac NF
0: Keep
1: CLR bits
0: Keep
1: CLR bits
O

0: Keep
1: CLR bits
u@ C

0: Keep
1: CLR bits
.Li K

0: Keep
1: CLR bits
no TE

0: Keep
1: CLR bits
Ar IA
0: Keep
1: CLR bits
0: Keep
R ED
1: CLR bits
0: Keep
1: CLR bits
FO M

0: Keep
1: CLR bits
A0020010 GPIO_DIR1 GPIO Direction Control 00004000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIO5 GPIO5 GPIO5 GPIO5 GPIO4 GPIO4


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5 4 1 0 9 8
Type RW RW RW RW RW RW
Reset 0 0 0 0 0 0
US IAL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
EO
7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Overview: Configures GPIO direction
hk T
m. EN
0: GPIO as input
1: GPIO as output
19 GPIO51
.co ID GPIO51_DIR
0:
1: GPIO as output
GPIO

as input
sac NF
0: GPIO as input
1: GPIO as output
0: GPIO as input
1: GPIO as output
O

0: GPIO as input
1: GPIO as output
u@ C

0: GPIO as input
1: GPIO as output
.Li K

0: GPIO as input
no TE
1: GPIO as output
0: GPIO as input
1: GPIO as output
Ar IA
0: GPIO as input
1: GPIO as output
R ED
0: GPIO as input
1: GPIO as output
0: GPIO as input
1: GPIO as output
FO M

0: GPIO as input
1: GPIO as output
0: GPIO as input
1: GPIO as output
0: GPIO as input
1: GPIO as output


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0: GPIO as input
1: GPIO as output
EO
0: GPIO as input
1: GPIO as output
hk T
0: GPIO as input
1: GPIO as output
m. EN
0: GPIO as input
1: GPIO as output
0: GPIO as input
1: GPIO as output
0:
1: GPIO as output
GPIO as input
sac NF
0: GPIO as input
1: GPIO as output
O
0: GPIO as input
1: GPIO as output
u@ C
GPIO_DIR1_SE
.Li K

T
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
no TE

Name 5 4 1 0 9 8
Type WO WO WO WO WO WO
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3
Ar IA
7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R ED

FO M
0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits


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US IAL
0: Keep
1: SET bits
EO
0: Keep
1: SET bits
hk T
0: Keep
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
1: SET bits
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
O
0: Keep
1: SET bits
u@ C
0: Keep
1: SET bits
.Li K
0: Keep
1: SET bits
no TE

0: Keep
1: SET bits
0: Keep
Ar IA
1: SET bits
0: Keep
1: SET bits
R ED

0: Keep
1: SET bits
FO M
0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits


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0: Keep
US IAL
1: SET bits
EO
0: Keep
1: SET bits
hk T
GPIO_DIR1_CL
m. EN
R
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
5 4 1 0 9 8
Reset 0 0 0 0 0 0
Bit
Type
7
WO
15
6
.co ID
14
5 4
13
3
12
2 1
11
WO WO WO WO WO WO WO WO WO WO WO WO
0
10
9 8
9
7 6
8
5
7
4 3
WO WO WO
6
2
5 4 3 2 1 0
sac NF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

O

u@ C
0: Keep
1: CLR bits
0: Keep
.Li K
1: CLR bits
no TE
0: Keep
1: CLR bits
0: Keep
1: CLR bits
Ar IA

0: Keep
1: CLR bits
R ED
0: Keep
1: CLR bits
0: Keep
FO M
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep


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1: CLR bits
US IAL
0: Keep
EO
1: CLR bits
0: Keep
1: CLR bits
hk T
0: Keep
m. EN
1: CLR bits
0: Keep
1: CLR bits
6 GPIO38
.co ID GPIO38_DIR
0:
1: CLR bits
Bitwise CLR operation of GPIO38 direction
Keep
sac NF
0: Keep
1: CLR bits
0: Keep
1: CLR bits
O

0: Keep
1: CLR bits
u@ C

0: Keep
1: CLR bits
.Li K

0: Keep
1: CLR bits
no TE

0: Keep
1: CLR bits
Ar IA
0: Keep
1: CLR bits
R ED
A0020100 GPIO_PULLEN0 GPIO Pull-up/down Enable Control 43C00BFF

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO3 GPIO2 GPIO2 GPIO2 GPIO2
Name 0 5 4 3 2
FO M
Type RW RW RW RW RW
Reset 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO1
Name GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
1
Type RW RW RW RW RW RW RW RW RW RW RW
Reset 1 1 1 1 1 1 1 1 1 1 1
Overview: Configures GPIO pull enabling


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30 GPIO30 GPIO30_PULLEN GPIO30 PULLEN
0: Disable
EO
1: Enable
0: Disable
1: Enable
hk T
0: Disable
m. EN
1: Enable
0: Disable
1: Enable
11 GPIO11
.co ID GPIO11_PULLEN
0:
1: Enable
GPIO11 PULLEN
Disable
sac NF
0: Disable
1: Enable
0: Disable
1: Enable
O

0: Disable
1: Enable
u@ C

0: Disable
1: Enable
.Li K

0: Disable
no TE
1: Enable
0: Disable
1: Enable
Ar IA
0: Disable
1: Enable
R ED
0: Disable
1: Enable
0: Disable
1: Enable
FO M

0: Disable
1: Enable
0: Disable
1: Enable


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GPIO_PULLEN0
A0020104 GPIO Pull-up/down Enable Control 00000000
_SET
US IAL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name 0 5 4 3 2
Type WO WO WO WO WO
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO1
hk T
1
Type WO WO WO WO WO WO WO WO WO WO WO
Reset
m. EN
0 0 0 0 0 0 0 0 0 0 0
Overview: For bitwise access of GPIO_PULLEN0
30 GPIO30
.co ID
Bit(s) Mnemonic Name
GPIO30_PULLEN
Description
Bitwise SET operation of GPIO30 PULLEN_SET
0:
1: SET bits
Keep
sac NF
25 GPIO25 GPIO25_PULLEN Bitwise SET operation of GPIO25 PULLEN_SET
0: Keep
1: SET bits
O
0: Keep
1: SET bits
u@ C
0: Keep
1: SET bits
.Li K
0: Keep
1: SET bits
no TE
0: Keep
1: SET bits
0: Keep
1: SET bits
Ar IA

0: Keep
1: SET bits
R ED

0: Keep
1: SET bits
0: Keep
FO M
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits


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0: Keep
US IAL
1: SET bits
EO
0: Keep
1: SET bits
0: Keep
hk T
1: SET bits
m. EN
0: Keep
1: SET bits
A0020108
Bit 31
.co ID
GPIO_PULLEN0
_CLR
30
GPIO3
29 28 27 26 25 24 23
GPIO2 GPIO2 GPIO2 GPIO2
22 21 20 19 18
00000000
17 16
sac NF
Name
0 5 4 3 2
Type WO WO WO WO WO
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO1
O
1
Reset 0 0 0 0 0 0 0 0 0 0 0
u@ C

.Li K

30 GPIO30 GPIO30_PULLEN Bitwise CLR operation of GPIO30 PULLEN_CLR
no TE
0: Keep
1: CLR bits
0: Keep
1: CLR bits
Ar IA

0: Keep
1: CLR bits
R ED
0: Keep
1: CLR bits
0: Keep
FO M
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep


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1: CLR bits
US IAL
0: Keep
EO
1: CLR bits
0: Keep
1: CLR bits
hk T
0: Keep
m. EN
1: CLR bits
0: Keep
1: CLR bits
2 GPIO2
.co ID GPIO2_PULLEN
0:
1: CLR bits
Bitwise CLR operation of GPIO2 PULLEN_CLR
Keep
sac NF
0: Keep
1: CLR bits
0: Keep
1: CLR bits
O

0: Keep
1: CLR bits
u@ C
.Li K
A0020110 GPIO_PULLEN1 GPIO Pull-up/down Enable Control 00F01800

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
no TE

Name 5 4 3 2
Type RW RW RW RW
Reset 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO4 GPIO4
Ar IA
Name
4 3
Type RW RW
Reset 1 1
R ED
Overview: Configures GPIO pull enabling

FO M
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable


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0: Disable
1: Enable
EO
0: Disable
1: Enable
hk T
0: Disable
1: Enable
m. EN
GPIO_PULLEN1
_SET
Bit
Name
Type
31
.co ID
30 29 28 27 26 25 24 23 22 21
5 4
WO WO WO WO
3 2
20 19 18 17 16
sac NF
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO4 GPIO4
Name
4 3
Type WO WO
Reset 0 0
O

u@ C

.Li K
0: Keep
1: SET bits
no TE

0: Keep
1: SET bits
0: Keep
Ar IA
1: SET bits
0: Keep
1: SET bits
R ED

0: Keep
1: SET bits
FO M
0: Keep
1: SET bits
GPIO_PULLEN1
_CLR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


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Name
5 4 3 2
Type WO WO WO WO
US IAL
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
GPIO4 GPIO4
Name 4 3
Type WO WO
Reset 0 0
hk T
m. EN
0: Keep
1: CLR bits
22
21
GPIO54
GPIO53
.co ID GPIO54_PULLEN
GPIO53_PULLEN
0:
1: CLR bits
Keep
sac NF
0: Keep
1: CLR bits
0: Keep
O
1: CLR bits
0: Keep
u@ C
1: CLR bits
0: Keep
.Li K
1: CLR bits
no TE
A0020200 GPIO_DINV0 GPIO Data Inversion Control 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name INV31 INV30 INV29 INV28 INV27 INV26 INV25 INV24 INV23 INV22 INV21 INV20 INV19 INV18 INV17 INV16
Ar IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Overview: Configures GPIO inversion enabling

FO M

31 INV31 GPIO31_DINV GPIO31 inversion control
0: Keep input value
1: Invert input value
0: Keep input value


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0: Keep input value
US IAL
EO
0: Keep input value
0: Keep input value
hk T
m. EN
0: Keep input value
0: Keep input value
24
23
INV24
INV23
.co ID GPIO24_DINV
GPIO23_DINV
GPIO24 inversion control
0: Keep
input value
sac NF
0: Keep input value
0: Keep input value
O

0: Keep input value
u@ C

0: Keep input value
.Li K

0: Keep input value
no TE

0: Keep input value
Ar IA

0: Keep input value
R ED
0: Keep input value

0: Keep input value
FO M

0: Keep input value
0: Keep input value
0: Keep input value


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0: Keep input value
EO
0: Keep input value
hk T
0: Keep input value
m. EN
0: Keep input value
6 INV6
.co ID GPIO6_DINV
0: Keep
input value
sac NF
0: Keep input value
0: Keep input value
O

0: Keep input value
u@ C

0: Keep input value
.Li K

0: Keep input value
no TE

0: Keep input value
Ar IA
0: Keep input value

R ED
GPIO_DINV0_S
A0020204 GPIO Data Inversion Control 00000000
ET
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Overview: For bitwise access of GPIO_DINV0


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31 INV31 GPIO31_DINV Bitwise SET operation of GPIO31 inversion control
US IAL
0: Keep
1: SET bits
EO
0: Keep
1: SET bits
hk T
0: Keep
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
26 INV26 .co ID GPIO26_DINV

1: SET bits
Bitwise SET operation of GPIO26 inversion control
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
O
0: Keep
1: SET bits
u@ C
0: Keep
1: SET bits
.Li K
0: Keep
1: SET bits
no TE

0: Keep
1: SET bits
0: Keep
Ar IA
1: SET bits
0: Keep
1: SET bits
R ED

0: Keep
1: SET bits
FO M
0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits


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0: Keep
US IAL
1: SET bits
EO
0: Keep
1: SET bits
0: Keep
hk T
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
1: SET bits
9
8
INV9
INV8
.co ID GPIO9_DINV
GPIO8_DINV
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
0: Keep
O
1: SET bits
0: Keep
u@ C
1: SET bits
0: Keep
.Li K
1: SET bits
0: Keep
no TE
1: SET bits
0: Keep
1: SET bits
Ar IA

0: Keep
1: SET bits
R ED
0: Keep
1: SET bits
0: Keep
1: SET bits
FO M
GPIO_DINV0_C
LR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


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Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US IAL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
hk T
31 INV31 GPIO31_DINV Bitwise CLR operation of GPIO31 inversion control
m. EN
0: Keep
1: CLR bits
0: Keep
1: CLR bits
29
28
INV29
INV28
.co ID GPIO29_DINV
GPIO28_DINV
Bitwise CLR operation of GPIO29 inversion control
0:
1: CLR bits
Keep
sac NF
0: Keep
1: CLR bits
0: Keep
O
1: CLR bits
0: Keep
u@ C
1: CLR bits
0: Keep
.Li K
1: CLR bits
0: Keep
no TE
1: CLR bits
0: Keep
1: CLR bits
Ar IA

0: Keep
1: CLR bits
R ED
0: Keep
1: CLR bits
0: Keep
1: CLR bits
FO M

0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep


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1: CLR bits
US IAL
0: Keep
EO
1: CLR bits
0: Keep
1: CLR bits
hk T
0: Keep
m. EN
1: CLR bits
0: Keep
1: CLR bits
11 INV11
.co ID GPIO11_DINV
0:
1: CLR bits
Keep
sac NF
0: Keep
1: CLR bits
0: Keep
1: CLR bits
O

0: Keep
1: CLR bits
u@ C

0: Keep
1: CLR bits
.Li K

0: Keep
1: CLR bits
no TE

0: Keep
1: CLR bits
Ar IA
0: Keep
1: CLR bits
0: Keep
R ED
1: CLR bits
0: Keep
1: CLR bits
FO M

0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


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US IAL
A0020210 GPIO_DINV1 GPIO Data Inversion Control 00000000
EO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name INV55 INV54 INV53 INV52 INV51 INV50 INV49 INV48
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
hk T
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m. EN
Overview: Configures GPIO inversion enabling

23 INV55
.co ID GPIO55_DINV GPIO55 inversion control
0: Keep
input value
sac NF
0: Keep input value
0: Keep input value
O

u@ C
0: Keep input value

.Li K
0: Keep input value

no TE
0: Keep input value

0: Keep input value
Ar IA

0: Keep input value
R ED

0: Keep input value
0: Keep input value
FO M

0: Keep input value
0: Keep input value


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0: Keep input value
US IAL
EO
0: Keep input value
0: Keep input value
hk T
m. EN
0: Keep input value
0: Keep input value
6
5
INV38
INV37
.co ID GPIO38_DINV
GPIO37_DINV
0: Keep
input value
sac NF
0: Keep input value
0: Keep input value
O

0: Keep input value
u@ C

0: Keep input value
.Li K

0: Keep input value
no TE

0: Keep input value
Ar IA
GPIO_DINV1_S
R ED

ET
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0
FO M
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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US IAL
0: Keep
1: SET bits
EO
0: Keep
1: SET bits
hk T
0: Keep
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep

1: SET bits
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
O
0: Keep
1: SET bits
u@ C
0: Keep
1: SET bits
.Li K
0: Keep
1: SET bits
no TE

0: Keep
1: SET bits
0: Keep
Ar IA
1: SET bits
0: Keep
1: SET bits
R ED

0: Keep
1: SET bits
FO M
0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits


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0: Keep
US IAL
1: SET bits
EO
0: Keep
1: SET bits
0: Keep
hk T
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
1: SET bits
1
0
INV33
INV32
.co ID GPIO33_DINV
GPIO32_DINV
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
O
GPIO_DINV1_C
LR
u@ C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
.Li K
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
no TE
WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Ar IA

0: Keep
R ED
1: CLR bits
0: Keep
1: CLR bits
FO M
0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


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US IAL
0: Keep
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
0: Keep
1: CLR bits
m. EN
0: Keep
1: CLR bits
0: Keep

1: CLR bits
0:
1: CLR bits
Keep
sac NF
0: Keep
1: CLR bits
O
0: Keep
1: CLR bits
u@ C
0: Keep
1: CLR bits
.Li K
0: Keep
1: CLR bits
no TE

0: Keep
1: CLR bits
0: Keep
Ar IA
1: CLR bits
0: Keep
1: CLR bits
R ED

0: Keep
1: CLR bits
FO M
0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


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0: Keep
US IAL
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
A0020300 GPIO_DOUT0 GPIO Output Data Control 04000800
m. EN
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
Reset
5
RW
0
4
RW
0
.co ID
3
RW
0
2
RW
0
1
RW
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
sac NF
Overview: Configures GPIO output value

O
31 GPIO31 GPIO31_OUT GPIO31 data output value

0: GPIO output LO
1: GPIO output HI
u@ C

0: GPIO output LO
1: GPIO output HI
.Li K

0: GPIO output LO
no TE
1: GPIO output HI
0: GPIO output LO
1: GPIO output HI
Ar IA
0: GPIO output LO
1: GPIO output HI
0: GPIO output LO
R ED
1: GPIO output HI
0: GPIO output LO
1: GPIO output HI
FO M

0: GPIO output LO
1: GPIO output HI
0: GPIO output LO
1: GPIO output HI
0: GPIO output LO
1: GPIO output HI


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US IAL
0: GPIO output LO
1: GPIO output HI
EO
0: GPIO output LO
1: GPIO output HI
hk T
0: GPIO output LO
1: GPIO output HI
m. EN
0: GPIO output LO
1: GPIO output HI
0: GPIO output LO
16 GPIO16.co ID GPIO16_OUT
1: GPIO output HI
GPIO16 data output value
0:
1: GPIO output HI
GPIO output LO
sac NF
0: GPIO output LO
1: GPIO output HI
O
0: GPIO output LO
1: GPIO output HI
u@ C
0: GPIO output LO
1: GPIO output HI
.Li K
0: GPIO output LO
1: GPIO output HI
no TE

0: GPIO output LO
1: GPIO output HI
0: GPIO output LO
Ar IA
1: GPIO output HI
0: GPIO output LO
1: GPIO output HI
R ED

0: GPIO output LO
1: GPIO output HI
FO M
0: GPIO output LO
1: GPIO output HI
0: GPIO output LO
1: GPIO output HI
0: GPIO output LO
1: GPIO output HI


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0: GPIO output LO
US IAL
1: GPIO output HI
EO
0: GPIO output LO
1: GPIO output HI
0: GPIO output LO
hk T
1: GPIO output HI
m. EN
0: GPIO output LO
1: GPIO output HI
0: GPIO output LO
1: GPIO output HI
.co ID
GPIO_DOUT0_S
sac NF
A0020304 GPIO Output Data Control 00000000
ET
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
u@ C
5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.Li K

no TE

31 GPIO31 GPIO31_OUT Bitwise SET operation of GPIO31 data output value
0: Keep
1: SET bits
Ar IA

0: Keep
1: SET bits
R ED
0: Keep
1: SET bits
0: Keep
FO M
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep


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1: SET bits
US IAL
0: Keep
EO
1: SET bits
0: Keep
1: SET bits
hk T
0: Keep
m. EN
1: SET bits
0: Keep
1: SET bits
19 GPIO19
.co ID GPIO19_OUT
0:
1: SET bits
Bitwise SET operation of GPIO19 data output value
Keep
sac NF
0: Keep
1: SET bits
0: Keep
1: SET bits
O

0: Keep
1: SET bits
u@ C

0: Keep
1: SET bits
.Li K

0: Keep
1: SET bits
no TE

0: Keep
1: SET bits
Ar IA
0: Keep
1: SET bits
0: Keep
R ED
1: SET bits
0: Keep
1: SET bits
FO M

0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits


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US IAL
0: Keep
1: SET bits
EO
0: Keep
1: SET bits
hk T
0: Keep
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
2 GPIO2 .co ID GPIO2_OUT

1: SET bits
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
O
0: Keep
1: SET bits
u@ C
GPIO_DOUT0_C
.Li K

LR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
no TE
Name 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ar IA
5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R ED

31 GPIO31 GPIO31_OUT Bitwise CLR operation of GPIO31 data output value
FO M
0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


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US IAL
0: Keep
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
0: Keep
1: CLR bits
m. EN
0: Keep
1: CLR bits
0: Keep
1: CLR bits
Bitwise CLR operation of GPIO23 data output value
0:
1: CLR bits
Keep
sac NF
0: Keep
1: CLR bits
O
0: Keep
1: CLR bits
u@ C
0: Keep
1: CLR bits
.Li K
0: Keep
1: CLR bits
no TE

0: Keep
1: CLR bits
0: Keep
Ar IA
1: CLR bits
0: Keep
1: CLR bits
R ED

0: Keep
1: CLR bits
FO M
0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


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0: Keep
US IAL
1: CLR bits
EO
0: Keep
1: CLR bits
0: Keep
hk T
1: CLR bits
m. EN
0: Keep
1: CLR bits
0: Keep
1: CLR bits
6
5
GPIO6
GPIO5
.co ID GPIO6_OUT
GPIO5_OUT
0:
1: CLR bits
Keep
sac NF
0: Keep
1: CLR bits
0: Keep
O
1: CLR bits
0: Keep
u@ C
1: CLR bits
0: Keep
.Li K
1: CLR bits
0: Keep
no TE
1: CLR bits
0: Keep
1: CLR bits
Ar IA
A0020310 GPIO_DOUT1 GPIO Output Data Control 00004000

R ED
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
5 4 1 0 9 8
Reset 0 0 0 0 0 0
FO M
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Overview: Configures GPIO output value


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US IAL
0: GPIO output LO
1: GPIO output HI
EO
0: GPIO output LO
1: GPIO output HI
hk T
0: GPIO output LO
1: GPIO output HI
m. EN
0: GPIO output LO
1: GPIO output HI
0: GPIO output LO
1: GPIO output HI
GPIO48 data output value
0:
1: GPIO output HI
GPIO output LO
sac NF
0: GPIO output LO
1: GPIO output HI
O
0: GPIO output LO
1: GPIO output HI
u@ C
0: GPIO output LO
1: GPIO output HI
.Li K
0: GPIO output LO
1: GPIO output HI
no TE

0: GPIO output LO
1: GPIO output HI
0: GPIO output LO
Ar IA
1: GPIO output HI
0: GPIO output LO
1: GPIO output HI
R ED

0: GPIO output LO
1: GPIO output HI
FO M
0: GPIO output LO
1: GPIO output HI
0: GPIO output LO
1: GPIO output HI
0: GPIO output LO
1: GPIO output HI


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0: GPIO output LO
US IAL
1: GPIO output HI
EO
0: GPIO output LO
1: GPIO output HI
0: GPIO output LO
hk T
1: GPIO output HI
m. EN
0: GPIO output LO
1: GPIO output HI
0: GPIO output LO
1: GPIO output HI
.co ID
GPIO_DOUT1_S
sac NF
ET
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
5 4 1 0 9 8
O
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
u@ C
7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.Li K

no TE

0: Keep
1: SET bits
Ar IA

0: Keep
1: SET bits
R ED
0: Keep
1: SET bits
0: Keep
FO M
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep


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1: SET bits
US IAL
0: Keep
EO
1: SET bits
0: Keep
1: SET bits
hk T
0: Keep
m. EN
1: SET bits
0: Keep
1: SET bits
9 GPIO41
.co ID GPIO41_OUT
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
0: Keep
1: SET bits
O

0: Keep
1: SET bits
u@ C

0: Keep
1: SET bits
.Li K

0: Keep
1: SET bits
no TE

0: Keep
1: SET bits
Ar IA
0: Keep
1: SET bits
0: Keep
R ED
1: SET bits
0: Keep
1: SET bits
FO M

0: Keep
1: SET bits
GPIO_DOUT1_C
LR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


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Name
5 4 1 0 9 8
US IAL
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
Name 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
hk T
m. EN
0: Keep
1: CLR bits
22
19
GPIO54
GPIO51
.co ID GPIO54_OUT
GPIO51_OUT
0:
1: CLR bits
Keep
sac NF
0: Keep
1: CLR bits
0: Keep
O
1: CLR bits
0: Keep
u@ C
1: CLR bits
0: Keep
.Li K
1: CLR bits
0: Keep
no TE
1: CLR bits
0: Keep
1: CLR bits
Ar IA

0: Keep
1: CLR bits
R ED
0: Keep
1: CLR bits
0: Keep
1: CLR bits
FO M

0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep


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1: CLR bits
US IAL
0: Keep
EO
1: CLR bits
0: Keep
1: CLR bits
hk T
0: Keep
m. EN
1: CLR bits
0: Keep
1: CLR bits
2 GPIO34
.co ID GPIO34_OUT
0:
1: CLR bits
Keep
sac NF
0: Keep
1: CLR bits
0: Keep
1: CLR bits
O

0: Keep
1: CLR bits
u@ C
.Li K
A0020400 GPIO_DIN0 GPIO Input Data Value 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
no TE
Name 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ar IA
5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R ED
Overview: Reads GPIO input value

31 GPIO31 GPIO31_DIN GPIO31 data input value
FO M



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US IAL
EO
hk T
m. EN
11
10
9
GPIO11
GPIO10
GPIO9
.co ID GPIO11_DIN
GPIO10_DIN
GPIO9_DIN
GPIO11 data input value
sac NF
O

u@ C

.Li K
no TE
A0020410 GPIO_DIN1 GPIO Input Data Value 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO4 GPIO4
Name 5 4 3 2 1 0 9 8
Ar IA
Type RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
R ED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Overview: Reads GPIO input value

FO M



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US IAL
EO
hk T
m. EN
5
4
3
GPIO37
GPIO36
GPIO35
.co ID GPIO37_DIN
GPIO36_DIN
GPIO35_DIN
sac NF
O
GPIO_PULLSEL
u@ C
A0020500 GPIO Pullsel Control 00000000

0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
.Li K
0 5 4 3 2
Type RW RW RW RW RW
Reset 0 0 0 0 0
no TE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO1
1
Reset 0 0 0 0 0 0 0 0 0 0 0
Ar IA
Overview: Configures GPIO PUPD selection

R ED
30 GPIO30 GPIO30_PULLSEL GPIO30 PULLSEL

0: Pull down
1: Pull up
FO M
0: Pull down
1: Pull up
0: Pull down
1: Pull up
0: Pull down
1: Pull up


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US IAL
0: Pull down
1: Pull up
EO
0: Pull down
1: Pull up
hk T
0: Pull down
1: Pull up
m. EN
0: Pull down
1: Pull up
0: Pull down
6 GPIO6 .co ID GPIO6_PULLSEL

1: Pull up
GPIO6 PULLSEL
0:
1: Pull up
Pull down
sac NF
0: Pull down
1: Pull up
O
0: Pull down
1: Pull up
u@ C
0: Pull down
1: Pull up
.Li K
0: Pull down
1: Pull up
no TE

0: Pull down
1: Pull up
0: Pull down
Ar IA
1: Pull up
R ED
GPIO_PULLSEL
0_SET
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name 0 5 4 3 2
FO M
Type WO WO WO WO WO
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO1
1
Reset 0 0 0 0 0 0 0 0 0 0 0
Overview: For bitwise access of GPIO_PULLSEL0


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US IAL
30 GPIO30 GPIO30_PULLSEL Bitwise SET operation of GPIO30 PULLSEL_SET
0: Keep
EO
1: SET bits
0: Keep
1: SET bits
hk T
0: Keep
m. EN
1: SET bits
0: Keep
1: SET bits
11 GPIO11
.co ID GPIO11_PULLSEL
0:
1: SET bits
Bitwise SET operation of GPIO11 PULLSEL_SET
Keep
sac NF
0: Keep
1: SET bits
0: Keep
1: SET bits
O

0: Keep
1: SET bits
u@ C

0: Keep
1: SET bits
.Li K

0: Keep
no TE
1: SET bits
0: Keep
1: SET bits
Ar IA
0: Keep
1: SET bits
R ED
0: Keep
1: SET bits
0: Keep
1: SET bits
FO M

0: Keep
1: SET bits
0: Keep
1: SET bits


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GPIO_PULLSEL
0_CLR
US IAL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name 0 5 4 3 2
Type WO WO WO WO WO
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO1
hk T
1
Reset
m. EN
0 0 0 0 0 0 0 0 0 0 0
30 GPIO30
.co ID
GPIO30_PULLSEL
Description
Bitwise CKR operation of GPIO30 PULLSEL_CLR
0:
1: CLR bits
Keep
sac NF
25 GPIO25 GPIO25_PULLSEL Bitwise CKR operation of GPIO25 PULLSEL_CLR
0: Keep
1: CLR bits
O
0: Keep
1: CLR bits
u@ C
0: Keep
1: CLR bits
.Li K
0: Keep
1: CLR bits
no TE
0: Keep
1: CLR bits
0: Keep
1: CLR bits
Ar IA

0: Keep
1: CLR bits
R ED

0: Keep
1: CLR bits
0: Keep
FO M
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


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0: Keep
US IAL
1: CLR bits
EO
0: Keep
1: CLR bits
0: Keep
hk T
1: CLR bits
m. EN
0: Keep
1: CLR bits
A0020510
Bit 31
.co ID
GPIO_PULLSEL
1
30
29 28 27 26 25 24 23 22 21
20 19 18
00000000
17 16
sac NF
Name
5 4 3 2
Type RW RW RW RW
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO4 GPIO4
Name
O
4 3
Type RW RW
Reset 0 0
u@ C
Overview: Configures GPIO PUPD selection

.Li K

no TE
0: Pull down
1: Pull up
0: Pull down
1: Pull up
Ar IA

0: Pull down
1: Pull up
R ED
0: Pull down
1: Pull up
0: Pull down
FO M
1: Pull up
0: Pull down
1: Pull up
A0020514 GPIO_PULLSEL GPIO Pullsel Control 00000000


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1_SET
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US IAL
Name 5 4 3 2
Type WO WO WO WO
EO
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO4 GPIO4
Name
4 3
Type WO WO
hk T
Reset 0 0
m. EN

22 GPIO54
.co ID GPIO54_PULLSEL
0:
1: SET bits
Bitwise SET operation of GPIO54 PULLSEL_SET
Keep
sac NF
0: Keep
1: SET bits
0: Keep
1: SET bits
O

0: Keep
1: SET bits
u@ C

0: Keep
1: SET bits
.Li K

0: Keep
1: SET bits
no TE
GPIO_PULLSEL
Ar IA
1_CLR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
5 4 3 2
R ED
Type WO WO WO WO
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO4 GPIO4
Name 4 3
Type WO WO
FO M
Reset 0 0

0: Keep
1: CLR bits


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US IAL
0: Keep
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
0: Keep
1: CLR bits
m. EN
0: Keep
1: CLR bits
0: Keep
.co ID 1: CLR bits

sac NF
A0020600 GPIO_SMT0 GPIO SMT Control 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
u@ C
5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.Li K
Overview: Configures GPIO Schmit trigger control

no TE

31 GPIO31 GPIO31_SMT SMT for GPIO31
0: Disable
1: Enable
Ar IA

0: Disable
1: Enable
R ED

0: Disable
1: Enable
0: Disable
FO M
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable


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1: Enable
US IAL
0: Disable
EO
1: Enable
0: Disable
1: Enable
hk T
0: Disable
m. EN
1: Enable
0: Disable
1: Enable
19 GPIO19
.co ID GPIO19_SMT
0:
1: Enable
SMT for GPIO19
Disable
sac NF
0: Disable
1: Enable
0: Disable
1: Enable
O

0: Disable
1: Enable
u@ C

0: Disable
1: Enable
.Li K

0: Disable
1: Enable
no TE

0: Disable
1: Enable
Ar IA
0: Disable
1: Enable
0: Disable
R ED
1: Enable
0: Disable
1: Enable
FO M

0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable


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US IAL
0: Disable
1: Enable
EO
0: Disable
1: Enable
hk T
0: Disable
1: Enable
m. EN
0: Disable
1: Enable
0: Disable
2 GPIO2 .co ID GPIO2_SMT

1: Enable
SMT for GPIO2
0:
1: Enable
Disable
sac NF
0: Disable
1: Enable
O
0: Disable
1: Enable
u@ C
GPIO_SMT0_SE
.Li K
A0020604 GPIO SMT Control 00000000

T
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
no TE
Name 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ar IA
5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R ED
Overview: For bitwise access of GPIO_SMT0

31 GPIO31 GPIO31_SMT Bitwise SET operation of GPIO31 SMT
FO M
0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits


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US IAL
0: Keep
1: SET bits
EO
0: Keep
1: SET bits
hk T
0: Keep
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
23 GPIO23.co ID GPIO23_SMT
1: SET bits
Bitwise SET operation of GPIO23 SMT
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
O
0: Keep
1: SET bits
u@ C
0: Keep
1: SET bits
.Li K
0: Keep
1: SET bits
no TE

0: Keep
1: SET bits
0: Keep
Ar IA
1: SET bits
0: Keep
1: SET bits
R ED

0: Keep
1: SET bits
FO M
0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits


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0: Keep
US IAL
1: SET bits
EO
0: Keep
1: SET bits
0: Keep
hk T
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
1: SET bits
6
5
GPIO6
GPIO5
.co ID GPIO6_SMT
GPIO5_SMT
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
0: Keep
O
1: SET bits
0: Keep
u@ C
1: SET bits
0: Keep
.Li K
1: SET bits
0: Keep
no TE
1: SET bits
0: Keep
1: SET bits
Ar IA
GPIO_SMT0_CL
R ED

R
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
FO M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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31 GPIO31 GPIO31_SMT Bitwise CLR operation of GPIO31 SMT
US IAL
0: Keep
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
0: Keep
1: CLR bits
m. EN
0: Keep
1: CLR bits
0: Keep
1: CLR bits
Bitwise CLR operation of GPIO26 SMT
0:
1: CLR bits
Keep
sac NF
0: Keep
1: CLR bits
O
0: Keep
1: CLR bits
u@ C
0: Keep
1: CLR bits
.Li K
0: Keep
1: CLR bits
no TE

0: Keep
1: CLR bits
0: Keep
Ar IA
1: CLR bits
0: Keep
1: CLR bits
R ED

0: Keep
1: CLR bits
FO M
0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


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0: Keep
US IAL
1: CLR bits
EO
0: Keep
1: CLR bits
0: Keep
hk T
1: CLR bits
m. EN
0: Keep
1: CLR bits
0: Keep
1: CLR bits
9
8
GPIO9
GPIO8
.co ID GPIO9_SMT
GPIO8_SMT
0:
1: CLR bits
Keep
sac NF
0: Keep
1: CLR bits
0: Keep
O
1: CLR bits
0: Keep
u@ C
1: CLR bits
0: Keep
.Li K
1: CLR bits
0: Keep
no TE
1: CLR bits
0: Keep
1: CLR bits
Ar IA

0: Keep
1: CLR bits
R ED
0: Keep
1: CLR bits
0: Keep
1: CLR bits
FO M
A0020610 GPIO_SMT1 GPIO SMT Control 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
1 0 9 8
Type RW RW RW RW
Reset 0 0 0 0


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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
US IAL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Overview: Configures GPIO Schmit trigger control
hk T
m. EN
0: Disable
1: Enable
0: Disable
1: Enable
17
16
GPIO49
GPIO48
.co ID GPIO49_SMT
GPIO48_SMT
SMT for GPIO49
0:
1: Enable
SMT for GPIO48
Disable
sac NF
0: Disable
1: Enable
0: Disable
O
1: Enable
0: Disable
u@ C
1: Enable
0: Disable
.Li K
1: Enable
0: Disable
no TE
1: Enable
0: Disable
1: Enable
Ar IA

0: Disable
1: Enable
R ED
0: Disable
1: Enable
0: Disable
1: Enable
FO M

0: Disable
1: Enable
0: Disable
1: Enable
0: Disable


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1: Enable
US IAL
0: Disable
EO
1: Enable
0: Disable
1: Enable
hk T
0: Disable
m. EN
1: Enable
0: Disable
1: Enable
.co ID 0:
1: Enable
Disable
sac NF
GPIO_SMT1_SE
T
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
O

Name 1 0 9 8
Type WO WO WO WO
u@ C
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
.Li K
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
no TE

Ar IA
0: Keep
1: SET bits
R ED
0: Keep
1: SET bits
0: Keep
1: SET bits
FO M

0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits


MT2503D
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US IAL
0: Keep
1: SET bits
EO
0: Keep
1: SET bits
hk T
0: Keep
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
1: SET bits
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
O
0: Keep
1: SET bits
u@ C
0: Keep
1: SET bits
.Li K
0: Keep
1: SET bits
no TE

0: Keep
1: SET bits
0: Keep
Ar IA
1: SET bits
0: Keep
1: SET bits
R ED

0: Keep
1: SET bits
FO M
GPIO_SMT1_CL
R
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name 1 0 9 8
Type WO WO WO WO
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


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7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
US IAL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
hk T
0: Keep
m. EN
1: CLR bits
0: Keep
1: CLR bits
16 GPIO48
.co ID GPIO48_SMT
0:
1: CLR bits
0:
Keep
Keep
sac NF
1: CLR bits
0: Keep
1: CLR bits
O

0: Keep
1: CLR bits
u@ C

0: Keep
1: CLR bits
.Li K

0: Keep
1: CLR bits
no TE

0: Keep
1: CLR bits
Ar IA
0: Keep
1: CLR bits
0: Keep
R ED
1: CLR bits
0: Keep
1: CLR bits
FO M

0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


MT2503D
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US IAL
0: Keep
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
0: Keep
1: CLR bits
m. EN
0: Keep
1: CLR bits
0: Keep
.co ID 1: CLR bits

sac NF
A0020700 GPIO_SR0 GPIO SR Control FFFFFFFF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
O
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
u@ C
5 4 3 2 1 0
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
.Li K
Overview: Configures GPIO slew rate control

no TE

31 GPIO31 GPIO31_SR SR for GPIO31
0: Disable
1: Enable
Ar IA

0: Disable
1: Enable
R ED

0: Disable
1: Enable
0: Disable
FO M
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable


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1: Enable
US IAL
0: Disable
EO
1: Enable
0: Disable
1: Enable
hk T
0: Disable
m. EN
1: Enable
0: Disable
1: Enable
19 GPIO19
.co ID GPIO19_SR
0:
1: Enable
SR for GPIO19
Disable
sac NF
0: Disable
1: Enable
0: Disable
1: Enable
O

0: Disable
1: Enable
u@ C

0: Disable
1: Enable
.Li K

0: Disable
1: Enable
no TE

0: Disable
1: Enable
Ar IA
0: Disable
1: Enable
0: Disable
R ED
1: Enable
0: Disable
1: Enable
FO M

0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable


MT2503D
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US IAL
0: Disable
1: Enable
EO
0: Disable
1: Enable
hk T
0: Disable
1: Enable
m. EN
0: Disable
1: Enable
0: Disable
2 GPIO2 .co ID GPIO2_SR

1: Enable
SR for GPIO2
0:
1: Enable
Disable
sac NF
0: Disable
1: Enable
O
0: Disable
1: Enable
u@ C
A0020704 GPIO_SR0_SET GPIO SR Control 00000000

.Li K
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
no TE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5 4 3 2 1 0
Ar IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Overview: For bitwise access of GPIO_SR0

R ED

31 GPIO31 GPIO31_SR Bitwise SET operation of GPIO31 SR
0: Keep
FO M
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep


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1: SET bits
US IAL
0: Keep
EO
1: SET bits
0: Keep
1: SET bits
hk T
0: Keep
m. EN
1: SET bits
0: Keep
1: SET bits
22 GPIO22
.co ID GPIO22_SR
0:
1: SET bits
Bitwise SET operation of GPIO22 SR
Keep
sac NF
0: Keep
1: SET bits
0: Keep
1: SET bits
O

0: Keep
1: SET bits
u@ C

0: Keep
1: SET bits
.Li K

0: Keep
1: SET bits
no TE

0: Keep
1: SET bits
Ar IA
0: Keep
1: SET bits
0: Keep
R ED
1: SET bits
0: Keep
1: SET bits
FO M

0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits


MT2503D
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US IAL
0: Keep
1: SET bits
EO
0: Keep
1: SET bits
hk T
0: Keep
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep

1: SET bits
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
O
0: Keep
1: SET bits
u@ C
0: Keep
1: SET bits
.Li K
0: Keep
1: SET bits
no TE

0: Keep
1: SET bits
Ar IA
A0020708 GPIO_SR0_CLR GPIO SR Control 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ED
Name 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO M
5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 GPIO31 GPIO31_SR Bitwise CLR operation of GPIO31 SR
0: Keep


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1: CLR bits
US IAL
0: Keep
EO
1: CLR bits
0: Keep
1: CLR bits
hk T
0: Keep
m. EN
1: CLR bits
0: Keep
1: CLR bits
25 GPIO25
.co ID GPIO25_SR
0:
1: CLR bits
Bitwise CLR operation of GPIO25 SR
Keep
sac NF
0: Keep
1: CLR bits
0: Keep
1: CLR bits
O

0: Keep
1: CLR bits
u@ C

0: Keep
1: CLR bits
.Li K

0: Keep
1: CLR bits
no TE

0: Keep
1: CLR bits
Ar IA
0: Keep
1: CLR bits
0: Keep
R ED
1: CLR bits
0: Keep
1: CLR bits
FO M

0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


MT2503D
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NL
US IAL
0: Keep
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
0: Keep
1: CLR bits
m. EN
0: Keep
1: CLR bits
0: Keep

1: CLR bits
Bitwise CLR operation of GPIO8 SR
0:
1: CLR bits
Keep
sac NF
0: Keep
1: CLR bits
O
0: Keep
1: CLR bits
u@ C
0: Keep
1: CLR bits
.Li K
0: Keep
1: CLR bits
no TE

0: Keep
1: CLR bits
0: Keep
Ar IA
1: CLR bits
0: Keep
1: CLR bits
R ED

0: Keep
1: CLR bits
FO M
A0020710 GPIO_SR1 GPIO SR Control 000FF81F

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name 1 0 9 8
Type RW RW RW RW
Reset 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


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7 6 5 4 3 6 5 4 3 2
Type RW RW RW RW RW RW RW RW RW RW
Reset 1 1 1 1 1 1 1 1 1 1
US IAL
Overview: Configures GPIO slew rate control
EO
hk T
0: Disable
1: Enable
m. EN
0: Disable
1: Enable
0: Disable
16 GPIO48.co ID GPIO48_SR
1: Enable
SR for GPIO48
0:
1: Enable
Disable
sac NF
0: Disable
1: Enable
O
0: Disable
1: Enable
u@ C
0: Disable
1: Enable
.Li K
0: Disable
1: Enable
no TE

0: Disable
1: Enable
0: Disable
Ar IA
1: Enable
0: Disable
1: Enable
R ED

0: Disable
1: Enable
FO M
0: Disable
1: Enable
0: Disable
1: Enable


MT2503D
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A0020714 GPIO_SR1_SET GPIO SR Control 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US IAL
Name 1 0 9 8
EO
Type WO WO WO WO
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
7 6 5 4 3 6 5 4 3 2
hk T
Type WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0
m. EN

19
18
GPIO51
GPIO50
.co ID GPIO51_SR
GPIO50_SR
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
0: Keep
1: SET bits
O

0: Keep
u@ C
1: SET bits
0: Keep
.Li K
1: SET bits
0: Keep
no TE
1: SET bits
0: Keep
1: SET bits
Ar IA

0: Keep
1: SET bits
R ED
0: Keep
1: SET bits
0: Keep
1: SET bits
FO M

0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep


MT2503D
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1: SET bits
US IAL
0: Keep
EO
1: SET bits
hk T
A0020718 GPIO_SR1_CLR GPIO SR Control 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
m. EN
Name 1 0 9 8
Type WO WO WO WO
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
Reset
7
WO
0
6
.co ID
5
WO WO WO WO
0 0
4
0
3
0
6
WO WO
0
5
0
4 3
WO WO WO
0 0
2
0
sac NF

O
0: Keep
1: CLR bits
u@ C

0: Keep
1: CLR bits
.Li K
0: Keep
1: CLR bits
no TE

0: Keep
1: CLR bits
0: Keep
Ar IA
1: CLR bits
0: Keep
1: CLR bits
R ED

0: Keep
1: CLR bits
FO M
0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


MT2503D
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NL
US IAL
0: Keep
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
0: Keep
1: CLR bits
m. EN
0: Keep
1: CLR bits
A0020720
Bit 31
.co ID
GPIO_SIM_SR
30 29 28
GPIO SIM SR Control
27 26 25 24 23 22 21 20 19 18
003F003F
17 16
sac NF
Name 2 1 0 9 8 7
Reset 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
O
2 1 0 9 8 7
Reset 1 1 1 1 1 1
u@ C
Overview: Configures GPIO slew rate control for SIM IO

.Li K

21 GPIO42 GPIO42_SR1 SR1 control for GPIO42
no TE
0: Disable
1: Enable
0: Disable
1: Enable
Ar IA

0: Disable
1: Enable
R ED

0: Disable
1: Enable
0: Disable
FO M
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable


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1: Enable
US IAL
0: Disable
EO
1: Enable
0: Disable
1: Enable
hk T
0: Disable
m. EN
1: Enable
0: Disable
1: Enable
A0020724
.co ID
GPIO_SIM_SR_
SET
GPIO SIM SR Control 00000000
sac NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name 2 1 0 9 8 7
Reset 0 0 0 0 0 0
O
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
2 1 0 9 8 7
u@ C
Reset 0 0 0 0 0 0
.Li K
Overview: For bitwise access of GPIO_SIM_SR

no TE

21 GPIO42 GPIO42_SR1 Bitwise SET operation of GPIO42 SR1 control
0: Keep
1: SET bits
Ar IA
0: Keep
1: SET bits
R ED
0: Keep
1: SET bits
0: Keep
1: SET bits
FO M

0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits


MT2503D
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Y
NL
US IAL
0: Keep
1: SET bits
EO
0: Keep
1: SET bits
hk T
0: Keep
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
.co ID 1: SET bits

sac NF
GPIO_SIM_SR_
A0020728 GPIO SIM SR Control 00000000
CLR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
O
2 1 0 9 8 7
Reset 0 0 0 0 0 0
u@ C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
2 1 0 9 8 7
.Li K
Reset 0 0 0 0 0 0
Overview: For bitwise access of GPIO_SIM_SR

no TE

21 GPIO42 GPIO42_SR1 Bitwise CLR operation of GPIO42 SR1 control
0: Keep
Ar IA
1: CLR bits
0: Keep
1: CLR bits
R ED

0: Keep
1: CLR bits
FO M
0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


MT2503D
Confidential A
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NL
US IAL
0: Keep
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
0: Keep
1: CLR bits
m. EN
0: Keep
1: CLR bits
0: Keep
0 GPIO37.co ID GPIO37_SR0
1: CLR bits
Bitwise CLR operation of GPIO37 SR0 control
0:
1: CLR bits
Keep
sac NF
A0020800 GPIO_DRV0 GPIO DRV Control 00000000

O
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DRV0[31:16]
Type RW
u@ C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DRV0[15:0]
Type RW
.Li K
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
no TE
Overview: Configures GPIO driving control

31:0 DRV0 GPIO_DRV0
Ar IA
[1: 0]: GPIO_0

[3: 2]: GPIO_1
[5: 4]: GPIO_2
[7: 6]: GPIO_3
[9: 8]: GPIO_4
R ED
[11: 10]: GPIO_5

[13: 12]: GPIO_6
[15: 14]: GPIO_7
[17: 16]: GPIO_8
[19: 18]: GPIO_9
FO M
[21: 20]: URXD1

[21: 20]: UTXD1
[23: 22]: KCOL4
[25: 24]: KCOL3
[27: 26]: KCOL2
[29: 28]: KCOL1
[31: 30]: KCOL0


MT2503D
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GPIO_DRV0_SE
A0020804 GPIO DRV Control 00000000
T
US IAL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DRV0[31:16]
EO
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DRV0[15:0]
Type WO
hk T
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m. EN
Overview: For bitwise access of GPIO_DRV0

31:0 DRV0 Bitwise SET operation of GPIO_DRV0_SET
.co ID 0:
1: SET bits
Keep
sac NF
GPIO_DRV0_CL
R
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
O
Name DRV0[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
u@ C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DRV0[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.Li K

no TE

31:0 DRV0 Bitwise CLR operation of GPIO_DRV0_CLR
0: Keep
Ar IA
1: CLR bits
R ED
A0020810 GPIO_DRV1 GPIO DRV Control 00C00000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DRV1[25:16]
Type RW
Reset 0 0 1 1 0 0 0 0 0 0
FO M
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DRV1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Overview: Configures GPIO driving control


MT2503D
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25:0 DRV1 GPIO_DRV1
US IAL
[1: 0]: KROW4
[3: 2]: KROW3
EO
[5: 4]: KROW2
[7: 6]: KROW1
[9: 8]: KROW0
[11: 10]: BPI_BUS2
[11: 10]: BPI_BUS1
hk T
[11: 10]: BPI_BUS0
[13: 12]: CMRST
[13: 12]: CMPDN
m. EN
[13: 12]: CMCSD0
[13: 12]: CMCSD1
[13: 12]: CMMCLK
[13: 12]: CMCSK
[15: 14]: MCCK
.co ID [15:
[15:
[15:
[15:
[15:
14]:
14]:
14]:
14]:
14]:
MCCM0
MCDA0
MCDA1
MCDA2
MCDA3
sac NF
[17: 16]: SIM1_SIO
[17: 16]: SIM1_SRST
[17: 16]: SIM1_SCLK
[19: 18]: SIM2_SIO
[19: 18]: SIM2_SRST
O
[19: 18]: SIM2_SCLK

[21: 20]: SCL28
[21: 20]: SDA28
u@ C
[23: 22]: TESTMODE_D

[23: 22]: LSCE_B
[23: 22]: LSCK
[23: 22]: LSDA
.Li K
[23: 22]: LSA0

[23: 22]:LPTE
[25: 24]:RESETB
no TE
GPIO_DRV1_SE
T
Ar IA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DRV1[25:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0
R ED
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DRV1[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO M

25:0 DRV1 Bitwise SET operation of GPIO_DRV1_SET
0: Keep
1: SET bits


MT2503D
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GPIO_DRV1_CL
US IAL
R
EO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DRV1[25:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
hk T
Name DRV1[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m. EN

25:0
.co ID DRV1 Bitwise CLR operation of GPIO_DRV1_CLR
0:
1: CLR bits
Keep
sac NF
A0020900 GPIO_IES0 GPIO IES Control 43C00BFF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
O

Name
0 5 4 3 2
Type RW RW RW RW RW
u@ C
Reset 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO1
1
.Li K
Reset 1 1 1 1 1 1 1 1 1 1 1
no TE
Overview: Configures GPIO input enabling control

Ar IA
30 GPIO30 GPIO30_IES Input buffer for GPIO30

0: Disable
1: Enable
R ED
0: Disable
1: Enable
0: Disable
1: Enable
FO M

0: Disable
1: Enable
0: Disable
1: Enable
0: Disable


MT2503D
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1: Enable
US IAL
0: Disable
EO
1: Enable
0: Disable
1: Enable
hk T
0: Disable
m. EN
1: Enable
0: Disable
1: Enable
4 GPIO4
.co ID GPIO4_IES
0:
1: Enable
Input buffer for GPIO4
Disable
sac NF
0: Disable
1: Enable
0: Disable
1: Enable
O

0: Disable
1: Enable
u@ C

0: Disable
1: Enable
.Li K

0: Disable
1: Enable
no TE
A0020904 GPIO_IES0_SET GPIO IES Control 00000000

Ar IA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name 0 5 4 3 2
Type WO WO WO WO WO
R ED
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO1
1
Reset 0 0 0 0 0 0 0 0 0 0 0
FO M
Overview: For bitwise access of GPIO_IES0

30 GPIO30 GPIO30_IES Bitwise SET operation of GPIO30 input buffer
0: Keep
1: SET bits


MT2503D
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NL
US IAL
0: Keep
1: SET bits
EO
0: Keep
1: SET bits
hk T
0: Keep
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
9 GPIO9 .co ID GPIO9_IES

1: SET bits
Bitwise SET operation of GPIO9 input buffer
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
O
0: Keep
1: SET bits
u@ C
0: Keep
1: SET bits
.Li K
0: Keep
1: SET bits
no TE

0: Keep
1: SET bits
0: Keep
Ar IA
1: SET bits
0: Keep
1: SET bits
R ED

0: Keep
1: SET bits
FO M
0: Keep
1: SET bits
GPIO_IES0_CL
A0020908 GPIO IES Control 00000000
R
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIO3 GPIO2 GPIO2 GPIO2 GPIO2


MT2503D
Confidential A
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0 5 4 3 2
Type WO WO WO WO WO
Reset 0 0 0 0 0
US IAL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO1
EO
1
Reset 0 0 0 0 0 0 0 0 0 0 0
hk T
m. EN
30 GPIO30 GPIO30_IES Bitwise CLR operation of GPIO30 input buffer
0: Keep
1: CLR bits
24 GPIO24
.co ID GPIO24_IES
0:
1: CLR bits
Bitwise CLR operation of GPIO24 input buffer
Keep
sac NF
0: Keep
1: CLR bits
0: Keep
1: CLR bits
O

0: Keep
1: CLR bits
u@ C

0: Keep
1: CLR bits
.Li K

0: Keep
no TE
1: CLR bits
0: Keep
1: CLR bits
Ar IA
0: Keep
1: CLR bits
R ED
0: Keep
1: CLR bits
0: Keep
1: CLR bits
FO M

0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


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US IAL
0: Keep
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
m. EN
A0020910 GPIO_IES1 GPIO IES Control 00001FE0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit
Name
Type
Reset
15
.co ID
14 13
RW
1
12
RW
1
11
RW
1
1
RW
1
10
0
RW
1
9
9
RW
1
8
RW
1
8
4 3 2 7
RW
1
7 6 5 4 3 2 1 0
sac NF
Overview: Configures GPIO input enabling control

O

0: Disable
u@ C
1: Enable
0: Disable
.Li K
1: Enable
0: Disable
no TE
1: Enable
0: Disable
1: Enable
Ar IA

0: Disable
1: Enable
R ED
0: Disable
1: Enable
0: Disable
1: Enable
FO M

0: Disable
1: Enable
A0020914 GPIO_IES1_SET GPIO IES Control 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


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Name
Type
Reset
US IAL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
EO
4 3 2 1 0 9 8 7
Reset 0 0 0 0 0 0 0 0
hk T
m. EN
0: Keep
1: SET bits
10 GPIO42
.co ID GPIO42_IES
0:
1: SET bits
Bitwise SET operation of GPIO42 input buffer
Keep
sac NF
0: Keep
1: SET bits
0: Keep
1: SET bits
O

0: Keep
1: SET bits
u@ C

0: Keep
1: SET bits
.Li K

0: Keep
no TE
1: SET bits
0: Keep
1: SET bits
Ar IA
GPIO_IES1_CL
A0020918 GPIO IES Control 00000000
R
R ED
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO M

Name
4 3 2 1 0 9 8 7
Reset 0 0 0 0 0 0 0 0


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US IAL
0: Keep
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
0: Keep
1: CLR bits
m. EN
0: Keep
1: CLR bits
0: Keep
7 GPIO39.co ID GPIO39_IES
1: CLR bits
Bitwise CLR operation of GPIO39 input buffer
0:
1: CLR bits
Keep
sac NF
0: Keep
1: CLR bits
O
0: Keep
1: CLR bits
u@ C
A0020A00 GPIO_PUPD0 GPIO PUPD Control 303E0000

.Li K
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO3 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO1 GPIO1 GPIO1 GPIO1
Name 1 9 8 7 6 1 0 9 8 7 6
no TE
Reset 0 1 1 0 0 1 1 1 1 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5 4 3 2 0
Ar IA
Type RW RW RW RW RW
Reset 0 0 0 0 0
Overview: Configures GPIO PUPD control

R ED

31 GPIO31 GPIO31_PUPD PUPD for GPIO31
0: Disable
FO M
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable


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1: Enable
US IAL
0: Disable
EO
1: Enable
0: Disable
1: Enable
hk T
0: Disable
m. EN
1: Enable
0: Disable
1: Enable
17 GPIO17
.co ID GPIO17_PUPD
0:
1: Enable
PUPD for GPIO17
Disable
sac NF
0: Disable
1: Enable
0: Disable
1: Enable
O

0: Disable
1: Enable
u@ C

0: Disable
1: Enable
.Li K

0: Disable
1: Enable
no TE

0: Disable
1: Enable
Ar IA
0: Disable
1: Enable
R ED
GPIO_PUPD0_S
A0020A04 GPIO PUPD Control 00000000
ET
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO M
Name 1 9 8 7 6 1 0 9 8 7 6
Reset 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5 4 3 2 0
Type WO WO WO WO WO
Reset 0 0 0 0 0


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Overview: For bitwise access of GPIO_PUPD0
US IAL
31 GPIO31 GPIO31_PUPD Bitwise SET operation of GPIO31 PUPD
EO
0: Keep
1: SET bits
0: Keep
hk T
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
1: SET bits
26 GPIO26
.co ID GPIO26_PUPD Bitwise SET operation of GPIO26 PUPD
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
0: Keep
O
1: SET bits
u@ C
0: Keep
1: SET bits
0: Keep
.Li K
1: SET bits
no TE
0: Keep
1: SET bits
0: Keep
1: SET bits
Ar IA

0: Keep
1: SET bits
R ED

0: Keep
1: SET bits
0: Keep
FO M
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits


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GPIO_PUPD0_C
US IAL
LR
EO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name 1 9 8 7 6 1 0 9 8 7 6
Reset 0 0 0 0 0 0 0 0 0 0 0
hk T
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name 5 4 3 2 0
m. EN
Type WO WO WO WO WO
Reset 0 0 0 0 0
31 GPIO31
.co ID
GPIO31_PUPD
Description
Bitwise CLR operation of GPIO31 PUPD
0: Keep
sac NF
1: CLR bits
29 GPIO29 GPIO29_PUPD Bitwise CLR operation of GPIO29 PUPD
0: Keep
1: CLR bits
O

0: Keep
1: CLR bits
u@ C

0: Keep
1: CLR bits
.Li K

0: Keep
1: CLR bits
no TE

0: Keep
1: CLR bits
Ar IA
0: Keep
1: CLR bits
0: Keep
R ED
1: CLR bits
0: Keep
1: CLR bits
FO M
0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


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US IAL
0: Keep
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
0: Keep
1: CLR bits
m. EN
0: Keep
1: CLR bits
A0020A10
Bit 31
.co ID
GPIO_PUPD1
30 29 28
GPIO PUPD Control
27 26 25 24 23 22 21 20 19 18
0007A7FE
17 16
sac NF
Name 1 0 9 8
Type RW RW RW RW
Reset 0 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3
O
7 6 5 2 1 0 9 8 7 6 5 4 3 2
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 1 0 1 1 1 1 1 1 1 1 1 1 1 0
u@ C
Overview: Configures GPIO PUPD control

.Li K

no TE
0: Disable
1: Enable
0: Disable
1: Enable
Ar IA

0: Disable
1: Enable
R ED

0: Disable
1: Enable
0: Disable
FO M
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable


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1: Enable
US IAL
0: Disable
EO
1: Enable
0: Disable
1: Enable
hk T
0: Disable
m. EN
1: Enable
0: Disable
1: Enable
4 GPIO36
.co ID GPIO36_PUPD
0:
1: Enable
PUPD for GPIO36
Disable
sac NF
0: Disable
1: Enable
0: Disable
1: Enable
O

0: Disable
1: Enable
u@ C

0: Disable
1: Enable
.Li K

0: Disable
1: Enable
no TE
GPIO_PUPD1_S
Ar IA
ET
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name 1 0 9 8
R ED
Type WO WO WO WO
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
7 6 5 2 1 0 9 8 7 6 5 4 3 2
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO
FO M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0: Keep
1: SET bits


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US IAL
0: Keep
1: SET bits
EO
0: Keep
1: SET bits
hk T
0: Keep
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
13 GPIO45.co ID GPIO45_PUPD
1: SET bits
Bitwise SET operation of GPIO45 PUPD
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
O
0: Keep
1: SET bits
u@ C
0: Keep
1: SET bits
.Li K
0: Keep
1: SET bits
no TE

0: Keep
1: SET bits
0: Keep
Ar IA
1: SET bits
0: Keep
1: SET bits
R ED

0: Keep
1: SET bits
FO M
0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits


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GPIO_PUPD1_C
US IAL
LR
EO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name 1 0 9 8
Type WO WO WO WO
Reset 0 0 0 0
hk T
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3
Name 7 6 5 2 1 0 9 8 7 6 5 4 3 2
m. EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19 GPIO51
.co ID
GPIO51_PUPD
Description
0: Keep
sac NF
1: CLR bits
0: Keep
1: CLR bits
O

0: Keep
1: CLR bits
u@ C

0: Keep
1: CLR bits
.Li K

0: Keep
1: CLR bits
no TE

0: Keep
1: CLR bits
Ar IA
0: Keep
1: CLR bits
0: Keep
R ED
1: CLR bits
0: Keep
1: CLR bits
FO M
0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


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US IAL
0: Keep
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
0: Keep
1: CLR bits
m. EN
0: Keep
1: CLR bits
0: Keep
0 GPIO32.co ID GPIO32_PUPD
1: CLR bits
0:
1: CLR bits
Keep
sac NF
GPIO_RESEN0_
A0020B00 GPIO R0 Control B83FF400
O
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
u@ C
Name 1 9 8 7 6 1 0 9 8 7 6
Reset 1 1 1 1 0 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.Li K

5 4 3 2 0
Type RW RW RW RW RW
no TE
Reset 1 1 1 1 1
Overview: Configures GPIO R0 control

Ar IA

31 GPIO31 GPIO31_R0 R0 for GPIO31
0: Disable
1: Enable
R ED

0: Disable
1: Enable
FO M
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable


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US IAL
0: Disable
1: Enable
EO
0: Disable
1: Enable
hk T
0: Disable
1: Enable
m. EN
0: Disable
1: Enable
0: Disable
16 GPIO16.co ID GPIO16_R0
1: Enable
R0 for GPIO16
0:
1: Enable
Disable
sac NF
0: Disable
1: Enable
O
0: Disable
1: Enable
u@ C
0: Disable
1: Enable
.Li K
0: Disable
1: Enable
no TE

0: Disable
1: Enable
Ar IA
GPIO_RESEN0_
A0020B04 GPIO R0 Control 00000000
0_SET
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ED
Name 1 9 8 7 6 1 0 9 8 7 6
Reset 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO M

5 4 3 2 0
Type WO WO WO WO WO
Reset 0 0 0 0 0
Overview: For bitwise access of GPIO_RESEN0_0


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31 GPIO31 GPIO31_R0 Bitwise SET operation of GPIO31 R0
US IAL
0: Keep
1: SET bits
EO
0: Keep
1: SET bits
hk T
0: Keep
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
1: SET bits
Bitwise SET operation of GPIO21 R0
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
O
0: Keep
1: SET bits
u@ C
0: Keep
1: SET bits
.Li K
0: Keep
1: SET bits
no TE

0: Keep
1: SET bits
0: Keep
Ar IA
1: SET bits
0: Keep
1: SET bits
R ED

0: Keep
1: SET bits
FO M
0: Keep
1: SET bits
0: Keep
1: SET bits
A0020B08 GPIO_RESEN0_ GPIO R0 Control 00000000


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0_CLR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US IAL
Name 1 9 8 7 6 1 0 9 8 7 6
EO
Reset 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5 4 3 2 0
Type WO WO WO WO WO
hk T
Reset 0 0 0 0 0
m. EN

31 GPIO31 GPIO31_R0 Bitwise CLR operation of GPIO31 R0
29 GPIO29
.co ID GPIO29_R0
0:
1: CLR bits
Bitwise CLR operation of GPIO29 R0
Keep
sac NF
0: Keep
1: CLR bits
0: Keep
1: CLR bits
O

0: Keep
1: CLR bits
u@ C

0: Keep
1: CLR bits
.Li K

0: Keep
1: CLR bits
no TE

0: Keep
1: CLR bits
Ar IA
0: Keep
1: CLR bits
0: Keep
R ED
1: CLR bits
0: Keep
1: CLR bits
FO M

0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


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US IAL
0: Keep
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
0: Keep
1: CLR bits
m. EN
GPIO_RESEN0_
A0020B10 GPIO R0 Control 0007A7FF
1
Bit
Name
Type
31
.co ID
30 29 28 27 26 25 24 23 22 21 20
RW
19
0
RW
18
9
RW
17
1 8
RW
16
sac NF
Reset 0 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
7 6 5 2 1 0 9 8 7 6 5 4 3 2
Reset 1 0 1 1 1 1 1 1 1 1 1 1 1 1
O

u@ C

.Li K
0: Disable
1: Enable
no TE

0: Disable
1: Enable
0: Disable
Ar IA
1: Enable
0: Disable
1: Enable
R ED

0: Disable
1: Enable
FO M
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable


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US IAL
0: Disable
1: Enable
EO
0: Disable
1: Enable
hk T
0: Disable
1: Enable
m. EN
0: Disable
1: Enable
0: Disable
1: Enable
R0 for GPIO36
0:
1: Enable
Disable
sac NF
0: Disable
1: Enable
O
0: Disable
1: Enable
u@ C
0: Disable
1: Enable
.Li K
0: Disable
1: Enable
no TE
GPIO_RESEN0_
1_SET
Ar IA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name 1 0 9 8
Type WO WO WO WO
R ED
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
7 6 5 2 1 0 9 8 7 6 5 4 3 2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO M

0: Keep
1: SET bits


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US IAL
0: Keep
1: SET bits
EO
0: Keep
1: SET bits
hk T
0: Keep
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
1: SET bits
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
O
0: Keep
1: SET bits
u@ C
0: Keep
1: SET bits
.Li K
0: Keep
1: SET bits
no TE

0: Keep
1: SET bits
0: Keep
Ar IA
1: SET bits
0: Keep
1: SET bits
R ED

0: Keep
1: SET bits
FO M
0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits


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GPIO_RESEN0_
US IAL
1_CLR
EO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name 1 0 9 8
Type WO WO WO WO
Reset 0 0 0 0
hk T
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name 7 6 5 2 1 0 9 8 7 6 5 4 3 2
m. EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19 GPIO51
.co ID
GPIO51_R0
Description
0: Keep
sac NF
1: CLR bits
0: Keep
1: CLR bits
O

0: Keep
1: CLR bits
u@ C

0: Keep
1: CLR bits
.Li K

0: Keep
1: CLR bits
no TE

0: Keep
1: CLR bits
Ar IA
0: Keep
1: CLR bits
0: Keep
R ED
1: CLR bits
0: Keep
1: CLR bits
FO M
0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


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US IAL
0: Keep
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
0: Keep
1: CLR bits
m. EN
0: Keep
1: CLR bits
0: Keep
1: CLR bits
0:
1: CLR bits
Keep
sac NF
GPIO_RESEN1_
O
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
u@ C
Name 1 9 8 7 6 1 0 9 8 7 6
Reset 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.Li K

5 4 3 2 0
Type RW RW RW RW RW
no TE
Reset 0 0 0 0 0

Ar IA

0: Disable
1: Enable
R ED

0: Disable
1: Enable
FO M
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable


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US IAL
0: Disable
1: Enable
EO
0: Disable
1: Enable
hk T
0: Disable
1: Enable
m. EN
0: Disable
1: Enable
0: Disable
1: Enable
R1 for GPIO16
0:
1: Enable
Disable
sac NF
0: Disable
1: Enable
O
0: Disable
1: Enable
u@ C
0: Disable
1: Enable
.Li K
0: Disable
1: Enable
no TE

0: Disable
1: Enable
Ar IA
GPIO_RESEN1_
0_SET
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ED
Name 1 9 8 7 6 1 0 9 8 7 6
Reset 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO M

5 4 3 2 0
Type WO WO WO WO WO
Reset 0 0 0 0 0


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US IAL
0: Keep
1: SET bits
EO
0: Keep
1: SET bits
hk T
0: Keep
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
1: SET bits
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
O
0: Keep
1: SET bits
u@ C
0: Keep
1: SET bits
.Li K
0: Keep
1: SET bits
no TE

0: Keep
1: SET bits
0: Keep
Ar IA
1: SET bits
0: Keep
1: SET bits
R ED

0: Keep
1: SET bits
FO M
0: Keep
1: SET bits
0: Keep
1: SET bits
A0020B28 GPIO_RESEN1_ GPIO R1 Control 00000000


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0_CLR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US IAL
Name 1 9 8 7 6 1 0 9 8 7 6
EO
Reset 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5 4 3 2 0
Type WO WO WO WO WO
hk T
Reset 0 0 0 0 0
m. EN

29 GPIO29
.co ID GPIO29_R1
0:
1: CLR bits
Keep
sac NF
0: Keep
1: CLR bits
0: Keep
1: CLR bits
O

0: Keep
1: CLR bits
u@ C

0: Keep
1: CLR bits
.Li K

0: Keep
1: CLR bits
no TE

0: Keep
1: CLR bits
Ar IA
0: Keep
1: CLR bits
0: Keep
R ED
1: CLR bits
0: Keep
1: CLR bits
FO M

0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


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US IAL
0: Keep
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
0: Keep
1: CLR bits
m. EN
GPIO_RESEN1_
1
Bit
Name
Type
31
.co ID
30 29 28 27 26 25 24 23 22 21 20
RW
19
0
RW
18
9
RW
17
1 8
RW
16
sac NF
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
7 6 5 2 1 0 9 8 7 6 5 4 3 2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
O

u@ C

.Li K
0: Disable
1: Enable
no TE

0: Disable
1: Enable
0: Disable
Ar IA
1: Enable
0: Disable
1: Enable
R ED

0: Disable
1: Enable
FO M
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable


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US IAL
0: Disable
1: Enable
EO
0: Disable
1: Enable
hk T
0: Disable
1: Enable
m. EN
0: Disable
1: Enable
0: Disable
1: Enable
R1 for GPIO36
0:
1: Enable
Disable
sac NF
0: Disable
1: Enable
O
0: Disable
1: Enable
u@ C
0: Disable
1: Enable
.Li K
0: Disable
1: Enable
no TE
GPIO_RESEN1_
1_SET
Ar IA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name 1 0 9 8
Type WO WO WO WO
R ED
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
7 6 5 2 1 0 9 8 7 6 5 4 3 2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO M

0: Keep
1: SET bits


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Y
NL
US IAL
0: Keep
1: SET bits
EO
0: Keep
1: SET bits
hk T
0: Keep
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
1: SET bits
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
O
0: Keep
1: SET bits
u@ C
0: Keep
1: SET bits
.Li K
0: Keep
1: SET bits
no TE

0: Keep
1: SET bits
0: Keep
Ar IA
1: SET bits
0: Keep
1: SET bits
R ED

0: Keep
1: SET bits
FO M
0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits


MT2503D
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GPIO_RESEN1_
US IAL
1_CLR
EO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name 1 0 9 8
Type WO WO WO WO
Reset 0 0 0 0
hk T
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name 7 6 5 2 1 0 9 8 7 6 5 4 3 2
m. EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19 GPIO51
.co ID
GPIO51_R1
Description
0: Keep
sac NF
1: CLR bits
0: Keep
1: CLR bits
O

0: Keep
1: CLR bits
u@ C

0: Keep
1: CLR bits
.Li K

0: Keep
1: CLR bits
no TE

0: Keep
1: CLR bits
Ar IA
0: Keep
1: CLR bits
0: Keep
R ED
1: CLR bits
0: Keep
1: CLR bits
FO M
0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


MT2503D
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US IAL
0: Keep
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
0: Keep
1: CLR bits
m. EN
0: Keep
1: CLR bits
0: Keep
0 .co ID
GPIO32 GPIO32_R1
1: CLR bits
0:
1: CLR bits
Keep
sac NF
KeyPad
KCOL0-4
O
PUPD R1 R0 WEAK PULL UP/DOWN STATE

0 0 0 Disable both resistors
u@ C
0 0 1 PU-36K ohms
0 1 0 PU-1200K ohms
.Li K
0 1 1 PU- 1200K//36K ohms

no TE
1 0 1 PD-36K ohms
1 1 0 PD-1200K ohms
1 1 1 PD- 1200K//36K ohms
Ar IA
KROW0-4
R ED
0 0 1 PU-36K ohms
0 1 0 PU-1K ohms
0 1 1 PU- 1K//36K ohms
FO M
1 0 1 PD-36K ohms
1 1 0 PD-1K ohms
1 1 1 PD- 1K//36K ohms
URXD:
CMPDN/CMCSD0/CMCSD1/CMMCLK
MCCK/MCCM0/MCDA0/MCDA1/MCDA2/MCDA3


MT2503D
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TESTMODE_D/LSCE_B/LSCK/LSDA/LSA0/LPTE
RESETB:
US IAL
EO
0 0 1 PU-47K ohms
0 1 0 PU-47K ohms
hk T
0 1 1 PU- 23.5K ohms
m. EN
1 0 1 PD-47K ohms
1 1 0 PD-47K ohms
1 1 1 PD- 23.5K ohms
A0020C00
.co ID
GPIO_MODE0 GPIO Mode Control 00000000
sac NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIO7 GPIO6 GPIO5 GPIO4
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
O

Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
u@ C
Overview: Configures GPIO aux. mode

.Li K

30:28 GPIO7 Aux. mode of GPIO_7
no TE
0: GPIO7 (IO)
1: EINT6 (I)
2: Reserved
3: BPI_BUS5 (O)
4: Reserved
5: Reserved
Ar IA
6: Reserved
7: Reserved
0: GPIO6 (IO)
R ED
1: EINT5 (I)
2: MCINS (I)
3: BPI_BUS4 (O)
4: Reserved
5: Reserved
FO M
6: Reserved
7: Reserved
0: GPIO5 (IO)
1: EINT4 (I)
2: Reserved
3: BPI_BUS3 (O)
4: Reserved
5: Reserved
6: Reserved


MT2503D
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7: Reserved
US IAL
0: GPIO4 (IO)
EO
1: EINT3 (I)
2: Reserved
3: Reserved
4: U1RTS (O)
5: Reserved
hk T
6: Reserved
7: Reserved
m. EN
0: GPIO3 (IO)
1: MCINS (I)
2: YM (AIO)
3: Reserved
.co ID 4:
5:
6:
7:
8:
PWM1
CMCSD1
EDICK
JTDO
BTJTDO
(O)
(I)
(O)
(O)
(O)
sac NF
9: FMJTDO (O)
0: GPIO2 (IO)
1: EINT2 (I)
2: YP (AIO)
O
3: GPSFSYNC (O)
4: PWM0 (O)
5: CMCSD0 (I)
u@ C
6: EDIWS (O)
7: JTRST_B (I)
8: BTJTRSTB (I)
9: FMJTRSTB (I)
.Li K

0: GPIO1 (IO)
no TE
1: EINT1 (I)
2: XM (AIO)
3: U3TXD (O)
4: U1CTS (I)
5: CMMCLK (O)
6: EDIDI (I)
Ar IA
7: JTMS (I)
8: BTJTMS (I)
9: FMJTMS (I)
R ED
0: GPIO0 (IO)
1: EINT0 (I)
2: XP (AIO)
3: U3RXD (I)
4: CMCSD2 (I)
FO M
5: CMCSK (I)
6: EDIDO (O)
7: JTDI (I)
8: BTJTDI (I)
9: FMJTDI (I)
A0020C04 GPIO_MODE0_ GPIO Mode Control 00000000


MT2503D
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SET
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US IAL
Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
hk T
Overview: For bitwise access of GPIO_MODE0
m. EN
30:28 GPIO7 Bitwise SET operation for Aux. mode of GPIO_7
0: Keep
26:24
.co ID GPIO6
1: SET bits
Bitwise SET operation for Aux. mode of GPIO_6
0:
1: SET bits
Keep
sac NF
0: Keep
1: SET bits
O
0: Keep
1: SET bits
u@ C
0: Keep
1: SET bits
.Li K
0: Keep
1: SET bits
no TE
0: Keep
1: SET bits
0: Keep
1: SET bits
Ar IA
R ED
GPIO_MODE0_
A0020C08 GPIO Mode Control 00000000
CLR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type WO WO WO WO
FO M
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


MT2503D
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30:28 GPIO7 Bitwise CLR operation for Aux. mode of GPIO_7
US IAL
0: Keep
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
0: Keep
1: CLR bits
m. EN
0: Keep
1: CLR bits
0: Keep
11:8 .co ID GPIO2

1: CLR bits
Bitwise CLR operation for Aux. mode of GPIO_2
0:
1: CLR bits
Keep
sac NF
0: Keep
1: CLR bits
O
0: Keep
1: CLR bits
u@ C
A0020C10 GPIO_MODE1 GPIO Mode Control 00001100

.Li K
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW RW RW RW
no TE
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW RW RW RW
Reset 0 0 1 0 0 1 0 0 0 0 0 0
Ar IA

R ED

0: GPIO15 (IO)
1: KCOL1 (IO)
2: GPSFSYNC (O)
FO M
3: U1CTS (I)
4: FMJTCK (I)
5: JTCK (I)
6: BTJTCK (I)
7: Reserved
0: GPIO14 (IO)
1: KCOL2 (IO)
2: EINT12 (I)
3: U1RTS (I)


MT2503D
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4: Reserved
US IAL
5: Reserved
6: Reserved
7: Reserved
EO
0: GPIO13 (IO)
1: KCOL3 (IO)
2: EINT11 (I)
hk T
3: PWM0 (O)
4: FMJTMS (I)
m. EN
5: JTMS (I)
6: BTJTMS (I)
7: Reserved
0: GPIO12 (IO)
.co ID 1:
2:
3:
4:
5:
KCOL4
U2RXD
EDIDI
FMJTDI
JTDI
(IO)
(I)
(I)
(I)
(I)
sac NF
6: BTJTDI (I)
7: Reserved
0: GPIO11 (IO)
1: U1TXD (O)
O
2: CMPDN (O)
3: EINT10 (I)
4: Reserved
u@ C
5: Reserved
6: Reserved
7: Reserved
.Li K

0: GPIO10 (IO)
1: U1RXD (I)
no TE
2: CMRST (O)
3: EINT9 (I)
4: MCINS (I)
5: Reserved
6: Reserved
7: Reserved
Ar IA

0: GPIO9 (IO)
1: EINT8 (I)
R ED
2: SDA (IO)
3: Reserved
4: Reserved
5: Reserved
6: Reserved
7: Reserved
FO M

0: GPIO8 (IO)
1: EINT7 (I)
2: SCL (IO)
3: Reserved
4: Reserved
5: Reserved
6: Reserved
7: Reserved


MT2503D
Confidential A
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US IAL
GPIO_MODE1_
SET
EO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
hk T
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. EN
Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
30:28 .co ID
GPIO15
Description
Bitwise SET operation for Aux. mode of KCOL1
0: Keep
sac NF
1: SET bits
26:24 GPIO14 Bitwise SET operation for Aux. mode of KCOL2
0: Keep
1: SET bits
O
0: Keep
1: SET bits
u@ C

0: Keep
1: SET bits
.Li K
14:12 GPIO11 Bitwise SET operation for Aux. mode of UTXD1

0: Keep
1: SET bits
no TE
10:8 GPIO10 Bitwise SET operation for Aux. mode of URXD1

0: Keep
1: SET bits
Ar IA
0: Keep
1: SET bits
0: Keep
R ED
1: SET bits
GPIO_MODE1_
FO M
CLR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0


MT2503D
Confidential A
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US IAL
EO
30:28 GPIO15 Bitwise CLR operation for Aux. mode of KCOL1
0: Keep
1: CLR bits
hk T
0: Keep
1: CLR bits
m. EN
0: Keep
1: CLR bits
14:12 .co ID GPIO11

0:
1: CLR bits
Bitwise CLR operation for Aux. mode of UTXD1
0:
Keep
Keep
sac NF
1: CLR bits
10:8 GPIO10 Bitwise CLR operation for Aux. mode of URXD1
0: Keep
1: CLR bits
O

0: Keep
1: CLR bits
u@ C

0: Keep
1: CLR bits
.Li K
no TE

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW RW RW RW
Reset 0 0 1 0 0 1 0 0 0 0 0 0
Ar IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
R ED

FO M

0: GPIO23 (IO)
1: BPI_BUS1 (O)
2: Reserved
3: Reserved
4: Reserved
5: Reserved
6: Reserved
7: Reserved


MT2503D
Confidential A
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US IAL
0: GPIO22 (IO)
1: BPI_BUS2 (O)
EO
2: Reserved
3: Reserved
4: Reserved
5: Reserved
6: Reserved
hk T
7: Reserved
m. EN
0: GPIO21 (IO)
1: KROW0 (IO)
2: Reserved
3: Reserved
4: Reserved
5: MCINS (I)
18:16
.co ID GPIO20
6:
7: Reserved
Aux. mode of GPIO_20
BTDBGIN (I)
sac NF
0: GPIO20 (IO)
1: KROW1 (IO)
2: EINT14 (I)
3: EDIDO (O)
4: BTPRI (IO)
5: JTRCK (O)
O
6: BTDBGACKN (O)
7: Reserved
u@ C
0: GPIO19 (IO)
1: KROW2 (IO)
2: PWM1 (O)
.Li K
3: EDIWS (O)
4: FMJTDO (O)
5: JTDO (O)
no TE
6: BTJTDO (O)
7: Reserved
0: GPIO18 (IO)
1: KROW3 (IO)
Ar IA
2: EINT13 (I)
3: CLKO0 (O)
4: FMJTRSTB (I)
5: JTRST_B (I)
6: BTJTRSTB (I)
R ED
7: Reserved
0: GPIO17 (IO)
1: KROW4 (IO)
2: U2TXD (O)
FO M
3: EDICK (O)
4: Reserved
5: Reserved
6: Reserved
7: Reserved
0: GPIO16 (IO)
1: KCOL0 (IO)
2: Reserved


MT2503D
Confidential A
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3: Reserved
US IAL
4: Reserved
5: Reserved
6: Reserved
EO
7: Reserved
hk T
GPIO_MODE2_
SET
m. EN
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset .co ID
0
GPIO19
WO
0 0 0
GPIO18
WO
0 0 0
GPIO17
WO
0 0 0
GPIO16
WO
0 0
sac NF

30:28 GPIO23 Bitwise SET operation for Aux. mode of BPI_BUS1
O
0: Keep
1: SET bits
u@ C

0: Keep
1: SET bits
22:20 GPIO21 Bitwise SET operation for Aux. mode of KROW0
.Li K
0: Keep
1: SET bits
no TE

0: Keep
1: SET bits
0: Keep
Ar IA
1: SET bits
0: Keep
1: SET bits
R ED

0: Keep
1: SET bits
FO M
0: Keep
1: SET bits
GPIO_MODE2_
CLR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


MT2503D
Confidential A
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Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US IAL
Type WO WO WO WO
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
hk T
30:28 GPIO23 Bitwise CLR operation for Aux. mode of BPI_BUS1
m. EN
0: Keep
1: CLR bits
0: Keep
22:20
.co ID GPIO21
1: CLR bits
Bitwise CLR operation for Aux. mode of KROW0
0:
1: CLR bits
Keep
sac NF
18:16 GPIO20 Bitwise CLR operation for Aux. mode of KROW1
0: Keep
1: CLR bits
O
0: Keep
1: CLR bits
u@ C
0: Keep
1: CLR bits
.Li K
0: Keep
1: CLR bits
no TE
0: Keep
1: CLR bits
Ar IA

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ED
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1
FO M

0: GPIO31 (IO)
1: MCCK (O)
2: Reserved


MT2503D
Confidential A
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3: Reserved
US IAL
4: U2RXD (I)
5: Reserved
6: Reserved
EO
7: Reserved
0: GPIO30 (IO)
1: CMCSK (I)
hk T
2: LPTE (I)
3: CMCSD2 (I)
m. EN
4: EINT16 (I)
5: Reserved
6: JTRCK (O)
7: Reserved
.co ID 0:
1:
2:
3:
4:
GPIO29
CMMCLK
LSA0DA1
DAISYNC
SPIMISO
(IO)
(O)
(O)
(O)
(IO)
sac NF
5: FMJTDO (O)
6: JTDO (O)
7: Reserved
8: MC2DA0 (IO)
O
0: GPIO28 (IO)
1: CMCSD1 (I)
2: LSDA1 (IO)
u@ C
3: DAIPCMOUT (O)
4: SPIMOSI (IO)
5: FMJTRSTB (I)
6: JTRST_B (I)
.Li K
7: Reserved
8: MC2CK (O)
no TE

0: GPIO27 (IO)
1: CMCSD0 (I)
2: LSCE_B1 (O)
3: DAIPCMIN (I)
4: SPISCK (IO)
Ar IA
5: FMJTCK (I)
6: JTCK (I)
7: Reserved
8: MC2CM0 (O)
R ED

0: GPIO26 (IO)
1: CMPDN (O)
2: LSCK1 (O)
3: DAICLK (O)
FO M
4: SPICS (IO)
5: FMJTMS (I)
6: JTMS (I)
7: Reserved)
0: GPIO25 (IO)
1: CMRST (O)
2: TESTMODE_D (O)
3: CLKO1 (O)
4: EINT15 (I)


MT2503D
Confidential A
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5: FMJTDI (I)
US IAL
6: JTDI (I)
7: Reserved
EO
0: GPIO24 (IO)
1: BPI_BUS0 (O)
2: Reserved
3: Reserved
hk T
4: Reserved
5: Reserved
m. EN
6: Reserved
7: Reserved
A0020C34
Bit
Name
31
.co ID
GPIO_MODE3_
SET
30
GPIO Mode Control
29
GPIO31
28 27 26 25
GPIO30
24 23 22
GPIO29
21 20 19 18
GPIO28
00000000
17 16
sac NF
Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type WO WO WO WO
O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

u@ C

.Li K
30:28 GPIO31 Bitwise SET operation for Aux. mode of MCCK

0: Keep
1: SET bits
no TE
26:24 GPIO30 Bitwise SET operation for Aux. mode of CMCSK

0: Keep
1: SET bits
23:20 GPIO29 Bitwise SET operation for Aux. mode of CMMCLK
Ar IA
0: Keep
1: SET bits
19:16 GPIO28 Bitwise SET operation for Aux. mode of CMCSD1
0: Keep
R ED
1: SET bits
15:12 GPIO27 Bitwise SET operation for Aux. mode of CMCSD0
0: Keep
1: SET bits
10:8 GPIO26 Bitwise SET operation for Aux. mode of CMPDN
FO M
0: Keep
1: SET bits
6:4 GPIO25 Bitwise SET operation for Aux. mode of CMRST
0: Keep
1: SET bits
0: Keep
1: SET bits


MT2503D
Confidential A
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US IAL
GPIO_MODE3_
CLR
EO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
hk T
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. EN
Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
30:28 .co ID
GPIO31
Description
Bitwise CLR operation for Aux. mode of MCCK
0: Keep
sac NF
1: CLR bits
26:24 GPIO30 Bitwise CLR operation for Aux. mode of CMCSK
0: Keep
1: CLR bits
23:20 GPIO29 Bitwise CLR operation for Aux. mode of CMMCLK
O
0: Keep
1: CLR bits
u@ C
19:16 GPIO28 Bitwise CLR operation for Aux. mode of CMCSD1

0: Keep
1: CLR bits
.Li K
15:12 GPIO27 Bitwise CLR operation for Aux. mode of CMCSD0

0: Keep
1: CLR bits
no TE
10:8 GPIO26 Bitwise CLR operation for Aux. mode of CMPDN

0: Keep
1: CLR bits
6:4 GPIO25 Bitwise CLR operation for Aux. mode of CMRST
Ar IA
0: Keep
1: CLR bits
0: Keep
R ED
1: CLR bits

FO M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW RW RW RW
Reset 0 0 1 0 0 1 0 0 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0


MT2503D
Confidential A
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US IAL
EO
0: GPIO39 (IO)
1: SIM1_SCLK (IO)
2: Reserved
3: Reserved
hk T
4: Reserved
5: Reserved
6: Reserved
m. EN
7: Reserved
0: GPIO38 (IO)
1: SIM1_SRST (IO)
2: Reserved
.co ID 3:
4:
5:
6:
Reserved
Reserved
Reserved
Reserved
sac NF
7: Reserved
0: GPIO37 (IO)
1: SIM1_SIO (IO)
2: Reserved
O
3: Reserved
4: Reserved
5: Reserved
u@ C
6: Reserved
7: Reserved
0: GPIO36 (IO)
.Li K
1: MCDA3 (IO)
2: EINT19 (I)
3: CLKO2 (O)
no TE
4: DAIPCMOUT (O)
5: Reserved
6: Reserved
7: Reserved
Ar IA
0: GPIO35 (IO)
1: MCDA2 (IO)
2: EINT18 (I)
3: Reserved
R ED
4: DAICLK (O)
5: Reserved
6: Reserved
7: Reserved
FO M
0: GPIO34 (IO)
1: MCDA1 (IO)
2: EINT17 (I)
3: Reserved
4: DAIPCMIN (I)
5: Reserved
6: Reserved
7: Reserved
0: GPIO33 (IO)


MT2503D
Confidential A
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1: MCDA0 (IO)
US IAL
2: Reserved
3: Reserved
4: DAISYNC (O)
EO
5: Reserved
6: Reserved
7: Reserved
hk T
0: GPIO32 (IO)
1: MCCM0 (O)
m. EN
2: Reserved
3: Reserved
4: U2TXD (O)
5: Reserved
6: Reserved
7: Reserved
.co ID
GPIO_MODE4_
sac NF
SET
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type WO WO WO WO
O
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
u@ C
Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0

.Li K

no TE
30:28 GPIO39 Bitwise SET operation for Aux. mode of SIM1_SCLK

0: Keep
1: SET bits
26:24 GPIO38 Bitwise SET operation for Aux. mode of SIM1_SRST
Ar IA
0: Keep
1: SET bits
22:20 GPIO37 Bitwise SET operation for Aux. mode of SIM1_SIO
0: Keep
R ED
1: SET bits
18:16 GPIO36 Bitwise SET operation for Aux. mode of MCDA3
0: Keep
1: SET bits
FO M
0: Keep
1: SET bits
0: Keep
1: SET bits
0: Keep
1: SET bits


MT2503D
Confidential A
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2:0 GPIO32 Bitwise SET operation for Aux. mode of MCCM0
US IAL
0: Keep
1: SET bits
EO
GPIO_MODE4_
hk T
CLR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
m. EN
Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type WO WO WO WO
Reset
.co ID
0 0 0

0 0 0 0 0 0 0 0 0
sac NF
30:28 GPIO39 Bitwise CLR operation for Aux. mode of SIM1_SCLK
0: Keep
O
1: CLR bits
26:24 GPIO38 Bitwise CLR operation for Aux. mode of SIM1_SRST
0: Keep
u@ C
1: CLR bits
22:20 GPIO37 Bitwise CLR operation for Aux. mode of SIM1_SIO
0: Keep
.Li K
1: CLR bits
18:16 GPIO36 Bitwise CLR operation for Aux. mode of MCDA3
0: Keep
no TE
1: CLR bits
0: Keep
1: CLR bits
Ar IA

0: Keep
1: CLR bits
R ED
0: Keep
1: CLR bits
2:0 GPIO32 Bitwise CLR operation for Aux. mode of MCCM0
0: Keep
1: CLR bits
FO M

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW RW RW RW
Reset 0 0 0 0 0 1 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


MT2503D
Confidential A
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NL
Type RW RW RW RW
Reset 0 0 0 0 0 1 0 0 1 0 0 1
US IAL
EO
hk T
0: GPIO47 (IO)
1: LSCK0 (O)
m. EN
2: Reserved
3: CMPDN (O)
4: Reserved
5: Reserved
6: Reserved
7: Reserved
26:24
.co ID GPIO46 Aux. mode of GPIO_46
0:
1:
2:
GPIO46
LSCE_B0
EINT20
(IO)
(O)
(I)
sac NF
3: CMCSD0 (I)
4: CLKO4 (O)
5: Reserved
6: Reserved
7: Reserved
O

0: GPIO45 (IO)
1: TESTMODE_D (O)
u@ C
2: Reserved
3: CMRST (O)
4: Reserved
5: Reserved
.Li K
6: Reserved
7: Reserved
no TE

0: GPIO44 (IO)
1: SDA (IO)
2: Reserved
3: Reserved
4: Reserved
Ar IA
5: Reserved
6: Reserved
7: Reserved
R ED
0: GPIO43 (IO)
1: SCL (IO)
2: Reserved
3: Reserved
4: Reserved
FO M
5: Reserved
6: Reserved
7: Reserved
0: GPIO42 (IO)
1: SIM2_SCLK (IO)
2: LSCE1_B1 (O)
3: Reserved
4: SDA18 (IO)
5: Reserved


MT2503D
Confidential A
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NL
6: Reserved
US IAL
7: Reserved
EO
0: GPIO41 (IO)
1: SIM2_SRST (IO)
2: CLKO3 (O)
3: U2CTS (I)
4: SCL18 (IO)
hk T
5: Reserved
6: Reserved
m. EN
7: Reserved
0: GPIO40 (IO)
1: SIM2_SIO (IO)
2: Reserved
.co ID 3:
4:
5:
6:
7: Reserved
U2RTS (O)
Reserved
Reserved
Reserved
sac NF
GPIO_MODE5_
O
SET
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
u@ C
Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.Li K
Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
no TE

Ar IA
30:28 GPIO47 Bitwise SET operation for Aux. mode of LSCK

0: Keep
1: SET bits
26:24 GPIO46 Bitwise SET operation for Aux. mode of LSCE_B
R ED
0: Keep
1: SET bits
22:20 GPIO45 Bitwise SET operation for Aux. mode of TESTMODE_D
0: Keep
1: SET bits
FO M
18:16 GPIO44 Bitwise SET operation for Aux. mode of SDA28

0: Keep
1: SET bits
14:12 GPIO43 Bitwise SET operation for Aux. mode of SCL28
0: Keep
1: SET bits
10:8 GPIO42 Bitwise SET operation for Aux. mode of SIM2_SCLK
0: Keep


MT2503D
Confidential A
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NL
1: SET bits
US IAL
6:4 GPIO41 Bitwise SET operation for Aux. mode of SIM2_SRST
0: Keep
EO
1: SET bits
2:0 GPIO40 Bitwise SET operation for Aux. mode of SIM2_SIO
0: Keep
1: SET bits
hk T
m. EN
GPIO_MODE5_
CLR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type
Reset
Bit
Name
15 .co ID
0
14
WO
0
13
GPIO43
0
12 11
0
10
WO
0
9
GPIO42
0
8 7
0
6
WO
0
5
GPIO41
0
4 3
0
2
WO
0
1
GPIO40
0
0
sac NF
Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0

O

30:28 GPIO47 Bitwise CLR operation for Aux. mode of LSCK
u@ C
0: Keep
1: CLR bits
26:24 GPIO46 Bitwise CLR operation for Aux. mode of LSCE_B
.Li K
0: Keep
1: CLR bits
22:20 GPIO45 Bitwise CLR operation for Aux. mode of TESTMODE_D
no TE
0: Keep
1: CLR bits
18:16 GPIO44 Bitwise CLR operation for Aux. mode of SDA28
0: Keep
Ar IA
1: CLR bits
14:12 GPIO43 Bitwise CLR operation for Aux. mode of SCL28
0: Keep
1: CLR bits
R ED
10:8 GPIO42 Bitwise CLR operation for Aux. mode of SIM2_SCLK

0: Keep
1: CLR bits
6:4 GPIO41 Bitwise CLR operation for Aux. mode of SIM2_SRST
FO M
0: Keep
1: CLR bits
2:0 GPIO40 Bitwise CLR operation for Aux. mode of SIM2_SIO
0: Keep
1: CLR bits


MT2503D
Confidential A
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NL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW RW RW RW
US IAL
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
Type RW RW RW RW
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0
hk T
m. EN
0: AGPIO55 (AGIO)
1: Reserved
2: Reserved
.co ID 3:
4:
5:
6:
Reserved
Reserved
Reserved
Reserved
sac NF
7: Reserved
0: AGPIO54 (AGIO)
1: Reserved
2: Reserved
O
3: Reserved
4: Reserved
5: Reserved
u@ C
6: Reserved
7: Reserved
0: AGPIO53 (AGI)
.Li K
1: SRCLKENAI (I)
2: EINT24 (I)
3: Reserved
no TE
4: Reserved
5: Reserved
6: Reserved
7: Reserved
Ar IA
0: AGPI52 (AGI)
1: Reserved
2: EINT23 (I)
3: Reserved
R ED
4: Reserved
5: Reserved
6: Reserved
7: Reserved
FO M
0: GPIO51 (IO)
1: RESETB (IO)
2: Reserved
3: Reserved
4: Reserved
5: Reserved
6: Reserved
7: Reserved
0: GPIO50 (IO)


MT2503D
Confidential A
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NL
1: LPTE (I)
US IAL
2: EINT22 (I)
3: CMCSK (I)
4: CMCSD2 (I)
EO
5: Reserved
6: MCINS (I)
7: Reserved
8: Reserved
hk T
9: CLKO5 (O)
m. EN
0: GPIO49 (IO)
1: LSA0DA0 (O)
2: LSCE1_B0 (O)
3: CMMCLK (O)
4: Reserved
5: Reserved
2:0
.co ID GPIO48
6:
7: Reserved
Aux. mode of GPIO_48
0: GPIO48
Reserved
(IO)
sac NF
1: LSDA0 (IO)
2: EINT21 (I)
3: CMCSD1 (I)
4: WIFITOBT (I)
5: Reserved
O
6: Reserved
7: Reserved
u@ C
GPIO_MODE6_
.Li K
SET
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
no TE
Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type WO WO WO WO
Ar IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

R ED

30:28 GPIO55 Bitwise SET operation for Aux. mode of SRCLKENAI
0: Keep
1: SET bits
FO M
26:24 GPIO54 Bitwise SET operation for Aux. mode of EINT

0: Keep
1: SET bits
22:20 GPIO53 Bitwise SET operation for Aux. mode of TP4
0: Keep
1: SET bits
18:16 GPIO52 Bitwise SET operation for Aux. mode of TP3
0: Keep


MT2503D
Confidential A
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1: SET bits
US IAL
14:12 GPIO51 Bitwise SET operation for Aux. mode of RESETB
0: Keep
EO
1: SET bits
11:8 GPIO50 Bitwise SET operation for Aux. mode of LPTE
0: Keep
1: SET bits
hk T
6:4 GPIO49 Bitwise SET operation for Aux. mode of LSA0
0: Keep
m. EN
1: SET bits
2:0 GPIO48 Bitwise SET operation for Aux. mode of LSDA
0: Keep
1: SET bits
A0020C68
.co ID
GPIO_MODE6_
CLR
GPIO Mode Control 00000000
sac NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
O

Type WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
u@ C

.Li K

30:28 GPIO55 Bitwise CLR operation for Aux. mode of SRCLKENAI
no TE
0: Keep
1: CLR bits
26:24 GPIO54 Bitwise CLR operation for Aux. mode of EINT
0: Keep
Ar IA
1: CLR bits
22:20 GPIO53 Bitwise CLR operation for Aux. mode of TP4
0: Keep
1: CLR bits
R ED
18:16 GPIO52 Bitwise CLR operation for Aux. mode of TP3

0: Keep
1: CLR bits
14:12 GPIO51 Bitwise CLR operation for Aux. mode of RECLRB
FO M
0: Keep
1: CLR bits
11:8 GPIO50 Bitwise CLR operation for Aux. mode of LPTE
0: Keep
1: CLR bits
6:4 GPIO49 Bitwise CLR operation for Aux. mode of LSA0
0: Keep
1: CLR bits
2:0 GPIO48 Bitwise CLR operation for Aux. mode of LSDA


MT2503D
Confidential A
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NL
0: Keep
US IAL
1: CLR bits
EO
A0020D10 GPIO_TDSEL GPIO TDSEL Control 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
hk T
Name GPIO50
Type RW
Reset 0 0
m. EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIO46 GPIO42 GPIO41 GPIO36 GPIO25 GPIO18 GPIO9 GPIO8
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.co ID
Overview: GPIO TX duty control register

sac NF
17:16 GPIO50 GPIO50_TDSEL GPIO50 Tx duty control
O

u@ C

.Li K
no TE
GPIO_TDSEL_S
A0020D14 GPIO TDSEL Control 00000000
ET
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIO50
Ar IA
Type WO
Reset 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Overview: For bitwise access of GPIO_TDSEL

FO M

17:16 GPIO50 GPIO50_TDSEL Bitwise SET operation of GPIO50_TDSEL Tx duty control
0: Keep
1: SET bits
0: Keep
1: SET bits


MT2503D
Confidential A
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NL
0: Keep
US IAL
1: SET bits
EO
0: Keep
1: SET bits
0: Keep
hk T
1: SET bits
m. EN
0: Keep
1: SET bits
0: Keep
1: SET bits
3:2
1:0
GPIO9
GPIO8
.co ID GPIO9_TDSEL
GPIO8_TDSEL
Bitwise SET operation of GPIO9_TDSEL Tx duty control
0:
1: SET bits
Bitwise SET operation of GPIO8_TDSEL Tx duty control
Keep
sac NF
0: Keep
1: SET bits
O
GPIO_TDSEL_C
A0020D18 GPIO TDSEL Control 00000000
LR
u@ C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIO50
Type WO
.Li K
Reset 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
no TE
WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Overview: For bitwise access of GPIO_TDSEL

Ar IA

17:16 GPIO50 GPIO50_TDSEL Bitwise CLR operation of GPIO50_TDSEL Tx duty control
0: Keep
R ED
1: CLR bits
0: Keep
1: CLR bits
FO M
0: Keep
1: CLR bits
0: Keep
1: CLR bits
0: Keep
1: CLR bits


MT2503D
Confidential A
Y
NL
US IAL
0: Keep
1: CLR bits
EO
0: Keep
1: CLR bits
hk T
0: Keep
1: CLR bits
m. EN
0: Keep
1: CLR bits
A0020E00
Bit
Name
31
.co ID
CLK_OUT0
30 29 28
27 26 25 24 23 22 21 20 19 18
00000004
17 16
sac NF
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CLK_OUT0
Type RW
O
Reset 0 1 0 0
Overview: CLK OUT0 Setting

u@ C

.Li K
3:0 CLK_OUT0 CFG0 Selects clock output for CLKO_0

[1]: 26Mhz clock
[4]: 32Khz_clock
no TE
others: debug clock

Ar IA
A0020E10 CLK_OUT1 CLK Out Selection Control 00000004

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
R ED
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CLK_OUT1
Type RW
Reset 0 1 0 0
FO M
Overview: CLK OUT1 setting

[1]: 26Mhz clock
[4]: 32Khz_clock
others: debug clock


MT2503D
Confidential A
Y
NL
US IAL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
EO
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CLK_OUT2
hk T
Type RW
Reset 0 1 0 0
m. EN

.co ID [1]:
[4]:
others: debug clock
26Mhz clock
32Khz_clock
sac NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
O
Name
Type
Reset
u@ C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CLK_OUT3
Type RW
Reset 0 1 0 0
.Li K

no TE

[1]: 26Mhz clock
Ar IA
[4]: 32Khz_clock
others: debug clock
R ED

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
FO M
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CLK_OUT4
Type RW
Reset 0 1 0 0


MT2503D
Confidential A
Y
NL
US IAL
[1]: 26Mhz clock
[4]: 32Khz_clock
EO
others: debug clock
hk T
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
m. EN
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CLK_OUT5
Type RW
Reset
.co ID
0 1 0 0
sac NF
[1]: 26Mhz clock
[4]: 32Khz_clock
O
others: debug clock

u@ C
3.5 General-purpose Timer

.Li K
no TE
3.5.1 General Descriptions
Three general-purpose timers are provided. Two timers are 16 bits long and one timer is 32 bits long.
Ar IA
Each runs independently. GPT1 ~ 2 use 32k clock source to count, whereas GPT4 uses 26M clock
source. The 26M clock source can be gated when the system enters the sleep mode, and this will
cause GPT4 to stop counting, whereas 32k clock source is always toggling. GPT1 and GPT2 can
R ED
operate in one of the two modes: one-shot mode and auto-repeat mode. GPT4 are free running timer.
In the one-shot mode, when the timer counts down and reaches 0, it will be halted. In the auto-repeat
mode, when the timer reaches 0, it will simply be reset to counting down the initial value and
repeating the count-down to 0. This loop keeps repeating until the disabling signal is set to 1.
FO M
Regardless of the timer’s mode, if the countdown initial value (i.e. GPTIMER1_DAT for GPT1 or
GPTIMER_DAT2 for GPT2) is written when the timer is running, the new initial value will not take
effect until the next time the timer is restarted. In the auto-repeat mode, the new countdown start
value is used on the next countdown iteration. Therefore, before enabling the timer, the desired values
for GPTIMER_DAT and the GPTIMER_PRESCALER registers must first be set.
Note that GPTimer’s design is inherited form MT6260, GPT3 is removed for achieving lower cost.


MT2503D
Confidential A
Y
NL
For other timers, register addresses are the same with those of MT6260.
US IAL
EO
Module name: GPTimer base address: (+A00C0000h)
hk T
A00C0000 GPTIMER1_CON 32 GPT1 control register
m. EN
A00C0004 GPTIMER1_DAT 32 GPT1 time-out interval register
A00C000C GPTIMER2_DAT 32 GPT2 time-out Interval register
A00C0010 GPTIMER_STA 32 GPT status register
A00C0014
A00C0018
.co ID
GPTIMER1_PRESCALER
GPTIMER2_PRESCALER
32
32
GPT1 prescaler register
GPT2 prescaler register
sac NF
A00C002C GPTIMER4_DAT 32 GPT4 data register
O
A00C0000 GPTIMER1_CON GPT1 Control Register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
u@ C
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.Li K
Name EN MODE
Type RW RW
Reset 0 0
no TE

15 EN EN Controls GPT1 to start counting or to stop
0: Disable GPT1
Ar IA
1: Enable GPT1
14 MODE MODE Controls GPT1 to count repeatedly (in a loop) or just one-shot
0: One-shot mode is selected.
R ED
1: Auto-repeat mode is selected.
A00C0004 GPTIMER1_DAT GPT1 Time-out Interval Register 0000FFFF

FO M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CNT
Type RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


MT2503D
Confidential A
Y
NL
Initial counting value
US IAL
15:0 CNT CNT GPT1 counts down from GPTIMER1_DAT. When GPT1 counts down
to 0, a GPT1 interrupt will be generated.
EO
hk T
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
m. EN
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name EN MODE
Type RW RW
Reset 0 0
Bit(s)
15 EN
.co ID
Mnemonic Name
EN
Description
Controls GPT2 to start counting or to stop
sac NF
0: Disable GPT2
1: Enable GPT2
14 MODE MODE Controls GPT2 to count repeatedly (in a loop) or just one-shot
0: One-shot mode is selected.
O
1: Auto-repeat mode is selected.

u@ C
A00C000C GPTIMER2_DAT GPT2 Time-out Interval Register 0000FFFF

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
.Li K
Name
Type
Reset
no TE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CNT
Type RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Ar IA

Initial counting value
15:0 CNT CNT GPT2 counts down from GPTIMER2_DAT. When GPT2 counts down
R ED
to 0, a GPT2 interrupt will be generated.
A00C0010 GPTIMER_STA GPT Status Register 00000000

FO M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPT2 GPT1
Type RC RC
Reset 0 0


MT2503D
Confidential A
Y
NL
1 GPT2 GPT2 GP timer time-out status
US IAL
Each flag is set when the corresponding timer count-down is
completed. Can be cleared when the CPU reads the status register.
EO
0 GPT1 GPT1 GP timer time-out status
Each flag is set when the corresponding timer count-down is
completed. Can be cleared when the CPU reads the status register.
hk T
m. EN
GPTIMER1_PRE
A00C0014 GPT1 Prescaler Register 00000004
SCALER
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit
Name
Type
15
.co ID
14 13 12 11 10 9 8 7 6 5 4 3 2 1
PRESCALER
RW
0
sac NF
Reset 1 0 0

Controls the counting clock for GP timer 1
O
0: 16,384Hz
1: 8,192Hz
PRESCALE 2: 4,096Hz
u@ C
2:0 PRESCALER 3: 2,048Hz

R
4: 1,024Hz
5: 512Hz
6: 256Hz
.Li K
7: 128Hz
no TE
GPTIMER2_PRE
A00C0018 GPT2 Prescaler Register 00000004
SCALER
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Ar IA
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ED
Name PRESCALER
Type RW
Reset 1 0 0

FO M
Controls the counting clock for GP timer 2

0: 16,384Hz
1: 8,192Hz
PRESCALE 2: 4,096Hz
2:0 PRESCALER 3: 2,048Hz
R
4: 1,024Hz
5: 512Hz
6: 256Hz
7: 128Hz


MT2503D
Confidential A
Y
NL
US IAL
EO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
hk T
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name LOCK EN
m. EN
Type RW RW
Reset 0 0

1 LOCK
.co ID LOCK Controls GPT4 EN bit can be modified or not

If LOCK = 0, EN can be modified. If LOCK = 1, the EN value will be
fixed, and the LOCK bit will always be 1 and cannot be modified until
hardware reset.
sac NF
0: Unlock
1: Lock
0 EN EN Controls GPT4 to start counting or to stop
0: Disable GPT4
1: Enable GPT4
O
u@ C
A00C002C GPTIMER4_DAT GPT4 Data Register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CNT[31:16]
.Li K
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
no TE
Name CNT[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Ar IA

If EN = 1, GPT4 will be a free running timer. This register records the
GPT4 value. If EN = 0, this register will be cleared to 0. This register
31:0 CNT CNT
does not allow continuous read. It requires at least 1 26M clock cycle
R ED
between 2 APB reads.
3.5.3 Application Note

FO M
When the GPT is in running status, GPTIMER_DAT cannot be configured. To start GPT1 or GPT2,
SW should make sure the timer has finished counting for at least 3 cycles of the 32kHz clock.


MT2503D
Confidential A
Y
NL
3.6 MCU OSTIMER
US IAL
3.6.1 Overview
EO
Clock Control
hk T
Sleep
m. EN
Processor APB OS Timer
Manager
.co ID IRQ
Controller
Wakeup
Sources
sac NF
Figure 31. OS timer system view
The OS timer is a hardware timer which specifies the OS time frame duration and generates time-out
interrupts by programming the frame counter number. The OS timer has the pause mode. The user
O
can specify pause duration period before the pause mode, and the timer will resume from the pause
mode by the external wakeup sources or when the pause duration is timed out.
u@ C
3.6.2 Terminology
.Li K
Table 46. Abbreviations

no TE
Abbreviation
R/W Read/Write
RO Read only
Ar IA
WO Write only
W1C Write 1 to clear
R/W1C Read/Write 1 to clear
R ED
FRC Free running counter in the system

OST OS timer
FO M
3.6.3 Introduction to Wakeup Source

The OS timer only accepts level trigger wakeup source. The wakeup sources are all treated as
asynchronous input (will be changed) and will be synchronized by OST clock in OST wakeup source
controller.
The possible wakeup sources are listed in the table below.


MT2503D
Confidential A
Y
NL
Table 47. Wakeup sources
US IAL
No Wakeup source
EO
0 GPT
1 EINT
2 Timer trigger
hk T
3 KP
4 MSDC
m. EN
5 ANALOG
6 DSP
7 MSDC2
8 SPISLV
.co ID 9
10
11
Reserved
Reserved
DSP_ASYNC
sac NF
12 Reserved
13 Reserved
14 Reserved
O
15 Reserved
16 Reserved
u@ C
Table 48. Characteristics of wakeup sources

.Li K
No Wakeup source Edge/Level SW clear Clock domain

0 GPT Edge F32k_CK
no TE
1 EINT Edge/Level F32k_CK

2 Timer trigger Level F32k_CK
3 KP Edge
4 MSDC Level
Ar IA
5 ANALOG Edge/Level
6 DSP Level DSP_CK
7 MSDC2 Level
R ED
8 SPISLV Level
9 Reserved
10 Reserved
11 DSP_ASYNC Level DSP_CK
FO M
12 Reserved
13 Reserved
14 Reserved
15 Reserved
16 Reserved


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Processor
US IAL
EO
IRQ Controller
Wakeup_irq_b
irq_b
hk T
Wakeup Source
OST WAKEUP
m. EN
Wakeup_event_b CONTROL
Figure 32. Wakeup event and Irq_b integration diagram
.co ID
wakeup_irq_b may be asserted before wakeup_event_b is asserted from the wakeup source
peripheral to ensure the software will enter wakeup ISR after the pause command is set.
sac NF
Recommended software programming sequence:
1. I-BIT is set when a pause command is executed.
2. Set up IRQ mask registers to select IRQ wakeup sources
O
3. Pause criteria are met.

4. Set up pause command.
u@ C
5. Confirm the pause command is executed at OST, and check if the pause command is pending or
not.
6. Set up processor in request for interrupt state.
.Li K
7. The processor clock will be off if there is no interrupt.

8. Check if the pause request command is completed (after the processor clock is active or
no TE
resumes).
9. Clear I-BIT.
Ar IA

R ED
OS timer control register

0XA01F0000 OST_CON 32 Only updated when OST_CMD.OST_WR is set and
OST_STA.WR_RDY is high.
OS timer command
0XA01F0004 OST_CMD 32
Only valid when the write data BIT31 to BIT16 is 0x1153.
FO M
0XA01F0008 OST_STA 32 OS timer status

OS timer frame duration
Specifies OS timer frame duration by micron second
0XA01F000C OST_FRM 32 resolution. The maximum duration is 8ms and minimum
duration is 1ms. This register should be set before OS timer
is enabled. The hardware will set up OST_ISR[0] periodically
at frame duration period when the OS timer is enabled.
0XA01F0010 OST_FRM_F32K 32 OS timer frame duration by 32K clock


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Specifies OS timer frame duration with 30.5176 micron
US IAL
second (32kHz) resolution. The maximum duration is 8ms
and minimum duration is 1ms. This register should be set
before the OS timer is enabled.
EO
OST_FRAM_F32K*30.5176us should be less than
OST_FRM_NUM*OST_FRM*1us - 30.5176us.
Set up OST_FRM_NUM if the frame duration is shorter than
system settling time.
hk T
OS timer un-alignment frame number
Specifies OS timer un-alignment event frame number count.
m. EN
This register value is updated to OS timer only when
OST_CMD.OST_WR is set. The read value of this register
may not be the current OS time Un-alignment frame number.
The hardware will count down the OST_UFN counter at
0XA01F0014 OST_UFN 32 frame time-out and stop the count-down when the current
.co ID value is 0. When the OS timer is in the pause mode, this

counter is still active and wakes up the OS timer when
OST_UFN becomes 0 at frame time-out boundary.
The software should enable the OS timer pause mode when
sac NF
OST_UFN is larger than 1, or the pause command will be
ignored by the hardware.
OS timer alignment frame number
Specifies OS timer alignment event frame number count.
This register value is updated to the OS timer only when
O
OST_CMD.OST_WR is set. The read value of this register

may not be the current OS time alignment frame number.
The hardware will count down the OST_AFN counter at
u@ C
0XA01F0018 OST_AFN 32 frame time-out and stop the count-down when the current
value is 0. The hardware will set OST_ISR[1] when
OST_AFN is 1 or 0 at frame time-out, and the OS timer is in
normal mode. OST_AFN is current hardware AFN down
.Li K
counter value, and the software cannot read this register

directly. The software can only read the current frame
number through the OST_AFN_R register, and there is
no TE
synchronization latency from OST_AFN to OST_AFN_R.

OS timer alignment frame delay number count
Specifies the OS timer alignment event frame delay count
0XA01F001C OST_AFN_DLY 32 due to OS timer pause mode. The software has to use the
Ar IA
OST_CMD.OST_RD command to update this register value,

or the value may be out of date.
Current OS timer un-alignment frame number
0XA01F0020 OST_UFN_R 32 Specifies the OS timer current un-alignment frame number.
R ED
The software has to use the OST_CMD.OST_RD command

to update this register value, or the value may be out of date.
Current OS timer alignment frame number
0XA01F0024 OST_AFN_R 32 Specifies the OS timer current alignment frame number. The
software has to use the OST_CMD.OST_RD command to
FO M
update this register value, or the value may be out of date.

OS timer interrupt mask
0XA01F0030 OST_INT_MASK 32
Specifies the OS timer interrupt mask control.
OS timer interrupt status
Specifies the OS timer interrupt status. The software has to
0XA01F0040 OST_ISR 32 write 1 at the corresponding bit to clear the interrupt status
bit. OSR_ISR[2-0] are also cleared when the OSR_WR
command is executed and AFN, UFN are updated.


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OS timer event mask
US IAL
OST_EVENT_MAS
0XA01F0050 32 Specifies which wakeup event will be masked to wake up the
K
OS timer in the OS timer pause mode.
EO
OST_WAKEUP_ST
0XA01F0054 32 OS timer event wakeup status
A
OST_DBG_WAKE
0XA01F0060 32 OS timer debug wakeup
UP
hk T
m. EN
0XA01F0000 OS Timer Control Register OST_CON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit
Name
15 .co ID
14 13 12 11 10 9 8 7 6 5 4 3 2
OST_ UFN_
DBG DOWN
1
EN
0
sac NF
Type RW RW RW
Reset 0 1 0
Overview: This registers is only updated when OST_CMD.OST_WR is set and OST_STA.WR_RDY is high.
O

u@ C
2 OST_DBG Enables OST wakeup debugging function

0: Disable
1: Enable
.Li K
1 UFN_DOWN Enables OST_UFN count-down

0: Disable OST_UFN count-down
1: Enable OST_UFN count-down
no TE
0 EN Enables OS timer
0: OS timer is disabled. Then all internal timers are stopped.
1: OS Timer is enabled. The software has to ensure OST_AFN, OST_UFN,
OST_FRAM are configured before enabling the OS timer.
Ar IA
0XA01F0004 OS Timer Command OST_CMD

R ED
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name OST_KEY
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO M
OST_ OST_ OST_ PAUS

OST_ OST_
Name CON_ AFN_ UFN_ E_ST
WR RD
WR WR WR R
Type RW RW RW WO WO WO
Reset 0 0 0 0 0 0
Overview: The command is only valid when the write data BIT31 to BIT16 is 0x1153.


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31:16 OST_KEY
US IAL
15 OST_CON_WR Updates OST_CON when the OST_WR command is active.
14 OST_AFN_WR Updates OST_AFN when the OST_WR command is active.
EO
13 OST_UFN_WR Updates OST_UFN when the OST_WR command is active.
2 OST_WR Write 1 to this bit to update the bus clock domain OS timer configuration into
the OST SYSCLK domain
hk T
1 OST_RD Write 1 to this bit to update the current OS timer status to the bus clock
domain
m. EN
0 PAUSE_STR Write 1 to this bit to enable the OS timer pause function. The command will be
ignored if the current OST UFN is less than 2. The software has to ensure
OST_CMD.OST_WR is completed before the next software pause sequence.
0XA01F0008
Bit
Name
31
.co ID
30 29 28
OS Timer Status
27 26 25 24 23 22 21 20 19 18
OST_STA
17 16
sac NF
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_ AFN_
CMD_ READ
Name SLEE
O
DLY_ PAUSE_REQ
CPL Y
P OVER
Type RO RO RO RO RO
Reset
u@ C
0 0 0 0 1 0
.Li K
no TE
Ar IA
R ED
FO M


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US IAL
EO
hk T
m. EN
.co ID
sac NF
O
u@ C
.Li K
no TE
Figure 33. Pause command complete and pause request state

Ar IA

15 CPU_SLEEP The processor is in the sleep mode. (for debugging)
R ED
0: Active
1: Sleep
6 AFN_DLY_OVER AFN_DLY counter overflows. This bit is cleared when AFN is updated.
0: Does not overflow
FO M
1: Overflow
4:3 PAUSE_REQ An OS timer pause request is pending. A pause command will be
completed when the pause command is set.
1. Processor is in the sleep mode (processor clock is off), UFN ≥ 2 and no
wakeup sources
2. Any wakeup sources are sensed after the pause command is set.
3. UFN < 2
00: The last pause command request is not completed yet (CP15 is not enable


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and no wakeup source).
US IAL
01: The last pause command request is completed with OST pause mode
being active.
EO
10: The last pause command request is completed with wakeup sources.
11: The last pause command request is completed with UFN < 2.
1 CMD_CPL OST command is completed. It takes several clocks from OST_CMD
being updated to command being active.
hk T
0: OST command is not completed.
1: OST command is completed.
m. EN
0 READY OS timer status
0: OST is in pause mode.
1: OST is in normal mode.
0XA01F000C
Bit 31
.co ID
30 29 28
OS Timer Frame Duration
27 26 25 24 23 22 21 20 19 18
OST_FRM
17 16
sac NF
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name OST_FRM
O
Type RW
Reset 1 0 0 0 0 0 1 0 0 1 0 0 1
u@ C
Overview: This register specifies the OS timer frame duration by micron second resolution. The maximum
duration is 8ms and minimum duration is 1ms. This register should be set before the OS timer is enabled. The
hardware will set up OST_ISR[0] periodically at frame duration period when the OS timer is enabled.
.Li K

no TE
12:0 OST_FRM
Ar IA
0XA01F0010 OS Timer Frame Duration by 32K Clock OST_FRM_F32K

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
R ED
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name OST_UFN OST_FRM_F32K
Type RW RW
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
FO M
Overview: This register specifies the OS timer frame duration with 30.5176 micron second (32kHz) resolution.
The maximum duration is 8ms and minimum duration is 1ms. This register should be set up before the OS timer
is enabled. OST_FRAM_F32K*30.5176us should be less than OST_FRM_NUM*OST_FRM*1us - 30.5176us. Set
up OST_FRM_NUM if the frame duration is shorter than the system settling time.


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15:12 OST_UFN
US IAL
11:0 OST_FRM_F32K
EO
0XA01F0014 OS Timer Un-alignment Frame Number OST_UFN
hk T
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name OST_UFN[31:16]
Type RW
m. EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name OST_UFN[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.co ID
Overview: This register specifies the OS timer un-alignment event frame number count. This register value is
updated to the OS timer only when OST_CMD.OST_WR is set. The read value of this register may not be the
sac NF
current OS time un-alignment frame number. The hardware will count down the OST_UFN counter at frame time-
out and stop the count-down when the current value is 0. When the OS timer is in the pause mode, this counter is
still active and wakes up the OS timer when OST_UFN becomes 0 at frame time-out boundary. The software
should enable the OS timer pause mode when OST_UFN is larger than 1, or the pause command will be ignored
O
by hardware.
u@ C

31:0 OST_UFN
.Li K
0XA01F0018 OS Timer Alignment Frame Number OST_AFN

no TE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name OST_AFN[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ar IA
Name OST_AFN[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R ED
Overview: This register specifies the OS timer alignment event frame number count. This register value is
updated to the OS timer only when OST_CMD.OST_WR is set. The read value of this register may not be the
current OS time alignment frame number. The hardware will count down the OST_AFN counter at frame time-out
and stop the count-down when the current value is 0. The hardware will set up OST_ISR[1] when OST_AFN is 1
FO M
or 0 at frame time-out and the OS timer is in the normal mode. OST_AFN is the current hardware AFN down
counter value, and the software cannot read this register directly. The software can only read the current frame
number through the OST_AFN_R register, and there is synchronization latency from OST_AFN to OST_AFN_R.

31:0 OST_AFN


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0XA01F001C OS Timer Alignment Frame Delay Number Count OST_AFN_DLY
US IAL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name OST_AFN_DLY[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name OST_AFN_DLY[15:0]
hk T
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m. EN
Overview: This register specifies the OS Timer Alignment event frame delay count due to OS timer pause mode.
Software has to use OST_CMD.OST_RD command to update this register value, or the value maybe out of date.
Bit(s)
31:0
Name
.co ID
OST_AFN_DLY
Description
sac NF
0XA01F0020 Current OS Timer Un-alignment Frame Number OST_UFN_R
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name OST_UFN_R[31:16]
O
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
u@ C
Name OST_UFN_R[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.Li K
Overview: This register specifies the OS timer current un-alignment frame number. The software has to use the
no TE
OST_CMD.OST_RD command to update this register value, or the value may be out of date.

31:0 OST_UFN_R
Ar IA
0XA01F0024 Current OS Timer Alignment Frame Number OST_AFN_R

R ED
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name OST_AFN_R[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO M
Name OST_AFN_R[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Overview: This register specifies the OS timer current alignment frame number. The software has to use the
OST_CMD.OST_RD command to update this register value, or the value may be out of date.


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31:0 OST_AFN_R
US IAL
EO
0XA01F0030 OS Timer Interrupt Mask OST_INT_MASK
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
hk T
Type
Reset
m. EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name OST_INT_MASK
Type RW
Reset 1 1 1 1 1
Bit(s) Name
.co ID
Overview: This register specifies the OS timer interrupt mask control.
Description
sac NF
0: Mask OS timer frame time-out interrupt
1: Mask OS timer alignment frame time-out interrupt
4:0 OST_INT_MASK 2: Mask OS timer un-alignment frame time-out interrupt
3: Mask OS timer pause abort interrupt
O
4: Mask OS timer pause interrupt

u@ C
0XA01F0040 OS Timer Interrupt Status OST_ISR

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
.Li K
Name
Type
Reset
no TE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name OST_ISR
Type W1C
Reset 0 0 0 0 0
Ar IA
Overview: This register specifies the OS timer interrupt status. The software has to write 1 to the corresponding
bit to clear the interrupt status bit. OSR_ISR[2-0] are also cleared when the OSR_WR command is executed and
AFN, UFN are updated.
R ED

0: OS timer frame time-out interrupt status
1: OS timer alignment frame time-out interrupt status
FO M
4:0 OST_ISR 2: OS timer un-alignment frame time-out interrupt status

3: OS timer pause abort interrupt status
4: OS timer pause interrupt status
0XA01F0050 OS Timer Event Mask OST_EVENT_MASK

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


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OST_EVENT_MASK
Name
[18:16]
Type RW
US IAL
Reset 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
Name OST_EVENT_MASK[15:0]
Type RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
hk T
Overview: This register specifies which wakeup event will be masked to wake up the OS timer in the OS timer
pause mode.
m. EN
18:0 OST_EVENT_MASK
0XA01F0054
.co ID OS Timer Event Wakeup Status OST_WAKEUP_STA
sac NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OST_WAKEUP_STA
Name
[18:16]
Type RO
Reset 0 0 0
O
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name OST_WAKEUP_STA[15:0]
Type RO
u@ C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

.Li K
18:0 OST_WAKEUP_STA
no TE
0XA01F0060 OS Timer Debug Wakeup OST_DBG_WAKEOSUP

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Ar IA
CIRQ_
OST_DBG_WAKEU
Name MASK
P[18:16]
_EN
Type RW
Reset 0 0 0 0
R ED
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name OST_DBG_WAKEUP[15:0]
Type
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO M

31 CIRQ_MASK_EN 0: Disable cirq mask function
1: Enable cirq mask function
18:0 OST_DBG_WAKEUP Controls wakeup status in debug timing event1


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To OST Wakeup Contol
US IAL
EO
OST_DBG
MUX
1
hk T
DBG_WAKE[0] DBG_WAKE[1] DBG_WAKE[n]
m. EN
OST_DBG_WAKEUP DeMUX
.co ID
sac NF
GPT_EVENT_B Wakeup Sources
Figure 34. Debug wakeup events

O
3.7 UART1
u@ C

.Li K
The baseband chipset houses two UARTs. The UARTs provide full duplex serial communication
channels between baseband chipset and external dev ices.
no TE
The UART has M16C450 and M16550A modes of operation, which are compatible with a range of
standard software drivers. The extensions have been designed to be broadly software compatible
with 16550A variants, but certain areas offer no consensus.
Ar IA
In common with the M16550A, the UART supports word lengths from 5 to 8 bits, an optional parity
bit and one or two stop bits, and is fully programmable by an 8-bit CPU interface. A 16-bit
R ED
programmable baud rate generator and an 8-bit scratch register are included, together with separate
transmit and receive FIFOs. 8 modem control lines and a diagnostic loop-back mode are provided.
UART also includes two DMA handshake lines, indicating when the FIFOs are ready to transfer data
to the CPU. Interrupts can be generated from any of the 10 sources.
FO M
Note that UART is designed so that all internal operation is synchronized by the CLK signal. This
synchronization results in minor timing differences between the UART and industry standard 16550A
device, which means that the core is not clock for clock identical to the original device.
After a hardware reset, UART will be in M16C450 mode. Its FIFOs can then be enabled and UART
can enter M16550A mode. UART has further functions beyond the M16550A mode. Each of the


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extended functions can be selected individually under software control.
US IAL
UART provides more powerful enhancements than the industry-standard 16550:
EO
 Hardware flow control. This feature is very useful when the ISR latency is hard to predict and
control in the embedded applications. The MCU is relieved of having to fetch the received data
within a fixed amount of time.
hk T
Note that in order to enable any of the enhancements, the Enhanced Mode bit, EFR[4], must be set. If
m. EN
EFR[4] is not set, IER[7:5], FCR[5:4], IIR[5:4] and MCR[7:6] cannot be written. The enhanced mode
bit ensures that UART is backward compatible with the software that has been written for 16C450 and
16550A devices. Figure 35 is the block diagram of the UART1 device.
.co ID Baud Rate

Generator
Baud Divisor
sac NF
Clock
TX Machine Uart_tx_data
TX FIFO
O
APB
APB Bus
BUS RX FIFO
RX Machine
u@ C
I/F Uart_rx_data
Modem Modem Outputs

.Li K
Control
Modem Inputs
no TE
Figure 35. Block Diagram of UART1

Ar IA

Module name: UART1 Base address: (+A0080000h)
R ED

RX Buffer Register
A0080000 RBR 8
Note: Only when LCR[7] = 0.
TX Holding Register
A0080000 THR 8
Note: Only when LCR[7] = 0
FO M
Divisor Latch (LS)

A0080000 DLL 8 Divides the bclk frequency
Note: Nodified when LCR[7]!=0
Interrupt Enable Register
A0080004 IER 8 By storing 1 to a specific bit position, the interrupt associated
with that bit is enabled. Otherwise, the interrupt will be
disabled.


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IER[3:0] are modified when LCR[7] = 0.
US IAL
IER[7:4] are modified when LCR[7] = 0 & EFR[4] = 1.
Divisor Latch (MS)
EO
A0080004 DLM 8 uesd to divid the bclk frequency .*NOTE: modified when
LCR[7]!=0
Interrupt Identification Register
Note: Only when LCR!=BF'h. Priority is from high to low as
hk T
the following.
IIR[5:0]=0X1: No interrupt pending
m. EN
IIR[5:0]=0X6: Line status interrupt (under IER[2]=1)
IIR[5:0]=0Xc: RX data time-out interrupt (under IER[0]=1)
A0080008 IIR 8 IIR[5:0]=0X4: RX data are placed in the RX bBuffer register
or the RX trigger level is reached. (under IER[0]=1).
IIR[5:0]=0X2: TX holding register is empty or the contents of
.co ID the TX FIFO have been reduced to its trigger level (under
IER[1]=1).
IIR[5:0]=0X10: XOFF
IER[5]=1,EFR[4] = 1).
character received (under
sac NF
FIFO Control Register
FCR is used to control the trigger levels of the FIFOs or
A0080008 FCR 8 flush the FIFOs.
FCR[7:6] is modified when LCR != BFh
FCR[5:4] is modified when LCR != BFh & EFR[4] = 1
O

Enhanced Feature Register
A0080008 EFR 8
u@ C
Note: Only when LCR=BF'h

Line Control Register
A008000C LCR 8
Determines characteristics of serial communication signals.
.Li K
Modem Control Register

A0080010 MCR 8 Controls interface signals of the UART.
MCR[5:0] are modified when LCR != 8'hBF,
no TE
MCR[7] can be read when LCR != 8'hBF & EFR[4] = 1.

XON1 Char Register
A0080010 XON1 8
Note: XON1 is modified only when LCR=BF'h.
Line Status Register
Ar IA
A0080014 LSR 8
Modified when LCR != BFh.
XOFF1 Char Register
A0080018 XOFF1 8
*Note: XOFF1 is modified only when LCR=BF'h.
R ED
Scratch Register
A008001C SCR 8 A general purpose read/write register. After reset, its value
will be un-defined.
A0080020 AUTOBAUD_EN 8 Auto Baud Detect Enable Register
FO M
A0080024 HIGHSPEED 8 High Speed Mode Register

Sample Counter Register
A0080028 SAMPLE_COUNT 8 When HIGHSPEED=3, sample_count will be the threshold
value for UART sample counter (sample_num).
Count from 0 to sample_count.
Sample Point Register
A008002C SAMPLE_POINT 8 When HIGHSPEED=3, UART gets the input data when
sample_count=sample_num, e.g. system clock = 13MHz,


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921600 = 13000000/14. Therefore, sample_count = 13, and
US IAL
sample point = 6 (sampling the central point to decrease the
inaccuracy)
SAMPLE_POINT is usually (SAMPLE_COUNT-1)/2 without
EO
decimal.
Auto Baud Monitor Register
A0080030 AUTOBAUD_REG 8 the autobaud detection state ,it will not change until enable
hk T
the autobaud_en again.
A0080034 RATEFIX_AD 8 Clock Rate Fix Register
m. EN
Auto Baud Sample Register
Since the system clock may change, autobaud sample
AUTOBAUDSAMPL duration should change as the system clock changes.
A0080038 8
E When system clock = 13MHz, autobaudsample = 6; when
system clock = 26MHz, autobaudsample = 13. When system
A008003C
A0080040
.co ID
GUARD
ESCAPE_DAT
8
8
clock = 52MHz, autobaudsample = 27.
Guard Time Added Register
Escape Character Register
sac NF
A0080044 ESCAPE_EN 8 Escape Enable Register
A0080048 SLEEP_EN 8 Sleep Enable Register
A008004C DMA_EN 8 DMA Enable Register
A0080050 RXTRI_AD 8 Rx Trigger Address
O
A0080054 FRACDIV_L 8 Fractional Divider LSB Address

A0080058 FRACDIV_M 8 Fractional Divider MSB Address
u@ C
A008005C FCR_RD 8 FIFO Control Register

.Li K
A0080000 RBR RX Buffer Register 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
no TE
Name RBR
Type RU
Reset 0 0 0 0 0 0 0 0
Ar IA

Read-only register
7:0 RBR The received data can be read by accessing this register.
Only when LCR[7] = 0.
R ED
A0080000 THR TX Holding Register 00

FO M
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name THR
Type WO
Reset 0 0 0 0 0 0 0 0

TX Holding Register
7:0 THR Write-only register. The data to be transmitted are written to this register and sent to the
PC via serial communication.


MT2503D
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US IAL
EO
A0080000 DLL Divisor Latch (LS) 01
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DLL
hk T
Type RW
Reset 0 0 0 0 0 0 0 1
m. EN
Divisor latch low 8-bit data
7:0 DLL
Note: Modified when LCR[7]!=0.
A0080004
.co ID
IER Interrupt Enable Register 00
sac NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CTSI RTSI XOFFI EDSSI ELSI ETBEI ERBFI
Type RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0
O

7 CTSI Masks an interrupt that is generated when a rising edge is detected on the CTS
modem control line.
u@ C
Note: This interrupt is only enabled when hardware flow control is enabled.
0: Mask an interrupt that is generated when a rising edge is detected on the CTS
modem control line.
1: Unmask an interrupt that is generated when a rising edge is detected on the CTS
.Li K
modem control line.

6 RTSI Masks an interrupt that is generated when a rising edge is detected on the RTS
modem control line.
no TE
0: Mask an interrupt that is generated when a rising edge is detected on the RTS
modem control line.
1: Unmask an interrupt that is generated when a rising edge is detected on the RTS
modem control line.
Ar IA
5 XOFFI Masks an interrupt that is generated when an XOFF character is received.

Note: This interrupt is only enabled when software flow control is enabled.
0: Mask an interrupt that is generated when an XOFF character is received.
1: Unmask an interrupt that is generated when an XOFF character is received.
R ED
3 EDSSI When set to 1, an interrupt will be generated if DCTS (MSR[0]) becomes set.
0: No interrupt is generated if DCTS (MSR[0]) becomes set.
1: An interrupt is generated if DCTS (MSR[0]) becomes set.
2 ELSI When set to1, an interrupt will be generated if BI, FE, PE or OE (LSR[4:1])
becomes set.
FO M
0: No interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes set.

1: An interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes set.
1 ETBEI When set to 1, an interrupt will be generated if the TX holding register is empty or
the contents of the TX FIFO have been reduced to its trigger level.
0: No interrupt will be generated if the TX holding register is empty or the contents of the
TX FIFO have been reduced to its trigger level.
1: An interrupt will be generated if the TX folding register is empty or the contents of the
TX FIFO have been reduced to its trigger level.
0 ERBFI When set to 1, an interrupt will be generated if RX data are placed in RX buffer
register or the RX trigger level is reached.


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0: No interrupt will be generated if RX data are placed in the RX buffer register or the RX
US IAL
trigger level is reached.
1: An interrupt will be generated if RX Data are placed in the RX buffer register or the
RX trigger level is reached.
EO
A0080004 DLM Divisor Latch (MS) 00
hk T
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DLM
m. EN
Type RW
Reset 0 0 0 0 0 0 0 0

Divisor latch high 8-bit data
.co ID Note: Modified when LCR[7]!=0. DLL & DLM can only be updated when DLAB(LCR[7])
is set to 1. Division by 1 will generate a BAUD signal that is constantly high. DLL & DLM
setting formula is {DLH,DLL}=(system clock frequency/baud_pulse/baud_rate).
When RATE_FIX(RATEFIX_AD[0])=0, system clock frequency = 52MHz.
sac NF
When RATE_FIX(RATEFIX_AD[0])=1 and RATE_FIX(RATEFIX_AD[2])=0, system clock
7:0 DLM
frequency = 26MHz.
When RATE_FIX(RATEFIX_AD[0])=1 and RATE_FIX(RATEFIX_AD[2])=1, system clock
frequency = 13MHz.
For baud_pulse value, refer to HIGH_SPEED(offset=24H) register
For example, when at 52MHz, default speed mode and 115200 baud rate,
O
{DLH,DLL}=52MHz/16/115200=28.
u@ C
A0080008 IIR Interrupt Identification Register 01

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.Li K
Name FIFOE ID
Type RO RU
Reset 0 0 0 0 0 0 0 1
no TE

7:6 FIFOE
5:0 ID IIR[5:0] Priority level interrupt source
Ar IA
000001 - No interrupt pending

000110 1 Line status interrupt:
BI, FE, PE or OE set in LSR. (Under IER[2]=1)
001100 2 RX data time-out:
R ED
Time-out on character in RX FIFO. (Under IER[0]=1)

000100 3 RX data received:
RX data received or RX trigger level reached. (Under IER[0]=1)
000010 4 TX holding register empty:
000000 5 Modem status change:
DCTS set in MSR. (Under IER[3]=1)
FO M
TX Holding Register empty or TX FIFO trigger level reached. (Under IER[1]=1)

010000 6 Software flow control:
XOFF Character received. (Under IER[5]=1)
100000 7 Hardware flow control:
CTS or RTS Rising Edge. (Under IER[7]=1 or IER[6]=1)
Line status interrupt: A RX line status interrupt (IIR[5:0] = 000110b) will be generated if
ELSI (IER[2]) is set and any of BI, FE, PE or OE (LSR[4:1]) becomes set. The interrupt
is cleared by reading the line status register.
RX data time-out interrupt: When the virtual FIFO mode is disabled, RX data time-out


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interrupt will be generated if all of the following conditions are applied:
US IAL
1. FIFO contains at least one character.
2. The most recent character is received longer than four character periods ago
(including all start, parity and stop bits);
EO
3. The most recent CPU read of the FIFO is longer than four character periods ago.
The timeout timer is restarted upon receipt of a new byte from the RX shift register or
upon a CPU read from the RX FIFO.
hk T
The RX data time-out interrupt is enabled by setting EFRBI (IER[0]) to 1 and is cleared
by reading RX FIFO.
m. EN
When the virtual FIFO mode is enabled, RX data time-out interrupt will be generated if
all of the following conditions are applied:
1. FIFO is empty.
2. The most recent character is received longer than four character periods ago
(including all start, parity and stop bits).
3. The most recent CPU read of the FIFO is longer than four character periods ago.
.co ID The timeout timer is restarted upon receipt of a new byte from the RX shift register or
reading DMA_EN register.
The RX Data Timeout Interrupt is enabled by setting EFRBI (IER[0]) to 1 and is cleared
by reading DMA_EN register.
sac NF
RX data received interrupt: A RX received interrupt (IER[5:0] = 000100b) is generated
if EFRBI (IER[0]) is set and either RX data are placed in the RX buffer register or the RX
trigger level is reached. The interrupt is cleared by reading the RX buffer register or the
RX FIFO (if enabled).
O
TX holding register empty interrupt: A TX holding register empty interrupt (IIR[5:0] =

000010b) is generated if ETRBI (IER[1]) is set and either the TX holding register is
empty or the contents of the TX FIFO are reduced to its trigger level. The interrupt is
u@ C
cleared by writing to the TX holding register or TX FIFO if FIFO is enabled.
Modem status change interrupt: A modem status change Interrupt (IIR[5:0] =

000000b) will be generated if EDSSI (IER[3]) is set and e DCTS (MSR[3:0]) becomes
.Li K
set. The interrupt is cleared by reading the modem status register.
Software flow control interrupt: A software flow control interrupt (IIR[5:0] = 010000b)
will be generated if the software flow control is enabled and XOFFI (IER[5]) becomes
no TE
set, indicating that an XOFF character has been received. The interrupt is cleared by
reading the interrupt identification register.
Hardware flow control interrupt: A hardware flow control interrupt (IER[5:0] =

100000b) will be generated if the hardware flow control is enabled and either RTSI
Ar IA
(IER[6]) or CTSI (IER[7]) becomes set indicating that a rising edge has been detected
on either the RTS/CTS modem control line. The interrupt is cleared by reading the
interrupt identification register.
R ED
A0080008 FCR FIFO Control Register 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RFTL1_RFTL0 TFTL1_TFTL0 CLRT CLRR FIFOE
FO M
Type WO WO WO WO WO
Reset 0 0 0 0 0 0 0

7:6 RFTL1_RFTL0 RX FIFO trigger threshold
RX FIFO contains total 32 bytes.
0: 1
1: 6
2: 12


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3: RXTRIG
US IAL
5:4 TFTL1_TFTL0 TX FIFO trigger threshold
TX FIFO contains total 32 bytes.
EO
0: 1
1: 4
2: 8
3: 14
2 CLRT Control bit to clear TX FIFO
hk T
0: No effect
1: Clear TX FIFO
m. EN
1 CLRR Control bit to clear RX FIFO
0: No effect
1: Clear RX FIFO
0 FIFOE Enables FIFO
This bit must be set to 1 for any of other bits in the registers to have any effect.
.co ID 0: Disable
1: Enable both RX and TX FIFOs.
both RX and TX FIFOs.
sac NF
A0080008 EFR Enhanced Feature Register 00
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name AUTO_ AUTO_ ENABL
SW_FLOW_CONT
CTS RTS E_E
O
Type RW RW RW RW
Reset 0 0 0 0 0 0 0
u@ C

7 AUTO_CTS Enables hardware transmission flow control
0: Disable
.Li K
1: Enable
6 AUTO_RTS Enables hardware reception flow control
no TE
0: Disable
1: Enable
4 ENABLE_E Enables enhancement feature
0: Disable
1: Enable
Ar IA
3:0 SW_FLOW_CONT Software flow control bits

00xx: No TX flow control
10xx: Transmit XON1/XOFF1 as flow control bytes
xx00: No RX flow control
R ED

xx10: Receive XON1/XOFF1 as flow control bytes
FO M
A008000C LCR Line Control Register 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DLAB SB SP EPS PEN STB WLS1_WLS0
Reset 0 0 0 0 0 0 0 0

7 DLAB Divisor latch access bit


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0: RX and TX registers are read/written at Address 0 and the IER register is read/written
US IAL
at Address 4.
1: Divisor Latch LS is read/written at Address 0 and the Divisor Latch MS is read/written
at Address 4.
EO
6 SB Set break
0: No effect
1: SOUT signal is forced to the 0 state.
5 SP Stick parity
hk T
0: No effect.
1: The parity bit is forced to a defined state, depending on the states of EPS and PEN: If
EPS=1 & PEN=1, the parity bit will be set and checked = 0. If EPS=0 & PEN=1, the
m. EN
parity bit will be set and checked = 1.
4 EPS Selects even parity
0: When EPS=0, an odd number of ones is sent and checked.
1: When EPS=1, an even number of ones is sent and checked.
3 PEN Enables parity
2 STB
.co ID 0: The
Number of STOP bits

0: One
parity
STOP
is neither
1: The parity is transmitted and checked.
bit is
transmitted
always added.
nor checked.
sac NF
1: Two STOP bits are added after each character is sent; unless the character length is
5 when 1 STOP bit is added.
1:0 WLS1_WLS0 Selects word length
0: 5 bits
1: 6 bits
O
2: 7 bits
3: 8 bits
u@ C
A0080010 MCR Modem Control Register 00

.Li K
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XOFF_
Name STATU Loop RTS
no TE
S
Type RU RW RW
Reset 0 0 0

Ar IA
7 XOFF_STATUS Read-only bit

0: When an XON character is received.
1: When an XOFF character is received.
R ED
4 Loop Loop-back control bit

0: No loop-back is enabled.
1: Loop-back mode is enabled.
1 RTS Controls the state of the output NRTS, even in loop mode.
0: RTS will always output 1.
1: RTS's output will be controlled by flow control condition.
FO M
A0080010 XON1 XON1 Char Register 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name XON1
Type RW
Reset 0 0 0 0 0 0 0 0


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US IAL
XON1 character for software flow control
7:0 XON1
Modified only when LCR=BF'h.
EO
A0080014 LSR Line Status Register 60
hk T
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOE
Name TEMT THRE BI FE PE OE DR
m. EN
RR
Type RU RU RU RU RU RU RU RU
Reset 0 1 1 0 0 0 0 0

7
6 TEMT
.co ID
FIFOERR RX FIFO error indicator
0: No PE, FE, BI set in the
1: Set to 1 when there is at least one PE, FE or BI in the RX FIFO.
TX holding register (or TX FIFO) and the TX shift register are empty.
RX FIFO.
sac NF
0: Empty conditions below are not met.
1: If FIFOs are enabled, the bit will be set whenever the TX FIFO and the TX shift
register are empty. If FIFOs are disabled, the bit will be set whenever TX holding register
and TX shift register are empty.
5 THRE Indicates if there is room for TX holding register or TX FIFO is reduced to its
O
trigger level
0: Reset whenever the contents of the TX FIFO are more than its trigger level (FIFOs
are enabled), or whenever TX holding register is not empty (FIFOs are disabled).
u@ C
1: Set whenever the contents of the TX FIFO are reduced to its trigger level (FIFOs are
enabled), or whenever TX holding register is empty and ready to accept new data
(FIFOs are disabled).
4 BI Break interrupt
.Li K
0: Reset by the CPU reading this register

1: If the FIFOs are disabled, this bit will be set whenever the SIN is held in the 0 state for
more than one transmission time (START bit + DATA bits + PARITY + STOP bits).
no TE
If the FIFOs are enabled, this error will be associated with a corresponding character in
the FIFO and is flagged when this byte is at the top of the FIFO. When a break occurs,
only one zero character is loaded into the FIFO: The next character transfer is enabled
when SIN goes into the marking state and receives the next valid start bit.
3 FE Framing error
Ar IA

1: If the FIFOs are disabled, this bit will be set if the received data do not have a valid
STOP bit. If the FIFOs are enabled, the state of this bit will be revealed when the byte it
refers to is the next to be read.
2 PE Parity error
R ED

1: If the FIFOs are disabled, this bit will be set if the received data do not have a valid
parity bit. If the FIFOs are enabled, the state of this bit will be revealed when the
referred byte is the next to be read.
1 OE Overrun error
FO M
0: Reset by the CPU reading this register.

1: If the FIFOs are disabled, this bit will be set if the RX buffer is not read by the CPU
before the new data from the RX shift register overwrites the previous contents. If the
FIFOs are enabled, an overrun error will occur when the RX FIFO is full and the RX shift
register becomes full. OE will be set as soon as this happens. The character in the shift
register is then overwritten, but not transferred to the FIFO.
0 DR Data ready
0: Cleared by the CPU reading the RX buffer or by reading all the FIFO bytes.
1: Set by the RX buffer becoming full or by the FIFO becoming no empty.


MT2503D
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A0080018 XOFF1 XOFF1 Char Register 00
US IAL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
EO
XOFF1
Type RW
Reset 0 0 0 0 0 0 0 0
hk T
XOFF1 character for software flow control
7:0 XOFF1
m. EN
A008001C SCR Scratch Register 00
Bit
Name
Type
Reset
15
.co ID
14 13 12 11 10 9 8 7
0
6
0
5
0
4
0
SCR
RW
3
0
2
0
1
0
0
0
sac NF
General purpose read/write register
7:0 SCR
After reset, its value will be undefined. Modified when LCR != BFh.
O
u@ C
A0080020 AUTOBAUD_EN Auto Baud Detect Enable Register 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLEEP AUTOB AUTOB
.Li K
Name _ACK_ AUD_S AUD_E

SEL EL N
Type RW RW RW
Reset 0 0 0
no TE

2 SLEEP_ACK_SEL Selects sleep ack when autobaud_en
0: Support sleep_ack when autobaud_en is opened .
Ar IA
1: Does not support sleep_ack when autobaud_en is opened .

1 AUTOBAUD_SEL Selects auto-baud
0: Support standard baud rate detection
1: Support non_standard baud rate detection (support baud from 110 to 115200;
R ED
recommended to use 52MHz to auto fix) .

0 AUTOBAUD_EN Auto-baud enabling signal
0: Disable auto-baud function
1: Enable auto-baud function (UARTn+0024h SPEED should be set to 0.)
Note: When AUTOBAUD_EN is active, there should not be A*/a* char before the auto
FO M
baud char AT/at. If A*/a* is Inevitable, autobaud will fail and please disable
AUTOBAUD_EN to reset the autobaud feature and autobaud_en again.
A0080024 HIGHSPEED High Speed Mode Register 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SPEED
Type RW


MT2503D
Confidential A
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Reset 0 0
US IAL
UART sample counter base
EO
0: Based on 16*baud_pulse, baud_rate = system clock frequency/16/{DLH, DLL}
1:0 SPEED 1: Based on 8*baud_pulse, baud_rate = system clock frequency/8/{DLH, DLL}
3: Based on sampe_count * baud_pulse, baud_rate = system clock frequency /
(sampe_count+1)/{DLM, DLL}
hk T
m. EN
SAMPLE_COUN
A0080028 Sample Counter Register 00
T
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
.co ID 0 0 0
SAMPLECOUNT
0
RW
0 0 0 0
sac NF
7:0 SAMPLECOUNT Only useful when HIGHSPEED mode = 3.
O
A008002C SAMPLE_POINTSample Point Register FF

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
u@ C
Name SAMPLEPOINT
Type RW
Reset 1 1 1 1 1 1 1 1
.Li K

SAMPLE_POINT is usually (SAMPLE_COUNT-1)/2 without decimal. Effective only
7:0 SAMPLEPOINT
no TE
when HIGHSPEED=3.
AUTOBAUD_RE
Ar IA
A0080030 Auto Baud Monitor Register 00

G
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BAUD_STAT BAUD_RATE
R ED
Type RU RU
Reset 0 0 0 0 0 0 0 0

7:4 BAUD_STAT Autobaud state (only true value in standard autobaud detection)
FO M
0: Autobaud is detecting.
1: AT_7N1
2: AT_7O1
3: AT_7E1
4: AT_8N1
5: AT_8O1
6: AT_8E1
7: at_7N1
8: at_7E1
9: at_7O1
10: at_8N1


MT2503D
Confidential A
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11: at_8E1
US IAL
12: at_8O1
13: Autobaud detection fails
3:0 BAUD_RATE Autobaud baud rate (only true value in standard autobaud detection)
EO
0: 115,200
1: 57,600
2: 38,400
3: 19,200
hk T
4: 9,600
5: 4,800
6: 2,400
m. EN
7: 1,200
8: 300
9: 110
A0080034
Bit 15 .co ID
RATEFIX_AD
14 13 12
Clock Rate Fix Register
11 10 9 8 7 6 5 4 3 2 1
AUTOB
0
00
sac NF
FREQ_ AUD_R RATE_
Name
SEL ATE_FI FIX
X
Type RW RW RW
Reset 0 0 0
O

2 FREQ_SEL 0: Select 26MHz as system clock
u@ C
1: Select 13MHz as system clock

1 AUTOBAUD_RATE_FIX 0: Use 52MHz as system clock for UART auto baud detection
1: Use 26MHz/13MHz (depending on FREQ_SEL) as system clock for UART auto baud
.Li K
detection
0 RATE_FIX 0: Use 52MHz as system clock for UART TX/RX
1: Use 26MHz/13MHz (depending on FREQ_SEL) as system clock for UART TX/RX
no TE
AUTOBAUDSA
A0080038 Auto Baud Sample Register 0D
Ar IA
MPLE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name AUTOBAUDSAMPLE
Type RW
R ED
Reset 0 0 1 1 0 1

clk diveision for autobaud rate detection
For standard baud rate detection.
FO M
System clk 52m: 'd 27

5:0 AUTOBAUDSAMPLE System clk 26m: 'd 13
For non-standard baud rate detection.
:15.
A008003C GUARD Guard Time Added Register 0F


MT2503D
Confidential A
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GUAR
GUARD_CNT
D_EN
US IAL
Type RW RW
Reset 0 1 1 1 1
EO
4 GUARD_EN Guard interval add enabling signal
0: No guard interval added
hk T
1: Add guard interval after stop bit.
3:0 GUARD_CNT Guard interval count value
m. EN
Guard interval = [1/(system clock/div_step/div)]*GUARD_CNT.
A0080040 ESCAPE_DAT Escape Character Register FF

Bit
Name
Type
Reset
15
.co ID
14 13 12 11 10 9 8 7
1
6
1
5
1
4
ESCAPE_DAT
1
RW
1
3 2
1
1
1
0
1
sac NF
Escape character added before software flow control data and escape character
7:0 ESCAPE_DAT
If TX data are xon (31h), with esc_en =1, UART will transmit data as esc + CEh (~xon).
O
u@ C
A0080044 ESCAPE_EN Escape Enable Register 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.Li K
ESC_E
Name
N
Type RW
Reset 0
no TE

Adds escape character in transmitter and removes escape character in receiver
by UART
0 ESC_EN
Ar IA
0: Does not deal with the escape character

1: Add escape character in transmitter and remove escape character in receiver
R ED
A0080048 SLEEP_EN Sleep Enable Register 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLEEP
Name
_EN
FO M
Type RW
Reset 0

For sleep mode issue
0: Does not deal with sleep mode indicate signal
0 SLEEP_EN 1: Activate hardware flow control or software control according to software initial setting
when the chip enters sleep mode. Release hardware flow when the chip wakes up.
However, for software control, UART sends xon when awaken and when FIFO does not


MT2503D
Confidential A
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NL
reach threshold level.
US IAL
EO
A008004C DMA_EN DMA Enable Register 00
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TO_CN
FIFO_l TX_DM RX_DM
hk T
Name T_AUT
sr_sel A_EN A_EN
ORST
Type RW RW RW RW
m. EN
Reset 0 0 0 0

3 FIFO_lsr_sel Selects FIFO LSR mode
2 .co ID
TO_CNT_AUTORST
0: LSR will hold the first line status error state until you read the LSR register.
1: LSR will update automatically.
Time-out counter auto reset register
0: After RX time-out happens, SW shall reset the interrupt by reading UART 0x4C.
1: The time-out counter will be auto reset. Set this register when Rain's new DMA is
sac NF
used.
1 TX_DMA_EN TX_DMA mechanism enabling signal
0: Does not use DMA in TX
1: Use DMA in TX. When this register is enabled, the flow control will be based on the
DMA threshold and generate a time-out interrupt for DMA.for DMA.
O
0 RX_DMA_EN RX_DMA mechanism enabling signal

0: Does not use DMA in RX
u@ C
1: Use DMA in RX. When this register is enabled, the flow control will be based on the
DMA threshold and generate a time-out interrupt
.Li K
A0080050 RXTRI_AD Rx Trigger Address 00

no TE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RXTRIG
Type RW
Reset 0 0 0 0
Ar IA

When {rtm,rtl}=2'b11, the RX FIFO threshold will be Rxtrig. The value is suggested to be
3:0 RXTRIG
smaller than half of RX FIFO size, which is 32 bytes.
R ED
A0080054 FRACDIV_L Fractional Divider LSB Address 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO M
Name FRACDIV_L
Type RW
Reset 0 0 0 0 0 0 0 0

Adds sampling count (+1) from state data7 to data0 to contribute fractional divisor.only
7:0 FRACDIV_L
when high_speed=3.


MT2503D
Confidential A
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A0080058 FRACDIV_M Fractional Divider MSB Address 00
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US IAL
Name FRACDIV_M
Type RW
EO
Reset 0 0

Adds sampling count when in state stop to parity to contribute fractional divisor.only
hk T
1:0 FRACDIV_M
when high_speed=3.
m. EN
A008005C FCR_RD FIFO Control Register 00
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
.co ID
RFTL1_RFTL0 TFTL1_TFTL0 CLRT CLRR FIFOE
Type RO RO RO RO RO
Reset 0 0 0 0 0 0 0
sac NF
0: 1
1: 6
O
2: 12
3: RXTRIG
u@ C

0: 1
1: 4
2: 8
.Li K
3: 14
2 CLRT 0: TX FIFO is not cleared.
1: TX FIFO is cleared.
no TE
1 CLRR 0: RX FIFO is not cleared.

1: RX FIFO is cleared.
Ar IA
0: RX and TX FIFOs are not enabled.

1: RX and TX FIFOs are enabled.
R ED
3.8 UART2
FO M


MT2503D
Confidential A
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NL
US IAL
transmit and receive FIFOs. 8 modem control lines and a diagnostic loop-back mode are provided.
EO
UART also includes two DMA handshake lines, indicating when the FIFOs are ready to transfer data
to the CPU. Interrupts can be generated from any of the 10 sources.
hk T
Note that UART is designed so that all internal operation is synchronized by the CLK signal. This
synchronization results in minor timing differences between the UART and industry standard 16550A
m. EN
device, which means that the core is not clock for clock identical to the original device.
After a hardware reset, UART will be in M16C450 mode. Its FIFOs can then be enabled and UART
can enter M16550A mode. UART has further functions beyond the M16550A mode. Each of the
.co ID
extended functions can be selected individually under software control.
UART provides more powerful enhancements than the industry-standard 16550:

sac NF
 Hardware flow control. This feature is very useful when the ISR latency is hard to predict
and control in the embedded applications. The MCU is relieved of having to fetch the
O
received data within a fixed amount of time.
Note that in order to enable any of the enhancements, the Enhanced Mode bit, EFR[4], must be set. If
u@ C
EFR[4] is not set, IER[7:5], FCR[5:4], IIR[5:4] and MCR[7:6] cannot be written. The enhanced mode
bit ensures that UART is backward compatible with the software that has been written for 16C450 and
.Li K
16550A devices. Figure 35 is the block diagram of the UART2 device.

no TE
Baud Rate
Generator
Baud Divisor
Ar IA
Clock
TX FIFO
APB
R ED
APB Bus
BUS RX FIFO
RX Machine Uart_rx_data
I/F
Modem Modem Outputs

FO M
Control
Modem Inputs
Figure 36. Block Diagram of UART2


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US IAL
Module name: UART2 Base address: (+A0090000h)
EO
RX Buffer Register
A0090000 RBR 8
TX Holding Register
A0090000 THR 8
hk T
Note: Only when LCR[7] = 0
Divisor Latch (LS)
m. EN
A0090000 DLL 8 Divides the bclk frequency
Note: Nodified when LCR[7]!=0
Interrupt Enable Register
By storing 1 to a specific bit position, the interrupt associated
A0090004
.co ID
IER 8 with that bit is enabled. Otherwise, the interrupt will be
disabled.
IER[3:0] are modified when LCR[7]
= 0.
sac NF
Divisor Latch (MS)
A0090004 DLM 8 uesd to divid the bclk frequency .*NOTE: modified when
LCR[7]!=0
Interrupt Identification Register
O
Note: Only when LCR!=BF'h. Priority is from high to low as

the following.
IIR[5:0]=0X1: No interrupt pending
u@ C
IIR[5:0]=0X6: Line status interrupt (under IER[2]=1)

IIR[5:0]=0Xc: RX data time-out interrupt (under IER[0]=1)
A0090008 IIR 8 IIR[5:0]=0X4: RX data are placed in the RX bBuffer register
.Li K
or the RX trigger level is reached. (under IER[0]=1).

IIR[5:0]=0X2: TX holding register is empty or the contents of
the TX FIFO have been reduced to its trigger level (under
no TE
IER[1]=1).
IIR[5:0]=0X10: XOFF character received (under
IER[5]=1,EFR[4] = 1).
FIFO Control Register
FCR is used to control the trigger levels of the FIFOs or
Ar IA
A0090008 FCR 8 flush the FIFOs.

R ED
Enhanced Feature Register

A0090008 EFR 8
Note: Only when LCR=BF'h
Line Control Register
A009000C LCR 8
Determines characteristics of serial communication signals.
FO M

A0090010 MCR 8 Controls interface signals of the UART.
XON1 Char Register
A0090010 XON1 8
Note: XON1 is modified only when LCR=BF'h.
Line Status Register
A0090014 LSR 8


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XOFF1 Char Register
US IAL
A0090018 XOFF1 8
*Note: XOFF1 is modified only when LCR=BF'h.
Scratch Register
EO
A009001C SCR 8 A general purpose read/write register. After reset, its value
will be un-defined.
A0090020 AUTOBAUD_EN 8 Auto Baud Detect Enable Register
hk T
A0090024 HIGHSPEED 8 High Speed Mode Register
m. EN
Sample Counter Register
A0090028 SAMPLE_COUNT 8 When HIGHSPEED=3, sample_count will be the threshold
value for UART sample counter (sample_num).
Sample Point Register
A009002C
.co ID
SAMPLE_POINT 8
When HIGHSPEED=3, UART gets the input data when
sample_count=sample_num, e.g. system clock = 13MHz,
921600 = 13000000/14. Therefore, sample_count = 13, and
sample point = 6 (sampling the central point to decrease the
sac NF
inaccuracy)
SAMPLE_POINT is usually (SAMPLE_COUNT-1)/2 without
decimal.
Auto Baud Monitor Register
A0090030 AUTOBAUD_REG 8 the autobaud detection state ,it will not change until enable
O
the autobaud_en again.

A0090034 RATEFIX_AD 8 Clock Rate Fix Register
u@ C
Auto Baud Sample Register

Since the system clock may change, autobaud sample
AUTOBAUDSAMPL duration should change as the system clock changes.
A0090038 8
E When system clock = 13MHz, autobaudsample = 6; when
.Li K
system clock = 26MHz, autobaudsample = 13. When system

clock = 52MHz, autobaudsample = 27.
no TE
A009003C GUARD 8 Guard Time Added Register

A0090040 ESCAPE_DAT 8 Escape Character Register
A0090044 ESCAPE_EN 8 Escape Enable Register
A0090048 SLEEP_EN 8 Sleep Enable Register
Ar IA
A009004C DMA_EN 8 DMA Enable Register

A0090050 RXTRI_AD 8 Rx Trigger Address
A0090054 FRACDIV_L 8 Fractional Divider LSB Address
R ED
A0090058 FRACDIV_M 8 Fractional Divider MSB Address

A009005C FCR_RD 8 FIFO Control Register
FO M
A0090000 RBR RX Buffer Register 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RBR
Type RU
Reset 0 0 0 0 0 0 0 0


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Read-only register
US IAL
7:0 RBR The received data can be read by accessing this register.
EO
A0090000 THR TX Holding Register 00
hk T
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name THR
m. EN
Type WO
Reset 0 0 0 0 0 0 0 0
7:0 THR .co ID TX Holding Register

Write-only register. The data to be transmitted are written to this register and
sent to the PC via serial communication.
sac NF
A0090000 DLL Divisor Latch (LS) 01

O
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DLL
Type RW
u@ C
Reset 0 0 0 0 0 0 0 1

.Li K
Divisor latch low 8-bit data

7:0 DLL
Note: Modified when LCR[7]!=0.
no TE
A0090004 IER Interrupt Enable Register 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ar IA
Name CTSI RTSI XOFFI EDSSI ELSI ETBEI ERBFI

Reset 0 0 0 0 0 0 0
R ED

7 CTSI Masks an interrupt that is generated when a rising edge is detected on
the CTS modem control line.
FO M
0: Mask an interrupt that is generated when a rising edge is detected on the

CTS modem control line.
1: Unmask an interrupt that is generated when a rising edge is detected on the
CTS modem control line.
6 RTSI Masks an interrupt that is generated when a rising edge is detected on
the RTS modem control line.
0: Mask an interrupt that is generated when a rising edge is detected on the
RTS modem control line.
1: Unmask an interrupt that is generated when a rising edge is detected on the


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RTS modem control line.
US IAL
5 XOFFI Masks an interrupt that is generated when an XOFF character is
received.
EO
3 EDSSI When set to 1, an interrupt will be generated if DCTS (MSR[0]) becomes
hk T
set.
0: No interrupt is generated if DCTS (MSR[0]) becomes set.
m. EN
1: An interrupt is generated if DCTS (MSR[0]) becomes set.
2 ELSI When set to1, an interrupt will be generated if BI, FE, PE or OE (LSR[4:1])
becomes set.
1
.co ID
ETBEI When set to 1, an interrupt will be generated if the TX holding register is
empty or the contents of the TX FIFO have been reduced to its trigger
level.
0: No interrupt will be generated if the TX holding register is empty or the
sac NF
contents of the TX FIFO have been reduced to its trigger level.
1: An interrupt will be generated if the TX folding register is empty or the
contents of the TX FIFO have been reduced to its trigger level.
0 ERBFI When set to 1, an interrupt will be generated if RX data are placed in RX
buffer register or the RX trigger level is reached.
O
0: No interrupt will be generated if RX data are placed in the RX buffer register

or the RX trigger level is reached.
1: An interrupt will be generated if RX Data are placed in the RX buffer register
u@ C
or the RX trigger level is reached.

.Li K
A0090004 DLM Divisor Latch (MS) 00

no TE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DLM
Type RW
Reset 0 0 0 0 0 0 0 0
Ar IA

Divisor latch high 8-bit data
Note: Modified when LCR[7]!=0. DLL & DLM can only be updated when
DLAB(LCR[7]) is set to 1. Division by 1 will generate a BAUD signal that is
R ED
constantly high. DLL & DLM setting formula is {DLH,DLL}=(system clock

frequency/baud_pulse/baud_rate).
7:0 DLM When RATE_FIX(RATEFIX_AD[0])=1 and RATE_FIX(RATEFIX_AD[2])=0,
system clock frequency = 26MHz.
FO M
When RATE_FIX(RATEFIX_AD[0])=1 and RATE_FIX(RATEFIX_AD[2])=1,

system clock frequency = 13MHz.
For baud_pulse value, refer to HIGH_SPEED(offset=24H) register
For example, when at 52MHz, default speed mode and 115200 baud rate,
{DLH,DLL}=52MHz/16/115200=28.


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A0090008 IIR Interrupt Identification Register 01
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US IAL
Name FIFOE ID
Type RO RU
EO
Reset 0 0 0 0 0 0 0 1
hk T
7:6 FIFOE
5:0 ID IIR[5:0] Priority level interrupt source
m. EN
000110 1 Line status interrupt:
001100 2 RX data time-out:
Time-out on character in RX FIFO. (Under IER[0]=1)
000100 3 RX data received:
.co ID RX data received or RX trigger level reached. (Under IER[0]=1)

000010
000000
DCTS set in
4
5
MSR.
TX holding register empty:
Modem status change:
(Under IER[3]=1)
sac NF
TX Holding Register empty or TX FIFO trigger level reached. (Under IER[1]=1)
010000 6 Software flow control:
100000 7 Hardware flow control:
O
Line status interrupt: A RX line status interrupt (IIR[5:0] = 000110b) will be

generated if ELSI (IER[2]) is set and any of BI, FE, PE or OE (LSR[4:1])
u@ C
becomes set. The interrupt is cleared by reading the line status register.
RX data time-out interrupt: When the virtual FIFO mode is disabled, RX data
time-out interrupt will be generated if all of the following conditions are applied:
.Li K
1. FIFO contains at least one character.

2. The most recent character is received longer than four character periods
ago (including all start, parity and stop bits);
no TE
3. The most recent CPU read of the FIFO is longer than four character periods
ago.
The timeout timer is restarted upon receipt of a new byte from the RX shift
register or upon a CPU read from the RX FIFO.
Ar IA
The RX data time-out interrupt is enabled by setting EFRBI (IER[0]) to 1 and is

cleared by reading RX FIFO.
When the virtual FIFO mode is enabled, RX data time-out interrupt will be
R ED
generated if all of the following conditions are applied:

1. FIFO is empty.
2. The most recent character is received longer than four character periods
ago (including all start, parity and stop bits).
3. The most recent CPU read of the FIFO is longer than four character periods
FO M
ago.
The timeout timer is restarted upon receipt of a new byte from the RX shift
register or reading DMA_EN register.
The RX Data Timeout Interrupt is enabled by setting EFRBI (IER[0]) to 1 and
is cleared by reading DMA_EN register.
RX data received interrupt: A RX received interrupt (IER[5:0] = 000100b) is

generated if EFRBI (IER[0]) is set and either RX data are placed in the RX
buffer register or the RX trigger level is reached. The interrupt is cleared by


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reading the RX buffer register or the RX FIFO (if enabled).
US IAL
TX holding register empty interrupt: A TX holding register empty interrupt
(IIR[5:0] = 000010b) is generated if ETRBI (IER[1]) is set and either the TX
EO
holding register is empty or the contents of the TX FIFO are reduced to its
trigger level. The interrupt is cleared by writing to the TX holding register or TX
FIFO if FIFO is enabled.
hk T
Modem status change interrupt: A modem status change Interrupt (IIR[5:0]
= 000000b) will be generated if EDSSI (IER[3]) is set and e DCTS (MSR[3:0])
becomes set. The interrupt is cleared by reading the modem status register.
m. EN
Software flow control interrupt: A software flow control interrupt (IIR[5:0] =
010000b) will be generated if the software flow control is enabled and XOFFI
(IER[5]) becomes set, indicating that an XOFF character has been received.
The interrupt is cleared by reading the interrupt identification register.
.co ID Hardware flow control interrupt: A hardware flow control interrupt (IER[5:0]
= 100000b) will be generated if the hardware flow control is enabled and either
RTSI (IER[6]) or CTSI (IER[7]) becomes set indicating that a rising edge has
sac NF
been detected on either the RTS/CTS modem control line. The interrupt is
cleared by reading the interrupt identification register.
O
A0090008 FCR FIFO Control Register 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
u@ C
Name RFTL1_RFTL TFTL1_TFTL

CLRT CLRR FIFOE
0 0
Type WO WO WO WO WO
Reset 0 0 0 0 0 0 0
.Li K

no TE

0: 1
1: 6
2: 12
Ar IA
3: RXTRIG
0: 1
R ED
1: 4
2: 8
3: 14
2 CLRT Control bit to clear TX FIFO
FO M
0: No effect
1: Clear TX FIFO
1 CLRR Control bit to clear RX FIFO
0: No effect
1: Clear RX FIFO
0: Disable both RX and TX FIFOs.
1: Enable both RX and TX FIFOs.


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US IAL
A0090008 EFR Enhanced Feature Register 00
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name AUTO AUTO ENAB
SW_FLOW_CONT
_CTS _RTS LE_E
Type RW RW RW RW
Reset 0 0 0 0 0 0 0
hk T
m. EN
7 AUTO_CTS Enables hardware transmission flow control
0: Disable
1: Enable
6 AUTO_RTS Enables hardware reception flow control
4
.co ID
ENABLE_E
0:
1: Enable
Enables enhancement feature
0:
Disable
Disable
sac NF
1: Enable
3:0 SW_FLOW_CONT Software flow control bits
O
10xx: Transmit XON1/XOFF1 as flow control bytes

u@ C
xx10: Receive XON1/XOFF1 as flow control bytes

.Li K
A009000C LCR Line Control Register 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
no TE
Name DLAB SB SP EPS PEN STB WLS1_WLS0

Reset 0 0 0 0 0 0 0 0

Ar IA
7 DLAB Divisor latch access bit

0: RX and TX registers are read/written at Address 0 and the IER register is
read/written at Address 4.
R ED
1: Divisor Latch LS is read/written at Address 0 and the Divisor Latch MS is

read/written at Address 4.
6 SB Set break
0: No effect
1: SOUT signal is forced to the 0 state.
FO M
5 SP Stick parity
0: No effect.
1: The parity bit is forced to a defined state, depending on the states of EPS
and PEN: If EPS=1 & PEN=1, the parity bit will be set and checked = 0. If
EPS=0 & PEN=1, the parity bit will be set and checked = 1.
4 EPS Selects even parity
0: When EPS=0, an odd number of ones is sent and checked.
1: When EPS=1, an even number of ones is sent and checked.


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3 PEN Enables parity
US IAL
0: The parity is neither transmitted nor checked.
1: The parity is transmitted and checked.
EO
2 STB Number of STOP bits
0: One STOP bit is always added.
1: Two STOP bits are added after each character is sent; unless the character
length is 5 when 1 STOP bit is added.
hk T
1:0 WLS1_WLS0 Selects word length
0: 5 bits
m. EN
1: 6 bits
2: 7 bits
3: 8 bits
A0090010
Bit 15
.co ID
MCR
14 13 12
11 10 9 8 7
XOFF
6 5 4 3 2 1 0
00
sac NF
Name _STAT Loop RTS
US
Type RU RW RW
Reset 0 0 0
O

7 XOFF_STATUS Read-only bit
u@ C
0: When an XON character is received.

1: When an XOFF character is received.
4 Loop Loop-back control bit
.Li K
0: No loop-back is enabled.
1: Loop-back mode is enabled.
1 RTS Controls the state of the output NRTS, even in loop mode.
no TE
0: RTS will always output 1.

1: RTS's output will be controlled by flow control condition.
Ar IA
A0090010 XON1 XON1 Char Register 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name XON1
R ED
Type RW
Reset 0 0 0 0 0 0 0 0

FO M
XON1 character for software flow control

7:0 XON1
A0090014 LSR Line Status Register 60

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOE
Name TEMT THRE BI FE PE OE DR
RR


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Type RU RU RU RU RU RU RU RU
Reset 0 1 1 0 0 0 0 0
US IAL
EO
7 FIFOERR RX FIFO error indicator
0: No PE, FE, BI set in the RX FIFO.
1: Set to 1 when there is at least one PE, FE or BI in the RX FIFO.
6 TEMT TX holding register (or TX FIFO) and the TX shift register are empty.
hk T
0: Empty conditions below are not met.
1: If FIFOs are enabled, the bit will be set whenever the TX FIFO and the TX
m. EN
shift register are empty. If FIFOs are disabled, the bit will be set whenever TX
holding register and TX shift register are empty.
5 THRE Indicates if there is room for TX holding register or TX FIFO is reduced to
its trigger level
0: Reset whenever the contents of the TX FIFO are more than its trigger level
.co ID (FIFOs are enabled), or whenever TX holding register is not empty (FIFOs are
disabled).
1: Set whenever the contents of the TX FIFO are reduced to its trigger level
(FIFOs are enabled), or whenever TX holding register is empty and ready to
sac NF
accept new data (FIFOs are disabled).
4 BI Break interrupt
1: If the FIFOs are disabled, this bit will be set whenever the SIN is held in the
0 state for more than one transmission time (START bit + DATA bits + PARITY
O
+ STOP bits).
If the FIFOs are enabled, this error will be associated with a corresponding
character in the FIFO and is flagged when this byte is at the top of the FIFO.
u@ C
When a break occurs, only one zero character is loaded into the FIFO: The
next character transfer is enabled when SIN goes into the marking state and
receives the next valid start bit.
.Li K
3 FE Framing error
1: If the FIFOs are disabled, this bit will be set if the received data do not have
no TE
a valid STOP bit. If the FIFOs are enabled, the state of this bit will be revealed
when the byte it refers to is the next to be read.
2 PE Parity error
1: If the FIFOs are disabled, this bit will be set if the received data do not have
Ar IA
a valid parity bit. If the FIFOs are enabled, the state of this bit will be revealed
when the referred byte is the next to be read.
1 OE Overrun error
R ED
0: Reset by the CPU reading this register.

1: If the FIFOs are disabled, this bit will be set if the RX buffer is not read by
the CPU before the new data from the RX shift register overwrites the
previous contents. If the FIFOs are enabled, an overrun error will occur when
the RX FIFO is full and the RX shift register becomes full. OE will be set as
soon as this happens. The character in the shift register is then overwritten,
FO M
but not transferred to the FIFO.

0 DR Data ready
0: Cleared by the CPU reading the RX buffer or by reading all the FIFO bytes.
1: Set by the RX buffer becoming full or by the FIFO becoming no empty.
A0090018 XOFF1 XOFF1 Char Register 00


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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name XOFF1
Type RW
US IAL
Reset 0 0 0 0 0 0 0 0
EO
XOFF1 character for software flow control
7:0 XOFF1
hk T
m. EN
A009001C SCR Scratch Register 00
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SCR
Type RW
Reset
Bit(s) Name
.co ID Description
0 0 0 0 0 0 0 0
sac NF
General purpose read/write register
7:0 SCR
After reset, its value will be undefined. Modified when LCR != BFh.
O
A0090020 AUTOBAUD_EN Auto Baud Detect Enable Register 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
u@ C
SLEE AUTO AUTO

Name P_AC BAUD BAUD
K_SEL _SEL _EN
Type RW RW RW
.Li K
Reset 0 0 0

no TE
2 SLEEP_ACK_SEL Selects sleep ack when autobaud_en

0: Support sleep_ack when autobaud_en is opened .
1: Does not support sleep_ack when autobaud_en is opened .
1 AUTOBAUD_SEL Selects auto-baud
Ar IA
0: Support standard baud rate detection

1: Support non_standard baud rate detection (support baud from 110 to
115200; recommended to use 52MHz to auto fix) .
0 AUTOBAUD_EN Auto-baud enabling signal
R ED
0: Disable auto-baud function

1: Enable auto-baud function (UARTn+0024h SPEED should be set to 0.)
Note: When AUTOBAUD_EN is active, there should not be A*/a* char before
the auto baud char AT/at. If A*/a* is Inevitable, autobaud will fail and please
disable AUTOBAUD_EN to reset the autobaud feature and autobaud_en
FO M
again.
A0090024 HIGHSPEED High Speed Mode Register 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SPEED
Type RW
Reset 0 0


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US IAL
UART sample counter base
0: Based on 16*baud_pulse, baud_rate = system clock frequency/16/{DLH,
EO
DLL}
1:0 SPEED 1: Based on 8*baud_pulse, baud_rate = system clock frequency/8/{DLH, DLL}
3: Based on sampe_count * baud_pulse, baud_rate = system clock frequency
hk T
/ (sampe_count+1)/{DLM, DLL}
m. EN
SAMPLE_COUN
A0090028 Sample Counter Register 00
T
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset .co ID 0 0 0
SAMPLECOUNT
0
RW
0 0 0 0
sac NF
7:0 SAMPLECOUNT Only useful when HIGHSPEED mode = 3.
O
A009002C SAMPLE_POINTSample Point Register FF

u@ C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SAMPLEPOINT
Type RW
Reset 1 1 1 1 1 1 1 1
.Li K

no TE
SAMPLE_POINT is usually (SAMPLE_COUNT-1)/2 without decimal. Effective

7:0 SAMPLEPOINT
only when HIGHSPEED=3.
Ar IA
AUTOBAUD_RE
A0090030 Auto Baud Monitor Register 00
G
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ED
Name BAUD_STAT BAUD_RATE

Type RU RU
Reset 0 0 0 0 0 0 0 0

FO M
7:4 BAUD_STAT Autobaud state (only true value in standard autobaud detection)
0: Autobaud is detecting.
1: AT_7N1
2: AT_7O1
3: AT_7E1
4: AT_8N1
5: AT_8O1
6: AT_8E1
7: at_7N1


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8: at_7E1
US IAL
9: at_7O1
10: at_8N1
11:
EO
at_8E1
12: at_8O1
13: Autobaud detection fails
3:0 BAUD_RATE Autobaud baud rate (only true value in standard autobaud detection)
hk T
0: 115,200
1: 57,600
2: 38,400
m. EN
3: 19,200
4: 9,600
5: 4,800
6: 2,400
7: 1,200
.co ID 8:
9: 110
300
sac NF
A0090034 RATEFIX_AD Clock Rate Fix Register 00
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTO
FREQ BAUD RATE
Name
O
_SEL _RAT _FIX

E_FIX
Type RW RW RW
u@ C
Reset 0 0 0

.Li K
2 FREQ_SEL 0: Select 26MHz as system clock

1: Select 13MHz as system clock
no TE
1 AUTOBAUD_RATE_FI 0: Use 52MHz as system clock for UART auto baud detection
X 1: Use 26MHz/13MHz (depending on FREQ_SEL) as system clock for UART
auto baud detection
0 RATE_FIX 0: Use 52MHz as system clock for UART TX/RX
1: Use 26MHz/13MHz (depending on FREQ_SEL) as system clock for UART
Ar IA
TX/RX
R ED
AUTOBAUDSA
A0090038 Auto Baud Sample Register 0D
MPLE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name AUTOBAUDSAMPLE
FO M
Type RW
Reset 0 0 1 1 0 1

clk diveision for autobaud rate detection
For standard baud rate detection.
5:0 AUTOBAUDSAMPLE System clk 52m: 'd 27


MT2503D
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For non-standard baud rate detection.
US IAL
:15.
EO
A009003C GUARD Guard Time Added Register 0F
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
hk T
Name GUAR
GUARD_CNT
D_EN
Type RW RW
m. EN
Reset 0 1 1 1 1

4 GUARD_EN Guard interval add enabling signal
3:0
.co ID
GUARD_CNT
0: No guard
1: Add guard interval after stop bit.
Guard interval count value
interval added
sac NF
Guard interval = [1/(system clock/div_step/div)]*GUARD_CNT.
A0090040 ESCAPE_DAT Escape Character Register FF

O
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ESCAPE_DAT
Type RW
u@ C
Reset 1 1 1 1 1 1 1 1

.Li K
Escape character added before software flow control data and escape
character
7:0 ESCAPE_DAT
no TE
If TX data are xon (31h), with esc_en =1, UART will transmit data as esc +
CEh (~xon).
Ar IA
A0090044 ESCAPE_EN Escape Enable Register 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ESC_
Name
EN
R ED
Type RW
Reset 0

FO M
Adds escape character in transmitter and removes escape character in

receiver by UART
0 ESC_EN 0: Does not deal with the escape character
1: Add escape character in transmitter and remove escape character in
receiver


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A0090048 SLEEP_EN Sleep Enable Register 00
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US IAL
SLEE
Name P_EN
EO
Type RW
Reset 0
hk T
For sleep mode issue
0: Does not deal with sleep mode indicate signal
m. EN
0 SLEEP_EN 1: Activate hardware flow control or software control according to software
initial setting when the chip enters sleep mode. Release hardware flow when
the chip wakes up. However, for software control, UART sends xon when
awaken and when FIFO does not reach threshold level.
A009004C
Bit 15
.co ID
DMA_EN
14 13 12
DMA Enable Register
11 10 9 8 7 6 5 4 3 2 1 0
00
sac NF
TO_C
TX_D RX_D
FIFO_l NT_A
Name sr_sel UTOR
MA_E MA_E
N N
ST
Type RW RW RW RW
O
Reset 0 0 0 0
u@ C

3 FIFO_lsr_sel Selects FIFO LSR mode
0: LSR will hold the first line status error state until you read the LSR register.
1: LSR will update automatically.
.Li K
2 TO_CNT_AUTORST Time-out counter auto reset register

0: After RX time-out happens, SW shall reset the interrupt by reading UART
no TE
0x4C.
1: The time-out counter will be auto reset. Set this register when Rain's new
DMA is used.
1 TX_DMA_EN TX_DMA mechanism enabling signal
0: Does not use DMA in TX
Ar IA
1: Use DMA in TX. When this register is enabled, the flow control will be based
on the DMA threshold and generate a time-out interrupt for DMA.for DMA.
0 RX_DMA_EN RX_DMA mechanism enabling signal
R ED
0: Does not use DMA in RX

1: Use DMA in RX. When this register is enabled, the flow control will be
based on the DMA threshold and generate a time-out interrupt
FO M
A0090050 RXTRI_AD Rx Trigger Address 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RXTRIG
Type RW
Reset 0 0 0 0


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When {rtm,rtl}=2'b11, the RX FIFO threshold will be Rxtrig. The value is
US IAL
3:0 RXTRIG
suggested to be smaller than half of RX FIFO size, which is 32 bytes.
EO
A0090054 FRACDIV_L Fractional Divider LSB Address 00
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
hk T
Name FRACDIV_L
Type RW
m. EN
Reset 0 0 0 0 0 0 0 0

Adds sampling count (+1) from state data7 to data0 to contribute fractional
7:0 FRACDIV_L
divisor.only when high_speed=3.
.co ID
sac NF
A0090058 FRACDIV_M Fractional Divider MSB Address 00
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FRACDIV_M
Type RW
Reset 0 0
O

u@ C
Adds sampling count when in state stop to parity to contribute fractional

1:0 FRACDIV_M
divisor.only when high_speed=3.
.Li K
A009005C FCR_RD FIFO Control Register 00

no TE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFTL1_RFTL TFTL1_TFTL
Name CLRT CLRR FIFOE
0 0
Type RO RO RO RO RO
Reset 0 0 0 0 0 0 0
Ar IA

R ED

0: 1
1: 6
2: 12
3: RXTRIG
FO M

0: 1
1: 4
2: 8
3: 14
2 CLRT 0: TX FIFO is not cleared.
1: TX FIFO is cleared.


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1 CLRR 0: RX FIFO is not cleared.
US IAL
1: RX FIFO is cleared.
EO
0: RX and TX FIFOs are not enabled.
1: RX and TX FIFOs are enabled.
hk T
m. EN
3.9 UART3

.co ID
sac NF
O
transmit and receive FIFOs. Eight modem control lines and a diagnostic loop-back mode are
provided. The UART also includes two DMA handshake lines, used to indicate when the FIFOs are
u@ C
ready to transfer data to the CPU. Interrupts can be generated from any of the 10 sources.
Note: The UART has been designed so that all internal operations are synchronized by the CLK
.Li K
signal. This synchronization results in minor timing differences between the UART and the industry
standard 16550A device, which means that the core is not clock for clock identical to the original
no TE
device.
After a hardware reset, the UART is in M16C450 mode. Its FIFOs can be enabled and the UART can
then enter M16550A mode. The UART adds further functionality beyond M16550A mode. Each of
the extended functions can be selected individually under software control.
Ar IA
The UART provides more powerful enhancements than the industry-standard 16550:
Note: In order to enable any of the enhancements, the Enhanced Mode bit, EFR[4], must be set. If
EFR[4] is not set, IER[7:5], FCR[5:4], IIR[5:4] and MCR[7:6] cannot be written. The Enhanced Mode
R ED
bit ensures that the UART is backward compatible with software that has been written for 16C450 and
16550A devices.
Figure 35 shows the block diagram of the UART3 device.
FO M


MT2503D
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Baud Rate
Generator
US IAL
Baud Divisor
EO
Clock
TX FIFO
hk T
APB
APB Bus
BUS RX FIFO
RX Machine
m. EN
I/F Uart_rx_data
.co ID Figure 37. Block Diagram of UART3

sac NF
3.9.2 Register Definitions
Module name: UART3 Base address: (+A00A0000h)
O
A00A0000 RBR 8 RX Buffer Register

*NOTE:onnly when LCR[7] = 0.
u@ C
A00A0000 THR 8 TX Holding Register

*NOTE:only when LCR[7] = 0.
A00A0000 DLL 8 Divisor Latch (LS)
uesd to divid the bclk frequency .*NOTE: modified when LCR[7]!=0
.Li K
A00A0004 IER 8 Interrupt Enable Register

*NOTE:onnly when LCR[7] = 0.
no TE
By storing a '1' to a specific bit position, the interrupt associated with that bit
is enabled. Otherwise, the interrupt is disabled.
IER[3:0] are modified when LCR[7] = 0.
A00A0004 DLM 8 Divisor Latch (MS)
uesd to divid the bclk frequency .*NOTE: modified when LCR[7]!=0
Ar IA
A00A0008 IIR 8 Interrupt Identification Register

*NOTE:only when LCR!=BF'h. priority is from high to low as
following .IIR[5:0]==0X1: no interrupt pending .IIR[5:0]==0X6:line status
interrup(Under IER[2]=1). IIR[5:0]==0Xc:rx data timeout interrup(Under
R ED
IER[0]=1). IIR[5:0]==0X4:RX Data is placed in the RX Buffer Register or the

RX Trigger Level is reached.(Under IER[0]=1) .
IIR[5:0]==0X2: TX Holding Register is empty or the contents of the TX FIFO
have been reduced to its Trigger Level(Under IER[1]=1).
IIR[5:0]==0X10: XOFF character recieved (Under IER[5]=1,EFR[4] = 1).
A00A0008 FCR 8 FIFO Control Register
FO M
FCR is used to control the trigger levels of the FIFOs, or flush the FIFOs.
A00A0008 EFR 8 Enhanced Feature Register
*NOTE: Only when LCR=BF'h
A00A000C LCR 8 Line Control Register
Line Control Register. Determines characteristics of serial communication
signals.


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A00A0010 MCR 8 Modem Control Register
Modem Control Register. Control interface signals of the UART.
US IAL
A00A0010 XON1 8 XON1 Char Register
EO
*Note: XON1modified only when LCR=BF'h.
A00A0014 LSR 8 Line Status Register
Line Status Register.
hk T
A00A0018 XOFF1 8 XOFF1 Char Register
*Note: , XOFF1 modified only when LCR=BF'h.
m. EN
A00A001C SCR 8 Scratch Register
A general purpose read/write register. After reset, its value is un-defined.
A00A0020 AUTOBAUD_EN 8 Auto Baud Detect Enable Register
A00A0024 HIGHSPEED 8 High Speed Mode Register
A00A0028
.co ID
SAMPLE_COUNT 8 Sample Counter Register
When HIGHSPEED=3, the sample_count is the threshold value for UART
sample counter
(sample_num).
sac NF
A00A002C SAMPLE_POINT 8 Sample Point Register
When HIGHSPEED=3, UART gets the input data when
sample_count=sample_num.
e.g. system clock = 13MHz, 921600 = 13000000 / 14
sample_count = 13 and sample point = 6 (sample the central point to
O
decrease the inaccuracy)

The SAMPLE_POINT is usually (SAMPLE_COUNT-1)/2 and remove the
decimal.
u@ C
A00A0030 AUTOBAUD_REG 8 Auto Baud Monitor Register

the autobaud detection state ,it will not change until enable the
autobaud_en again.
A00A0034 RATEFIX_AD 8 Clock Rate Fix Register
.Li K
A00A0038 AUTOBAUDSAMPLE 8 Auto Baud Sample Register

Since the system clock may change, autobaud sample duration should
change as system clock changes.
no TE
When system clock = 13MHz, autobaudsample = 6; when system clock =

26MHz, autobaudsample = 13;When system clock = 52MHz,
autobaudsample = 27.
A00A003C GUARD 8 Guard time added register
A00A0040 ESCAPE_DAT 8 Escape character register
Ar IA
A00A0044 ESCAPE_EN 8 Escape enable register

A00A0048 SLEEP_EN 8 Sleep enable register
A00A004C DMA_EN 8 DMA enable register
R ED
A00A0050 RXTRI_AD 8 Rx Trigger Address

A00A0054 FRACDIV_L 8 Fractional Divider LSB Address
A00A0058 FRACDIV_M 8 Fractional Divider MSB Address
A00A005C FCR_RD 8 FIFO Control Register
FO M
A00A0000 RBR RX Buffer Register 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RBR
Type RU
Reset 0 0 0 0 0 0 0 0


MT2503D
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7:0 RBR Read-only register. The received data can be read by accessing this register.
US IAL
EO
A00A0000 THR TX Holding Register 00
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
hk T
Name THR
Type WO
Reset 0 0 0 0 0 0 0 0
m. EN
7:0 THR TX Holding Register. Write-only register. The data to be transmitted is written to
this register, and then sent to the PC via serial communication.
.co ID only when LCR[7] = 0.

sac NF
A00A0000 DLL Divisor Latch (LS) 01
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DLL
Type RW
Reset 0 0 0 0 0 0 0 1
O

u@ C
7:0 DLL divisor Latch low 8bit data.

*NOTE: modified when LCR[7]!=0
.Li K
A00A0004 IER Interrupt Enable Register 00

no TE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name XOFFI ELSI ETBEI ERBFI
Type RW RW RW RW
Reset 0 0 0 0
Ar IA

R ED
5 XOFFI Masks an interrupt that is generated when an XOFF character is received.

FO M
2 ELSI When set ("1"), an interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes
set.
1 ETBEI When set ("1"), an interrupt is generated if the TX Holding Register is empty or the
contents of the TX FIFO have been reduced to its Trigger Level.
0: No interrupt is generated if the TX Holding Register is empty or the contents of the TX
FIFO have been reduced to its Trigger Level.
1: An interrupt is generated if the TX Holding Register is empty or the contents of the TX
FIFO have been reduced to its Trigger Level


MT2503D
Confidential A
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0 ERBFI When set ("1"), an interrupt is generated if RX Data is placed in the RX Buffer
Register or the RX Trigger Level is reached.
0: No interrupt is generated if RX Data is placed in the RX Buffer Register or the RX
US IAL
Trigger Level is reached.
1: An interrupt is generated if RX Data is placed in the RX Buffer Register or the RX
EO
Trigger Level is reached.
hk T
A00A0004 DLM Divisor Latch (MS) 00
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m. EN
Name DLM
Type RW
Reset 0 0 0 0 0 0 0 0

7:0 DLM
.co ID divisor Latch high 8bit data..

*NOTE: modified when
division by 1 generates a BAUD signal that is constantly high.

Note: DLL & DLM setting formula is
LCR[7]!=0
Note: DLL & DLM can only be updated when DLAB(LCR[7]) is set to 1, Note to that
{DLH,DLL}=(system clock
sac NF
frequency/baud_pulse/baud_rate).
When RATE_FIX(RATEFIX_AD[0])=1 and RATE_FIX(RATEFIX_AD[2])=0, system
clock frequency = 26MHz.
When RATE_FIX(RATEFIX_AD[0])=1 and RATE_FIX(RATEFIX_AD[2])=1, system
clock frequency = 13MHz.
O
For baud_pulse value refer to HIGH_SPEED(offset=24H) register.

e.g. When 52MHz,default speed mode and 115200 baud rate, the
{DLH,DLL}=52MHz/16/115200=28.
u@ C
.Li K
A00A0008 IIR Interrupt Identification Register 01

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FIFOE ID
no TE
Type RO RU
Reset 0 0 0 0 0 0 0 1

Ar IA
7:6 FIFOE
5:0 ID IIR[5:0] Priority Level Interrupt Source
000110 1 Line Status Interrupt:
R ED

001100 2 RX Data Timeout:
Timeout on character in RX FIFO. (Under IER[0]=1)
000100 3 RX Data Received:
RX Data received or RX Trigger Level reached. (Under IER[0]=1)
000010 4 TX Holding Register Empty:
FO M
000000 5 Modem Status change:

DCTS set in MSR. (Under IER[3]=1)
TX Holding Register empty or TX FIFO Trigger Level reached. (Under IER[1]=1)
010000 6 Software Flow Control:
100000 7 Hardware Flow Control:
Line Status Interrupt: A RX Line Status Interrupt (IIR[5:0] == 000110b) is generated if

ELSI (IER[2]) is set and any of BI, FE, PE or OE (LSR[4:1]) becomes set. The interrupt
is cleared by reading the Line Status Register.


MT2503D
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RX Data Timeout Interrupt:When virtual FIFO mode is disabled, RX Data Timeout
Interrupt is generated if all of the following apply:
1. FIFO contains at least one character;
US IAL
2. The most recent character was received longer than four character periods ago
3. The most recent CPU read of the FIFO was longer than four character periods ago.
EO
The timeout timer is restarted on receipt of a new byte from the RX Shift Register, or on
a CPU read from the RX FIFO.
The RX Data Timeout Interrupt is enabled by setting EFRBI (IER[0]) to 1, and is cleared
by reading RX FIFO.
When virtual FIFO mode is enabled, RX Data Timeout Interrupt is generated if all of the
hk T
following apply:
1. FIFO is empty;
2. The most recent character was received longer than four character periods ago
m. EN
3. The most recent CPU read of the FIFO was longer than four character periods ago.
The timeout timer is restarted on receipt of a new byte from the RX Shift Register or
reading DMA_EN register.
The RX Data Timeout Interrupt is enabled by setting EFRBI (IER[0]) to 1, and is cleared
by reading DMA_EN register.
.co ID RX Data Received Interrupt: A RX Received interrupt (IER[5:0] == 000100b) is

generated if EFRBI (IER[0]) is set and either RX Data is placed in the RX Buffer
Register or the RX Trigger Level is reached. The interrupt is cleared by reading the RX
Buffer Register or the RX FIFO (if enabled).
sac NF
TX Holding Register Empty Interrupt: A TX Holding Register Empty Interrupt (IIR[5:0] =
000010b) is generated if ETRBI (IER[1]) is set and either the TX Holding Register is
empty or the contents of the TX FIFO have been reduced to its Trigger Level. The
interrupt is cleared by writing to the TX Holding Register or TX FIFO if FIFO enabled.
O
Modem Status Change Interrupt: A Modem Status Change Interrupt (IIR[5:0] = 000000b)
is generated if EDSSI (IER[3]) is set and e DCTS (MSR[3:0]) becomes set. The
interrupt is cleared by reading the Modem Status Register.
u@ C
Software Flow Control Interrupt: A Software Flow Control Interrupt (IIR[5:0] = 010000b)
is generated if Software Flow Control is enabled and XOFFI (IER[5]) becomes set,
indicating that an XOFF character has been received. The interrupt is cleared by
reading the Interrupt Identification Register.
.Li K
Hardware Flow Control Interrupt: A Hardware Flow Control Interrupt (IER[5:0] =

100000b) is generated if Hardware Flow Control is enabled and either RTSI (IER[6]) or
no TE
CTSI (IER[7]) becomes set indicating that a rising edge has been detected on either the
RTS/CTS Modem Control line. The interrupt is cleared by reading the Interrupt
Identification Register.
Ar IA
A00A0008 FCR FIFO Control Register 00

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RFTL1_RFTL TFTL1_TFTL
CLRT CLRR FIFOE
R ED
0 0
Type WO WO WO WO WO
Reset 0 0 0 0 0 0 0

FO M
7:6 RFTL1_RFTL0 RX FIFO trigger threshold. (RX FIFO contains total 32 bytes.)
0: 1
1: 6
2: 12
3: RXTRIG
5:4 TFTL1_TFTL0 TX FIFO trigger threshold (TX FIFO contains total 32 bytes.)
0: 1
1: 4
2: 8
3: 14


MT2503D
Confidential A
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2 CLRT control bit to clear tx fifo
0:

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MT2503D SOC Processor Data Sheet

Specifications are subject to change without notice.

© 2015 MediaTek Inc.

[email protected],time=2016-03-29 15:29:32,ip=183.37.111.14,doctitle=MT2503D SOC Processor Data Sheet v1.0.pdf,company=SAC-Wearable_WCX

MediaTek Confidential © 2015 MediaTek Inc. Page 2 of 491

[email protected],time=2016-03-29 15:29:32,ip=183.37.111.14,doctitle=MT2503D SOC Processor Data Sheet v1.0.pdf,company=SAC-Wearable_WCX

1 System Overview ........................................................................................................................ 12

1.2 MODEM Features ............................................................................................................... 18

Multimedia Features ........................................................................................................... 20

1.6 FM Features ....................................................................................................................... 23

1.7 GPS feature ........................................................................................................................ 24

1.8 General Descriptions .......................................................................................................... 26

2 Product Descriptions ................................................................................................................. 28

2.1 Pin Description.................................................................................................................... 28

Ball Diagram ....................................................................................................... 28

2.1.2 Pin Coordination ................................................................................................. 28

2.1.3 Detailed Pin Description ..................................................................................... 31

2.1.4 Pin Multiplexing, Capability and Settings ........................................................... 45

2.2 Electrical Characteristics .................................................................................................... 52

2.2.1 Absolute Maximum Ratings ............................................................................... 52

2.2.2 Recommended Operating Conditions ................................................................ 53

2.2.3 Electrical Characteristics under Recommended Operating Conditions ............. 54

2.3 System Configuration ......................................................................................................... 61

2.3.1 Strapping Resistors ............................................................................................ 61

2.3.2 Mode Selection ................................................................................................... 61

2.4 Power-on Sequence and Protection Logic ......................................................................... 61

MediaTek Confidential © 2015 MediaTek Inc. Page 3 of 491

[email protected],time=2016-03-29 15:29:32,ip=183.37.111.14,doctitle=MT2503D SOC Processor Data Sheet v1.0.pdf,company=SAC-Wearable_WCX

2.5.3 Audio Mixed-Signal Blocks ................................................................................. 67

2.6.2 BOOST ............................................................................................................... 74

2.6.3 ISINK and KPLED Switches ............................................................................... 74

2.7.1 General Description............................................................................................ 82

2.7.2 Functional Block Diagram .................................................................................. 83

2.7.3 Electrical Characteristics .................................................................................... 83

2.8.1 Block Description................................................................................................ 87

2.8.2 Functional Specifications ................................................................................... 88

2.9.1 Block Description ................................................................................................ 90

2.9.2 Functional Specifications ................................................................................... 91

2.10 Package Information ........................................................................................................... 92

2.10.1 Package Outlines ............................................................................................... 92

2.10.2 Thermal Operating Specifications ...................................................................... 95

2.10.3 Lead-free Packaging .......................................................................................... 95

2.11 Ordering Information ........................................................................................................... 95

2.11.1 Top Marking Definition ....................................................................................... 95

3 Micro-Controller Unit Peripherals ............................................................................................. 96

3.1 Pulse-Width Modulation Outputs (2 Channel) .................................................................... 96

MediaTek Confidential © 2015 MediaTek Inc. Page 4 of 491

[email protected],time=2016-03-29 15:29:32,ip=183.37.111.14,doctitle=MT2503D SOC Processor Data Sheet v1.0.pdf,company=SAC-Wearable_WCX

3.2.1 Register Definition ............................................................................................ 103

3.2.4 Answering to Reset Sequence ......................................................................... 118

3.2.5 SIM Data Transfer ............................................................................................ 119

3.3.1 General Description.......................................................................................... 122

3.4 General Purpose Inputs/Outputs ...................................................................................... 132

3.4.1 General Description.......................................................................................... 132

3.4.2 Register Definitions .......................................................................................... 133

3.5 General-purpose Timer .................................................................................................... 269

3.5.1 General Descriptions ........................................................................................ 269

3.5.2 Register Definition ............................................................................................ 270

3.5.3 Application Note ............................................................................................... 273