An460 P82B96
An460 P82B96
AN460
Using the P82B96 for bus interface
2001 Feb 14
Philips Semiconductors Application note
The P82B96 offers many different ways in which it can be used as a There are also some issues which need to be considered in
bus interface. In its simplest application it can be used as an protecting the P82B96 from spurious signals in a bus line installed
interface between bus systems operating from different supply over a long distance, or where signals may be picked up which
voltages. Opto isolation between two bus systems is possible, and exceed the supply rail levels.
also the availability of the Tx and Rx signals permits interfacing of
the P82B96 with other bus systems which separate the forward
output path, from the backward input signal path. INTERFACING DIFFERENT SUPPLY/LOGIC
The fixed, low, logic levels used at Sx imply a restriction that the I2C LEVELS
bus connection on this chip should be used only with small I2C Figure 1 shows P82B96 applied with the I/O pins Tx and Rx linked
systems, contained typically on one printed circuit board, and not to provide a new bus with the same protocol and properties as I2C
connected with long wiring which could introduce noise. but operating at different logic levels. Because Tx has an open
It is the intention that the P82B96 be used as an interface to long or collector output a pull-up resistor is applied.
noisy bus systems so that the function of each local I2C bus node Supply voltages in the range 2 V to 15 V are permitted, allowing
remains within specification, and the P82B96 handles the more interfacing from a conventional 5 V I2C bus to 3 V logic systems or
difficult interfacing tasks. low current bus systems such as SMB with 350 µA pull-down
Series resistors in the SDA/SCL lines should also be avoided in the current. It must be remembered that the input threshold at Rx on the
Sx lines at I2C nodes that include P82B96. buffered bus side is nominally at one half of the VCC voltage.
A further implication of the way in which the P82B96 functions is that Hence longer cable runs and ground potential differences can be
if two P82B96 chips have their Sx pins connected to the same I2C accommodated by using a 15 V supply to improve noise immunity
node, then signals from the Rx input of one P82B96 will not while retaining the simplicity of I2C wiring.
propagate to Tx on the other. This is dictated by the non-latching
requirement that they must not propagate back to Tx within one The oscilloscope traces, Figures 2 and 3, show the waveforms at
chip. Tx, Rx, and Sx when Tx is not linked to Rx. Tx has a 330Ω pull-up to
the chip supply of 10 V, Sx has a 1600Ω pull-up to a 5 V supply.
As the buffered output of the P82B96 has increased drive capability There is no external capacitive bus loading. The propagation delay
over the normal I2C specification, these limitations do not present for signals from Sx to Tx is about 100ns, and from Rx to Sx it is
any great restriction. The buffered side can be used for about 300ns.
interconnection, and distance.
+VCC (2–15 V)
+5 V
R1
I2C
‘SDA’
SDA
(NEW LEVELS)
Tx
(SDA)
Rx
(SDA)
1/2 PB2B96
NOTE: The logic voltages and currents at ‘SDA’ are set by VCC and pull-up.
EXAMPLE: ‘SMB’ bus llow = 350 mA, use VCC = 5 V and pull-up R1 = 13 KW SU01021
Tx Rx
10V
Sx
Sx 5V
0V
CH1!2.00V = AVG CH1!2.00V = AVG
CH2!2.00V = BWL MTB 200ns – 0.98dvch1+ CH2!2.00V = BWL MTB 200ns – 0.98dvch1+
Horiz: 200ns/div. VertL 2V/div. SU01069 Horiz: 200ns/div. VertL 2V/div. SU01070
2001 Feb 14 2
Philips Semiconductors Application note
GALVANIC BUS ISOLATION Low speed applications can include: Driving remote displays,
In Figure 4 the Tx and Rx signals are shown interfaced via security systems, access control systems, data logging, remote
opto-couplers to provide galvanic separation. control of appliances or lighting. Isolation can simply be included in
I2C systems at any point on the bus where safety isolation or ground
This simple circuit can use general purpose 4N36 opto-couplers potential differences require it.
having published switching times around 50µs for the load
impedances shown. That will limit the design bus clock speed to Figure 5 shows how faster opto-couplers can be applied to achieve
around 5kHz. Simple circuits like this can probably reach 20kHz by full 100kHz clock speed.
changing the type of opto-coupler or the circuit values.
+VCC +VCC1
R4
R2
R5
R3
I2C
SDA
+5 V
Rx
(SDA)
R1
I2C
SDA Tx
(SDA)
1/2 P82B96
+5 V 6N137 +5 V
x2
*0.1 mF
2K2 560 560
USUAL I2C
PULL-UP
USUAL I2C
PULL-UP
I2C
SDA
I2C
SDA Tx
(SDA)
6 7 8 2
Rx
(SDA)
5 3
2N2907
2001 Feb 14 3
Philips Semiconductors Application note
+VCC +VCC
+5 V +5 V
I2C I2C
SDA SDA
Tx TxD canh TxD Tx
(SDA) (SDA)
canl
Rx RxD RxD Rx
(SDA) (SDA)
1/2 PB2B96 1/2 PB2B96
PCA82C250 PCA82C250
+VCC
+5 V
I2C
SDA
TxD Tx
(SDA)
RxD Rx
(SDA)
1/2 PB2B96
PCA82C250
LINE TERMINATION
2001 Feb 14 4
Philips Semiconductors Application note
+VCC = 15 V +VCC = 15 V
+5 V +5 V
1K 1K
SDA SDA
Tx Tx
NOTE: Schottky diode and zener clamps applied to limit spurious signals SU01020
Power dissipation under fault conditions With Tx connected to Rx, when it reaches 50% of the VCC supply
The current drive capability of the buffered Tx and Ty outputs voltage the Rx input senses that Tx has been released, and returns
exceeds 100 mA. If a wiring fault causes a short from these pins to a ‘high’ signal to its output at Sx, allowing this voltage to continue its
VCC (or to a buffered bus supply when using different supplies) then rise again towards the I2C supply. It will be recognized as high by
high dissipations result when Sx or Sy are driven low. The rated 300 other I2C chips when it reaches their logic threshold. Typical
mW dissipation can be exceeded within a very short time. waveforms are shown in Figure 8.
Appropriate precautions should be taken to ensure that such a This delay in termination of the low signal on Sx will be further
short-circuit does not occur. extended if Tx and Rx are not directly linked and there are other
delays inherent in the signal path between Tx and Rx. Including slow
Bus characteristics and rise/fall times opto-couplers in the loop will exaggerate these delays (see Figure 4).
In general terms, the rise times which will be observed on a bus
driven by the P82B96 will be simply determined by the pull-up
resistor used and the total capacitive load presented to the bus.
ch1: freq = 624 kHz
The fall time is determined mostly by the dynamic pull down current
Rx/Tx
capability and the capacitive load, with some modification caused by
the varying current in the bus pull up resistor.
The effective logic signal propagation time will depend on the input
logic thresholds of the P82B96, and of any other devices connected Sx
to the I2C or buffered bus.
On a 2 V supply, the Sx and Sy thresholds are approaching half the
supply rail. On a 5V supply their (0.65V) threshold is much closer to
GND than usual for logic inputs. This causes some additional delay
in the effective propagation time on falling edges, and reduces those
delays on the rising edges. Horiz: 200ns/div. VertL 2V/div. SU01071
For Rx and Ry, the threshold is always 50% of VCC so switching Figure 8. Low to High propagation of Sx with Tx linked to RX
levels are ‘conventional’ when the buffered bus pull-ups are Sx = 5V I2C bus, Tx = buffered bus with pull-up to VCC = 10V
connected to VCC. However, if the buffered bus pull-ups connect to a
supply voltage different to VCC, the rise/fall times required to reach
the Rx threshold may need to be taken into account.
2001 Feb 14 5
Philips Semiconductors Application note
Terminology capability in one direction only. Its two sides are linked by an internal
Because the I2C bus handles bi-directional data flow, any buffer 30 Ω resistor. This means that the loading on one side of the chip is
device must be bi-directional. So inputs are also outputs. Describing always part of the loading seen at the other side. It does not allow
a buffer operation without reference to ‘input’ and ‘output’ signals different logic levels between busses having different voltages. The
presents difficulties: forgive the occasional use of these descriptions. bus voltages on each side of P82B715 are always matched within
100 mV.
We also make assumptions about the possible system connections
to the chip, but these should not be taken to imply restrictions. In The P82B96 is not pin-compatible with the P82B715, but its 30 mA
many of the applications described it would also be possible to static sink capability will overlap some P82B715 applications.
exchange the terms ‘I2C’ and ‘Buffered’ bus. P82B96 can also directly drive the 10x load that P82B715
drives — and P82B96 extends operation down to 2 V supply.
Sx and Sy: the I2C side
We have named one side of the P82B96 the ‘I2C’ side (Sx and Sy).
We intend that this I/O pin will mostly be connected to a normal 5V P82B96 FEATURES
I2C bus comprising just a few chips and short wiring — for example
a system not more complex than the I2C demonstration boards such Buffered bus drive capability
as OM4151 or OM1016. While this I/O pin is COMPATIBLE with The 30 mA buffered bus static sink capability is useful when driving
normal I2C signals, the logic voltage thresholds we use on this ‘I2C’ opto-couplers.
pin are non-standard.
It is also possible to drive low impedance, high voltage, long busses
Tx, Rx, and Ty, Ry: the buffered side directly from the P82B96, but the overall performance will be
The other side of the chip features the separated input and output dependent on the characteristics of the bus and it is difficult to fully
pins Tx and Rx. While that provides the possibility to include address this in the specifications for the P82B96.
opto-couplers or to interface to other bus systems, in many
1. The 30 mA Tx and Ty outputs do not guarantee full 100 kHz
applications those two pins will simply be linked together to form an
operation when directly driving a long, high voltage bus. This is
I/O with properties exactly the same as any conventional I2C bus
because a 15 V supply and 30 mA static drive implies a
product. We refer to the linked Rx/Tx I/O as the ‘buffered’ bus side.
minimum pull-up resistor of 500Ω. With 500Ω, a 4 nF bus load
This buffered I/O is intended for connection into all the unusual bus means a time-constant of 2 µsecs., which exceeds the I2C
systems — anything from 2 V to 15 V, with currents from microamps risetime specification.
to 30 mA static sink, and conventional 0.4 V saturation. Its input
On 5 V, the 30 mA drive permits a pull-up of 167Ω, so the time
logic threshold adapts to be always half the P82B96 VCC.
constant with a 4 nF bus load easily permits full 100 kHz
When the buffered bus pull-ups return to VCC the buffered bus is operation.
fully I2C compliant.
Typically, applications for long, high voltage, busses will use low
Comparison between the P82B96 and the P82B715 speeds. For example the clock speed will usually be chosen
lower than 30 kHz when working with a bus longer than 100
bus extender meters.
In the P82B96 the I2C and buffered bus loads are independent. The
bus loading on one input does not influence the load to be driven by 2. If the buffered side is used to directly drive long wires then
devices connected to the corresponding ‘buffered’ output. While the ‘ringing’ on the output bus becomes a possibility, with a strong
I2C and buffered ports of one P82B96 share a common GND probability that the I/O pin will be driven below the ground
connection, opto-coupling the buffered signals allows connection to potential.
another I2C bus operating on a separate, isolated ground (Figures 4
The P82B96 does not allow I/O pins to be driven below ground
and 5).
or above 15 V. Therefore for long, ‘dirty’ busses we recommend
This is not the case in the P82B715 bus extender, which operates the use of external schottky diode and zener clamps (Figure 7).
by providing linear x10 current amplification of the bus current sink
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Table 1. Table of drive capability
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Type of application Will drive bus load To guaranteed clock
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Normal 5 V I2C All normal I2C loads 100 kHz
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Low impedance 5 V 1/10 R and 10*C (4 nF) 100 kHz
3.3 V ±10% bus All normal I2C loads 100 kHz
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Low impedance 3.3 V
ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
SMB bus (350 µA)
ÁÁÁÁÁÁÁÁÁÁÁÁ
1/10 normal R, 10*C
All SMB loads
100 kHz
normal SMB specs
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
15 V bus, 500Ω
ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
15 V bus > 500Ω
ÁÁÁÁÁÁÁÁÁÁÁÁ
< 2 nF
> 2 nF
100 kHz
depends on capacitance
2001 Feb 14 6
Philips Semiconductors Application note
Treatment of (unused) I/O pins point there will be no signals transmitted through the chip, and all
In some systems, one or other side of the P82B96 might be required I/Os will become open circuit. That voltage is of the order of 1 V.
to be ‘hot plugged’ to the I2C bus of some other separate equipment.
Margins on switching levels
This will require some pull up capability to be provided on both sides There are certain constraints that determine the two low levels on
of the plug. the I2C bus interface Sx and Sy. The I2C bus must always be driven
Each input pin (Sx or Rx) is a high impedance input and cannot be below the lowest level that guarantees a low on any bus to which it
left floating. Internal pull-ups have not been used because they is connected.
would only pull-up to the IC supply (VCC), thereby demanding that For a normal 5 V I2C bus the minimum low is 1.5 V. The P82B96
VCC cannot be lower than the connected bus voltages. In the guaranteed low level is set well below this, at 1V maximum for the
P82B96 any input may be pulled up to +15 V, independent of VCC. I2C maximum allowed 3 mA. (It assumes a normal 5 V I2C bus on
No currents will flow into the I/O pins (except when outputs drive a the Sx/Sy side of the buffer, but this should not be taken as a
bus low). The inputs are like LM324 inputs, based on PNP input restriction)
transistors, so they source tiny currents when externally driven low. The externally connected I2C chips must, in turn, pull the I2C pin
External pull up resistors fitted at Sx pins should cause the specified below the threshold required to set Tx/Ty low.
minimum 200 µA to flow when that input is low. Those external chips all have a maximum static low specification of
The Rx input should be treated just like any op-amp input and not 0.4 V at 3 mA. Therefore the typical threshold for the Sx and Sy
left floating. A pull-up of 100 K should cope with PCB leakage in inputs is 650 mV at 25°C, with 600 mV as the minimum.
humid conditions. If there was not a difference between the Sx low output (the larger
Diodes have not been fitted between I/O pins and VCC, to allow voltage) at the smallest permitted load current, and the Sx input
them to be pulled to voltages above the chip’s VCC. This permits, for threshold (a lesser voltage) the chip would latch.
example, use of the P82B96 on a 3 V supply, driving a 3 V buffered As the Sx sink current decreases the output low level at Sx decreases.
bus, to interface with a normal 5 V I2C input. It also allows the I2C For this reason a minimum sink current at Sx is specified (200 µA)
busses to remain active even if the P82B96 VCC fails.
The temperature coefficient on the input and output thresholds of Sx
Failure of VCC and consequences for bus and Sy is –2 mV/K.
operation The other side (Tx/Rx and Ty/Ry) is designed for connection to any
The P82B96 maintains its function for VCC below 2 V. At normal bus from 2 V to 15 V.
temperatures it starts to shut off at around 1.2 V. That means that if
the normal VCC supply is 5 V, and that supply was to fall to 2 V, then The typical threshold switching level is 50% of VCC. Tolerances
it just retains normal operation — it cannot ‘release’ the busses even tighter than the normal 70/30% levels have been specified so the
though the supply is now only 40% of normal. guaranteed noise margins, especially when working with long 15V
busses, are improved.
During failure of the VCC power supply no abnormal signals are
caused on any I/O until the supply falls below a value below which
2001 Feb 14 7
Philips Semiconductors Application note
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
2001 Feb 14 8