Review question part one computer organization and addressing mode

Q1/Choose the correct answer in each of the following

1. The 80286 is a ------ microprocessor whereas the 80386 is a --- microprocessor.

a) 12bits-20bits
b) 16bits-32bits
c) 16bits-48bits
d) 8bits-16bits
2. The two units in the 8086up are
a) CU& PU
b) EU&CU
c) BIU&EU
d) BIU&PU
3.. Register of 8086 is either –—or ‫ ــــــــــــ‬in length.
a) 8 OR 16
b) 6 OR 30
c) 12 OR 48
d) 20 OR 42
4. The 8088Mp is

a) 8 bit
b) 16 bit
c) 32 bit
d) 48 bit
5.If the CS =FF59, the range of physical address is:
a) FF590….0F58F
b) 0F58F…..0F5FF
c) FF950…..FF9FF
d) 0F590….0F59F

6. The segment in 80386 real mode:

a) Overlapped
b) Either overlapped or non-overlapped
c) Non-overlapped
d) None of the mentioned
7.In real mode a segment is an area of memory that includes up to
a) 128 Kbytes
b) 512 Kbytes
c) 1M
d) 64 Kbytes

8. The size of physical memory capacity of 80386 is

a) 1M
b) 4M
c) 16M
d) 4G

9. The 80286 is a ------ microprocessor whereas the 80386 is a --- microprocessor.

e) 12bits-20bits
f) 16bits-32bits
g) 16bits-48bits
h) 8bits-16bits

10. The two units in the 8086up are

e) CU& PU
f) EU&CU
g) BIU&EU
h) BIU&PU
11. Register of 8086 is either –—or ‫ ــــــــــــ‬in length.
e) 8 OR 16
f) 6 OR 30
g) 12 OR 48
h) 20 OR 42

12. The processor that has four internal units called.

a) 8086
b) 80286
c) 8088
 d) 8085

13. the 8088Mp is

a) 8 bit
b) 16 bit
c) 32 bit
d) 48 bit

Q2: If DS = 3499H and the offset = 3FB9H, find:

(a) The physical address

(b) The logical address of the data being fetched
(c) The lower and upper range addresses of the data segment

Solution:

(a) Physical address = segment value (shifted left) + offset, therefore;

Physical address = 34990 + 3FB9 = 38949
(b) The logical address = 3499 : 3FB9
(c) Lower range = segment value (shifted left) + 0000, therefore;
The lower range = 34990 + 0000 = 34990
Upper range = segment value (shifted left) + FFFF, therefore;
The upper range = 34990 + FFFF = 4498F

Q3: If an instruction that needs to be fetched is in physical memory location

389F2 and CS = 2700, does the code segment range include it or not? If not, what
value should be assigned to CS if the IP must be = 1282?
Solution:

No, since the range is 27000 to 36FFF, location 389F2 is not included in this range.

- Physical address = Code segment value (shifted left) + IP

389F2 = segment value (shifted left) + 1282 → segment value (shifted left) =
37770 So that the CS value must be 3777

Q4: Assume that the DS register is 578C. To access a given byte of data at physical
memory location 67F66, does the data segment cover the range where the data is
located? If not, what changes need to be made?

Solution:

No, since the range is 578C0 to 678BF, location 67F66 is not included in this
range. To access that byte, DS must be changed so that its range will include that
byte.

Q5: Assume that SP = FF2EH, AX = 3291H, BX = F43CH, and CX = 09. Find the
content of the stack and stack pointer after the execution of each of the following
instructions.

PUSH AX
PUSH BX
PUSH CX
Solution:
Important Note:
 Register CX has a value of 09 but the real size of CX is 16-bit so that we must add
00 in the higher byte of CX, so CX will become 0009 before pushing its value into
the stack.

SS: 09
FF28

SS: 00
FF29

SS: 3C 3C
FF2A

SS: F4 F4
FF2B

SS: 91 91 91
FF2C

SS: 32 32 32
FF2D

SS:
FF2E
Start After After After
SP= FF2E Push AX Push BX
Push CX
SP = FF2C SP = FF2A SP =
FF28

Q6: If SP = 24FC, what is the offset address of the first location of the stack that is
available to push data into?

Solution: 24FB
Q7: Suppose that DS = 1200H, SS = 2000H, EAX = 00001000H, EBX = 00002000H,
ECX = 00003000H, BP = 0100H, and SI = 0250H. Give the type of addressing mode
and determine the physical address for each of the following instructions,
assuming real mode operation:

(a) MOV DL, [100H]

(b) MOV [SI+100H], EDX

(c) MOV CL, [EAX+2*EBX]

(d) MOV [BP+SI], AL

(e) MOV EAX, [EBX+ECX+8]

Solution:

Physical address = segment value (shifted left) + effective address (offset)

(a) Direct addressing

Physical address = 12000 + 100 = 12100H

(b) Register relative addressing

Physical address = 12000 + (0250 + 100) = 12350H

(c) Scaled index addressing

Physical address = 12000 + (00001000 + 00002000 * 2) = 17000H

(d) Base plus index addressing

Physical address = 20000 + (0100+0250) = 20350H

(e) Base relative plus index addressing

 Physical address = 12000 + (00002000 + 00003000 + 8) = 17008H

Q8: Given that BX = 1300H, SI = 2241H, Displacement = C237H.

Assuming real mode operation, determine the effective address (EA) (if
applicable) resulting from the above values when the addressing mode is:

(a) Immediate

(b) Direct

(c) Register addressing

(d) Register relative addressing. (using BX)

(e) Base relative plus index addressing.

Solution:

(a) Not applicable

(b) EA = C237H

(c) Not Applicable

(d) EA = 1300H + C237 = D537H

(e) EA = 1300H + 2241H + C237H = F778H

Q9/ Explain the functions of EU and BIU in the 8086 CPU.

Sol:

EU: is the execution unit responsible for executing instruction.

BIU: is the bus interface unit responsible for fetching the instructions from the
memory unit.

Q10: What are the different between 8088 and 8086?

Solution
In 8086 consist two unit (BIU and execute unit) there are queue of size 6 byte
connect this two units
In 8088 consist two unit (BIU and execute unit) there are queue of size 4 byte
connect this two units
In 8086 internal and external data bus 16 bits
In 8088 internal data bus 16 bits and external 8 bits

Q11: why 8085 cannot implement pipeline and 8086 can implement pipeline?
Solution
8085 has one unit only which is use in fetch and execute stage
8086 has two separate unit one for fetch call BIU and one for execute call execute
unit

Q12/ what is the major difference between 8088 and 8086 CPU?

Sol:

The major difference is that the external data for the 8086 is 16-bit while the 8088
has 8-bit external data bus.8085 consist one unit can not implement pipeline while
8086 consist two unit can implement pipeline

Q13/ give the size of address bus and physical memory capacity of the following

a. 8086 b. 80286 c. 80386

Sol

8086 80286 80386

Address bus 20-bit 24-bit 32-bit
Physical 1MB 16MB 4GB
memory
capacity

Q14/ state the major difference between the 80386 and 80386sx

Sol:

The major difference between 80386 and 80386sx is

80386 80386sx
External data 32-bit 16-bit
bus
Address bus 32-bit 24-bit

Q15/ list additional features of the 80286 CPU that were not present in the 8086
CPU.

Sol:

8086 80286
Physical 1MB 16MB
memory
Address bus 20-bit 24-bit

Q16/ state the difference between the physical address and logical address? List
three possible logical addresses corresponding to physical address 143F0.

Sol:

The physical address: is the 20-biy address that is actually put and decoded by the
memory interfacing circuitry.

The logical address: consists of a segment value and an offset address.

The possible logical addresses for 143F0 are

1- 143F:0000
2- 1430:00F0
3- 1400:03F0

Q17/ how large is the segment in 8086? Can the physical address 346E0 be the
starting address for a segment? Why or why not?

Sol:

The segment size in 8086 CPU is 64KB

Yes because 346E0 is evenly divisible by 16

Q18/ what is meant by addressing mode?

Sol: addressing mode allows the CPU to access operands (data) in various ways.

Q19/ make list of addressing modes available on the 80386.

Sol:

1- Register
2- Immediate
3- Direct
4- Register indirect
5- Based relative
6- Indexed relative
7- Base index relative
8- Scaled-index.

Q20/ what are the three elements that can be used to form the effective address of
an operand in the memory?

Sol:

1- Base
2- Index
3- Displacement
Q21/ name the five memory operand addressing modes and give an example for
each case.

Sol:

1- Register indirect ex: MOV AX,[SI]

2- Based relative ex: MOV AL,[BP]+5
3- Index relative ex: MOV AL,[SI]+5
4- Base index relative ex: MOV AH,[BX][SI]+1234H
5- Scaled index ex: MOV AL,[BX][SI*8]+55H

Q22/ Give the addressing mode for each of the following.

a. MOV AX,DS register

b. MOV BX,5678H immediate
c. MOV CX,[3000] direct
d. MOV AL,CH resister
e. MOV [DI],BX register indirect
f. MOV AL,[BX] register indirect
g. MOV DX,[BP+DI+4] base index relative
h. MOV CX, DS register
i. MOV [BP+6], AL base relative
j. MOV AH, [BX+SI+50] base index relative
k. MOV BL,[SI]+10 index relative
l. MOV [BP][SI]+12,AX base index relative

Q23: what are the different between RISC and CISC

Review question part two Intel microprocessor family
Q1: What are the Major changes in the 80386

Solution

1: The data bus was increased from 16 bits to 32 bits

2: All register are extended to 32 bits so that 80286 is 32 bit microprocessor

3: Address bus 32 bit so that provided 232 =4gigabyte of physical memory

4: The paging memory mechanism was introduced

5: A new addressing mode was added

6: Many new bit manipulation instruction were added

7: The 80386 can be switch from protected to real mode by software

Q2: draw the block diagram of 80386

Q3: list all enhancement in 80486

Solution

1:pipeline in 486 allows the processing of up five instruction to be overlapped

.Many 486 instructions are executed in only 1 clock cycle instead of 3 clock in
386

2: it has 8k byte of cache with the core of the CPU

3: Intel used of 1.2 million transistors to produce a math coprocessor on the same
chip

4: Another major addition to the 486 is the use of 4 pins for data parity (DP) which
allows implantation of parity error checking on system board?

5: 80486 involves the burst cycle clocks (performs 4 memory cycle in only 5 refer
a 2_1_1_1 which meant for reading 4 double word in 5 clocks) .While 386
performs 2 clocks each memory cycle refer as 2_2_2-2 which meant for reading 1
double word in 2 clocks).

6: adding 6 new instruction as show in table

(INVD ,INVLPG and WBINVD)work with cache and TLB.

XADD for especial load operand. CMPXCHG instruction in especial comparing

Q4: how 80486 implement pipeline support your answer by drawing

The instruction has five stage In 80486 so that the pipeline stage is broken
down to 5 stage

1:fetch (pre fetch)

2:decode 1

3:decode 2

4: execute
 5: register wrire backt

Figure show how pipeline implemented in 80486

Q5: Find the contents of memory location ES:4000 after executing the following
program

MOV EAX,[2000H]

BSWAP EAX

MOV ES:[4000H]

Assume that memory location

DS: 2000H=87H DS: 2001H=54H DS: 2002H=F2H DS: 2003H=99H

Solution:

1: MOV EAX[2000H]

EAX=87 54 F2 99

2: BSWAP EAX

EAX=99 F2 54 87

3: MOV ES:[4000H],EAX

ES:4000h =99 ES:4001H=F2 ES:4002H=54 ES:4003H=87

Q6: Assume that the values in registers AL=12h and BL=22hand that the byt=wide
memory location DS:2000H contains 12H what results are produce by execute the
instruction

CMPXCHG [2000h],BL

Solution

Since (AL)=(DS:2000H)=12H the zero flag is set and the value of source operand
is loaded into the destination this gives

(AL)=12h

(BL)=22H

(2000h)=22h

Q7: calculate the bus bandwidth of the followings system .assume that both
working with 33 MHz and 386 is zero wait state. also assume that the data is
aligned and in 4 consecutive double word memory locations.

1:386 2:bust mode 486

Solution

Bus bandwidth=(1/bus time) x bus width in byte

1:in 386 each memory cycle time takes 2 clock2 we have

memory cycle=2(1/33 MHz)=2*30 ns=60 ns

bus bandwidth=(1/60 ns)*4 bytes=66 megabyte/second

2: in 486 burst mode 486 performs 4 memory cycle in only 5 clocks

Memory cycle=5/4=1.25 clocks for each 32 bits

Band width=(1/(1.25 *30 ns))4 byte=106.66megabyte/second

Q8: list main Features of the Pentium

Solution

1: In the Pentium, the external data bus 64bits which bring twice as much code and
data into the CPU as 486. This is done by use 8 bus request BE0 to BE7

2: The Pentium has a total of 16kbyte of on chip cache 8k is for code and other 8k
for data. Code cache is write protected .it use Harvard architecture to access two
caches simultaneously. The Pentium's cache organization for both data and code is
2_way set associative

3: The on-chip math processor coprocessor referred to as floating point Unit

(FPU),and also Pentium consist integer unit (IU) responsible for execute integer
type ,FPU use 8 stage pipeline to process instruction , in contrast to the 5 stage
pipeline in (IU) as Show below

4: is superscalar architecture. a large number of transistor where use to put into two
executing unit inside the Pentium (U unit and V unit) .the two instruction can
execute in two unit if there are not depended between them. A complier use job
instruction scheduling to remove dependent. The process of issuing two instruction
to the two execute unit (U and V) are call instruction pairing ,each unit U and V
has instruction cycle of five stage .

5: Branch prediction unit to predict of jumping instruction using BTB(branch

target buffer) of 2 entries
6: the 386 and 486 has a page size 4k for virtual memory. The Pentium provided
4k or 4M for page size .4 k page options make it 386 and 486 compatible while 4M
page size option allows mapping of large program without any fragmentation

7: The Pentium has two set of TLB one for data and one for code. For data 64
entries for 4k page this means that the CPU has access to 256k (64*4k=265k).TLB
for code 32 entries of 4k page size therefore CPU has access 128k of code at any
time

8: The Pentium has both burst read and write cycles while 486 has only read burst

Q 9 :draw the internal architecture of Pentium processor

Q10: what is Intel’s overdrive technology?

Solution

The idea is to increase the internal frequency of CPU while the external l
frequency remains the same the CPU execute code and data internally faster
while motherboard cost remain the same, example 486x2-50 used the internal
frequency 50 MHz but the external frequency 25 MHz
Q11: How Branch prediction work in Pentium

Solution

The Pentium includes a branch prediction unit based on a Branch Target Buffer
(BTB). The BTB is a cache composed of 256 entries. The cache is written each time
a jump instruction is found, in this case the target address is stored in the cache
line. And when an instruction reaches the ID1 stage, its address is sent to the BTB:

Q12: what it meant by Instruction Pairing

Solution

The Pentium fetches two instructions at the same time and checks whether they
can be executed in parallel by the two pipelines (U and V). The two instruction
must not dependence one on other in order to execute in same time.in(V and U)

Q13 how many cache in Pentium II and Pentium III processor

solution

It has two cache

One-chip cache (L1) consist two 16 Kbyte 4-way associative and cache line 32bits.
The cache employ write-back mechanism and use LRU replacement algorithm.
The cache consist 8 bank interleaved on 4 boundaries.

Off-chip (L2) it is 12k it require 4 -10 cycle .if miss the access to main mmiory
take additional 11 cycle

Q14 :What is a Core and how it different from Multi-Core Processor?

Solution

A standard processor has one core (single-core.) Single core processors only
process one instruction at a time (although they do use pipelines internally, which
allow several instructions to be processed together; however, they are still run one
at a time. while
Q15: What is a Multi-Core Processor?

solution

A multi-core processor is composed of two or more independent cores, each

capable of processing individual instructions. A dual-core processor contains two
cores, a quad-core processor contains four cores, and a hexa-core processor
contains six cores.

Q16:Why do I Need Multiple Cores?

solution

Multiple cores can be used to run two programs side by side and when an intensive
program is running (AV Scan, Video conversion, CD ripping etc.) you can utilize
another core to run your browser to check your email etc.

Multiple cores really shine when you’re using a program that can utilize more than
one core (called Parallelization) to improve the program’s efficiency. Programs
such as graphic software, games etc. can run multiple instructions at the same time
and deliver faster, smoother results.

So if you use CPU-intensive software, multiple cores will likely provide a better
experience when using your PC. If you use your PC to check emails and watch the
occasional video, you really don’t need a multi-core processor.

Q17: How many cores do i3, i5, and i7′s have?

A Dual-core processor has two cores.

A Quad-core processor has four cores.

An i3 processor has 2 cores.

An i5 processor has 2 or 4 cores (depending on the model you have.)

An i7 processor has 2, 4 or 6 cores (depending on the model you have.)

Q18: how Pentium pro is both super pipelined and superscalar microprocessor?

Solution

The Pentium pro all x 86 instructions are converted to micro-ops. This conversion
allows an increase in pipeline stages with little difficulty. This means that Pentium
pro, more instruction can be worked on and finished at a time. The Pentium pro
with 12 stage pipelines referred as super-pipelined. Pentium pro has multiple
executing unit capable of work in parallel it is also referred as superscalar. Also,
Pentium pro use what call out-of-order execution to increase the performance of
CPU.

Q19: What is out of order execution? Support your answer by drawing.

The dependency between fetch and execute was resolve by use decoupling the

fetch and execute phases of instruction

In Pentium pro execute instructions as following

Stage 1: Instructions are fetching from memory and decoded them into series of
micro – ops, or RISC type instruction and placed into a pool called instruction
pool. This fetch/decoded of instruction is done in same order as program was
coded by program.

Stage 2: when the micro –ops are placed into instruction pool they can be executed
in any order as long as the data needed is available.

Stage 3: the dispatch/execute unit schedules the execution of micro-ops from

instruction pool subject to availability of needs resources 20-30 instruction can
execute . It is the job of the retire unit to provide the result to program register

According to the order the instruction were coded again .

Stage 4: store the results temporarily such a speculative executing can go 20 -30
instructions deep into program .it is job of retire unit to provide the result to
program according to programmer code order
Q20: draw the internal architecture of Pentium pro
Review question part three descriptor

Q1:chose the correct answer

1. The unit provides a four level protection mechanism for system's code and data
against application program is:

a) Segmentation unit
b) Central Processing Unit
c) Bus interface unit
d) None of mentioned

2. if the contents of the GDTR=00220000FFFF, there are

a) 1024 descriptor tables

b) 8192 descriptor tables
c) (0022000003 *FF) descriptor tables
d) (0022000003 *0F) descriptor tables

3. The GDTR is a

a) 32 bits
b) 16 bits
c) 48 bits
d) 42 bits

4. The size of access right of 80286 is

a) 8 bits
b) 10 bits
c) 14 bits
d) 12 bits

20: The size limit of 80286 is

a) 10 bits
 b) 8 bits
c) 14 bits
d) 12 bits

4. The size of access right of 80386 is

A 10 bits
b 14 bits
c 12 bits
d 8 bits

5: The size limit of 80386 is

e) 20 bits
f) 10 bits
g) 14 bits
h) 12 bits

6: The size limit and base of 80386 is

a) 20 bits 32 bits
b) 10 bits 20bits
c) 14 bits 32bits
d) 12 bits 24bits

7: The size limit and base of 80286 is

a) 16bits 24 bits
b) 10 bits 20bits
c) 14 bits 32bits
d) 12 bits 24bits
8. The segment that will be accessed in the protected mode of 80386Mp are

a) 4Kbyte to4Gbyte
b) 10 to 20 Mbytes
c) 20 to 30 Mbytes
d) 30 to 40 Mbytes

9. A descriptor contains information about.

a) Location
b) Length
c) Access right
d) All above

Q2: What is relocated program or data?

Solution

A re locatable a program meant you can be placed it’s into any area of memory
and executed without change by use segment and offset schema. The memory
segment can be moved to any place in memory system without changing any of
the offset addresses this is accomplished by moving the entire program as block
to new area and then changing only the contents of segment register

Q3 :what are the operation of segment register in protected mode?

Solution

• Protected mode allows access to data and programs located within and
above the first 1MB of memory.
– Microsoft Windows operates in protected mode.
• The segment registers are used differently in protected mode.
 – They no longer store the segment address.
– Instead, they contain a selector that selects a descriptor from a
descriptor table.
• A descriptor table can contain up to 8192 descriptors.
• Each descriptor has 8 byte.
• There are two types of descriptor tables:
– Global descriptors: contain segment definitions that apply to all
programs.
– Local descriptors: unique to an application.
• A descriptor contains information about:
– Memory segment’s location
– Length of the segment
Access rights

Q4: What are the perpouse of access right byt in dscriptor?

This byte describes how segment function in the system .The access right byte
allows complete control over the segment in protected mode

Q5: draw the Descriptor format for 80286 and 80386 and above
Q6: what are the size of limit and base and access right in 80286 and 80386?

Solution

Size of limit in 80286 16 bits and base has 24 bits

While 80386 limit 20 bits and base 32 bits

80286 did not content FS and GS

Size of access right 8 bits in 80286 and 12 bits in 80386

Q7: What are the perpouse of access right byt in dscriptor?

This byte describes how segment function in the system .The access right byte
allows complete control over the segment in protected mode

Q8: draw the register of 80386 in protected mode

Q9: assume the value of descriptor as show below find the start address and end
address and status of descriptor
8F 10 20 00 00 9F D8 30
Byte0 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7

Solution

Base (start address)=(30 00 00 20)16

Limit =(8 10 8F)16

End address =base + limit

End address= (30 00 00 20)16 +(8 10 8F)16 = (30 08 10 AF)16

G= 1 (segment 4k to 4G) AV=1 (segment is available) D=1 (32 bits offset)

Access right = (9F) 16 = (1 0 0 1 1 1 1 1)2

P=1 DPL=00 S =1 E=1 C=1 R=1 A=1

bit 7 bit 6.5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
P=1 segment is mapped into physical memory

DPL=00 privilege level 00

S=1 code or data segment descriptor

E=1 executable code segment

C=1 conforming code segment

R=1 readable code segment

A=1 segment has been accessed

Q10: Assume GDTR = (00 21 00 00 01 FF)16.

LDTR cache = (00 31 00 00 03 CF)16.

1: What is the starting and ending address of the GDT?

2: How large is the table (GDT) in bytes?
 3: How many descriptors can be stored in this table?
4: What is the address range of the second descriptor in the GDT?
5: If a value of 4004H is loaded into ES register, what is the requested
privilege level? What is the address of the segment descriptor?
6: If the selector loaded into LDTR is 0040H, what is the starting address of
the LDT descriptor that is to be loaded into the cache?
7: memory data as
(00 21 00 40)16 = (FF 01 00 30)16
(00 21 00 44)16= (00 9F 50 40)16 what are the base and limit of LDT and how
many descriptor it has?

Solution:

1: start address of GDT GDT start = Base of GDTR= (00210000)16

End address of GDT GDT end = Base of GDTR + Limit of GDTR

= (00210000)16 + (01FF)16 = (002101FF)16

2: GDT size= Limit of GDTR + 1= 01FFH+1= 0200H = 512 bytes

c
3: No. of descriptors = table size / (descriptor size)
= 512 bytes / 8 bytes = 64 descriptors.

4: second t descriptor starts at 00210008H

And ends at 0021000FH.

5: ES = 4004H = (0100 0000 0000 0100)2

RPL= (00) 2 = 0 (Highest).
TI = 1 LDT

Address of the segment descriptor = base of LDTR cache +Index × 8

= 00310000H + 4000H = 00314000H.

 6: Starting address of LDT descriptor = base of GDT + LDTR
= 00210000H + 0040 H = 0210040 H.

7: Base= (40 00 30 00)16

Limit =(0 01 FF)16

Size=limit +1 =(0 01 FF)16 =512

No of descriptor=512/8=64

Q11: Code a descriptor that describes a memory segment that begin at location
(62 11 00)16and ends at location (62 11 FF)16 .this memory segment is code
segment , present ,accessed and that can be read .the descriptor is an 80286
microprocessor

Solution

Base=start=62 10 00 h

Limit= end-start=62 11 FF -62 11 00=(00 FF)h

Access right=10011011=9Bh

A=1 E=1 C=0 R=1 DPL=00 P=1

The descriptor

FF 01 00 10 62 9B 00 00
Byte 0 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7

Q12: If the limit and base in global descriptor table are (0F FF)16 and (00 10 00
00)16.what is begin address of descriptor, size of the table in byte ,how many
descriptor can store and end address of table?
Solution

Begin address=base= (00 10 00 00)16

Size= limit +1 =(0F FF)16+1= (10 00)16 =8192 byte

Number of descriptor= 8192/8=1024 descriptor

Q13:Assume that base address of the LDT is ( 00 12 00 00)16 and the GDT base
address is ( 00 10 00 00)16, if the value of the selector loaded into the CS register is
1007H. What is the requested privilege level? Is the segment descriptor in the GDT
or LDT? What is the start address of the descriptor from descriptor table?

Solution:

CS=(1007)16= (0001 0000 0000 0111)2

RPL=(11)2 =3 =lowest privilege level

TI =1  the segment descriptor is in the LDT

Index = (0001 0000 0000 0)2

Offset = index × 8 = (0001 0000 0000 0)2 × 8

= (0001 0000 0000 0000)2 = 1000H

DESCRIPTOR address = 00120000H + 1000H

= 00121000H

Q14: The access rights byte of segment descriptor content (FE) 16 .what type
segment descriptor does it describes, and what are its characteristics?

Solution

(FE)16=( 1111 1110 )2

Since bit4 (S) is 1 the access right byte is for code/data segment descriptor. This
segment has the characteristics that follow

P=1 segment is mapped into physical memory

DPL=11 privilege level 11

E=1 executable code segment

C=1 conforming code segment

R=1 readable code segment

A=0 segment has not been accessed

Q15: what are the descriptor address and actual address in protected mode if
logical address DS: 10H and DS=13H and

GDTR=(00 00 20 00 00 FF)16

Use instruction MOV Ax.[10H]

Assume the value of selected descriptor is

FF 0F 12 01 14 00 00 00
Byte0 Byte7

Solution

DS=(13 )16= 0000 0000 0001 0011

RPL=11

Table index=0 global descriptor table

Index =2

From GDTR

GDT base =(00 00 20 00)16

GDT limit =00 FF

Descriptor address=GDT base +index *8= (00 00 20 10)16

From descriptor data

Segment base= (00 00 01 00)16 limit=(0F FF)16

Actual memory address= segment base + effective address

= (00 00 01 00)16+(10)16= (00 00 01 10)16

Figure below illustrated the operation

Q16: what are the descriptor address and actual address in protected mode if
logical address DS: 10H and DS=27H

GDTR= (00 00 20 00 00 FF)16 and LDTR=(00 38)16

Use instruction MOV Ax.[10H]

Assume descriptor value as

1F 00 00 00 10 00 00 00
Byte0 Byte7

Solution

DS=(27)16 =(0000 0000 0010 0111)2

RPL=11 lowest

TI=1 local descriptor table

Descriptor address =GDT base +LDTR

=(00 00 20 00)16 +(00 38)16 = (00 00 20 38)16

From memory data descriptor

Segment base= (00 10 00 00)16 limit=(1F 00)16

Actual address= segment base +effective address

(00 10 00 00)16 + (10)16= (00 10 00 10)16

Figure below illustrated the operation

Q17: draw the operation of segment register in protected mode

RPL: Requested privilege level where 00 is the highest and 11 is the lowest.

TI is Table Indicator, TI = 0 Global Descriptor Table.

TI = 1 Local descriptor table.

Selector = select one descriptor from 8192 descriptors in either the global or local
descriptor table.
Review question part four paging

Q1/Choose the correct answer in each of the following

1. The unit that is disabled in real address mode is

a) Paging Unit
b) Central Processing Unit
c) Memory Management Unit
d) Bus Control Unit.

2. The unit that organizes the physical memory in term of pages of 4KB size each
is:
a) Segmentation unit
b) Instruction unit
c) Paging unit
d) Exaction unit

3.The paging unit works under the control of

a) Memory Management Unit
b) Exaction unit
c) Instruction unit
d) Segmentation unit

4. The unit provides a four level protection mechanism for system's code and data
against application program is:
e) Segmentation unit
f) Central Processing Unit
g) Paging unit
h) None of mentioned

4. The unit provides a two level protection mechanism for system's code and data
against application program is:
a) Paging unit
b) Central Processing Unit
c) Segment unit
d) None of mentioned
5. Since the TLB in 386 keep the list of address for 32 most recently used pages it
allows the CPU to have access to
a) 64 Kbytes
b) 512 Kbytes
c) 128 Kbytes
d) 1M

6. In paging to get the address of code or data, the 80386 convert from

a) Physical to Logical
b) Physical to linear
c) Virtual to physical
d) Linear to physical

Q2: what is Virtual Memory?

A CPU with virtual memory is fooled into thinking that it has access to an limited
amount of physical memory (DRAM or main memory). In virtual memory every
time the CPU looks for certain information the operating system will first search
in main memory and if it is not there it will bring it into main memory from
secondary memory (hard disk).by use LRD algorithm

Q3: list all the mechanism using in Virtual memory

To implemented virtual memory, two methods are used:

1: segmentation : it is implemented by use two descriptor GDT and LDT size of

segment vary 1 to M or 4K to 4G

2:paging. It is implemented by using page directory table and page table with
CR3(page directory base address(PDBA) size of paging 4K

Q4: what are the benefit of Presence bit in paging

A presence bit (valid bit) in each location indicates whether the page has been
transformed from auxiliary memory into main memory. A =0 in the presence bit
indicates that this page is not available in main memory. A call to the operating
system is then generated to fetch the required page from auxiliary memory and
place it into main memory before resuming computation.

Q5: what are the benefit of dirty bits in paging

The a dirty bit is use to indicated that the page in main memory has be change or
not change If page altered (update) while residing in main memory this bit=1(
change to page in main memory) otherwise this bit =0 when the page has not
change in main memory?

Q6: how virtual memory reach 64 Tbyte

The are two descriptor each one 8kbyte

The maximum amount of virtual memory

16k * 4 G = 214 * 2 32=2 46= 26 * 240 =64Tbytes

Q7:what are Drawback 0f 80386 segmentation

There are two point of the drawbacks of 80386 segmentation

1: variable segment size, which leads to memory fragmentation.

2: absence of what is call a dirty bit in the access byte of the descriptor table.

Q8: Q: Why should the operating system care if memory is altered(written into
change)?

if the data is altered ,it is the job of operating system to save it on the disk to make
sure that the hard disk always has latest data.

If the dirty bit is zero (D=0).it means that the data has not been altered and the
operating system can leave when it needs room for new data (or code?) Since the
original copy is on hard disk.
If the dirty bit is one (D=1) ,the operating system must save the data before it lost
.both problems of variable segment size and lack of dirty bit in segmentation are
fixed in the paging method of virtual memory

Q9: draw how paged translation liner address to a physical address

Q10: why we use TLB (translation look –aside buffer),support your

answer by drawing
solution
Because the act of re paging a 4K-byte section of memory requires access to the
page directory and page table, which are both located in memory, Intel has
incorporated special type of cache called the TLB (translation look –aside buffer).

This cache used to store the 32 most recent page translation addresses .in this way
we speeds program execution because we did not want to translate the liner
address. if translation is not in TLB , the page directory and page table must be
accessed separate TLBs for each of their instruction and data caches.
Q11:what are the fields of a linear address

In paging, the linear address 32 bits is divided into three parts.

Page directory (A31-A22) 10 bits
Page entry (A21_A12) 10 bits
Offset (A10-A) 12 bits

Q12: draw the Segment translation

 Q13: draw the page translation

Q14 draw the segment and paging addressing mechanism

Q15: Explain using diagram the translation of the linear address (03 01 00 8A)16 to
physical address , if the value of PDBA of CR3 is (00010)16

Assume page directory entry =(05001)16 and page table entry=(00030)16

Solution

(03 01 00 8A)16 =

(0000 0011 00 00 0001 0000 0000 1000 1010)2

Dir =(0000 0011 00) 2= (0C)16

Page =(00 0001 0000)2=(10)16

Offset = (08A)16

Enter to page directory table= CR *8+ (0c*4)=(00 01 00 30)16

This location content =(05001)`16

Entry to page table =(05001)16 *8 +(10)16*4=(05001040)16

This location content=(00030)16

The entry to physical memory =(00030)16+offset=(0003008A)16

Q16: what are the different between segmentation and paging in 80386?

Feature Paging segmentation

Size 4k byte Any size
Level of privilege 2 4
Base address 4k byte aligned Any size
Dirty bit yes no
Review question part five 80386 microprocessor

Q1: What are the Major changes in the 80386 )‫(سؤال مكرر في الجزء الثاني‬

1: The data bus was increased from 16 bits to 32 bits

2: All register are extended to 32 bits so that 80286 is 32 bit microprocessor

3: Address bus 32 bit so that provided 232 =4gigabyte of physical memory

4: The paging memory mechanism was introduced

5: A new addressing mode was added

6: Many new bit manipulation instruction were added

7: The 80386 can be switch from protected to real mode by software

Q2: What is the IOPL (I/O privilege level)

IOPL is used in protected mode operation to select the privilege level for I/O
devices. If the current privilege level is higher or more trusted than the IOPL, then
I/O executes without hindrance .if the IOPL is lower than the current privilege
level, an interrupt occurs, causing execution to suspend, IOPL 00 highest and 11
lower

Q3: draw the block diagram of 80386

Q4 what dose T1 stands for? What happens in this part of bus cycle?

Solution

TI is one of two states of the bus cycle.

During T1 part of bus cycle the 80386 DX outputs the Address of start location
that is be accessed on the address bus in a case of write cycle write data are also
output on the data bus

Q5 What dose T2 stand for ? What happens in this part of bus cycle?

Solution

T2 is one of two states of the bus cycle.

During T2 external devices are to be accepting write data from the data bus and in
case of read cycle .put data on the data bus.

Q6 what dose bus cycle stand for?

solution

A bus cycle is activity preformed whenever a microprocessor access information

in program memory or data memory or input or output device and contain two T
state T1 and T2

Q7 What is mean by address access time?

solution

Is the amount of time that the address must be stable prior to read or write data
Q8 what is ideal state ?

solution

In case of 80386Dx pre fetch queue is already full and the instruction that
currently being executed does not need to access operands in memory .no bus
activity will take place in this case the bus goes into state of mode of operation
known as ideal state.
Q9 what does wait state?

Solution

A wait state can be inserted to extend the duration of 80386DX bus cycle this is
done in response to a request by an event in external hardware instead of an
internal event. In fact READY input of the 803806DX is provided specially for this
purpose.

Q10 what is meant by pipelining of the 80386Dx bus?

Solution

By pipelining we meant that the addressing for the next bus cycle is overlapped
with the data transfer of the prior bus cycle?
Q11 draw the timing diagram for non –pipelined read cycle?

Solution
Q12 draw timing diagram for a non-pipelined write –cycle?

Solution
Q 13 what two type of bus cycle can be performed by 80386DX?

solution

Pipelined bus cycle and non - Pipelined bus cycle.

Q 14 explains using timing signals?

a)Ideal state and wait state

b)Pipelining of the 386 bus

c)What dose T1 stands for? What happens in this part of bus cycle?

Solution
a)Idle state

At completion of bus cycle address for n .another bus cycle is initiated

immediately for address n+1. Sometimes another bus cycle will not be initiated
immediately ,for instance if the 80386DX prefetch queue is already full and the
instruction that is currently being executed does not need to access operand in
memory no bus activity will take place in this case the bus goes into mode of
operation call an idle state as show figure below. Note each Idle state=two CLK2

b)wait state
Wait state

Wait state can be inserted to extend the duration of 80386 bus cycle .this is done in
response to a request by an event in external hardware instead of an internal event.
READY input signal is use fro this purpose .this input signal is sampled in later of
T2 state of every bus cycle to determine if data transfer should be completed as
show in figure 9.13.whem READY logic one indicated that current cycle bus
should not completed as this signal high the read or write data transfer does not
take placed and the current T2 state become wait state (extended the duration of
bus cycle)

c)pipeline in 80386DX bus

In pipeline we mean that address for next bus cycle is overlapped with data transfer
of prior bus cycle .as show in figure above

Q 15 what are five types of data transfer that can tack place the data bus? How
many bus cycle are required for each of the data transfer?

solution

Accessing a byte of data One cycle

Accessing aligned word of data in One cycle
memory
Accessing miss aligned word of data in Two cycle
memory
Accessing aligned double-word of data One cycle
in memory
Accessing miss aligned double-word of Two cycle
data in memory

Q16 :explain non-pipeline read cycle and how 80386 got to wait state

Solution

1:read operation start at the begin of pahse1(0) in the T1 state of bus cycle in this
moment 80386DX output address of double word memory location to be access
on the address bus

2: output the byte enable signal BE0,BE1,BE2 and BE3

3: switch ADS to logic 0 to indicate that a valid address on the address bus at the
end of phase2(0) of T2 ads return to logic 1 inactive

4:bus cycle indicate signal M/IO , D/C and R/W are made valid at the begin of
phase1(0) of T1

5:at the begin of pahse2(0) of T2 of read cycle BS16 is active to indicate whether
the bus 16 bits or 32 bits
6:at the end of T2 the READY input signal tested by 80386DX whether the current
bus cycle completed if it have logic 0 or go to wait state if it logic 1

Q17 :explain the non-pipeline write cycle

1: write operation start at the begin of pahse1(0) of the T1 state ,address ,byte
(BE0 --- BE3), and bus cycle indicate (M/IO ,D/C .W/R 1,1,1 ) are output

2: this output signal are latched by use ADS which is go to logic 0 output in T!

At the end of phase2(0) of T2 ads return to logic 1 inactive

3:80386DX output the data on data bus at the begin of T1 and this data
maintained valid until the end of bus cycle

4:in the middle of T2 BS16 use to select 16 bits or 32 bits

5: at the end of T2 the READY input signal tested by 80386DX whether the
current bus cycle completed if it have logic 0 or go to wait state if it logic 1

Q18:what type of bus cycle is in progress when the bus status code M/IO ,D/C and
W/R Equal 010

Solution

Read from memory

Q6: 80386 -20 running if full speed what duration of bus cycle fro write operation
in no wait state and one wait state

Solution

80386dx-20 running at speed 20 Mhz

T=1/20*106 =50ns

For cycle with out waait two T=100ns

Fro cycle with one wait= 100+50=150ns

Q19: how many CLK2 cycles are in an 80386DX bus cycle that has no wait states?
how many T states are in this bus cycle? what would be the duration of this bus
cycle if 80386DX is operated at CLK2 50 MHz

Solution

Bus cycle =4 CLK2

Bus cycle =2 T

80386dx-50 running at speed 20 Mhz

T=1/50*106 =20ns

For cycle with out wait two T=40ns

Fro cycle with one wait= 40+20=60ns

Review question part six cache memory
Review questions
Q1- Cache is made of __SRAM____ (DRAM, SRAM).

Q2-From which dose the CPU asks for data first, cache or main memory?

solution

Cache memory
Q3-Rank the following from fastest to slowest as far as the CPU is concerned.

(A) Main memory (B) register (C) cache memory

solution

B: Register C: cache memory A: main memory

Q4- In fully associative cache of 512 depth, there will be _512___ comparisons
for each data request.

Q5- Which cache organization requires the least number of comparisons?

Solution

Direct mapping one comparison

Q6- A4-way set associative organization requires 4 comparisons.

Q7-what dose write-through refer to?

solution

Write through: write to both cache and main memory at same time
Q8-which one increases the bus traffic, write-through or write-back?

Solution

Write through
Q9-what does LRU stand for, and how is it used?

solution

LRU:-least recently used algorithm

The cache controller keeps account of which block of cache has been
accessed (used) .this replacement algorithm use with fully associative
and SET associative to swap block of data between cache memory and
main memory with block has maximum count .

Q10-Acache refill policy of 4 lines refers to _(4*4)_16bytes______.

Q11: what is cache memory?

Solution

Cache memory is fast small memory placed between the CPU and main memory.in
order to speed up the system. Cache has a smaller access time in order to reduce
the average memory access time and therefore reduce overall system memory
access time

Q12: what is memory hierarchy’s work?

solution

1: program tend to access data at level K more than then access level K+1

2: level K+1 is slower cheaper per bit and larger than level K

3: for level K the faster and smaller device serves (take block of data from) larger
slower device in level K+1
4: A large pool of memory that costs as much as the cheap Storage near the
bottom, but that serves data to programs at the rate of the fast storage near the top.

Q13: what are the Three types of cache organization?

Solution

Direct-mapping fully associative set associative

Q14: Compare between SRAM and DRAM

Solution

SRAM DRAM
Larger cell-> lower density higher cost Smaller cell->higher density lower cost
per bit per bit
No refresh required Need periodic refresh
Simple read->fast access Complex read ->longer access
Stander IC Special IC process
Natural for integration with logic Difficult to integration with logic circuits
Use in cache memory Use in main memory

Q15: why we use cache memory?

Solution

To speed up the system (memory access) by use faster and expansive SRAM near
to CPU (Cache memory is placed between the CPU and main memory).

it This takes advantage of the speed of SRAM and the high density and cheapness
of DRAM

Q16: What are the advantages and disadvantages of full associative mapped
address technique?

Solution
A: advantages:

1:Any incoming main memory block can be placed in any available cache
block.so that it efficiency use of cache memory high hit rate

Disadvantage:-

1: The search made in the Tag memory requires matching the tag field of the
address with each and every entry in the tag memory lead to a long delay.

Q17: determine the advantages and disadvantages of (direct mapping address)

method.

Solution

A: Advantages:

1 Simplicity direct determination of the cache block. One compression

Disadvantage:

1: Poor usage of the cache memory.low hit rate

Q18: Explain how set associative mid between direct and fully set cache

Solution

1: it is like direct mapping where each block in main memory goes to specific SET
in cache memory

2: when the block mapping to any SET it can maps to any location within the SET
size this is like fully associative.
Q19: What is cache coherency?

Solution

In multiple processor it must be ensured that cache always has the most recent
data. If the data in main memory has been changed by one processor, the cache of
that processor will have the copy of the latest data and the stale data in the cache
memory is marked as dirty (stale) before the processor uses it.in this when
processor tries to uses stale data it inform the situation . This is called cache
coherency.

Q20:A processor has an on-chip cache that runs in one cycle of 5 ns

(200MHz).This cache has a hit rate of 90%. A second-level [motherboard] cache
runs in three cycles and has a hit of 70% of all accesses that are not found in the
on-chip cache. All accesses that are not found in either cache are found in main
memory, with an access time of 60 ns.

Solution

Second –level cache rate and main memory rate=100% -90%=10%

So that second level cache rate=0.07%

Access of second level cache=3*5=15 ns

And main memory rate= 0.03%

Overall memory access time =0.90*5 ns +0.07*15 ns +0.03*60 ns =7.35 ns

Q21 :Microprocessor use fully associative mapping is send 16-bits address to

access a memory location that has 8-bits data and that the cache is holding 128 of
possible 65536 locations.

Solution
For tag cache
Tag width=address of CPU =16 bits
depth is 128 because size of cache 128.
Total size of tag cache =128*16bits=256 byte
For data cache
Width=8 bits
Depth=128 because size of cache 128
Total size of data cache= 128*8 bits =128 byte
So that the size of total SRAM 256+128=384 byte

Q22: System has 64k byte memory and cache depth 2k what are the address format
for direct cache mapping support you answer with block diagram. What are the
locations of main memory block F7A9 in cache and what are their tags?

Solution

Number of bits for index filed=log2 N where N size (depth of cache)

Index filed =log2 2k=log2 211 =11bits (A0 ---- A10)

tag filed=log2 (m.m/c.m)=log2(64k/2k)= log225=5 bits (A11--- A15)

or

number of CPU address bits=64k=2N where N number of address CPU bits

216=2N so that n=16bits

Number of bits in tag filed=cpu address bits-index bits=16-11=5 bits

The location F7A9

(F7A9)16=(1111 0111 1010 1001)2

Tag=(11110)2 =(1E)16

While index= (111 1010 1001)2 = ( 7A9)16

Q15:System has main memory 64kbyte and cache 2kbyte 2way set associative
depth of draw block diagram. Calculate size tag cache and data size cache

Solution

CPU address=log2 64k=log2 216=16 bits

Each SET depth=cache depth/ 2= 2k/2=1k depth

Index=log21k=log2210=10 bits
Tag=CPU address bits-index bits=16-10=6 bits

Figure 4.7show the Block diagram

Each SET has tag size=(6*1k)bit and Data cache =(1k*8)bits

Total SRAM (2* (1k*6+1k*8))=28k bits.

Q16: System has main memory 64kbyte and cache 2kbyte 4way set associative
depth of draw block diagram. draw block diagram. Calculate size tag cache and
data size cache

Solution

CPU address=log2 64k=log2 216=16 bits

Each SET depth=cache depth/ 4= 2k/4=512 depth

Index=log2512=log229=9 bits
Tag=CPU address bits-index bits=16-9=7 bits

Figure show the Block diagram

Each SET has tag size=(7*512) and Data cache =(8*512)

total SRAM=(512*7+512*8)*4=32k bits

Q17: Microprocessor system has main memory 16M byte and cache depth 256k
calculate the size SRAM and draw the block diagram of system use direct
mapping.

Solution

Address bus=log2 16M=log2 224=24 bits [A23 ------ A0]

Index bits=log2 256k=log2 218=18 bits [A17 ----- A0]

Tag bits=address CPU-index=24-18=6 bits [A23 --- A18]

Cache tag size=6*218 data cache=8*218

Total SRAM=(6*218 )8 + (8*218)/8=192kbyte+256kbye=484 kbyte

Q18: Microprocessor system has main memory 16M byte and cache depth 256k
calculate the size SRAM and draw the block diagram of system use 2 way set
associative .

Solution

Address bus=log2 16M=log2 224=24 bits [A23 ------ A0]

Index bits=log2 cache depth/2=log2 (256k/2)=log2 217=17 bits [A16 ----- A0]

Tag bits=address CPU-index=24-17=7 bits [A23 --- A17]

Each set

Cache tag size=7*217 data cache=8*217

Total SRAM=2* ((7*217 )8 + (8*217)/8)=192kbyte+256kbye=484 kbyte

Total=2(224byte +256kbyte)

Q19: Microprocessor system has main memory 16M byte and cache depth 256k
calculate the size SRAM and draw the block diagram of system use 4 way set
associative .

Solution

Address bus=log2 16M=log2 224=24 bits [A23 ------ A0]

Index bits=log2 cache depth/4=log2 (256k/2)=log2 216=16 bits [A15 ----- A0]

Tag bits=address CPU-index=24-16=8 bits [A23 --- A15]

Each set

Cache tag size=8*216 data cache=8*216

Total SRAM=2* ((7*216 )8 + (8*216)/8)=256kbyte+256kbye

Total=4*(256byte +256kbyte)

Q20: Calculate the tag and data cache sizes needed for each of the following cases
if the memory requesting address to main memory is 20 bits (A19-A0).Assume a
data bus of 8 bits. Draw a block for each case.

(a) Fully associative of 1024 depth

(b) direct mapped where A15-A0 is for the index

(c) 2-way set associative where A14-A0 is for index

(d)4-way set associative

(e)8-way set associative

Solution
(a) Fully associative of 1024 depth

Number of bits for index=log2 1024=log 210=10 bits

Number of bits in tag filed=20bit

Size=of tag cache=tag filed *depth of cache

20*1k=20h bits

Size of data cache=data bus *depth=8*1k+8k bits

(b) Direct mapped where A15-A0 is for the index

Cache depth=216 =64k

tag bits filed=20-16=4 bits [A20 ----A17]

Size of tag cache=tag*depth=4*64k=256k bits

Size of data cache=8*64k=512bits

(c) 2-way set associative where A14-A0 is for index

Number of bits in tag field= 20-15=5 bits

For two SET

Size of tag cache=2*(5*215/8)=10*212 byte

Size of cache filed=2(8*215/8)=2*216

(d)4-way set associative

Number of bits in tag field= 20-14=6

bits

For two SET

Size of tag cache=2*(6*214/8)=12*211 byte

Size of cache filed=2(8*214/8)=2*214

(e)8-way set associative

Number of bits in tag field= 20-13=7 bits

For two SET

Size of tag cache=2*(7*213/8)=14*210 byte

Size of cache filed=2(8*214/8)=2*214

Review question for cache controller 82385DX

Q1-the memory controller in 80386DX work either direct mapping or two way set
associative

Q2: If memory controller in 80386DX work in 2 way set associative it use LRU
for cache and memory swapping

Q3: the memory controller of 80386DX keeps track of which main memory
location are cached. It accomplishes this through what is called a cache directory.

Q4: in direct-mapping cache of (80386DX) the cache directory contain 1024 26-bit
entries

This 26 bit divided to 3 part

1:A7—A0 valid line (8 bits)

2: BIT 8 TAG valid (one bits)

3:A26-A8 (17 bits) TAG(PAGE)

Q5: In direct-mapping of 80386DX 4G-byte main memory physical address space

is treated as 𝟐𝟏𝟕 -1 (131.071) 32K-byte pages. Each pages 8k double word (double
word=32 bits)
Q6: In direct-mapping of 80386DX size of cache 8k*32 for data cache ,each of this
32 bit call line cache

Q7: what are the different between direct-mapping and 2 way-set associative cache
for 80386 microprocessor?

Direct mapping for 82358DX 2 way0set associative

It has 1024 SET It has 512 set
One Internal directory Two internal directory A and directory
B
Size of each page in main memory Size of each page in main memory
8k double word 8K*32 bits 4k double word 4K*32bits

Directory enter 26 line divided as Directory enter 27 line divided as

1:17 tag set 2:tag valid bit 3:8 valid line 1:18 tag set 2:tag valid bit 3:8 valid line
CPU address divided CPU address divided
1:17 bits which set of main memory 1:18 bits which set of main memory
2:10 bits which set in cache 2:9 bits which set in cache
3: 3 bits to line select of cache 3: 3 bits to line select of cache

One compare no algorithm sue for Use LRU algorithm for search
search

Q8: If cache directory entry for set 1 equals (00005FF)16 from which page of main
memory is the cache information ? is the cache entry valid? Which lines in set1 are
valid?

Solution

Expressing the SET 1 entry in binary forms gives

SET1 = (0000 0000 0000 0000 0101 1111 1111)2

From the binary form of set 1 we find that

TAG= (0000 0000 0000 0001 0)2 = (2)10

Therefore the entry is from page 2 of the main memory array next the valid bit is
Tag valid bit=bit8=1

And the tag entry is valid, finally the line valid bits are

Line valid bits = bit0 to bit7 =(1111 1111)2

This means that all lines information in set 1 is valid

Q9: design and draw for each of the followings by use direct mapped
external cache for 80386 processor assume that the cache page 32kb
(8k double word)
A) The cache directory set entry format
B) The address bit fields
C) The cache organization
Solution
80386 address bits=32 bits [A31 ---- A2]
RAM size=232=4 GB
Cache size=32kb=215
Number of page=arm size/cache size=232/215 =217
page 0 to page 217 -1
address= TAG +SET +line select
TAG=17 bits Line select =3bit address=30bits
Set=30-20=10bits for 1024 SET
A) The internal cache directory 26 bits
8 bits for line valid -> (B0 to B7)
One bits for TAG valid -> B8
17 bits in TAG=17 -> (B9 to B25)
The internal cache directory 26 bits

B)80386 address 32 bits [A31 – A2]

Main memory has 217 pages [A31—A15]
And external cache has 1024 set [A14—A5]
And each set 8 lines [A4—A2]
The address filed format as show
C) Cache origination

Q10: design and draw for each of the followings by use two way set
associative external cache for 80386 processor assume that the cache
page 32kb ( 8k double word)
A) The cache directory set entry format
B) The address bit fields
C) The cache organization
Solution
Since two way set associative there are two bank A and bank B
each data cache bank =cache size/2=32kb/2=16 kb
Number of page =main memory size/cache bank size
Number of pages=232/214=218 (page 0 to page 218-1)
Address=TAG +SET+ line select
TAG=18 bits
Line select =3bits
So that set =9 bits
A) There are two internal cache directory
Each of the internal cache directory 27 bits
8 bits for line valid -> (B0 to B7)
One bits for TAG valid -> B8
18 bits in TAG -> (B9 to B26)

B) Main memory has 218 pages

And external cache has 512 set
And each set 8 lines
The address filed format as show
C)cache organization

Q11: design and draw for each of the followings by use 4-way set
associative external cache for 80386 processor assume that the cache
page 128B
A) The cache directory set entry format
B) The address bit fields
C) The cache organization
Solution
Since 4-way set associative there are four bank A and bank B bank C
and bank D
Each data cache bank =cache size/4=128kb/2=32 kb
80386 address 30bits[A31 – A2] main memory=4GB
Number of page (in main memory)=size main memory/bank size
232/215=217 so that it has [page0 ---- page 217-1]
Address=TAG +SET+ line select
TAG=17 bits
Line select =3bits
So that set =10 bits there are 1024 set in each bank
A) There are four internal cache directory
Each of the internal cache directory 26 bits
8 bits for line valid -> (B0 to B7)
One bits for TAG valid -> B8
17 bits in TAG -> (B9 to B25)

The cache directory set entry format

The address bits format

Cache organization

Q12 for direct mapped cache of the 80386 explain using diagrams how
the processor can access the location (00142028)16 show the contents of
the address bit fields and the content of cache directory
Solution
Cache size=32KB=215
Main memory size 4GB=232
So that number of page= 223/215=217 -> TAG filed bits=17bits
CPU address=30bits [A31—A2]
Address=TAG +SET +select line
30 =17 +SET +3 - SET=10
A A A A A A A
3 1 1 5 4 3 2
1 5 4
0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0
17
! 17 bits TAG select 0 to 2 -1 page ! set 10 bits select !line select

Select 1 to 1024 1 to 8

0 to 1023 set

The CPU needs the data form page number =00000000000101000=40

from 217 page in main memory

The CPU select set number =0100000001=257 set from 1024 set

The cpu select line 010=2 from 8 line

Cache directory set

25 8 7 0

0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0

17 bits TAG (b25 --b9)

One Bit8 valid tag bit (b8)

8 bits line valid (b7 ---b0)

Cache organization