0a-Esp8285 Datasheet en
0a-Esp8285 Datasheet en
Datasheet
Related Product:
ESP8285N08
ESP8285H16
Version 2.5
Espressif Systems
Copyright © 2023
About This Guide
This document introduces the speci cations of ESP8285.
Release Notes
Date Version Release notes
2017.05 V1.3 Changed the chip's input impedance of 50Ω to output impedance of 39+j6 Ω.
Certi cation
Download certi cates for Espressif products from https://www.espressif.com/en/
certi cates.
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Table of Contents
1. Overview ................................................................................................................................1
1.1. Wi-Fi Key Features .....................................................................................................................2
1.2. Speci cations .............................................................................................................................2
1.3. Applications ...............................................................................................................................3
1. Overview
Espressif’s ESP8285 delivers highly integrated Wi-Fi SoC solution to meet users’
continuous demands for ef cient power usage, compact design and reliable performance
in the Internet of Things industry.
With the complete and self-contained Wi-Fi networking capabilities, ESP8285 can perform
either as a standalone application or as the slave to a host MCU. When ESP8285 hosts the
application, it promptly boots up from the ash. The integrated high-speed cache helps to
increase the system performance and optimize the system memory. Also, ESP8285 can be
applied to any microcontroller design as a Wi-Fi adaptor through SPI/SDIO or UART
interfaces.
ESP8285 integrates antenna switches, RF balun, power ampli er, low noise receive
ampli er, lters and power management modules. The compact design minimizes the PCB
size and requires minimal external circuitries.
Besides the Wi-Fi functionalities, ESP8285 also integrates an enhanced version of
Tensilica’s L106 Diamond series 32-bit processor and on-chip SRAM. It can be interfaced
with external sensors and other devices through the GPIOs. Software Development Kit
(SDK) provides sample codes for various applications.
Espressif Systems’ Smart Connectivity Platform (ESCP) enables sophisticated features
including:
• Fast switch between sleep and wakeup mode for energy-ef cient purpose
ESP8285N08 1 MB –40 °C ~ 85 °C
External Interface -
Security WPA/WPA2
Encryption WEP/TKIP/AES
📖 Note:
① The TX power can be con gured based on the actual user scenarios.
② The network protocols are provided within the ESP8266_RTOS_SDK SDK. The link to this SDK is
https://github.com/espressif/ESP8266_RTOS_SDK.
1.3. Applications
• Home appliances
• Home automation
• Smart plugs and lights
• Industrial wireless control
• Baby monitors
• IP cameras
• Sensor networks
• Wearable electronics
• Wi-Fi location-aware devices
• Security ID tags
• Wi-Fi position system beacons
2. Pin De nitions
Figure 2-1 shows the pin layout for 32-pin QFN package.
EXT_RSTB
XTAL_OUT
XTAL_IN
RES12K
U0RXD
U0TXD
VDDD
VDDA
32
31
30
29
28
27
26
25
VDDA 1 24 GPIO5
LNA 2 23 SD_DATA_1
VDD3P3 3 22 SD_DATA_0
VDD3P3 4 21 SD_CLK
ESP8285
VDD_RTC 5 20 SD_CMD
TOUT 6 19 SD_DATA_3
XDP_DCDC 8 17 VDDPST
9
10
11
12
13
14
15
16
MTMS
MTDI
VDDPST
MTCK
MTDO
GPIO2
GPIO0
GPIO4
RF antenna interface
2 LNA I/O Chip output impedance = 39 + j6 Ω. It is suggested to retain
the π-type matching network to match the antenna.
5 VDD_RTC P NC (1.1 V)
Chip Enable
7 CHIP_EN I High: On, chip works properly
Low: Off, small current consumed
📖 Note:
1. GPIO2, GPIO0, and MTDO are used to select booting mode and the SDIO mode;
2. ESP8285’s pins SDIO_CMD, SDIO_CLK, SDIO_DATA_0 and SDIO_DATA_1 are used for connecting
the embedded ash, and are not recommended for other uses;
3. U0TXD should not be pulled externally to a low logic level during the powering-up.
3. Functional Description
The functional diagram of ESP8285 is shown as in Figure 3-1.
GPIO
Switch
Digital baseband
I2C
CPU
RF Analog I2S
transmit transmit
SDIO
Sequencers
PWM
ADC
Accelerator
PLL VCO 1/2 PLL
SPI
For information about the Xtensa® Instruction Set Architecture, please refer to Xtensa®
Instruction Set Architecture (ISA) Summary.
3.1.2. Memory
ESP8285 Wi-Fi SoC integrates memory controller and memory units including SRAM and
ROM. MCU can access the memory units through iBus, dBus, and AHB interfaces. All
memory units can be accessed upon request, while a memory arbiter will decide the
running sequence according to the time when these requests are received by the
processor.
According to our latest version of RTOS SDK, the SRAM space (Heap + Data) available to
users is less than 75 kB when ESP8285 is working under the Station mode and connects
to the router.
📖 Note:
The remaining SRAM space is measured with the ESP8266_RTOS_SDK SDK. The link to this SDK is
https://github.com/espressif/ESP8266_RTOS_SDK.
3.1.3. Flash
ESP8285 has a built-in SPI ash to store user programs.
• Memory size: see Table 1-1.
3.2. Clock
3.2.1. High Frequency Clock
The high frequency clock on ESP8285 is used to drive both transmit and receive mixers.
This clock is generated from internal crystal oscillator and external crystal. The crystal
frequency ranges from 24 MHz to 52 MHz.
The internal calibration inside the crystal oscillator ensures that a wide range of crystals can
be used, nevertheless the quality of the crystal is still a factor to consider to have
reasonable phase noise and good Wi-Fi sensitivity. Refer to Table 3-1 to measure the
frequency offset.
Loading capacitance CL - 32 pF
Motional capacitance CM 2 5 pF
Series resistance RS 0 65 Ω
3.3. Radio
ESP8285 radio consists of the following blocks.
• 2.4 GHz receiver
• 2.4 GHz transmitter
• High speed clock generators and crystal oscillator
• Bias and regulators
• Power management
1 2412 8 2447
2 2417 9 2452
3 2422 10 2457
4 2427 11 2462
5 2432 12 2467
6 2437 13 2472
7 2442 14 2484
varying signal channel conditions, RF lters, automatic gain control (AGC), DC offset
cancelation circuits and baseband lters are integrated within ESP8285.
These built-in calibration functions reduce the product test time and make the test
equipment unnecessary.
3.4. Wi-Fi
ESP8285 implements TCP/IP and full 802.11 b/g/n WLAN MAC protocol. It supports Basic
Service Set (BSS) STA and SoftAP operations under the Distributed Control Function (DCF).
Power management is handled with minimum host interaction to minimize active-duty
period.
• Modem-sleep mode: The CPU is operational. The Wi-Fi and radio are disabled.
• Light-sleep mode: The CPU and all peripherals are paused. Any wake-up events
(MAC, host, RTC timer, or external interrupts) will wake up the chip.
• Deep-sleep mode: Only the RTC is operational and all other part of the chip are
powered off.
Wi-Fi TX packet
Active (RF working) Please refer to Table 5-2.
Wi-Fi RX packet
Light-sleep② - 0.9 mA
📖 Notes:
① Modem-sleep mode is used in the applications that require the CPU to be working, as in PWM or
I2S applications. According to 802.11 standards (like U-APSD), it shuts down the Wi-Fi Modem
circuit while maintaining a Wi-Fi connection with no data transmission to optimize power
consumption. E.g. in DTIM3, maintaining a sleep of 300 ms with a wakeup of 3 ms cycle to receive
AP’s Beacon packages at interval requires about 15 mA current.
② During Light-sleep mode, the CPU may be suspended in applications like Wi-Fi switch. Without
data transmission, the Wi-Fi Modem circuit can be turned off and CPU suspended to save power
consumption according to the 802.11 standards (U-APSD). E.g. in DTIM3, maintaining a sleep of
300 ms with a wakeup of 3ms to receive AP’s Beacon packages at interval requires about 0.9 mA
current.
③ During Deep-sleep mode, Wi-Fi is turned off. For applications with long time lags between data
transmission, e.g. a temperature sensor that detects the temperature every 100 s, sleeps for 300 s
and wakes up to connect to the AP (taking about 0.3 ~ 1 s), the overall average current is less than 1
mA. The current of 20 μA is acquired at the voltage of 2.5 V.
4. Peripheral Interface
4.1. General Purpose Input/Output Interface (GPIO)
ESP8285 has 17 GPIO pins which can be assigned to various functions by programming
the appropriate registers.
Each GPIO PAD can be con gured with internal pull-up or pull-down (XPD_DCDC can only
be con gured with internal pull-down, other GPIO PAD can only be con gured with internal
pull-up), or set to high impedance. When con gured as an input, the data are stored in
software registers; the input can also be set to edge-trigger or level trigger CPU interrupts.
In short, the IO pads are bi-directional, non-inverting and tristate, which includes input and
output buffer with tristate control inputs.
These pins, when working as GPIOs, can be multiplexed with other functions such as I2C,
I2S, UART, PWM, and IR Remote Control, etc.
📖 Note:
SPI mode can be implemented via software programming. The clock frequency is 80 MHz at maximum
when working as a master, 20 MHz at maximum when working as a slave.
📖 Note:
SPI mode can be implemented via software programming. The clock frequency is 20 MHz at maximum.
Both I2C Master and I2C Slave are supported. I2C interface functionality can be realized via
software programming, and the clock frequency is 100 kHz at maximum.
Data transfers to/from UART interfaces can be implemented via hardware. The data
transmission speed via UART interfaces reaches 115200 x 40 (4.5 Mbps).
UART0 can be used for communication. It supports ow control. Since UART1 features
only data transmit signal (TX), it is usually used for printing log.
📖 Note:
By default, UART0 outputs some printed information when the device is powered on and booting up. The
baud rate of the printed information is relevant to the frequency of the external crystal oscillator. If the
frequency of the crystal oscillator is 40 MHz, then the baud rate for printing is 115200; if the frequency of
the crystal oscillator is 26 MHz, then the baud rate for printing is 74880. If the printed information exerts
any in uence on the functionality of the device, it is suggested to block the printing during the power-on
period by changing (U0TXD, U0RXD) to (MTDO, MTCK).
The functionality of PWM interfaces can be implemented via software programming. For
example, in the LED smart light demo, the function of PWM is realized by interruption of the
timer, the minimum resolution reaches as high as 44 ns. PWM frequency range is
adjustable from 1000 μs to 10000 μs, i.e., between 100 Hz and 1 kHz. When the PWM
frequency is 1 kHz, the duty ratio will be 1/22727, and a resolution of over 14 bits will be
achieved at 1 kHz refresh rate.
MTMS 9 IO14 IR TX
GPIO5 24 IO 5 IR Rx
The functionality of Infrared remote control interface can be implemented via software
programming. NEC coding, modulation, and demodulation are supported by this interface.
The frequency of modulated carrier signal is 38 kHz, while the duty ratio of the square wave
is 1/3. The transmission range is around 1m which is determined by two factors: one is the
maximum current drive output, the other is internal current-limiting resistance value in the
infrared receiver. The larger the resistance value, the lower the current, so is the power, and
vice versa.
The following two measurements can be implemented using ADC (Pin6). However, they
cannot be implemented at the same time.
• Measure the power supply voltage of VDD3P3 (Pin3 and Pin4).
Optimize the RF circuit conditions based on the testing results of VDD3P3 (Pin3
RF Calibration Process
and Pin4).
Hardware Design The input voltage range is 0 to 1.0 V when TOUT is connected to external circuit.
📖 Notes:
esp_init_data_default.bin is provided in SDK package which contains RF initialization parameters (0 ~
127 bytes). The name of the 107th byte in esp_init_data_default.bin is vdd33_const, which is de ned as
below:
• When vdd33_const = 0xff, the power voltage of Pin3 and Pin4 will be tested by the internal self-
calibration process of ESP8285 itself. RF circuit conditions should be optimized according to the
testing results.
• When 18 =< vdd33_const =< 36, ESP8285 RF Calibration and optimization process is implemented
via (vdd33_const/10).
• When vdd33_const < 18 or 36 < vdd33_const < 255, vdd33_const is invalid. ESP8285 RF Calibration
and optimization process is implemented via the default value 3.3 V.
IPC/JEDEC J-
Maximum Soldering Temperature - - 260 ℃
STD-020
IMAX - - - 12 mA
Notes on CHIP_EN:
The gure below shows ESP8266EX power-up and reset timing. Details about the
parameters are listed in Table 5-2.
Sensitivity
OFDM, 6 Mbps - 31 - dB
OFDM, 54 Mbps - 14 - dB
HT20, MCS0 - 31 - dB
HT20, MCS7 - 13 - dB
6. Package Information
📖 Notes:
• INST_NAME refers to the IO_MUX REGISTER de ned in eagle_soc.h, for example MTDI_U refers to
PERIPHS_IO_MUX_MTDI_U.
• Net Name refers to the pin name in schematic.
• Function refers to the multifunction of each pin pad.
• Function number 1 ~ 5 correspond to FUNCTION 0 ~ 4 in SDK. For example, set MTDI to GPIO12 as
follows.
- #define FUNC_GPIO12 3 //defined in eagle_soc.h
- PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U,FUNC_GPIO12)
Description: This webpage provides links to both the ESP8266 ash download tools and
the ESP8266 performance evaluation tools.
• ESP8266 Apps
• ESP8266 Certi cation and Test Guide
• ESP8266 BBS
• ESP8266 Resources