Lectures On Digital Design Principles (River Publishers Electronic Materials, Circuits and Devices) 1st Edition Pinaki Mazumder

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Pinaki Mazumder
University of Michigan, USA
Idongesit E. Ebong
Nixon Peabody, USA
River Publishers
Published 2023 by River Publishers
River Publishers
Alsbjergvej 10, 9260 Gistrup, Denmark
www.riverpublishers.com
Distributed exclusively by Routledge

605 Third Avenue, New York, NY 10017, USA
4 Park Square, Milton Park, Abingdon, Oxon OX14 4RN
Lectures on Digital Design Principles / by Pinaki Mazumder, Idongesit E.
Ebong.
© 2023 River Publishers. All rights reserved. No part of this publication may
be reproduced, stored in a retrieval systems, or transmitted in any form or by
any means, mechanical, photocopying, recording or otherwise, without prior
written permission of the publishers.
Routledge is an imprint of the Taylor & Francis Group, an informa
business
ISBN 978-87-7022-361-4 (print)

978-10-0092-194-6 (online)
978-1-003-42576-2 (ebook master)
While every effort is made to provide dependable information, the publisher,
authors, and editors cannot be held responsible for any errors or omissions.
Publisher’s Note
The pilot version of the current book contains the first ten chapters and it is published to
receive feedback from instructors, students and readers, who may submit their comments and
errata to the publisher at [email protected]
The rest of the twelve chapters will comprise finite state machine design, high level state
machine design, register transfer level design, adder design, multiplier and divider design,
data path and control logic design, memory design, and a complete processor design, from
the specified instruction set architecture.
Due to Pianki Mazumder sustaining severe spinal cord injury after a recent accident, the
second part of this book will be delayed by a few months. The pilot version of the second
part of the book will be published in a similar manner to the first part to receive feedback
from the readers. Subsequently, all twenty two chapters will be combined to create an
integrated single book.
Contents
Preface xi
Acknowledgement xv
List of Figures xvii
List of Tables xxix
List of Abbreviations xxxi
1 Introduction 1
1.1 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Equation representation . . . . . . . . . . . . . . . 1
1.1.2 Hardware platform implementation . . . . . . . . . 3
1.1.3 Sequential design . . . . . . . . . . . . . . . . . . . 4
1.1.4 Datapath components . . . . . . . . . . . . . . . . . 6
1.1.5 Backend lectures . . . . . . . . . . . . . . . . . . . 6
1.2 Analog vs. Digital . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Digital Design . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.1 Levels of digital design . . . . . . . . . . . . . . . . 12
1.3.2 What do digital designers do? . . . . . . . . . . . . 13
2 Numeral Systems and BCD codes 17

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1.1 Unary numeral systems . . . . . . . . . . . . . . . . 18
2.1.2 The positional numeral system, or the place-value
system . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.2.1 Binary numbers . . . . . . . . . . . . . . 19
2.1.2.2 Hexadecimal numbers . . . . . . . . . . . 20
2.1.2.3 Octal numbers . . . . . . . . . . . . . . . 20
2.1.2.4 Converting from decimal to different bases 21
v
vi Contents
2.1.2.5 Converting from one arbitrary base (p) to

another arbitrary base (q) . . . . . . . . . 22
2.2 Addition and Subtraction in the Positional Numeral System . 24
2.3 Negative Numbers in Binary . . . . . . . . . . . . . . . . . 26
2.3.1 Signed magnitude . . . . . . . . . . . . . . . . . . 26
2.3.2 The 1’s complement . . . . . . . . . . . . . . . . . 28
2.3.2.1 Addition in the 1’s complement . . . . . . 30
2.3.2.2 Subtraction in the 1’s complement . . . . 31
2.3.3 The 2’s complement . . . . . . . . . . . . . . . . . 32
2.3.3.1 Addition in the 2’s complement . . . . . . 34
2.3.3.2 Subtraction in the 2’s complement . . . . 35
2.4 Strings of Bits and Binary-Coded Decimal Representations . 36
2.4.1 The 8421 BCD code . . . . . . . . . . . . . . . . . 36
2.4.2 The 2421, 631-1, 84-2-1, and Excess-3 BCD codes . 38
2.4.3 The biquinary code . . . . . . . . . . . . . . . . . . 39
2.4.4 The gray code . . . . . . . . . . . . . . . . . . . . . 39
2.4.5 BCD summary . . . . . . . . . . . . . . . . . . . . 43
2.5 More on Number Systems . . . . . . . . . . . . . . . . . . 44
2.6 Conclusion and Key Points . . . . . . . . . . . . . . . . . . 46
3 Boolean Algebra and Logic Gates 51

3.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.2 Huntington Postulates . . . . . . . . . . . . . . . . . . . . . 52
3.3 Basic Theorems of Boolean Algebra . . . . . . . . . . . . . 53
3.3.1 Basic postulates with 0 and 1 . . . . . . . . . . . . . 53
3.3.2 Idempotent laws . . . . . . . . . . . . . . . . . . . 54
3.3.3 The Law of involution . . . . . . . . . . . . . . . . 54
3.3.4 Complementarity laws . . . . . . . . . . . . . . . . 54
3.3.5 Commutative laws . . . . . . . . . . . . . . . . . . 55
3.3.6 Associative laws . . . . . . . . . . . . . . . . . . . 55
3.3.7 Distributive laws . . . . . . . . . . . . . . . . . . . 55
3.3.8 DeMorgan’s laws . . . . . . . . . . . . . . . . . . . 56
3.4 Duality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.4.1 What you should know from duality . . . . . . . . . 60
3.5 Logic Gates for Implementation of Boolean Networks . . . . 60
3.5.1 AND, OR, and NOT . . . . . . . . . . . . . . . . . 60
3.5.2 Implicant gates . . . . . . . . . . . . . . . . . . . . 61
3.5.3 Other logic gates . . . . . . . . . . . . . . . . . . . 62
3.5.4 Equivalent gates . . . . . . . . . . . . . . . . . . . 65
Contents vii
3.5.5 Concept of completeness . . . . . . . . . . . . . . . 67

3.6 CMOS Gates . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.7 General Complementary Switching Network . . . . . . . . . 70
3.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.9 Key Points . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4 Timing Diagrams 79
4.1 Notion of Timing Delay in a Circuit . . . . . . . . . . . . . 80
4.2 Definition of Propagation Delay . . . . . . . . . . . . . . . 82
4.3 Timing Diagrams of a Gated Logic . . . . . . . . . . . . . . 84
4.4 The Ring Oscillator: Good Use of Delays . . . . . . . . . . 86
4.5 Glitches and Hazards: Bad Effects Due to Unequal Path
Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.5.1 Correction of the static-1 hazard . . . . . . . . . . . 90
5 Combinational Logic Design Techniques: Part I 99

5.1 Designing a Digital System from a Problem Statement . . . 100
5.1.1 Stairwell lamp problem . . . . . . . . . . . . . . . . 100
5.1.2 BCD to seven-segment converter . . . . . . . . . . . 107
5.1.3 Event detector . . . . . . . . . . . . . . . . . . . . 110
6 Combinational Logic Design Techniques: Part II 115

6.1 Majority Gate Design . . . . . . . . . . . . . . . . . . . . . 116
6.1.1 SOP implementation . . . . . . . . . . . . . . . . . 117
6.1.2 POS implementation . . . . . . . . . . . . . . . . . 119
6.1.3 Self-duality . . . . . . . . . . . . . . . . . . . . . . 120
6.2 Why Different Representations: Two-Level Logic
Implementation Styles . . . . . . . . . . . . . . . . . . . . 121
6.2.1 SOP representations . . . . . . . . . . . . . . . . . 121
6.2.2 POS representations . . . . . . . . . . . . . . . . . 122
6.2.3 Compatible representations for CMOS design . . . . 122
6.3 Hardware Description Languages . . . . . . . . . . . . . . . 123
6.3.1 Majority gate and stairwell lamp verilog
Implementation . . . . . . . . . . . . . . . . . . . . 125
6.3.2 Full adder verilog implementation . . . . . . . . . . 126
6.3.3 Ripple carry adder . . . . . . . . . . . . . . . . . . 126
viii Contents
7 Combinational Logic Minimization 135

7.1 Representation for Minimization: Summarization . . . . . . 135
7.1.1 Intuitive design approach . . . . . . . . . . . . . . . 136
7.1.2 Boolean minimization . . . . . . . . . . . . . . . . 136
7.2 Graphical Method: The Karnaugh Map . . . . . . . . . . . . 137
7.3 Three- and Four-Variable Karnaugh Maps for Logic Circuits 139
7.4 Minimizing with Four-Variable K-maps . . . . . . . . . . . 142
7.4.1 Formal definitions . . . . . . . . . . . . . . . . . . 143
7.4.2 Example 1: detailed illustration of minimization . . 143
7.4.3 Example 2: prime implicant definition
reinforcement . . . . . . . . . . . . . . . . . . . . . 146
7.4.4 Example 3: dealing with “Don’t cares” . . . . . . . 146
8 Combinational Building Blocks 155

8.1 Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
8.1.1 Implementation of larger-bit decoders . . . . . . . . 156
8.1.2 Using decoders to implement boolean functions . . . 158
8.1.2.1 Example 1 . . . . . . . . . . . . . . . . . 158
8.1.2.2 Example 2 . . . . . . . . . . . . . . . . . 158
8.2 Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . 160
8.2.1 Implementation of larger-bit multiplexers . . . . . . 162
8.2.2 Using multiplexers to implement boolean
functions . . . . . . . . . . . . . . . . . . . . . . . 163
8.2.2.1 Example 1 . . . . . . . . . . . . . . . . . 163
8.2.2.2 Example 2 . . . . . . . . . . . . . . . . . 167
8.3 MSI Building Blocks . . . . . . . . . . . . . . . . . . . . . 167
8.3.1 Decoders . . . . . . . . . . . . . . . . . . . . . . . 167
8.3.1.1 The 74139 decoder . . . . . . . . . . . . 167
8.3.1.2 The 74138 Decoder . . . . . . . . . . . . 170
8.3.2 Tri-state buffers . . . . . . . . . . . . . . . . . . . . 170
8.3.2.1 Application . . . . . . . . . . . . . . . . 171
8.3.2.2 The 74541 three-state driver . . . . . . . . 173
8.3.3 Encoders . . . . . . . . . . . . . . . . . . . . . . . 173
8.3.3.1 The 74148 priority encoder . . . . . . . . 174
8.3.3.2 Verilog implementation . . . . . . . . . . 176
8.3.4 Multiplexers . . . . . . . . . . . . . . . . . . . . . 178
8.3.5 Parity circuits . . . . . . . . . . . . . . . . . . . . . 178
8.3.6 Comparison circuits . . . . . . . . . . . . . . . . . 181
Contents ix
8.3.6.1 Equality . . . . . . . . . . . . . . . . . . 181

8.3.6.2 Greater than and less than . . . . . . . . . 182
8.3.6.3 The 74682 magnitude comparator IC . . . 182
8.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . 183
8.5 Key Points . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
9 Foundations of Sequential Design: Part I 191

9.1 Taxonomy of Sequential Models . . . . . . . . . . . . . . . 191
9.1.1 The mealy machine . . . . . . . . . . . . . . . . . . 191
9.1.2 The moore machine . . . . . . . . . . . . . . . . . . 193
9.2 Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
9.2.1 Operation of flip-flops and their applications . . . . 193
9.2.2 Classification of flip-flops . . . . . . . . . . . . . . 194
9.2.2.1 S-R flip-flop . . . . . . . . . . . . . . . . 194
9.2.2.1.1 Characteristic table . . . . . . . 194
9.2.2.1.2 State diagram . . . . . . . . . . 196
9.2.2.2 T flip-flop . . . . . . . . . . . . . . . . . 197
9.2.2.2.2 State diagram . . . . . . . . . . 198
9.2.2.3 J-K flip-flop1 . . . . . . . . . . . . . . . . 198
9.2.2.3.2 State diagram . . . . . . . . . . 200
9.2.2.4 D flip-flop . . . . . . . . . . . . . . . . . 200
10 Foundations of Sequential Design: Part II 207

10.1 Gate Implementation of Flip-Flops and Timing Diagrams . . 208
10.1.1 Simple inverters without feedback . . . . . . . . . . 208
10.1.2 Single inverter with feedback (oscillator) . . . . . . 208
10.1.3 Two inverters with feedback (flip-flop) . . . . . . . . 209
10.1.4 S-R latch . . . . . . . . . . . . . . . . . . . . . . . 210
10.1.4.1 S-R latch timing diagram . . . . . . . . . 211
10.1.4.2 Problems with the S-R latch . . . . . . . . 213
10.2 Clocked Flip-Flops . . . . . . . . . . . . . . . . . . . . . . 214
10.2.1 Clocked S-R flip-flop . . . . . . . . . . . . . . . . . 215
10.2.2 Clocked J-K flip-flop . . . . . . . . . . . . . . . . . 216
10.2.2.1 J-K flip-flop timing diagram . . . . . . . . 217
10.2.2.2 Problems with the J-K flip-flop . . . . . . 218
10.2.3 Solutions to the race-around problem . . . . . . . . 219
x Contents
10.2.3.1 Narrowing the clock pulse width . . . . . 220

10.2.3.2 Separating the inputs and outputs of the
flip-flop . . . . . . . . . . . . . . . . . . 222
10.2.3.2.1 Master-Slave D flip-flop . . . . . 223
10.2.3.2.2 Master-Slave J-K flip-flop . . . . 224
10.2.4 IEEE symbols and flip-flop types . . . . . . . . . . 228
10.2.5 Timing analysis of flip-flop problems . . . . . . . . 230
10.2.5.1 Example 1: timing diagram of a J-K flip-flop 230
10.2.5.2 Example 2: timing diagram of J-K flip-
flops configured as a counter/binary divider 231
10.2.5.3 Example 3: Timing diagram of D flip-flops
configured as a ring counter . . . . . . . . 232
10.2.6 Effect of the width of the set pulse . . . . . . . . . . 233
10.2.7 Dealing with metastability and asynchronous inputs . 234
10.3 Conclusion and Key Point . . . . . . . . . . . . . . . . . . 235
10.4 Problems on Flip-Flops . . . . . . . . . . . . . . . . . . . . 236
Index 243
About the Authors 247

Preface
Thomas Watson, the president of IBM, once boldly predicted: “I think there
is a world market for maybe five computers.” At that time, the large-size
computers such as IBM 704 and IBM 709 were made of bulky and power-
hungry vacuum tubes, magnetic core and magnetic tape memories, and
CRT displays. Customers for gigantic computers that warranted a separate
air-conditioned building were few and far between in the early years of
commercial digital computing machines. Almost 30 years later, Ken Olsen,
the founder of Digital Equipment Corporation, which manufactured mid-size
computers such as PDP-11 and VAX-11, pronounced definitively: “There is
no reason anyone would want a computer in their home." In other words,
Olsen did not envision the market potential of personal computers like Apple
1 that Steve Jobs and Steve Wozniak had just introduced in the market in
1976. Watson and Olsen were pioneers in the computer industry who had
wrought upon the miracle of exponential growth of computing power that has
fueled the accelerated economic growth in the last 70 years. Nevertheless,
these doyens in computing were dead wrong in their prophecy! Now, 40
years later, more than one billion individuals in the world personally possess
at least five computing devices in their notebook, cell phone and smart
watch. Globally, more than 100 billion computing chips are now deployed
ubiquitously in every walk of the modern world!
This amazing story must inspire you to become a computer hardware
engineer who will push the envelope of computing in the 21st Century.
Moore’s Law in microelectronics that prognosticated the exponential growth
of computing power by shrinking geometries of transistors and wires in
microprocessor chips, is likely to sustain for a long time and hardware
engineers are expected to bring about more astounding inventions that will
profoundly impact our lives. The landscape of hardware design is continually
unfolding as computers, communications, and consumer electronics are
melding together to build the future digital systems equipped with ultra
high-definition cameras and displays. On the other hand, quite logically
you may aspire to become a software engineer as alluring job markets in
xi
xii Preface
information technology loom upon boundless opportunities for innovations.

Nevertheless, you must learn computer hardware very well as in modern
portable and energy scavenged systems both hardware and software are
optimized holistically as you might have witnessed in smart phones, smart
watches and other wearable products.
The purpose of this book that aggregates my lectures in an introductory
course for digital logic design is to teach rudimentary principles of digital
system design at first and then help you to design, build and test a custom
microprocessor using a field programmable gate array (FPGA). There are
altogether 21 chapters that I try to cover in my lectures for a one semester 4
credit course supplemented with 6 laboratory experiments to allow students
to apply their textbook knowledge and imbibe integrated hands-on training.
Students solve small real-word problems and then implement their design on
an FPGA prototyping system.
Though I have taught this course rather sporadically ever since I joined
the University of Michigan, I did not make any serious efforts to compile
my teaching materials to write a book. I used to teach the subject materials
by writing on chalkboard from my hand-written notes. The first push to
organize my lecture materials came rather unexpectedly, when the National
Technology University (NTU), the first accredited "virtual" university, invited
me to produce a video book in June 2005 by taping my lectures at the
MGM Studio of Disney World in Orlando, Florida. With the support of major
technology companies such as IBM, Motorola, and Hewlett-Packard, the on
line university (NTU) was founded in 1984 to deliver academic courses to
corporations’ training facilities via a unique satellite network. NTU, which
has now merged with Walden University, provided an imaginative and unique
model of educational integration as a way to award degrees through distance
education.
I took this opportunity to convert my hand-written notes into PowerPoint
slides that were parceled into 42 lectures for a one-semester on-line course. To
produce video streams of my lectures, professional MGM Studio equipment
was used in conjunction with Camtasia software running on my tablet PC.
Each lecture was nearly 90 minutes and the entire lecture was taped without
any retake and stopping. No coughing or sipping a beverage to clear my
throat. The streaming technology the equipment used was unforgiving. A few
times, someone involuntarily tripped over the long cable running across a
big room, thereby compelling me to restart my lecture all over again. A few
times, I floundered almost at the end of a lecture and had to restart the entire
lecture. The experience was also unique, as I had to sit on a chair inside a
Preface xiii
small studio cubicle virtually constrained by the viewing span of the camera
with bright lights blazing all around. This was a strange teaching experience
– sitting like a potted plant and talking to the fixed expressionless camera! As
I had not yet published a textbook on digital logic, I had to slightly change
my lecture notes to adapt my slides with two textbooks that students could
use in conjunction with my lectures and solving practice problems.
Soon after this video lecture production, I contemplated penning down
my lectures in the form of a written textbook. But I had to shelve my plan as
I went on a US Government assignment to the National Science Foundation
at Washington, DC to lead a showcase program on emerging technologies
comprising of nanoelectronics, quantum computing and bio-computing. After
I returned to the University of Michigan and resumed teaching in 2011, I
was asked to teach the logic design course. During the summer of 2011, I
started reviewing my videotape to regroup my lectures into different chapters.
My co-author, Idongesit Ebong listened very enthusiastically to my lectures,
and studied my PowerPoint slides and written notes. He then volunteered
to transcribe my lectures and accelerate the writing process. We ended up
writing about 250 pages that I adopted in my Fall 2011 class.
The progress became rather slow after that as I became involved in
developing a new graduate course on ultra-low-power sub-threshold CMOS1
systems that is at the heart of design of wearable electronic products. After
teaching other regular courses along with this new course several times, I
again got opportunity to teach the digital design course in Fall 2015. This
enabled me to fully concentrate on writing the textbook. Thanks to Yalcin
Yilmaz for helping me in transcribing some chapters.
Finally, computers and digital systems are now ubiquitous, pervading
all walks of our daily lives. They constitute the backbone for mission-
critical applications in outer space, satellite and wireless communications,
military missions in inhospitable terrains, and in underwater explorations.
Students must learn the design concepts of digital systems thoroughly,
because engineering mistakes are very costly and fatal as we have witnessed
in Boeing 737 Max crashes, the Challenger space station disaster, and so on.
Finally, computers and digital systems are now ubiquitous pervading
all walks of our daily lives. They constitute the backbone for mission-
critical applications in outer space, satellite and wireless communications,
military missions in inhospitable terrains, and in underwater explorations.
Students must learn the design concepts of digital systems thoroughly,
1
CMOS is acronym for Complementary Metal-Oxide Semiconductor
xiv Preface
because engineering mistakes are very costly and fatal as we have witnessed
in Boeing 737 Max crashes, the Challenger space station disaster, and so on.
Professional engineers must learn their subjects very thoroughly and
acquire disparate skills that will enable them to design their systems after
analyzing and critiquing them comprehensively.
Acknowledgement
Though the book is compilation of my lectures and my coauthor has helped

me to write these chapters, the structure of the book was conceived from the
syllabus of EECS 270: Introduction to Digital Logic Design, a sophomore
computer hardware course that is taught by several of my distinguished
colleagues at the Computer Science and Engineering Division of EECS
Department at the University of Michigan. I must express my unstinted
gratitude to them for sharing their homework and exams with me over the
course of so many years. I used some of the problems they provided to me as
multiple-choice exercise problems at the end of many a chapter.
When I joined the University of Michigan, my senior colleagues John
Hayes and Ward Getty were contemplating integrating Mentor Graphics
computer-aided design (CAD) tools such as QuickSim and MSPICE into
the existing laboratory experiments. They were previously using experiments
that required wire wrapping of medium-scale integrated (MSI) chips on
breadboards. The breadboard chores for students were pretty laborious and
fault-prone because those MSI chips used transistor-transistor logic (TTL)
technology that would malfunction if any wire was not firmly connected.
When I began teaching the course, they shared with me the courseware they
were developing for new laboratory experiments. That helped me to develop
a few new CAD laboratory experiments along with a tutorial for using the
Mentor Graphics tools in CAD experiments. Subsequently, I introduced the
accelerated version of the course in Spring 1991 by modifying some of those
laboratory experiments. My colleague Karem Sakallah was instrumental in
upgrading and enriching EECS 270 by adopting Xilinx FPGA boards in the
late 1990’s for the laboratory experiments. As Xilinx Foundation tool used
ABEL hardware description language (HDL) that had several limitations
compared to popular Verilog HDL that we use in lectures, Karem later
replaced them with the Altera FPGA DE-2 board and Quartus II CAD tools.
These programmable hardware boards and CAD tools allow students to
implement their digital design on a hardware platform, and then test and
xv
xvi Acknowledgement
debug their Verilog design. This is the key part of learning in digital logic
design.
In addition to the above-mentioned colleagues, I also taught in team with
Kang Shin and Janice Jenkins by sharing our lecture duties. Even though I
did not teach in team with Mark Brehob, Valeria Bertacco, Trevor Mudge,
Igor Markov, John Myers, Edward Davidson, and David Blaauw, they have
also significantly contributed to upgrading the course. I had interacted with
all of them now and then about different aspects of the course and shared
homework and exams. Matthew Smith manages the laboratory component
of EECS 270 quite deftly, making sure that students learn lecture materials
of the course through hands-on laboratory experience. In addition to Yalcin
Yilmaz, who assisted me in completing few chapters, my research associate,
Dr. Mikhail Erementchouk, and two of my doctoral students, Nan Zheng and
Soumitra Roy Joy perused the voluminous manuscript and provided me with
useful feedback.
Finally, my lectures were also partially influenced by the textbooks we
adopted over the course of last so many years. In order to ensure that students
who were enrolled in my class could relate to the prescribed textbook, I
had assimilated some aspects of my lectures with the styles and contents
of these textbooks1 . I would like to express my sincere thanks to the
authors for dedicating themselves to education and training of undergraduate
students. The last but not the least, students who undertake this journey
to enthusiastically learn computer hardware and apply their knowledge in
industry to design and manufacture cutting-edge hardware products are the
most important reasons for us, the educators, to continually learn ourselves
and assimilate our knowledge in our course offering.
Pinaki Mazumder, Professor

Dept. of Elec. Eng. and Comp. Sci.
University of Michigan, Ann Arbor, USA
April 28, 2019
1
Digital Design (2nd Edition) by Frank Vahid, Wiley, 2010 Digital Design: Principles and
Practices (4th Edition) by John F. Wakerly, Prentice Hall Publishing Company Introduction
to Digital Logic Design by John P. Hayes, Prentice Hall Logic and Computer Design
Fundamentals (3rd Edition) by Morris Mano and Charles Kime, Prentice Hall Publishing
Company Fundamentals of Logic Design (5th Edition) by Charles H. Roth, Thompson
Brooks/Cole Contemporary Logic Design (1st Edition) by Randy H. Katz, Pearson
List of Figures
Figure 1.1 Digital and analog signals. . . . . . . . . . . . . . 8

Figure 1.2 An Olympus digital camera and a picture from it
stored as compressed digital bit strings. . . . . . . 9
Figure 1.3 High-density DVD and analog VHS tape. . . . . . 10
Figure 1.4 A Rolex analog watch is priced at $10,000 while its
digital counterpart may cost only $150. . . . . . . . 10
Figure 1.5 From Gower model (1912) to modern cell phones:
the phone industry went digital. . . . . . . . . . . . 11
Figure 1.6 Example of a behavioral description of a 2-bit adder
in Verilog. . . . . . . . . . . . . . . . . . . . . . . 12
Figure 1.7 Example of a structural description of a circuit
implementing Z = (A + B)(B + C)(A + C). . . . . . 13
Figure 1.8 Layout example showing how transistors are viewed
from a geometric perspective. . . . . . . . . . . . . 14
Figure 2.1 (a) Tally mark counting to 7 and (b) Roman numeral
counting to 7. . . . . . . . . . . . . . . . . . . . . 18
Figure 2.2 203 is converted to binary, hexadecimal, and octal
to illustrate the conversion procedure. . . . . . . . 22
Figure 2.3 42.625 is converted to binary, hexadecimal, and
octal to show the conversion procedure when a radix
point is involved. . . . . . . . . . . . . . . . . . . 23
Figure 2.4 Conversion of a number from base p to base q. . . . 24
Figure 2.5 136 is added to 191 in decimal, binary, hexadecimal,
and octal. Addition involves digit-by-digit addition
starting from the least significant digit. . . . . . . . 25
Figure 2.6 111 is added to 101 in decimal, binary, hexadecimal,
and octal. . . . . . . . . . . . . . . . . . . . . . . 26
Figure 2.7 75 is subtracted from 182 in decimal, binary,
hexadecimal, and octal. . . . . . . . . . . . . . . . 26
Figure 2.8 52 is subtracted from 142 in decimal, binary,
hexadecimal, and octal. . . . . . . . . . . . . . . . 26
xvii
xviii List of Figures
Figure 2.9 Graphically comparing 4-bit (a) signed magnitude

numbers with (b) unsigned binary numbers. . . . . 27
Figure 2.10 Graphically showing all numbers in a 4-bit 1’s
complement representation. . . . . . . . . . . . . . 29
Figure 2.11 4-bit 1’s complement addition showing 2 + 5 = 7
and 5 + (–6) = –1. . . . . . . . . . . . . . . . . . . 30
Figure 2.12 Example showing what to do when an addition
yields a carry-out from the MSB position. . . . . . 31
Figure 2.13 Two cases where an overflow has occurred. When
two numbers of the same sign are added and they
yield a different sign, an overflow has occurred and
the result should be discarded. . . . . . . . . . . . 31
Figure 2.14 1’s complement subtraction showing –2 – (–5) = 3.
–2 is added to a negated –5. . . . . . . . . . . . . . 32
Figure 2.15 Graphically showing all numbers in a 4-bit 2’s
complement representation . . . . . . . . . . . . . 33
Figure 2.16 4-bit 2’s complement addition showing 2 + 5 = 7
and 5 + (–6) = –1. . . . . . . . . . . . . . . . . . . 34
Figure 2.17 4-bit 2’s complement addition showing 6 + (–4) =
2. The carry-out from the MSB is dropped in 2’s
complement addition. . . . . . . . . . . . . . . . . 34
Figure 2.18 When two numbers of the same sign are added and
they result in a number of a different sign, then an
overflow has occurred. . . . . . . . . . . . . . . . 35
Figure 2.19 2’s complement subtraction showing –2 – (–5) =
3. Subtraction involves negation of the subtracted
number, which involves complementing the number
and adding 1. 1 is added through a carry-in. . . . . 36
Figure 2.20 2’s complement arithmetic with –8. Although –
8 cannot be successfully negated, it may still be
subtracted and added to other numbers as long as
no overflow occurs. . . . . . . . . . . . . . . . . . 37
Figure 2.21 Examples of binary codes for decimal digit
representation. . . . . . . . . . . . . . . . . . . . . 37
Figure 2.22 Mechanical disk encoder using a 3-bit binary code. 40
Figure 2.23 Mechanical disk encoder using the Gray code. . . . 41
Figure 2.24 Mechanical disk encoder using an 8-bit Gray code. 41
List of Figures xix
Figure 2.25 Gray encoded digital signal generation by using an

optical source (Courtesy: PLCDev that manufactures
programmable logic controller devices.) . . . . . . 42
Figure 2.26 Electrical signals for the Gray code generated by
the phototransistors by converting the optical beams
transmitted through the rotary disk. . . . . . . . . . 43
Figure 2.27 Number system and its subsystems. . . . . . . . . 45
Figure 3.1 Two-input AND, OR, and NOT gate symbols and
truth tables defining each function. . . . . . . . . . 61
Figure 3.2 Number of possible Boolean functions for a two-
input gate is 16, and some function outputs are listed. 62
Figure 3.3 Truth table for all 16 logic functions that can be
made from two Boolean variables. . . . . . . . . . 63
Figure 3.4 Boolean expressions for all 16 functions. . . . . . . 63
Figure 3.5 Two-input NAND, NOR, XOR, XNOR, and buffer
gate symbols and truth tables defining each
function. . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 3.6 Equivalent gates through bubble logic for (from top
to bottom) XOR, XNOR, NAND, and NOR. . . . . 65
Figure 3.7 Implementation of the NOT, AND, and OR
functions to show the NAND is functionally
complete. . . . . . . . . . . . . . . . . . . . . . . 67
Figure 3.8 Symbolic representation of (a) an NMOS transistor
and (b) a PMOS transistor. . . . . . . . . . . . . . 68
Figure 3.9 CMOS inverter showing that PMOS and NMOS
transistors can be viewed as switches. . . . . . . . 69
Figure 3.10 CMOS NAND gate showing how input combinations
affect the output. . . . . . . . . . . . . . . . . . . 69
Figure 3.11 CMOS NOR gate showing how input combinations
determine the output. . . . . . . . . . . . . . . . . 70
Figure 3.12 Implementation of noninverting gates (buffer, OR,
AND) in a static CMOS. . . . . . . . . . . . . . . 70
Figure 3.13 Implementation of a Boolean function in arbitrary
technology with 3-terminal switches . . . . . . . . 71
Figure 4.1 Microprocessor. . . . . . . . . . . . . . . . . . . . 79
xx List of Figures
Figure 4.2 (a) CMOS NAND gate showing paths for charging
and discharging the storage capacitor and (b)
zoomed-in SEM picture of the microprocessor
showing interconnects are not perfectly straight or
composed of one metal piece. . . . . . . . . . . . . 81
Figure 4.3 (Top) AND gate showing the values of inputs and
output between times t=5 and t=8. (Bottom) A
timing diagram showing the effect of gate delay on
output response time due to change in inputs. . . . 82
Figure 4.4 Definition of propagation delay, fall time, and rise
time explained graphically. . . . . . . . . . . . . . 83
Figure 4.5 Timing diagram providing the parameters of the
given problem and the waveform of the given
input A. . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 4.6 Timing diagram isolating and showing the change
in output Y due to its inputs B and E. . . . . . . . . 85
Figure 4.7 Complete timing diagram defining the rise delay of
the entire chain of NAND gates. . . . . . . . . . . 86
Figure 4.8 Ring oscillator with three inverters and a given
starting state at t = 0. . . . . . . . . . . . . . . . . 87
Figure 4.9 Ring oscillator shown at different time steps with
truth tables to verify operation for skipped time
steps. . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 4.10 (a) MUX schematic with reconvergence showing
signal S passes through three gates (inverter, AND,
and OR) in one path and two gates (AND and OR)
in the other path to realize Y . (b)Timing diagram
showing that inverter delay causes a period between
time t = 3 and time t =4 where S and S equal 0.
(c)Timing diagram showing that the delay in (b) that
caused both S and S to equal 0 causes, the output
Y to be incorrect between time t = 5 and time t = 6. 89
Figure 4.11 (a) Static-1 hazard (expect a 1, but then there is a 0
measured somewhere). (b) Static-0 hazard (expect a
0, but then there is a 1 measured somewhere). . . . 90
List of Figures xxi
Figure 4.12 (a) Truth table for a MUX, (b) the MUX schematic,
(c) the MUX truth table converted to a K-
map representation, and (d) the MUX K-map
representation showing the switch from S = 1 to
S = 0. . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 4.13 (a) Modified MUX schematic with no static-1
hazard and (b) K-map of modified MUX, where the
dotted oval introduces an AND gate that takes care
of the static-1 hazard when switching from S = 1to
S = 0. . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 4.14 Two illustrated examples of dynamic hazards where
the output makes multiple transitions before settling
to its correct stable value. . . . . . . . . . . . . . . 93
Figure 4.15 Variant models showing that signals do not change
instantaneously and Logic 0 and Logic 1 values do
not mean signals behave in a square-wave fashion. . 93
Figure 4.16 Critical paths for the circuit. . . . . . . . . . . . . 94
Figure 5.1 (Left) Truth table for the stairwell problem. (Right)
State diagram showing transition from one state to
another. (Bottom) Verbally identified situations that
constitute the lamp being ON. . . . . . . . . . . . 102
Figure 5.2 Canonical SOP implemented with four AND gates
for the product terms and one OR gate. . . . . . . . 104
Figure 5.3 NAND, NOR, XOR and XNOR gate representations
with their equations. . . . . . . . . . . . . . . . . . 106
Figure 5.4 Example showing coversion of BCD to seven-
segment display, defining the bit variables for the
display. . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 5.5 Clock display generated from internal clock
oscillation showing the path from the internal clock
to the digital out. . . . . . . . . . . . . . . . . . . 109
Figure 5.6 Truth table and equations used to determine the
Boolean values for the seven segments. . . . . . . . 109
Figure 5.7 Die pattern detector intuitive implementation. . . . 110
Figure 6.1 Majority gate truth table showing all minterms and
maxterms. . . . . . . . . . . . . . . . . . . . . . . 117
Figure 6.2 AND-OR to NAND-NAND conversion and vice
versa. Interchange the gates and Z remains
unchanged! . . . . . . . . . . . . . . . . . . . . . 123
xxii List of Figures
Figure 6.3 OR-AND to NOR-NOR conversion and vice versa.

Interchange the gates and Z remains unchanged! . . 123
Figure 6.4 Incorrect conversion from OR-AND to NOR-NOR
(all inputs must be introduced in Level 2). . . . . . 123
Figure 6.5 Complex, messy circuit schematic with extraneous
information that reduces readability and
understanding. . . . . . . . . . . . . . . . . . . . . 124
Figure 6.6 Verilog code implementing the lamp function and
the majority gate function. . . . . . . . . . . . . . 126
Figure 6.7 Verilog code simulation results showing the outputs
for all input combinations. . . . . . . . . . . . . . 127
Figure 6.8 Verilog code simulation results shown graphically. . 128
Figure 6.9 Full adder implementation showing the sum and the
carry-out functions. . . . . . . . . . . . . . . . . . 129
Figure 6.10 Full adder module schematic and behavioral Verilog
description. . . . . . . . . . . . . . . . . . . . . . 129
Figure 6.11 Hierarchical ripple carry adder structural Verilog
implementation. . . . . . . . . . . . . . . . . . . . 130
Figure 7.1 Majority gate truth table with minterm
identification. . . . . . . . . . . . . . . . . . . . . 136
Figure 7.2 K-map representation from the SOP perspective.
From the truth table translation, A is the MSB and C
is the LSB. This arrangement produces the minterm
pattern in the K-map. The 1’s are grouped here,
hence an SOP. . . . . . . . . . . . . . . . . . . . . 138
Figure 7.3 K-map representation from the POS perspective.
From the truth table translation, A is the MSB and C
is the LSB. This arrangement produces the maxterm
pattern in the K-map. The 0’s are grouped here,
hence a POS. . . . . . . . . . . . . . . . . . . . . 138
Figure 7.4 Connecting the minimization techniques of the K-
map to Boolean algebra and the truth table. . . . . 140
Figure 7.5 A three-variable and a four-variable K-map from an
SOP perspective. . . . . . . . . . . . . . . . . . . 141
Figure 7.6 Three-variable K-map showing groupings of four
1’ssimplifythe expression to one literal. . . . . . . 142
Figure 7.7 Four-variable K-map showing that groupings of
four 1’s simplify the expression to a two-input AND
gate. . . . . . . . . . . . . . . . . . . . . . . . . . 142
List of Figures xxiii
Figure 7.8 Four-variable K-map showing that groupings of

eight 1’s simplify the expression to one literal. . . . 143
Figure 7.9 K-map problem for example 1. . . . . . . . . . . . 144
Figure 7.10 (a) K-map example showing all two-cluster implicants
and (b) K-map example showing all four-cluster
implicants. . . . . . . . . . . . . . . . . . . . . . . 144
Figure 7.11 Example of K-map showing two different minimum
representations. The green colored1 in a PI is a
distinguished minterm, making the PI into essential
PI (EPI). . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 7.12 Example 2’s K-map showing different implicants
and minimum solution. . . . . . . . . . . . . . . . 146
Figure 7.13 Example 3’s K-map showing different implicants
and multiple ways of approaching the problem. . . 147
Figure 7.14 Worked-out example for practice. . . . . . . . . . . 148
Figure 8.1 (a) 1:2 Decoder symbol and output expressions, (b)
circuit schematic of a 1:2 decoder, and (c) truth
table. . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 8.2 (a) 2:4 Decoder symbol and output expressions and
(b) 2:4 decoder truth table. . . . . . . . . . . . . . 157
Figure 8.3 (a) Hierarchical design of a 2:4 decoder using 1:2
decoders and (b) 2:4 decoder implementation with
AND gates. . . . . . . . . . . . . . . . . . . . . . 158
Figure 8.4 Circuit implementation of the function L(A,B,C)
given in Example 1 . . . . . . . . . . . . . . . . . 159
Figure 8.1 Implementation of L(A,B,C,D) function given in
Example-2 by tracing the minterms (solution-1). . . 160
Figure 8.2 Implementation of L (A,B,C,D) function given in
Example-2 by tracing the maxterms (solution-2). . 161
Figure 8.4 Multiplexer examples. From left to right: 2:1 MUX,
4:1 MUX, and 8:1 MUX. . . . . . . . . . . . . . . 161
Figure 8.5 Multiplexer K-maps. From left to right: 2:1 MUX,
4:1 MUX, and 8:1 MUX. . . . . . . . . . . . . . . 162
Figure 8.6 8:1 MUX realization using two 4:1 MUXes and a
2:1 MUX. . . . . . . . . . . . . . . . . . . . . . . 162
Figure 8.7 (a) K-map representation of L, (b) 16:1 MUX K-
map, and (c) 16:1 MUX implementation of L. . . . 164
xxiv List of Figures
Figure 8.8 (a) Four-input K-map representation of L, (b) three-

input K-map implementation of L, and (c) 8:1
MUX K-map (d) implementation of function L by
8:1 MUX. . . . . . . . . . . . . . . . . . . . . . . 165
Figure 8.9 (a) Four-input K-map representation of L,(b) two-
input K-map implementation of L, and (c) 4:1 MUX
K-map (d) implementation of function L by a 4:1
MUX. . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 8.10 (a) Four-input K-map representation of L, (b) two-
input K-map implementation of L, and (c) 4:1 MUX
K-map (d) implementation of function L by a 4:1
MUX. . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 8.11 (Top) 74139 logic symbol with package pin
numbers and (bottom) 74139 logic circuit
implementation. . . . . . . . . . . . . . . . . . . . 169
Figure 8.12 (Top) 74138 logic symbol with package pin
numbers and (bottom) 74138 logic circuit
implementation. . . . . . . . . . . . . . . . . . . . 171
Figure 8.13 Two 74138 3:8 decoders used to make a 4:16
decoder. . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 8.14 Verilog code implementation of the 74138decoder. 172
Figure 8.15 Three-state buffer with truth table. . . . . . . . . . 173
Figure 8.16 Multiple flavors of the three-state buffer. From left
to right: active-HIGH enable buffer, active-LOW
enable buffer, active-HIGH enable inverter, and
active-LOW enable inverter. . . . . . . . . . . . . 174
Figure 8.17 Eight sources sharing a 1-bit line. . . . . . . . . . . 174
Figure 8.18 74541 three-state buffer symbol and schematic. . . 175
Figure 8.19 74541 Verilog implementation. . . . . . . . . . . . 175
Figure 8.20 74148 priority encoder logic symbol and equations. 176
Figure 8.21 74148 schematic showing implementation of the
priority encoder. . . . . . . . . . . . . . . . . . . . 177
Figure 8.22 74148 Verilog implementation of the priority
encoder. . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 8.23 (Top) 74151 MUX schematic and logic symbol and
(bottom) 74151 MUX truth table. . . . . . . . . . . 179
Figure 8.24 Verilog implementation of the 74151 8:1 MUX. . . 180
Figure 8.25 (Top) XOR cascade as a sequence or chain and
(bottom) tree structure XOR cascade. . . . . . . . . 180
List of Figures xxv
Figure 8.26 Using four XOR gates to build a 4-bit magnitude

comparator. . . . . . . . . . . . . . . . . . . . . . 181
Figure 8.27 74682 magnitude comparator IC. . . . . . . . . . . 184
Figure 8.28 74682 IC outputs used to determine other magnitude
relationships. . . . . . . . . . . . . . . . . . . . . 184
Figure 9.1 Mealy machine. . . . . . . . . . . . . . . . . . . . 192
Figure 9.2 Moore machine. . . . . . . . . . . . . . . . . . . . 193
Figure 9.3 Flip-flop. In1 and In2 are inputs. Ck is the clock
input to the flip-flop. It synchronizes the changes in
the outputs Q and Q. . . . . . . . . . . . . . . . . 194
Figure 9.4 Clock signal. The FF output can change on the edge
and during the time period the clock is high. . . . . 194
Figure 9.5 S-R flip-flop symbol. . . . . . . . . . . . . . . . . 195
Figure 9.6 S-R flip-flop characteristic table. Q+ is the next state
of Q. If Q(t) is the value of Q at time t, then Q+ is
Q(t + 1). . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 9.7 The Karnaugh map for an S-R flip-flop. . . . . . . 196
Figure 9.8 S-R flip-flop state diagram. Arrows represent state
transitions. The conditions for the transitions are
listed next to the arrows. . . . . . . . . . . . . . . 196
Figure 9.9 T flip-flop. . . . . . . . . . . . . . . . . . . . . . . 197
Figure 9.10 T flip-flop characteristic table. . . . . . . . . . . . 197
Figure 9.11 Karnaugh map for a T flip-flop. . . . . . . . . . . . 198
Figure 9.12 T flip-flop state diagram. Arrows represent state
Figure 9.13 J-K flip-flop. . . . . . . . . . . . . . . . . . . . . . 199
Figure 9.14 J-K flip-flop characteristic table. . . . . . . . . . . 199
Figure 9.15 Karnaugh map for a J-K flip-flop. . . . . . . . . . . 199
Figure 9.16 J-K flip-flop state diagram. Arrows represent state
Figure 9.17 D flip-flop. (a) S-R FF configured as a D FF and
(b) S-R FF configured as a J-K FF, which is then
configured as a D FF. . . . . . . . . . . . . . . . . 201
Figure 9.18 D flip-flop characteristic table. . . . . . . . . . . . 201
Figure 9.19 D flip-flop state diagram. Arrows represent state
xxvi List of Figures
Figure 10.1 Simple chain of inverters. . . . . . . . . . . . . . . 208

Figure 10.2 (a) Oscillator realization with a single inverter in
feedback configuration and (b) output waveform. . 209
Figure 10.3 Two-inverter chain (a) storing 1 and (b) storing 0. . 210
Figure 10.4 S-R latch. (a) Schematic showing inputs and outputs
and (b) truth table showing different operations. . . 210
Figure 10.5 K-map groupings for S-R latch: (a) minterm
groupings and (b) maxterm groupings. . . . . . . . 211
Figure 10.6 S-R latch implementations: (a) NOR gate based and
(b) NAND gate based. . . . . . . . . . . . . . . . . 212
Figure 10.7 S-R latch timing diagram. (a) Timing for HOLD,
RESET and SET operations (valid inputs) and (b)
timing showing resulting oscillations due to invalid
input R=S=1 switching to R=S=0. . . . . . . . . . . 212
Figure 10.8 Graphical depiction of the race condition associated
with the S-R latch. . . . . . . . . . . . . . . . . . 213
Figure 10.9 A clock signal. . . . . . . . . . . . . . . . . . . . 214
Figure 10.10 Level-sensitive clocking. . . . . . . . . . . . . . . 215
Figure 10.11 Clocked S-R flip-flop implementation and symbol. 215
Figure 10.12 Clocked S-R flip-flop truth table. . . . . . . . . . . 216
Figure 10.13 Clocked S-R flip-flop timing diagram. . . . . . . . 217
Figure 10.14 Clocked J-K flip-flop implementation and symbol. . 217
Figure 10.15 Clocked J-K flip-flop truth table defining different
FF operations. . . . . . . . . . . . . . . . . . . . . 218
Figure 10.16 Clocked J-K flip-flop timing diagram. . . . . . . . 218
Figure 10.17 Trace of the J-K FF in the race condition for 5 × td . 219
Figure 10.18 Trace of the J-K FF in the race condition for 5 × td . 220
Figure 10.19 Clock pulse–narrowing circuitry used to realize
edge triggering. . . . . . . . . . . . . . . . . . . . 220
Figure 10.20 Pulse-narrowing circuitry operation. . . . . . . . . 221
Figure 10.21 Positive and negative edges. . . . . . . . . . . . . . 222
Figure 10.22 J-K FF symbols. (Left) Positive edge triggered.
(Right) Negative edge triggered. . . . . . . . . . . 222
Figure 10.23 DSETL: pulse-narrowing circuitry. . . . . . . . . . 222
Figure 10.24 DSETL: performance and power consumption
characteristics. . . . . . . . . . . . . . . . . . . . . 223
Figure 10.25 Master-slave clocking of D LSLs. . . . . . . . . . 224
List of Figures xxvii
Figure 10.26 Master-slave clocking operation. When the clock is

HIGH, the master is enabled and the slave is in the
HOLD state. When the clock is LOW, the master is
in the HOLD state and the slave is enabled. . . . . 224
Figure 10.27 Master-slaveclocking of J-K FFs illustrating no
race-around condition when J=K=1 and clock is
HIGH. . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 10.28 Master-slaveclocked J-K FF operation. . . . . . . . 225
Figure 10.29 Timing diagram of a master slave J-K flip-flop
illustrating ones catching. . . . . . . . . . . . . . . 226
Figure 10.30 Efficient implementation of Master-Slave D FF in
CMOS technology . . . . . . . . . . . . . . . . . 227
Figure 10.31 Commercial flip-flop: 7474 obtained from a TTL
data book. . . . . . . . . . . . . . . . . . . . . . . 229
Figure 10.32 IEEE FF symbols and types. . . . . . . . . . . . . 229
Figure 10.33 Commercial flip-flop: 74175. . . . . . . . . . . . . 230
Figure 10.34 Timing diagram of a J-Kflip-flop with PR and CLR
inputs. . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 10.35 A 3-bit binary counter . . . . . . . . . . . . . . . . 231
Figure 10.36 3-bit binary counter operation. . . . . . . . . . . . 232
Figure 10.37 4-bit ring counter. . . . . . . . . . . . . . . . . . . 232
Figure 10.38 4-bit ring counter operation. . . . . . . . . . . . . 233
Figure 10.39 Effect of width of set pulse. . . . . . . . . . . . . . 234
Figure 10.40 At the asynchronous input a synchronizing D flip-
flop is used to overcome metastability and timing
constraints. . . . . . . . . . . . . . . . . . . . . . 235
List of Tables
Table 7.1 Summary of cluster size and gate size relationship for
three-variable and four-variable K-maps. . . . . . . . 142
xxix
List of Abbreviations
BCD Binary coded decimal

SOP Sum of products
POS Product of sums
HDL Hardware description language
MSI Medium scale integration
FPGA Field-programmable gate array
PLD Programmable logic device
PLA Programmable logic array
ROM Read only memory
RTL Register transfer logic
ASIC Application specific integrated circuit
EDA Electronic design automation
APR Automatic place and route
FSM Finite state machine
HLSM High-level state machine
ISA Instruction set architecture
SRAM Static random access memory
DRAM Dynamic random access memory
TTL Transistor transistor logic
CMOS Complementary metal oxide semiconductor
CCD Charge coupled device
APS Active pixel sensors
IC-CAD Integrated circuit computer aided design
MSB Most significant bit
LSB Least significant bit
MUX Multiplexer
FF Flip flop
xxxi
1
Introduction
The goal of this lecture is to outline the objectives of the course and provide
a spring-board and perspective to the world of digital design.
1.1 Objectives
The goal of this course is to teach design techniques and then apply them
in a microprocessor1 design near to the completion of the course. Digital
design exists on many tracks, but the three tracks that will be handled in
this course are: theoretical representation through equations and basic gates,
implementation options using fabricated hardware, and sequential design
techniques.
1.1.1 Equation representation

The chapters under this representation take into account the development
of the theoretical framework necessary to understand digital design. First,
we begin with number systems to familiarize ourselves with the idea
of arithmetic with numbers in different bases. This sets up the idea of
arithmetic in binary (base 2). After a few examples, the concepts of number
representations and codes are introduced. Numbers can be represented in
1
A microprocessor can be programmed to execute various types of computational tasks
without requiring to redesign the hardware since the accompanying digital memories store
the application program in the form of binary information units, called bits, and work in
conjunction with the microprocessor to perform the intended tasks.
1
2 Introduction
different ways: signed magnitude, 1’s complement, 2’s complement, etc. We

use different number representations to show that some have advantages over
others and that choosing one number representation over another in hardware
could imply more complex circuitry. Binary coded decimal (BCD) numbers
are then used to bridge the gap between the computer world and human
understanding; BCD codes are essentially methods devised for hardware to
use binary numbers with decimal procedures so that humans can easily trace
through arithmetic.
After an extensive introduction into number systems, Boolean algebra
is introduced. The Boolean algebra lecture strives to set up the Boolean
algebra theory and provide a switching circuit implementation of Boolean
algebra. The Boolean expressions (or equations) are the first flavor of logic
representation. Boolean expressions are then taken one more level beyond
switching circuits to logic gates. The AND, OR, NOT, XOR, and XNOR
gates are introduced along with other functions, NAND, NOR, etc. Gate level
depiction provides enough introductory information to understand real-world
problems that may occur.
The problems are introduced in the timing diagrams lecture which focuses
on the role time plays in circuits and why switching time should be an
important factor a designer should be aware of when designing circuits.
Switching time or circuit delays may cause a theoretically flawless circuit
design to exhibit glitches and, therefore, fail in certain instances depending on
design specifications. Two types of hazards are mentioned: Static 1 hazards
and Static 0 hazards.
The equation representation culminates with the idea of translating
behavioral objectives to circuit equations and gate level schematics. The
lectures on combinational logic design will introduce the concept of thinking
through design problems and providing solutions in the form of equations.
These equations or expressions will be of the form of a sum of products
or a product of sums. Logic minimization techniques using Karnaugh maps
will be introduced to supplement Boolean algebra minimization techniques
previously learned. The visual Karnaugh map minimization will only work
effectively for less than five or six Boolean variables. Beyond that, the method
becomes cumbersome and a tabular method, known as the Quine–McCluskey
(Q-M) method, will be discussed toward the end of the course to show that
no matter how many input variables exist, the Q-M method can allow us to
derive the minimized Boolean equations.
1.1 Objectives 3
1.1.2 Hardware platform implementation

With the introduction of Boolean algebra, problems with respect to timing
inherent in real designs, and logic minimization completed, real-world
hardware implementations are considered. This phase of the course deals
with implementing Boolean functions using distinct components. It is not
as different from the previous section, except now the gates are physical
MSI gates. The design in this phase will coincide nicely with the laboratory
experiments since MSI chips are used in lab for hardware verification. In
addition to using gates to implement Boolean functions, multiplexers and
decoders are introduced to further add to the designers’ toolbox.
The decoder implementation of Boolean functions is especially
interesting because it introduces the basic workings of a read only memory
(ROM). This is the first true connection between Boolean functionality and
memory. It shows that the canonical sum of products and the product of
sums may be obtained by “reading” from memory locations that return
either true or false. The ROM cannot be changed and only implements one
Boolean function. The extension of the ROM implementation to one that
can withstand reprogramming to multiple Boolean functions is accomplished
with the programmable logic devices (PLDs). As the name suggests, the
PLDs can be programmed to implement different Boolean functions. There
are various types of PLDs such as programmable logic arrays (PLA) and the
field-programmable gate arrays (FPGA).
The PLA uses programmable AND and OR gates for direct
implementation of combinational logic in the canonical sum of products and
product of sums forms. It differs from the ROM in that the Boolean logic
function can be modified and reprogrammed. As will be seen, the circuits
implemented in the canonical form are very expensive in terms of hardware
resources. Also as Karnaugh maps explode to over 5 or 6 variables, the ability
of the design engineer to effectively minimize a Boolean function by hand
is very limited. Therefore, a more compact, intuitive design space called
sequential design is used.
FPGAs use a grid of logic gates that can be programmed on field by the
end-customer to implement arbitrary logic configurations. They also include
storage devices to implement sequential logic. The end-customer can test the
initial design of a digital circuit on FPGA, determine possible improvements
over the initial design, and make changes on the circuit. The FPGA then can
be reprogrammed to test the improved design. FPGAs are crucial in rapid
prototyping and reduce the test times and costs.
4 Introduction
In very large-scale designs, it becomes impossible to design every single

logic block by hand because it would take an infeasibly long time to obtain
an initial design. Engineers have created ingenious solutions to overcome this
problem by forming conventions that can define the circuits by their desired
functionality. These conventions are commonly referred to as hardware
description languages (HDLs). HDLs can be used to generate an initial design
of a digital circuit by defining the circuit structure and the circuit operations
in text. Verilog, VHDL, and SystemC are the most common HDLs used in
the industry.
For example, an engineer can first come up with the high level design
of a digital system, which he can implement in register transfer level (RTL)
using an HDL such as Verilog. RTL is an abstraction level that models the
digital circuits by defining the signal flow between registers and the logical
operations performed on these signals. The designer can then test and verify
the design using software tools. After the initial testing, the designer can
synthesize the design specified in Verilog using electronic design automation
(EDA) tools. This process converts the RTL level design into a netlist of logic
gates. The synthesized design can be further tested for functional correctness
and circuit timing using software tools and FPGAs. Finally, the design can be
physically laid out for fabrication using automatic place and route tools. The
steps mentioned above can be iterative and additional testing may be needed
at each step. This design methodology is referred to as application specific
integrated circuit (ASIC) design.
It is, therefore, of utmost importance that the digital design engineers
should attain the necessary skills to tackle the ever-increasing digital design
complexity by learning how to design using an industry standard HDL
such as Verilog. However, this does not mean that the manual design
skills are no longer necessary. In fact, it is the opposite. Automated tools
may not always provide the best performing or optimal design, and high-
performance system design requires careful manual design. Therefore, the
correct design methodology must be learned systematically. Systematic
design methodologies for both combinational and sequential system designs
will be provided in the following lectures.
1.1.3 Sequential design

Sequential design may be more compact due to reusing hardware, but it is
slower than combinational logic. Sequential design combines combinational
logic with memory and will be introduced from simple memory elements
1.1 Objectives 5
(cross-coupled inverters) to more complex and multi-bit memories (flip

flops and registers). Timing diagrams with flip flops, counters, and registers
are introduced before an in-depth procedure on how to design finite state
machines (FSM) using the Mealy machine or the Moore machine.
The FSM design phase will strive to set apart the combinational logic
design with the sequential design. Some problems that were tackled using
combinational logic will show that they can be implemented with fewer
hardware resources in sequential design. As number of states are kept low, the
hand design of FSMs are quite useful to help the designer minimize states,
but as the problem to be solved becomes more complex and the number of
states explodes, then a better method of design is necessary.
The introduction of high-level state machines (HLSMs) is made. HLSMs
are considered as problems become more complex, and inputs and outputs
are no longer single bits. The HLSM lecture is coupled with Verilog code
implementation because it provides a flavor as to how design is actually
done in industry. Most digital engineers do not go through the process of
minimizing Karnaugh maps or hand minimizing large state tables. The use of
HDLs such as Verilog is the key to quicker, robust logic implementations.
The motivation behind the switch to sequential design lies in the fact that
as the problem becomes more complex, logic design with Boolean algebra
and combinational design becomes very tedious. As FSMs were used to
alleviate this tediousness, as the state space grew, FSMs became tedious
because the number of flip-flops and their associated combinational gates also
grew substantially. Then HLSMs were introduced to handle larger, multibit
problems. HLSMs may have fewer states than FSM implementations, but
the more abstract we represent and combine states, the farther away from
hardware we are moving. In order to implement HLSMs, a higher-level
abstraction, called RTL descriptions, is used. There are many ways to design
HLSMs, but the RTL method is mostly used.
RTL is important because it can be easily synthesized into logic gates
from Verilog description. The design procedure splits up the HLSM into
two parts: the datapath and the control. The datapath is primarily designed
with combinational logic2 while the control contains FSMs, synchronized
2
Note that if pipelining is used to improve the system throughput, the combinational logic
is partitioned into various stages and each stage then, after computing the output values from
the inputs that come from its previous stage, latches its output to a set of flip-flops. Depending
on the number of pipelining stages, the system throughput improves considerably. Since the
datapath in the case contains an overlapping multiple data from the input stream, this type
of overlapping is called temporal parallelism, i.e., time-domain parallelism. If the datapath is
6 Introduction
with clock signals that generate handshake and control signals. Handshakes
between the datapath and the control blocks are used to synchronize data
between both blocks. RTL description enables for better understanding the
microprocessor, which is why it is very important. This collection of lectures
will be augmented with a few more lectures at the backend.
1.1.4 Datapath components

The later part of the lectures will extend the RTL description into a
microprocessor description, utilizing the same concepts as before with
the dichotomy between control and datapath. More datapath components,
specifically adders and multipliers, will be provided in detail. The adder
lecture will build upon full and half adders and then introduce serial and
parallel adders. The basis of this lecture is to establish the foundation that
there are multiple methods of accomplishing tasks in digital design, and
these methods can be classified under serial or parallel methods. After the
serial adder is implemented, several parallel architectures are provided, e.g.,
parallel prefix adders, conditional sum adders, carry select adder, etc. The
adder chapter concludes by connecting to an earlier lecture on the subtraction
of 2’s complement numbers.
With addition and subtraction covered, multiplication and division are
introduced. Multipliers are expounded on in detail following the same path
as the adder lecture with serial and parallel multiplication. Both encoded
schemes for multiplication are discussed for 2’s complement multiplication
before division is introduced. Although there are serial and parallel dividers,
serial dividers are not discussed in these lectures. The reason behind this is
that most designers today use serial division. Two main division algorithms
will be covered: restoring and nonrestoring algorithms. This division and
multiplication lecture essentially covers an essential part of the arithmetic
logic unit. The arithmetic logic unit is used in various applications, with the
general-purpose processor as the quintessential.
1.1.5 Backend lectures

The backend of these series of lectures holds value in the sense that
it combines the knowledge of the previous lectures to explain higher
level concepts like the general-purpose processors, Boolean and state
replicated multiple times to improve the system throughput, it is called spatial (space-domain)
parallelism.
1.2 Analog vs. Digital 7
minimization techniques, PLDs, and memory implementation. Besides the

minimization techniques lecture, these backend lectures provide potential
avenues of specialization for digital designers. The general-purpose processor
lecture will build upon the idea of a general-purpose processor with three
instructions. Afterwards, the concept of an instruction set architecture (ISA)
is introduced. The ISA provides the description necessary to determine what
a general-purpose processor can or cannot do. Afterward, an 8-bit general-
purpose processor example is described and a sample instruction set is
provided.
The general-purpose processor lecture gives room for the minimization
lecture, which looks at the Q-M method of minimization of Boolean functions
and state minimization techniques when implementing state machines. These
minimization tools show systemic ways of performing minimization that
allows for writing programs to go through this process. A large part of
digital design is being able to automate part of the design process; so
knowing algorithms that aid such automation is essential. The Q-M method
is compared to the Karnaugh map method from earlier lectures and the
state minimization method is compared to the intuitive reasoning of state
minimization used in the FSM lectures.
The minimization lectures yield way to the PLD lecture. In this lecture,
several fabrics are discussed, specifically, ROMs, PLA devices, complex
PLDs, and field PLAs. These fabrics are used to rapidly prototype Boolean
functions and are very useful for quickly designing products. After the PLD
lecture, a primer on memory is provided. The memory lecture will start with
memory hierarchies that may be part of a computing machine or server and
give reasons why many different levels of memory exist. Then the static
random access memory will be discussed in detail, juxtaposed with the
dynamic random access memory (DRAM). A brief mention of other types
of memory will then be discussed, focusing on promising future memory that
students may encounter during their studies or research. The memory lecture
is the final lecture in these series of lectures, so it deals more with devices
than other lectures.
1.2 Analog vs. Digital

The design space over the last 40+ years has moved from analog to digital.
An analog signal contains many frequencies while a digital signal is a
string of 0’s and 1’s as shown in Figure 1. The periodic analog signal can
be denoted as a superposition of multiple frequencies whose amplitudes
8 Introduction
Figure 1.1 Digital and analog signals.
may differ and is often represented by a Fourier series (http://www.fourier

series.com/fourierseries2/Lectures/ Intro_to_FS_lecture/index.html).
Digital signals normally take two values that are denoted as “Logic
0” and “Logic 1.” These can be different for different technologies, for
example, transistor–transistor logic values for Logic 0 at the output of logic
gates are voltages <0.4 V and Logic 1 is between 3.6 and 5 V. However,
modern complementary metal oxide semiconductor (CMOS) technology uses
a transistor and wire shrinking mechanism to scale down the supply voltage
progressively with the goal to minimize power consumption. This scaling
mechanism has allowed CMOS technology to grow the number of transistors
in a chip to several billion transistors within 1 cm2 of the silicon area and the
power supply voltage is typically between 700 mV and 1 V. Digital signals are
grouped into two levels, making them much simpler to deal with than analog
signals. Analog signals can take on values from 0 V to whatever the power
supply may provide. Analog signals for over-the-counter components may
require voltages between 15 and –15 V, i.e., a 30-V differential. Over-the
counter digital components usually do not require such a large differential.
Power consumption for analog circuits is, therefore, usually larger than digital
circuits.
In addition to power consumption, digital design has an advantage over
analog design in terms of density. Analog design usually involves very careful
design and methods that increase chip area. Since digital design is only
concerned with two logic levels, as long as these levels can be deciphered,
we do not care if the signal level is 0.1 or 0.09 V. Some simplification can
be made in digital, thereby allowing for simpler designs than their analog
counterpart. Simpler designs also mean better automation; so digital designs
can be generated by a computer program, while analog designs cannot. Also
by reducing the precision of a system to two levels, digital designs can be
operated much more quickly than analog design; hence, they are usually
1.2 Analog vs. Digital 9
much faster. It must be noted that faster circuits entail faster processing; so
analog processing that can be done digitally has quickly shifted to digital,
hence the ubiquitous scene of digital systems today. A few examples of
applications that were once analog and shifted to digital are provided below:
Still Photography: NASA has been very instrumental in the development of

the digital photography. They wanted an alternative to the use of vacuum
tubes on satellites for astronomy. The answer they sought was in the
development of the charge-coupled device (CCD) in Bell Laboratories. This
invention allowed the revolutionary explosion of digital photography (Figure
1.2). Today, CCD is on its way out and active pixel sensors with better
resolution, smaller size, and cheaper manufacturing costs are used in digital
cameras. Digital photography is definitely more prevalent than its analog
counterpart today because they are easy to transmit over long distances, easier
to store, and do not require hours for film exposure.
Figure 1.2 An Olympus digital camera and a picture from it stored as compressed digital bit
strings.
Sound and Video Recording: Just like photography, video recording has
changed significantly over the years. Today, Blu-Ray and digital video discs
(DVDs) are used to store video digitally. With the invention of the DVD
player and disks, analog video tapes such as video home system (VHS)
market were wiped out (Figure 1.3). The same pattern was observed after
CDs were invented. Although tape players stuck around much longer, their
longevity coincided with the lack of accessible CD burners. When CD burners
were more available to the consumer, the audio tape industry saw its last
throes.
Watches: Analog and digital watches have managed to coexist and one has
not completely taken over. Although analog watches were first invented,
10 Introduction
Figure 1.3 High-density DVD and analog VHS tape.
digital watches with their added functionality have been unable to make them
invalid. The reasons may be superficial to the point of marketing, preference,
and perception. Analog watches are usually viewed as more suave than the
digital watch, which is more casual and sporty (Figure 1.4).
Figure 1.4 A Rolex analog watch is priced at $10,000 while its digital counterpart may cost
only $150.
Television: TV sets and TV signal transmission have moved to the digital

domain. In the U.S., analog channels are no longer available. In Ann Arbor,
you may be able to get a couple of analog Canadian broadcast TV with an
antenna, but no more analog broadcasting is made in USA. Hence, television
1.3 Digital Design 11
production today is far friendlier to digital signals. For example, with an

antenna, the TV is able to show what shows will be on next and provide
descriptions of shows. Display technology today has phased out the CRT
monitors, and high definition televisions use active matrix LCDs, plasma, and
organic LEDs. Whereas the black-to-white contrast ratio that delineates the
picture quality attainable in CRT displays is in upper 100s, the contrast ratio
with LCD TV is about 50,000, with new generation LED back-lit LCD TV is
about 1,000,000 and it is above 2,000,000 with organic LED TV. The current
dominant digital TV manufacturers are Samsung Electronics, Panasonic,
Toshiba, Philips, LG Electronics, ProScan, Kogan, Sony, and Vizio. They
have pushed the TV technology beyond high-definition (HD), and currently
they have introduced more advanced designs such as ultra-high-definition
(UHD), three-dimensional (3D), and web television.
Telephony: Cordless telephones became digital because digital signals are

easier to compress, transmit, encode, and decode compared to analog signals
(Figure 1.5). Analog cordless phones would be choppy over a long distance
while talking; so, virtually, all cordless phones today are digital. Cellphones
became an extension of the cordless phone principle and so are all devices
that work with digital signals. The companies who still dabble with analog
telephony are in niche markets and find profit in the fact that they do not need
to sell very many analog telephones because the production cost for each
telephone is cheaper than the digital phone.
Figure 1.5 From the Gower model (1912) to modern cell phones: the phone industry went
digital.
12 Introduction
1.3 Digital Design

The objectives of the course have been laid out and many examples have
shown how digital design for several important applications has overtaken
analog design. The truth of the matter is digital design lies in a large space
and requires the amalgamation of different skills in order to take an idea
or specification and turn it into a product. This section will provide three
broad levels (behavioral, structural, and geometric) of digital design and then
attempt to provide a picture of what digital designers actually do.
1.3.1 Levels of digital design

Behavioral
Behavioral level lies in using English words, equations, or programming
languages to describe circuit actions and activities. Included in this level
are FSM flow descriptions, Boolean equations, RTL design, and using HDLs
such as VHDL or Verilog to describe circuit block behavior. An example of
a Verilog behavioral description of an arithmetic adder unit that provides the
digital sum of two binary bits along with an input carry bit is shown in Figure
1.6. Inputs and outputs are defined and the code essentially uses an equation
to relate the inputs to the output.
module add2bit (A, B, Cin, S);

input [1:0] A, B;
input Cin;
output reg [1:0] S;
always @ (A or B or Cin)
begin
S = A+B+Cin;
end
endmodule
Figure 1.6 Example of a behavioral description of a 2-bit adder in Verilog.
Structural
Structural level lies in creating a schematic representation out of behavioral
descriptions. There are different flavors of structural implementation, e.g.,
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Lectures On Digital Design Principles (River Publishers Electronic Materials, Circuits and Devices) 1st Edition Pinaki Mazumder

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Lectures On Digital Design Principles (River Publishers Electronic Materials, Circuits and Devices) 1st Edition Pinaki Mazumder

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Lectures on Digital Design Principles

(River Publishers Electronic Materials,

Electrical and Electronic Devices, Circuits, and

Electronic Devices, Circuits, and Applications 8th

Understanding Nanoelectromechanical Quantum Circuits

Electronic Devices and Circuits: In Three Volumes 2nd

Introduction to Analog-to-Digital Converters:

Multiplier-Cum-Divider Circuits: Principles, Design,

Radiation Detection Systems: Sensor Materials, Systems,

Analog Function Circuits: Fundamentals, Principles,

Jan van der Spiegel Dennis Sylvester

Massimo Alioto Mikael Östling

Koﬁ Makinwa Albert Wang

For a list of other books in this series, visit www.riverpublishers.com

Distributed exclusively by Routledge

ISBN 978-87-7022-361-4 (print)

List of Figures xvii

List of Tables xxix

List of Abbreviations xxxi

2 Numeral Systems and BCD codes 17

2.1.2.5 Converting from one arbitrary base (p) to

3 Boolean Algebra and Logic Gates 51

3.5.5 Concept of completeness . . . . . . . . . . . . . . . 67

5 Combinational Logic Design Techniques: Part I 99

6 Combinational Logic Design Techniques: Part II 115

7 Combinational Logic Minimization 135

8 Combinational Building Blocks 155

8.3.6.1 Equality . . . . . . . . . . . . . . . . . . 181

9 Foundations of Sequential Design: Part I 191

10 Foundations of Sequential Design: Part II 207

10.2.3.1 Narrowing the clock pulse width . . . . . 220

About the Authors 247

information technology loom upon boundless opportunities for innovations.

Though the book is compilation of my lectures and my coauthor has helped

Pinaki Mazumder, Professor

Figure 1.1 Digital and analog signals. . . . . . . . . . . . . . 8

Figure 2.9 Graphically comparing 4-bit (a) signed magnitude

Figure 2.25 Gray encoded digital signal generation by using an

Figure 6.3 OR-AND to NOR-NOR conversion and vice versa.

Figure 7.8 Four-variable K-map showing that groupings of

Figure 8.8 (a) Four-input K-map representation of L, (b) three-

Figure 8.26 Using four XOR gates to build a 4-bit magnitude

Figure 10.1 Simple chain of inverters. . . . . . . . . . . . . . . 208

Figure 10.26 Master-slave clocking operation. When the clock is

BCD Binary coded decimal

1.1.1 Equation representation

different ways: signed magnitude, 1’s complement, 2’s complement, etc. We

1.1.2 Hardware platform implementation

In very large-scale designs, it becomes impossible to design every single

1.1.3 Sequential design

(cross-coupled inverters) to more complex and multi-bit memories (ﬂip

1.1.4 Datapath components

1.1.5 Backend lectures

minimization techniques, PLDs, and memory implementation. Besides the

1.2 Analog vs. Digital

Figure 1.1 Digital and analog signals.

may differ and is often represented by a Fourier series (http://www.fourier­

Still Photography: NASA has been very instrumental in the development of

Figure 1.3 High-density DVD and analog VHS tape.

Television: TV sets and TV signal transmission have moved to the digital

production today is far friendlier to digital signals. For example, with an

Telephony: Cordless telephones became digital because digital signals are

1.3 Digital Design

may differ and is often represented by a Fourier series (http://www.fourier