DATA SHEET

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Quad 2-Input NAND Gate

14
MM74HCT00
1

General Description TSSOP−14,

The MM74HCT00 is a NAND gates fabricated using advanced CASE 948G
silicon−gate CMOS technology which provides the inherent benefits
of CMOS—low quiescent power and wide power supply range.
This device is input and output characteristic and pin−out compatible MARKING DIAGRAM
with standard 74LS logic families. All inputs are protected from static
14
discharge damage by internal diodes to VCC and ground.
MM74HCT devices are intended to interface between TTL and $Y&Z&2&K
NMOS components and standard CMOS devices. These parts are also HCT00G
plug−in replacements for LS−TTL devices and can be used to reduce
power consumption in existing designs. 1

Features $Y = Logo
• TTL, LS Pin−out and Threshold Compatible &Z = Assembly Plant Code
&2 = 2−Digit Date Code
• Fast Switching: tPLH, tPHL = 14 ns (typ.) (Year and Week)
• Low Power: 5 mW at DC &K = 2−Digit Lot Run
Traceability Code
• High Fan Out, 10 LS−TTL Loads
HCT00 = Device Code
• This Device is Pb−Free and Halide Free
(Note: Microdot may be in either location)

Connection Diagram
LOGIC DIAGRAM
(1 of 4 gates)

ORDERING INFORMATION
See detailed ordering and shipping information on page 4 of
this data sheet.

Top View

Figure 1. Pin Assignments for TSSOP

© Semiconductor Components Industries, LLC, 1984 1 Publication Order Number:

November, 2022 − Rev. 2 MM74HCT00/D
 MM74HCT00

ABSOLUTE MAXIMUM RATINGS (Note 1)

Symbol Parameter Rating Unit
VCC Supply Voltage −0.5 to +7.0 V
VIN DC Input Voltage −0.5 to VCC +0.5 V
VOUT DC Output Voltage −0.5 to VCC +0.5 V
IIK, IOK Clamp Diode Current ±20 mA
IOUT DC Output Current, per pin ±25 mA
ICC DC VCC or GND Current, per pin ±50 mA
TSTG Storage Temperature Range −65 to +150 °C
TL Lead Temperature (Soldering 10 seconds) 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Unless otherwise specified all voltages are referenced to ground.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit
VCC Supply Voltage 4.5 5.5 V
VIN, VOUT DC Input or Output Voltage 0 VCC V
TA Operating Temperature Range −55 +125 °C
tr, tf Input Rise or Fall Times − 500 ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.

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 MM74HCT00

DC ELECTRICAL CHARACTERISTICS (VCC = 5 V ±10% (unless otherwise specified))

TA = −40°C TA = −55°C
TA = 25°C to 85°C to 125°C

Symbol Parameter Conditions Typ. Guaranteed Limits Unit

VIH Minimum HIGH Level − 2.0 2.0 2.0 V
Input Voltage

VIL Maximum LOW Level − 0.8 0.8 0.8 V

Input Voltage
VOH Minimum HIGH Level VIN = VIH or VIL, VCC VCC − 0.1 VCC − 0.1 VCC − 0.1 V
Output Voltage ⎮IOUT⎪ = 20 mA
VIN = VIH or VIL, 4.2 3.98 3.84 3.7
⎮IOUT⎪ = 4.0 mA,
VCC = 4.5 V
VIN = VIH or VIL, 5.2 4.98 4.84 4.7
⎮IOUT⎪ = 4.8 mA,
VCC = 5.5 V
VOL Maximum LOW Level VIN = VIH 0 0.1 0.1 0.1 V
Voltage ⎮IOUT⎪ = 20 mA
VIN = VIH 0.2 0.26 0.33 0.4
⎮IOUT⎪ = 4.0 mA
VCC = 4.5 V
VIN = VIH 0.2 0.26 0.33 0.4
⎮IOUT⎪ = 4.8 mA
VCC = 5.5 V
IIN Maximum Input Current VIN = VCC or GND, − ±0.05 ±0.5 ±1.0 mA
VIH or VIL
ICC Maximum Quiescent VIN = VCC or GND, − 1.0 10 40 mA
Supply Current IOUT = 0 mA
VIN = 2.4 V or 0.5 V 0.18 0.3 0.4 0.5 mA
(Note 2)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. This is measured per input with all other inputs held at VCC or ground.

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3
 MM74HCT00

AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0 V, tr = tf = 6 ns, CL = 15 pF, TA = 25°C (unless otherwise specified))

Symbol Parameter Conditions Typ. Guaranteed Limit Unit

tPLH, tPHL Maximum Propagation Delay 14 18 ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0 V ±10%, tr = tf = 6 ns, CL = 50 pF (unless otherwise specified))

TA = 25°C TA = −40°C TA = −55°C

to 85°C to 125°C

Symbol Parameter Conditions Typ. Guaranteed Limits Unit

tPLH, tPHL Maximum Propagation Delay 18 23 29 35 ns
tTHL, tTLH Maximum Output Rise 8 15 19 22 ns
and Fall Time

CPD Power Dissipation Capacitance (Note 3) 30 − − − pF

CIN Input Capacitance 5 10 10 10 pF

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption,
IS = CPD VCC f + ICC.

ORDERING INFORMATION
Device Package Shipping†
MM74HCT00MTCX TSSOP−14 WB, Case 948G 2500 Units / Tape & Reel
(Pb−Free and Halide Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NOTE: All packages are lead free per JEDEC: J−STD−020B standard.

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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

TSSOP−14 WB
CASE 948G
14 ISSUE C
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF NOTES:
1. DIMENSIONING AND TOLERANCING PER
0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
N EXCEED 0.15 (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE
2X L/2 INTERLEAD FLASH OR PROTRUSION.
M INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE DAMBAR
−U− N PROTRUSION. ALLOWABLE DAMBAR
PIN 1 PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IDENT. F IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 7
DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
0.15 (0.006) T U S
A K
MILLIMETERS INCHES
K1

ÉÉÉ
ÇÇÇ
−V− DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200

ÇÇÇ
ÉÉÉ
B 4.30 4.50 0.169 0.177
J J1 C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
SECTION N−N G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C −W− K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
0.10 (0.004) L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
−T− SEATING D G H DETAIL E
PLANE GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT XXXX
XXXX
7.06
ALYWG
G
1 1

A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
0.65 G = Pb−Free Package
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
14X
device data sheet for actual part marking.
14X Pb−Free indicator, “G” or microdot “G”, may
0.36
1.26 or may not be present. Some products may
DIMENSIONS: MILLIMETERS
not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASH70246A Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: TSSOP−14 WB PAGE 1 OF 1

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