MLParest: Machine Learning based Parasitic

Estimation for Custom Circuit Design

Brett Shook ([email protected]), Prateek Bhansali ([email protected]),
Chandramouli Kashyap ([email protected]), Chirayu Amin ([email protected]),
Siddhartha Joshi ([email protected])
Intel Corporation, Hillsboro, OR, USA

Abstract—A novel machine learning based parasitic estimation power. Fig. 1 shows the differences in measurements between
(MLParest) method for pre-layout custom circuit design is pre-layout and post-layout simulations for this set of 10nm
presented. It reduces the error between pre-layout and post-layout analog circuits. This collection of circuits includes a duty-cycle
circuit simulation from 37% to 8% on average for different corrector, PLL clock generator, CTLE, Op-Amp, sense-
measurements across a variety of analog circuits. MLParest can amplifier, TX-driver, level-shifter, ring oscillator, and a PLL
thus greatly reduce the number of iterations between pre-layout delay line. We plot the average and maximum of absolute
and post-layout design phases. The key contributions of this work values of error (%) across a set of measurements for each circuit
are a machine learning based approach to parasitic estimation and in order to avoid cancellation of positive and negative errors.
a push-button model training framework, scalable across different
From the plot, we can see that there is a huge difference in the
technology nodes. To the best of our knowledge, a machine
learning based framework of parasitic estimation is an industry
performance of the circuits when interconnect parasitics are not
first. included in the simulations. This leads to multiple iterations
between the pre-layout and post-layout phases leading to
Keywords—parasitic estimation, resistance, capacitance, circuit resizing and layout fixes. To circumvent this problem, circuit
simulation, machine learning, post-layout, analog design designers often put excessive margins in specifications as guard
bands in pre-layout design phase. This leads to sub-optimal
designs in terms of power, performance, and area.
I. INTRODUCTION
Pre-Layout vs. Post-Layout Simulation Measurement
Traditional analog IP development cycles start with schematic
design, which is based on the architecture and specifications
expected of an analog block. After initial sizing, analog Circuit-9
designers perform performance, reliability and variation Circuit-8
analysis using a SPICE-like circuit simulator. If the circuit fails Circuit-7
to meet a specification across any process, temperature or Circuit-6
Max Error
voltage corner, analog designers must resize the circuit in the Circuit-5
schematic. This phase is known as pre-layout design. Once Circuit-4 Average Error
specifications are met in the schematic, a layout of circuit
Circuit-3
schematic is drawn. During the layout, a team of mask designers,
translates the abstract schematic to a technology specific format Circuit-2
which can be fabricated. This process is time consuming, often Circuit-1
taking anywhere from days to weeks, and is expected to be even 0.0 50.0 100.0 150.0 200.0 250.0 300.0
longer in the future as design rules of advanced technology
Error (%)
nodes become increasingly complex. Once the layout is ready,
circuit designers perform interconnect parasitic (resistance and
capacitance) extraction. Next, using the extracted parasitics Fig. 1. Bar plot showing the error in pre-layout simulation measurements
back-annotated into the schematic design netlist, post-layout when compared to the corresponding post-layout simulation measurements.
SPICE simulations are performed. Only at this stage, if all the
specifications of the analog block are met, the design cycle To address this issue, we present our machine learning based
completes. If any specification is not met in the post-layout parasitic estimation framework called MLParest in this paper.
simulations, the schematic is resized or rearchitected and sent MLParest provides an accurate estimate of expected post-layout
back for layout and extraction causing several iterations between interconnect parasitics in the pre-layout design phase. Note that
schematic and mask design phases. both the interconnect resistance and capacitance can be
estimated using MLParest to aid circuit designers. This allows
Usually, the performance of post-layout circuits is widely designers to incorporate the interconnect effects on performance
different from pre-layout circuits due to the addition of of the circuit during the schematic design stage. This reduces the
interconnect parasitics and complex device layout effects in gap between post-layout and pre-layout simulation results which
post-layout circuits. To illustrate this, we performed simulations helps reduce design iterations between these two phases.
on a set of representative analog IP blocks on a 10 nm MLParest can thus lead to a much faster turn-around time for
technology across design metrics such as delay, rise/fall time, analog designs.
duty cycle, frequency, bandwidth, DC gain, leakage current and

978-1-7281-1085-1/20/$31.00 ©2020 IEEE

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The rest of the paper is organized as follows. Section II discusses III. MACHINE LEARNING BASED PARASITIC ESTIMATION
background and related work. In Section III, we present our To address the issues outlined in the previous section, a
machine learning based parasitic estimation flow. Section IV parasitic estimation engine, MLParest, has been developed. We
summarizes the results. Section V concludes this paper. leverage machine learning techniques with existing post-layout
II. RELATED WORK extraction data to train estimation models and predict
interconnect parasitics. Machine learning has been proposed for
There are no known tools currently in the Electronic Design pre-routing timing prediction in the digital domain[6]. In the
Automation (EDA) industry which predict interconnect parasitic analog mixed signal domain, it is worthwhile to emphasize that
RC for pre-layout circuits based on just the information using a machine learning paradigm in the context of parasitic
contained in the schematics. Prior work [1], [2] has proposed estimation is an industry first.
the use of floor-planning, placement, and routing information in
addition to schematic information to estimate interconnect In order to introduce our approach to parasitic estimation, let
parasitics. However, this information is not easily available to us consider an example of a pre-layout schematic net and its
analog designers in the early stages of design, which limits its post-layout counterpart shown in Fig. 3. Here a pre-layout net
usage. There is a growing body of research on automatic transforms into a multi-port RC circuit after interconnect
generation of analog layouts [3], [4]. However, these tools are parasitics are extracted. This transformation happens for every
still not fully automated and mature. The current industry net of a circuit, which then leads to significant differences in pre-
standard practice is to either move to the initial layout phase layout and post-layout circuit simulation. With MLParest we
quickly or use designer experience to manually guesstimate the aim to estimate this RC-network for each pre-layout net and then
parasitic values for particular nets in a circuit. If the schematic use it as a proxy for the post-layout network in pre-layout
designers don’t have an accurate estimate of the interconnect simulations.
parasitics, it can take multiple cycles of re-design at both the
schematic and layout design stages which increases the total
design time.
Although interconnect capacitance affects the performance
of the circuit by directly changing its power and delay
characteristics, estimating this capacitance alone is not enough.
Interconnect resistance estimation is increasingly important as
process technology scales downward [5] and is especially
critical for analog circuits. Fig. 2. shows the large impact of
interconnect resistance on simulation accuracy by plotting the
difference between post-layout designs with and without
interconnect resistance included. Hence, it is important to
correctly estimate both R and C during the pre-layout design
phase to avoid surprises in the post-layout phase, where it is
costlier to rework the design to meet expected power and Fig. 3. Pre-layout and post-layout representation of a net.
performance targets.
A. Modeling
Error of Capacitance-only Post-layout
w.r.t. Full RC Post-layout
Extracted nets can be of an arbitrary structure, typically a
tree, with several resistors and capacitors. Each net can be
Circuit-9 different from others in terms of its topology and routing. In
Circuit-8 order to make this problem tractable with machine learning, we
Circuit-7 approximate each post-layout net using two scalars – effective
Circuit-6 capacitance and effective resistance. Effective capacitance,
Circuit-5 Max Error , is the sum of total capacitance incident on a net – including
Circuit-4
Average Error grounding and cross-capacitance to other nets. To compute
Circuit-3 effective resistance, , we use linear time-invariant (LTI)
Circuit-2 circuit theory. Here we define the concept of an effective time
Circuit-1 constant, τ , which accounts for the time constants of the
0.0 10.0 20.0 30.0 40.0 50.0 original circuit system. For a system with N poles, , , … , ,
Error (%) an effective time constant is defined as below:

Fig. 2. Bar plot showing the aggregate measurement error between τ ⋯ ⋯ (1)
simulations where interconnect resistance is removed with respect to full post-
layout interconnect resistance and capacitance.
This allows us to compute effective resistance as follows:
(2)

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 Having computed effective resistance and capacitance, we We now specialize the general ML training algorithm to the
can synthesize a post-layout net using a simple star topology problem of parasitic estimation as shown in Fig. 6. We start with
shown in Fig. 5, where where M is the number a collection of circuits with pre-layout (schematic) and post-
layout extracted (RC) data. Next, we extract features of each net
of transistor connections to the net. The star topology has a time for all circuits by traversing their netlists. The variables in the
constant equal to the effective time constant of the post-layout dataset, on a per net basis, are the features from the pre-layout
net. We selected a star topology, instead of a dense multi-port netlist which are: the number of connections on a net, the
admittance matrix, for two reasons. The first being that a dense number of hierarchies the net traverses, the number of the drain,
multi-port matrix for each net is prohibitively expensive to gate and source connections, the total width of all MOS devices,
compute. Secondly, based on our extensive testing on industry net type (internal or port), and the number of p-type and n-type
circuits we found that the star topology suffices for our parasitic
devices. The y variables are the and values from the
estimation application.
past layout circuits. We learn two functions: one for resistance
and one for capacitance. Since we use supervised learning, we
compute actual and using post-layout nets. As
explained previously, is the sum of the total incident
capacitance on a net. To compute , we first obtain a set of
dominant poles using PRIMA [8] of the multi-port net. These
dominant poles are then used to compute τ , which then
yields based on (2).

Fig. 4. Modeling of a multi-port net using the star topology.

B. Training
As shown in Fig. 5, the starting point of any Machine
Learning (ML) based approach is collecting a large amount of
training data called the dataset. In Fig. 5, is the vector of input
variables and is the response i.e. . It is this unknown
function that an ML algorithm tries to learn given a dataset.
The learning algorithm chooses from a set of candidate functions
called the hypothesis set [7]. Based on appropriate error criteria,
such as Mean Square Error (MSE) or Mean Absolute Error
(MAE), the best function from the hypothesis set is
selected. ) is an approximation to the actual function ,
which is unknown. The learned function ) is then used in Fig. 6. Model training for parasitic estimation.
applications as a proxy for ). The richness of the hypothesis
set provides a trade-off between the accuracy of the learned After evaluating several machine learning methods like
model and overfitting. At one extreme, if the hypothesis set has neural-networks, linear regression, etc., we chose the Random
only one candidate, it could turn out to be very inaccurate. On Forest model [7], [9] for supervised learning since it offered the
the other hand, if the hypothesis set has too many candidates, best prediction accuracy based on our experiments. From the
there could be overfitting since the learning algorithm could in total collection of nets derived from all the circuits in the dataset,
principle pick a candidate that fits the training data exactly. This we randomly select 70% for training and 30% for testing. We
balancing act, called the bias-variance trade-off, is at the heart used an K-fold cross-validation scheme to tune the parameters
of machine learning algorithms including ours. of the decision trees such as depth, the number of trees in the
forest, etc. We also use the RANSAC algorithm to remove
outliers [10]. These outliers may be present in the data due to
extraction with dirty layouts, inconsistency between schematic
and layout, etc.
C. Inference
Once a model has been learned, we use it to predict
interconnect parasitics of pre-layout schematic nets that haven’t
been seen before. As illustrated in Fig. 7, we first parse the pre-
layout netlist and extract the features of each net. Next, these
features are fed to the trained Random Forest models for
and yielding predicted values. Using these scalars, we
Fig. 5. Flowchart of the general machine learning paradigm. synthesize a star topology for each net. This is pictorially shown

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in Fig. 8, for an M-port net. For simulation purposes, we TABLE I. MODEL TRAINING RESULTS
generate an industry-standard format called Standard Parasitic Criterion 10nm 14nm
Exchange Format (SPEF) [11] to write estimated parasitic
Number of analog IP buildings blocks 686 212
information. SPEF file contains star topology of every net in the Number of nets 276K 176K
circuit. Finally, the pre-layout netlist and SPEF file are Cap. R2 score 0.95 0.94
consumed by SPICE-like simulators to perform circuit Res. R2 score 0.80 0.73
simulation. In analog design, it is important to have parasitic
matching at some differential nodes to reduce variation. By
design, since those nets have exactly the same features, In Fig. 9-12, we compare actual and predicted values of effective
MLParest honors analog matching. resistance and capacitance for 10nm and 14nm nets. As can be
seen, Random Forest models predict R and C well. It is observed
that the variation in resistance predictions is greater than the
variation seen in capacitance. This is potentially due to the fact
that our feature list is missing placement information which
affects wire-length and hence the resistance. As is the case with
machine learning, we do find outliers in our prediction. Based
on our investigation they usually occur on enable, clock, and
global signals with several thousands of devices connected to
them. In practice, once such signals are turned on, they do not
contribute much to measurements which affect circuit
performance due to their constant nature. However, we are
working towards improving and capturing such outliers in our
Fig. 7. MLParest inference flow diagram. modeling.

NET A MReff MReff

MReff MReff
Ceff

Fig. 8. Parasitic representation of a pre-layout net for simulation with

MLParest.

IV. RESULTS
A. MLParest training Fig. 9. Scatter plot comparing normalized actual and predicted resistance
values for 14nm
We implemented the MLParest framework and associated
model learning in Python with the scikit-learn package [12]. For
MLParest, we used 212 and 647 analog blocks to train on a
14nm and 10nm process, respectively. The 10nm and 14nm
datasets contain a wide variety of industrial analog circuits.
Table I shows some statistics for both the 10nm and 14nm
training and analysis. As part of data gathering, we first traverse
design databases for archived data. Then, we learn and
values from previous post-layout designs which is
subsequently used for training the Random Forest models. It is
important to note that, MLParest does not depend on test
benches with stimuli. Thus, we can leverage early post-layout
data available for certain key analog blocks and use it across the
board for hundreds of other designs on the same process node
without waiting for layout. MLParest has been used to gather
data and train models for several different process technologies
with very little modification to the overall flow. Fig. 10. Scatter plot comparing normalized actual and predicted capacitance
values for 14nm

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 MLParest vs. Pre-layout
w.r.t. Post-layout

Circuit-9
Circuit-8
Circuit-7
Circuit-6
Circuit-5 MLParest RC
Circuit-4
Pre-layout
Circuit-3
Circuit-2
Circuit-1
Fig. 11. Scatter plot comparing normalized actual and predicted resistance
values for 10nm 0.0 20.0 40.0 60.0 80.0 100.0 120.0
Average of absolute error (%)

Fig. 13. Average MLParest error with respect to post-layout simulation.

MLParest vs. Pre-layout

w.r.t. Post-layout

Circuit-9
Circuit-8
Circuit-7
Circuit-6
Circuit-5
ML Parest RC
Circuit-4
Circuit-3 Pre-layout
Fig. 12. Scatter plot comparing normalized actual and predicted capacitance Circuit-2
values for 10nm
Circuit-1

0.0 50.0 100.0 150.0 200.0 250.0

Maximum absolute error (%)
B. Accuracy
In this section, we present our results from using MLParest on
the nine 10nm analog circuits introduced earlier. These nine Fig. 14. Maximum MLParest error with respect to post-layout simulation.
circuits are not part of the training set. Fig. 13 shows the average
of absolute error (%) (MAE) across simulation measurements
on the 10nm test cases for pre-layout and MLParest against the
post-layout results. These metrics include delay, rise/fall time,
bandwidth, gain, average current over time, leakage current, and
oscillator frequency. Fig. 14 shows the maximum absolute error
(%) comparison between pre-layout and MLParest against post-
layout simulation results. Fig. 13 and Fig. 14 clearly show that
MLParest significantly improves simulation accuracy over pre-
layout simulations.
Fig. 15 shows the AC output response waveforms from the
Circuit 5 test case. It is clear that the MLParest predicted RC
parasitics track post-layout results for metrics such as DC gain,
peaking frequency, and bandwidth much better than the pre-
layout schematic only results. In Fig. 16, we compare transient
response of a signal. As is evident from the figure, MLParest
closes the gap between pre-layout and post-layout circuit.
Fig. 15. AC response of an output signal for Circuit 5.

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 works seamlessly across multiple industry-standard analog
simulators. MLParest is not limited to analog design and can be
used in mixed-signal validation flows as well. MLParest does
not depend on test benches with stimuli and is easily scalable
across different technology nodes. Finally, MLParest supports
industry-standard input and output formats allowing it to be
incorporated alongside a variety of EDA tools.
The experimental results show a significantly improved
accuracy with respect to pre-layout simulations. Our future work
includes early prediction for electromigration and IR drop to
avoid potential issues before the layout design phase is started.
Another possible extension of our work includes an enhanced
placement based parasitic estimation for achieving better
accuracy on designs that are sensitive to device placement.
VI. ACKNOWLEDGEMENT
We would like to thank Jian Gong, Mikalai Kisialiou,
Renuka Lokare, Sunder Kankipati, Reshma Kamat, and Kunal
Fig. 16. Transient response of a Circuit 9 Kishore for sharing background knowledge on parasitic
estimation and circuit simulator integration.
Table 2 shows data from two specific 14nm test cases. RC
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