BEC405A - MICROCONTROLLERS

2.1 An 8051 Addressing Modes:

The 8051 microcontroller supports several addressing modes that determine how operands are accessed during
instruction execution. These addressing modes provide flexibility in programming and allow efficient use of
memory. The 8051 microcontroller utilizes various addressing modes to specify the location of operands (data)
within instructions. These modes determine how the CPU retrieves the data for operations. The 8051
microcontroller utilizes various addressing modes to specify the location of operands (data) within instructions.
These modes determine how the CPU retrieves the data for operations.

1. Immediate Addressing (#)

2. Register Addressing
3. Direct Addressing
4. Indirect Addressing (@)
5. Indexed Addressing

1. Immediate Addressing (#): In immediate addressing mode, the operand is a constant value that is included in
the instruction itself. In these instructions, the # symbol is used for immediate data. In the last instruction, there
is DPTR. The DPTR stands for Data Pointer. Using this, it points the external data memory location. In the first
instruction, the immediate data is AFH, but one 0 is added at the beginning. So when the data is starting with A
to F, the data should be preceded by 0.

 The operand itself is included within the instruction byte following the opcode.
 This mode is useful for constant values that don't require separate storage in memory.

For example: MOV A, #35H (Move the immediate value 35H to the accumulator register A).

MOV R1, #25H loads the accumulator with the immediate value 25H.

2. Register Addressing (R): In register addressing mode, the operand is a register in the microcontroller. In the
register addressing mode the source or destination data should be present in a register (R0 to R7).

 The operand is located in one of the general-purpose registers (A, B, or R0 to R7) of the 8051.
 The opcode specifies which register to use.
 This mode is efficient for data already stored in registers.

For example: ADD A, R2 (Add the contents of register R2 to the accumulator A).

MOV A, R1 loads the accumulator with the contents of register R1.

3. Direct Addressing: In direct addressing mode, the operand is the address of a memory location where the data
is stored. In this mode, the source or destination address is specified by using 8-bit data in the instruction. Only
the internal data memory can be used in this mode. The first instruction will send the content of registerR6 to port
P0 (Address of Port 0 is 80H). The second one is forgetting content from 45H to R2. The third one is used to get
data from Register R5 (When register bank RB0 is selected) to register R5.

 The operand's address is directly encoded in the instruction byte following the opcode.
 This mode can only access internal RAM locations (00h to 7Fh) due to the 8-bit address limitation.

For example: MOV P1, 20H (Move the value at memory location 20H to Port 1).

MOV A, 40H loads the accumulator with the value stored at memory location 40H.

4. Indirect Addressing: In register indirect addressing mode, the operand is a register that contains the address of
the data. In this mode, the source or destination address is given in the register. By using register indirect
addressing mode, the internal or external addresses can be accessed. The R0 and R1 are used for 8-bit addresses,
and DPTR is used for 16-bit addresses, no other registers can be used for addressing purposes. Let us see some
examples of this mode. In the instructions, the @ symbol is used for register indirect addressing.

 The address of the operand is stored in a register (R0 or R1).

 The CPU first retrieves the address from the register and then fetches the actual operand from that memory
location.
 This mode provides some level of indirection, allowing you to use registers as pointers to data.

For example: MOV A, @R0 Move the value from the memory location pointed to by register R0 to A.

MOV A, @R0 loads the accumulator with the value stored at the memory location pointed to by the R0 register.

5. Indexed Addressing: In indexed addressing mode, the operand is the sum of a register and an offset. In the
indexed addressing mode, the source memory can only be accessed from program memory only. The destination
operand is always the register A.

 This mode combines an 8-bit constant with a register (usually DPTR) to form the operand's address.
 The constant is added to the content of the register to get the final address.
 This mode is useful for accessing data elements within arrays or tables stored in memory.

For example: MOV A, 10H + DPTR (Move the value from the memory location 10H bytes beyond the value in
DPTR to the accumulator A).

MOV A, 20H+R2 loads the accumulator with the value stored at memory location 20H offset by the value
in register R2.
2.1 Data Transfer Instructions:

Any instruction given to the microcontroller contains two parts: an opcode and an operand. The opcode is
responsible for telling the microcontroller what to do, whereas the operand holds the data on which the operations
are to be performed. The 8051 microcontroller has an 8-bit opcode which gives it the ability to handle 2^8(255)
instructions. The operands, on the other hand, can be of 0 bytes, 1 byte or 2 bytes. In this article, we will be talking
about the data transfer instructions in 8051 that are a subset of the instructions it offers. These instructions are
responsible for moving data from one place to another in the microcontroller.

List of data transfer instructions: Data transfer instructions are responsible for transferring data between
various memory storing elements like registers, RAM, and ROM.

 MOV Instruction
 MOVC Instruction
 MOVX Instruction
 Stack operations
o The PUSH operation
o The POP operation
 Exchange Instructions

1. MOV Instruction: The MOV instruction has two operands, the source, and the destination. The second operand
is the source, whereas the first one is the destination. This instruction uses various addressing modes to move data
in the RAM space of the microcontroller.

For examples:

o MOV A, R0 Moves data from the register R0 to the accumulator

o MOV R0,50H Moves data stored in memory location 50H to Ro
o MOV A, @R0 Uses data stored in R0 register as an address and moves the data at that location to the
accumulator

2. MOVC Instruction: The MOVC instruction is responsible for moving data from the Program memory (Flash
memory) to the RAM for processing it.

For examples:

o MOVC A, @A+DPTR
o MOVC A, @A+PC
3. MOVX Instruction: The 8051 microcontrollers in most cases has an on-chip 4K flash memory, but due to its
16-bit address bus, it can access 64k memory locations. Due to this reason, the 8051 can be interfaced with
external memory using ports 0 and 2. To access data in this external memory, the MOVX instruction is used.

o MOVX @R0, A
o MOVX A, @DPTR

4. Stack operations: The RAM of the 8051 microcontroller is home to a set of 32 general-purpose registers (00H-
1FH). These registers are 8 bits wide and are bundled in groups of 8 forming four register banks. Stack operations
can be used to place data into these registers in an efficient manner. These stack operations use special commands
(PUSH, POP) to place and extract data from these general purpose’s registers.

4.1 PUSH operation: The PUSH operation is used to place data into the stack. When this command is
given the value of address stored in the stack pointer is increased by one. After incrementing the address in the
stack pointer, data is placed at that memory location. For example, when the 8051 is powered up, it holds the
address 07H. When it receives the first PUSH instruction, the address is updated to 08H, and data is stored in that
location.

Example (R6 contains 80H and stack pointer points at 07H)

PUSH 6; This instruction moves data stored in register R6 to 08H

4.2 POP operation: The POP operation is used to extract data that is stored in the stack. This operation is
the complete opposite of the PUSH operation. It extracts the data from the location which the stack pointer points
to and then decreases the value of the SP by 1.

Example (Stack pointer points at memory location 08H which contains 50H)

POP 6; register R6 now contains the data 50H and the stack pointer points to 07H

5. Exchange Instructions: This operation is used to exchange data between the source and the destination
operands.

For example:

o XCH A, R0; Exchanges the data stored in the accumulator and R0

o XCHD A, @R0; Exchanges the lower four bits of a memory location stored in a register with the
accumulator.
2.3 Arithmetic instructions:

When it comes to crunching numbers, computers are far superior to humans. All computing devices contain an
Arithmetic Logic Unit, which is responsible for performing mathematical operations at lightning-fast speeds. A
set of registers input data into the ALU on which the ALU performs operations based on the instructions it
receives. The PSW register plays a vital role in these operations as they have special flag bits to gain additional
information about the results of these operations. The ADDITION, SUBTRACTION, MULTIPLICATION,
DIVISION, INCREMENTING AND DECREMENTING and DECIMAL ADJUST can be used to perform
arithmetic operations. The arithmetic opcodes are –

MNEMONIC OPERATION
ADD destination, source Add source to destination
ADDC destination, source Add source to destination with carry.
SUBB destination, source Subtract with barrow, source from destination
MUL AB Multiply the contents of register A and B
DIV AB Divide the contents of register A by the contents of register B
DA A Decimal Adjust the A register
INC destination Increment destination by 1
DEC destination Decrement destination by 1

2.3.1 Addition operation:

The ADD (addition without carry) and ADDC (addition with carry) opcodes are used to perform addition. For
the addition operation to occur, the destination operand should always be the accumulator, whereas the source
operand can be a memory address, data, or a register.

a. ADD Destination, Source (Addition Without Carry)

Function: Addition on two operands without carry Flags: CY, OV, AC
All addition is done with the A register as the destination of the result. All addressing modes may be used
for the source. The following table lists the addition mnemonics.

MNEMONIC OPERATION
ADD A, #n
Eg: ADD A, #3C Add A and the immediate number n ; put the sum in A
ADD A, Rr
Eg: ADD A, R4 Add A and register Rr; put the sum in A
ADD A, add
Eg: ADD A, 3C Add A and address contents; put the sum in A
ADD A, @ Rp
Eg: ADD A, @R1 Add A and the contents of the address in Rp; put the sum in A
ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumulator. Four source
operand addressing modes are allowed: register, direct, register-indirect, or immediate.

b. ADDC Destination, Source (Addition with Carry)

Function: Addition on two operands with carry Flags: CY, OV, AC
If carry is to be added to the higher order bytes of the addition operation, ADDC instruction is used. The
following table lists the ADD instruction with carry mnemonics.

MNEMONIC OPERATION
ADDC A, #n
Add A and the immediate number n and the C flag; put the sum in A
Eg: ADDC A, #45
ADDC A, Rr
Add A and register Rr and C flag; put the sum in A
Eg: ADDC A, R3
ADDC A, add
Add A and address contents and C flag; put the sum in A
Eg: ADDC A, 45
ADDC A, @Rp
Add A and the contents of the address in Rp and C flag; put the sum in A
Eg: ADDC A, @R0
In all the above instructions the result is stored in A.

Given below is a list of addition opcodes with their description.

Execution Flags affected
Opcode Operand Description Size Over Auxilary
time Carry
flow carry
Adds the value stored in Rn with
1 12 clock
A, Rn that of the accumulator and stores yes yes yes
byte cycles
the result in the accumulator
Adds the value at an address with
2 12 clock
A, Address that of the accumulator and stores yes yes yes
bytes cycles
the result in the accumulator
Uses the value stored in Rn as an
ADD address and adds the data at that
1 12 clock
A, @Rn address with that of the accumulator yes yes yes
byte cycles
and stores the result in the
accumulator
Adds the data given by the
programmer with the value stored in 2 12 clock
A, #data yes yes yes
the accumulator and stores the result bytes cycles
in the accumulator
Adds the value stored in Rn with
that of the accumulator. It adds the 1 12 clock
A, Rn yes yes yes
carry bit to the result and then stores byte cycles
the result in the accumulator
ADDC Adds the value stored at a given
address with that of the
2 12 clock
A, Address accumulator. It adds the carry bit to yes yes yes
bytes cycles
the result and then stores the result
in the accumulator
 Uses the data stored in Rn as an
address and adds the value at that
address with the accumulator. It 1 12 clock
A, @Ri yes yes yes
adds the carry bit to the result and byte cycles
then stores the result in the
accumulator
Adds the value given by the
programmer with that of the
2 12 clock
A, #Data accumulator. It adds the carry bit to yes yes yes
bytes cycles
the result and then stores the result
in the accumulator
2.3.2 Subtraction operation:

Function: Subtraction on two operands Flags: CY, OV, AC

Subtraction can be done by taking the two`s complement of the number to be subtracted (subtrahend), and adding
it to another number (minuend). Register A is the destination address for the subtraction. All addressing modes
may be used for source address. The commands treat the Carry flag as a borrow flag and always subtract the carry
flag as part of the operation. The following table lists the subtraction mnemonics.

MNEMONIC OPERATION
SUBB A, #n Subtract the immediate number n and the C flag from A; put the result in A
Eg: SUBB A, #55
SUBB A, Rr Subtract register Rr and C flag from A; put the result in A
Eg: SUBB A, R6
SUBB A,add
Subtract the address contents and C flag from A; put the sum in A
Eg: SUBB A, 55
SUBB A, @Rp Subtract the contents of the address in Rp and C flag from A; put the sum in A
Eg: SUBB A, @1
In all the above instructions the result is stored in A.

2.3.3 Multiplication operation:

Multiplication operation uses registers A and B as both source and destination addresses for the operation. The
number in register A is multiplied by the number in register B as indicated in the following instruction. The MUL
instruction is used to perform multiplication of two 8-bit numbers. Both the operands should be placed in registers
A and B to perform multiplication operation. The result from the multiplication operation is also stored in A
(Lower 8 bits) and B (Upper 8 bits).

MNEMONIC OPERATION
Multiply A by B; put the lower order byte of the product in A, and higher
MUL AB order byte of the product in B
For example:

MOV A, #25H; loads 25H to the accumulator

MOV B, #65H; loads 65H into register B

MUL AB; multiplies 25H * 65H =E99 where A = 99H, B = OEH

2.3.4 Division operation:

Division operation uses registers A and B as both source and destination addresses for the operation. The number
in register A is divided by the number in register B as indicated in the following instruction. During the DIV
operation, the numerator is stored in the accumulator, and the denominator is stored in register B. Once the
operation is performed, the quotient is placed in A, and the remainder is stored in B.

MNEMONIC OPERATION
Divide A by B; put the integer part of the quotient in register A and integer
DIV AB part of the reminder in B
For example:

MOV A, #95H; Moves 95H into the accumulator

MOV B, #10H; Moves 10H into register B

DIV AB; performs A/B and stores the quotient in A and remainder in B

2.3.5 Decimal Adjust:

All might be familiar with the binary and hexadecimal formats of numbering, but there is another format that is
widely used; the binary coded decimal or BCD. This format represents numbers in a different manner. For
example, 11 in binary is 1011, but in BCD, it is 0001 0001. In BCD code, counting resets after 1001. Here’s a
table to help you understand better.
When it comes to adding BCD numbers in microcontrollers, normal binary addition will give the wrong results.
So, to solve this issue, microcontrollers use the DA command, which converts the binary results to BCD. The
DA command can take only one operand; A.

For example:

MOV A, #47H; A=47H first BCD operand (0100 0111 BCD)

MOV B, #25H; B=25 second BCD operand (0010 0101 BCD)

ADD A, B; hex addition (A=6CH)

DA A; adjusts for BCD addition (A=72H)

2.3.6 Increment operation:

Function: Increment Description: INC increments the indicated variable by 1.

An original value of 0FFH overflows to 00H. No flags are affected. Three addressing modes are allowed: register,
direct, or register-indirect.

Note: When this instruction is used to modify an output port, the value used as the original port data will be read
from the output data latch, not the input pins.

MNEMONIC OPERATION
INC A Add 1 to accumulator
INC Rp Add 1 to register Rr
INC @Rp Add 1 to contents of the direct memory address
INC add Add 1 to contents of memory address in Rp
INC DPTR Add 1 to 16-bit contents of DPTR
2.3.6 Decrement operation:

Function: Decrement Description: DEC byte decrements the variable indicated by 1.

An original value of 00H underflows to 0FFH. No flags are affected. Four operand addressing modes are allowed:
accumulator, register, direct, or register-indirect.

Note: When this instruction is used to modify an output port, the value used as the original port data will be read
from the output data latch, not the input pins.

MNEMONIC OPERATION
DEC A Subtract 1 from accumulator
DEC Rr Subtract 1 from register Rr
DEC add Subtract 1from contents of the direct memory address
DEC @Rp Subtract 1 from contents of memory address in Rp
Note: There is no DEC DPTR instruction.
2.4 Logical instructions:

The Boolean operators are – AND, OR, NOT and XOR. The 8051 microcontroller boasts a rich set of logical
instructions that perform bitwise operations on data. These instructions are essential for data manipulation, flag
control, and implementing logical decision-making within your programs. The two data levels –byte or bit at
which the Boolean instructions operate are as shown in the following table

Boolean operator 8051 Mnemonic

AND ANL (logical AND)
OR ORL (logical OR)
XOR XRL (logical Exclusive OR)
NOT CPL (complement)

2.4.1 AND (ANL) Operation:

o Performs a bitwise AND operation between two operands.

o The result is stored in the destination operand (accumulator or register).
o Only bits that are 1 in both operands result in a 1 in the output.

Variations:

 ANL A, source: Performs AND between the accumulator (A) and the source (register or memory
location).
 ANL destination, source: Performs AND between the specified destination (register or memory location)
and the source.

2.4.2 OR (ORL) Operation:

o Performs a bitwise OR operation between two operands.

o The result is stored in the destination operand (accumulator or register).
o Any bit that is 1 in either operand (or both) results in a 1 in the output.

Variations:

 ORL A, source: Performs OR between the accumulator (A) and the source (register or memory location).
 ORL destination, source: Performs OR between the specified destination (register or memory location)
and the source.

2.4.3 Exclusive OR (XOR):

o Performs a bitwise XOR (eXclusive OR) operation between two operands.

o The result is stored in the destination operand (accumulator or register).
 o A bit in the output becomes 1 only if the corresponding bits in the operands are different (one is 0 and the
other is 1).

Variations:

 XRL A, source: Performs XOR between the accumulator (A) and the source (register or memory location).
 XRL destination, source: Performs XOR between the specified destination (register or memory location)
and the source.

2.4.4 Complement (CPL):

o Inverts the bits of the operand (flips 0s to 1s and vice versa).

o The result is stored back in the same operand (accumulator or register).

Variations:

 CPL A: Complements the bits in the accumulator (A).

2.4.5 Set Bit (SETB):

o Forces a specific bit position in the operand to 1.

Variations:

 SETB bit number, destination: Sets the bit at the specified position (bit number) in the destination register
or memory location to 1.

2.4.6 Clear Bit (CLR):

o Forces a specific bit position in the operand to 0.

Variations:

 CLR bit number, destination: Clears the bit at the specified position (bit number) in the destination register
or memory location to 0.

The following are the byte level Boolean Operations.

MNEMONIC OPERATION
ANL A,#n
AND each bit of A with the same bit of immediate number n; put the results in A
Eg: ANL A,#8C
ANL A ,add
AND each bit of A with the same bit of direct RAM address; put the results in A
Eg: ANL A, 7C
ANL A,Rr
AND each bit of A with the same bit of register Rr; put the results in A
Eg: ANL A, R3
ANL A, @Rp AND each bit of A with the same bit of the contents of the RAM addresscontained
Eg: ANL A, @R1 in Rp; put the results in A
 ANL add , A AND each bit of A with the direct RAM address; put the results in direct RAM
Eg:ANL 27, A address.
ANL add,#n AND each bit of RAM address with the same bit in the number n ; put the results
Eg: ANL 4E,#5 in the direct RAM address.
ORL A,#n
OR each bit of A with the same bit of immediate number n; put the results in A
Eg: ORL A,#8C
ORL A ,add
OR each bit of A with the same bit of direct RAM address; put the results in A
Eg: ORL A, 7C
ORL A,Rr
OR each bit of A with the same bit of register Rr; put the results in A
Eg: ORL A, R3
ORL A, @Rp OR each bit of A with the same bit of the contents of the RAM address contained
Eg: ORL A, @R1 in Rp; put the results in A
ORL add , A OR each bit of A with the direct RAM address; put the results in direct RAM
Eg: ORL 27, A address.
ORL add,#n OR each bit of RAM address with the same bit in the number n ; put the results in
Eg: ORL 6F,#n the direct RAM address.
XRL A,#n
XOR each bit of A with the same bit of immediate number n; put the results in A
Eg: XRL A,#58
XRL A ,add
XOR each bit of A with the same bit of direct RAM address; put the results in A
Eg: XRL A ,68
XRL A,Rr
XOR each bit of A with the same bit of register Rr; put the results in A
Eg: XRL A,R2
XRL A, @Rp XOR each bit of A with the same bit of the contents of the RAM address
Eg: XRL A, @R1 contained in Rp; put the results in A
XRL add , A XOR each bit of A with the direct RAM address; put the results in direct RAM
Eg: XRL 80, A address.
XRL add,#n XOR each bit of RAM address with the same bit in the number n; put the results in
Eg: XRL 8C,#55 the direct RAM address.
CLR A Clear each bit of register A to 0
CPL A Complement each bit of A; every 1 becomes 0, and each 0 becomes 1.

The following table lists the bit level Boolean Operations

MNEMONIC OPERATION
ANL C,b AND C and the addressed bit b; put the result in C
ANL C, /b AND C and complement of the addressed bit b; put the result in C
ORL C, b OR C and the addressed bit b; put the result in C
ORL C, /b OR C and complement of the addressed bit b; put the result in C
CPL C Complement the C flag
CPL b Complement the addressed bit
CLR C Clear the C flag ( C = 0)
CLR b Clear the addressed bit
 MOV C, b Copy the addressed bit to C flag
MOV b, C Copy the C flag to the addressed bit
SETB C Set the carry flag ( C = 1)
SETB b Set the addressed bit to 1

2.5. Rotate and Swap operations:

The ability to rotate data is useful for inspecting bits of a byte. The A register can be rotated one-bit position to
the left or right with or without carry flag. If C flag is not used then the rotate operation involves 8 bits. If the
carry flag is used, the rotate operation uses 9 bits.

The SWAP operation interchanges the upper and lower nibbles of the Accumulator. In ROTATE and SWAP
operations, the A register is used.

MNEMONIC OPERATION
RL A Rotate the A register one-bit position to the left.
RLC A Rotate the A register and the carry flag as a ninth bit, one-bit position to the left.
RR A Rotate the A register one-bit position to the right
Rotate the A register and the carry flag as the ninth bit, one- bit position to the
RRC A
right.
SWAP A Interchange the nibbles of A register.
2.5.1 RR A: Rotate Accumulator right

The 8-bits of the accumulator are rotated right one bit. A0 is placed to A7 and every other bit moved right by 1
bit.

Eg: If A = 0011 0110 then RR A = 0001 1001

2.5.2 RL A: rotate Accumulator left

The 8-bits of the accumulator are rotated right one bit. A7 is placed to A0 and every other bit moved left by 1 bit.

Eg: If A = 0011 0110 then RLA = 0110 1100

2.5.3 RRC A: rotate Accumulator right through carry

In RRC A, accumulator bits are rotated right, the LSB A0 moves into carry and carry moves to A7. It is considered
as 9-bit rotation including carry.

Eg: If A = 0011 0110 and CY = 1, then RRC A = 1001 1011 CY = 0

2.5.4 RLC A: rotate Accumulator left through carry

In RLC A, accumulator bits are rotated left, the MSB A7 moves into carry and carry moves to A0. It is considered
as 9-bit rotation including carry.

Eg: If A = 0011 0110 and CY = 1, then RLC A = 0110 1101 and CY = 0

2.5.5 SWAP operation:

The SWAP operation interchanges the upper and lower nibbles of the Accumulator.

2.6 Jump & Call Instructions

The 8051 microcontroller provides a set of jump and call instructions that manipulate the program flow during
execution. These instructions are essential for creating control structures like loops, subroutines, and conditional
branching within the programs.

2.6.1 Jump Instructions:

 Conditional Jumps
 Unconditional Jumps
2.6.1.1 Conditional Jumps: These instructions transfer program flow only if a specific condition is met (based
on the status flags in the PSW register).

For examples:

 JZ address: Jumps if the Zero flag (Z) is set (accumulator content is zero).
 JNZ address: Jumps if the Zero flag (Z) is cleared (accumulator content is not zero).
 Similar jump instructions exist for other flags like Carry (JC, JNC), Overflow (JO, JNO), etc.
a. JC Address

Operation: JC Function: Jump if Carry Set Syntax: JC reladdr

Description: JC will branch to the address indicated by reladdr if the Carry Bit is set. If the Carry Bit is not set
program execution continues with the instruction following the JC instruction.

b. JNC Address

Operation: JNC Function: Jump if Carry Not Set Syntax: JNC reladdr

Description: JNC branches to the address indicated by reladdr if the carry bit is not set. If the carry bit is set
program execution continues with the instruction following the JNB instruction.

c. DJNC Register, Address

Operation: DJNZ Function: Decrement and Jump if Not Zero Syntax: DJNZ register, reladdr

Description: DJNZ decrements the value of register by 1. If the initial value of register is 0, decrementing the
value will cause it to reset to 255 (0xFF Hex). If the new value of register is not 0 the program will branch to the
address indicated by relative addr. If the new value of register is 0 program flow continues with the instruction
following the DJNZ instruction.

d. CJNE Operand1, Operand2, Address

Operation: CJNE Function: Compare and Jump If Not Equal Syntax: CJNE operand1, operand2, reladdr

Description: CJNE compares the value of operand1 and operand2 and branches to the indicated relative address
if operand1 and operand2 are not equal. If the two operands are equal program flow continues with the instruction
following the CJNE instruction.

e. JZ Address

Operation: JZ Function: Jump if Accumulator Zero Syntax: JNZ reladdr

Description: JZ branches to the address indicated by reladdr if the Accumulator contains the value 0. If the value
of the Accumulator is non-zero program execution continues with the instruction following the JNZ instruction.
 f. JNZ Address

Operation: JNZ Function: Jump if Accumulator Not Zero Syntax: JNZ reladdr

Description: JNZ will branch to the address indicated by reladdr if the Accumulator contains any value except 0.
If the value of the Accumulator is zero program execution continues with the instruction following the JNZ
instruction.

2.6.1.2 Unconditional Jumps: These instructions transfer program execution to a new address regardless of any
conditions.

For examples:

 LJMP address: Jumps to a long address (16-bit) in memory.

 AJMP address: Jumps to an address within the same 2KB memory block (uses 11 bits for
addressing).
 SJMP address: Jumps to an address within a signed 128-byte range relative to the current program
counter (PC).
i. LJMP address: Jumps to a long address (16-bit) in memory

Operation: LJMP Function: Long Jump Syntax: LJMP code addr

Description: LJMP jumps unconditionally to the specified code addr.

ii. AJMP address: Jumps to an address within the same 2KB memory block

Operation: AJMP Function: Absolute Jump Within 2K Block Syntax: AJMP code address

Description: AJMP unconditionally jumps to the indicated code address. The new value for the Program Counter
is calculated by replacing the least-significant-byte of the Program Counter with the second byte of the AJMP
instruction, and replacing bits 0-2 of the most-significant-byte of the Program Counter with 3 bits that indicate
the page of the byte following the AJMP instruction. Bits 3-7 of the most-significant-byte of the Program Counter
remain unchanged. Since only 11 bits of the Program Counter are affected by AJMP, jumps may only be made to
code located within the same 2k block as the first byte that follows AJMP.

iii. SJMP address: Jumps to an address within a signed 128-byte range relative to the current
program counter (PC).

Operation: SJMP Function: Short Jump Syntax: SJMP reladdr

Description: SJMP jumps unconditionally to the address specified reladdr. Reladdr must be within -128 or +127
bytes of the instruction that follows the SJMP instruction.
 iv. JMP Address

Operation: JMP Function: Jump to Data Pointer + Accumulator Syntax: JMP @A+DPTR

Description: JMP jumps unconditionally to the address represented by the sum of the value of DPTR and the
value of the Accumulator.

2.6.2 CALL instruction

 Transfers program control to a subroutine (a block of code that can be called from multiple
locations).
 The program counter (PC) is pushed onto the stack, effectively storing the return address.
 The subroutine is then executed at the specified address.
 CALL address: Calls a subroutine located at the given address.
a. LCALL Address

Operation: LCALL Function: Long Call Syntax: LCALL code addr

Description: LCALL calls a program subroutine. LCALL increments the program counter by 3 (to point to the
instruction following LCALL) and pushes that value onto the stack (low byte first, high byte second). The
Program Counter is then set to the 16-bit value which follows the LCALL opcode, causing program execution to
continue at that address.

b. ACALL Address

Operation: ACALL Function: Absolute Call Within 2K Block Syntax: ACALL code address

Description: ACALL unconditionally calls a subroutine at the indicated code address. ACALL pushes the address
of the instruction that follows ACALL onto the stack, least-significant-byte first, most-significant-byte second.
The Program Counter is then updated so that program execution continues at the indicated address.

The new value for the Program Counter is calculated by replacing the least significant- byte of the Program
Counter with the second byte of the ACALL instruction, and replacing bits 0-2 of the most-significant-byte of the
Program Counter with 3 bits that indicate the page. Bits 3-7 of the most-significant-byte of the Program

Counter remains unchanged. Since only 11 bits of the Program Counter are affected by ACALL, calls
may only be made to routines located within the same 2k block as the first byte that follows ACALL.
2.7 Stack & Subroutine Instructions of 8051

The 8051 microcontroller utilizes the stack and subroutine instructions to achieve modular programming and
efficient code execution.

2.7.1 The Stack:

 The stack is a Last-In-First-Out (LIFO) data structure implemented within the 8051's internal RAM (often
in the scratchpad area).
 It acts as temporary storage during program execution.
 The Stack Pointer (SP) register, a 16-bit register, keeps track of the top of the stack.

2.7.2 Stack Operations:

 PUSH: This instruction pushes data onto the stack. The SP is first decremented (pointing to one position
lower in memory), and then the data is stored at the new top of the stack.
 POP: This instruction retrieves data from the stack. The data at the top of the stack (pointed to by SP) is
copied to a register or memory location, and then the SP is incremented (pointing back to the previous top
position).
i. PUSH Instruction

Operation: PUSH Function: Push Value onto Stack Syntax: PUSH

Description: PUSH "pushes" the value of the specified iram addr onto the stack. PUSH first increments the value
of the Stack Pointer by 1, then takes the value stored in iram addr and stores it in Internal RAM at the location
pointed to by the incremented Stack Pointer.

Functionality:

 The PUSH instruction takes an operand (data to be stored) and pushes it onto the stack.
 Before pushing the data, the PUSH instruction performs the following:
o It decrements the Stack Pointer (SP) by 1. The SP is a 16-bit register that always points to the top
of the stack. Decrementing it allocates space for the new data on the stack.
o The operand is then copied to the memory location pointed to by the updated SP (which is now
one position lower).

For Example:

MOV A, #30H; Move the value 30H (48 in decimal) to accumulator A

PUSH A; Push the content of accumulator A (which is 30H) onto the stack
In this example, the value 30H is first moved to the accumulator (A). Then, the PUSH A instruction pushes the
content of register A (which is 30H) onto the stack. The Stack Pointer (SP) is automatically decremented to create
space for the new data on the stack.

ii. POP Instruction

Operation: POP Function: Pop Value from Stack Syntax: POP

Description: POP "pops" the last value placed on the stack into the iram addr specified. In other words, POP will
load iram addr with the value of the Internal RAM address pointed to by the current Stack Pointer. The stack
pointer is then decremented by 1.

Functionality:

 The POP instruction takes an operand (destination) that specifies where the retrieved data from the stack
will be stored.
 The POP instruction performs the following:
o It increments the Stack Pointer (SP) by 1. The SP is a 16-bit register that always points to the top
of the stack. Incrementing it moves the SP to point to the element below the current top element.
o The data located at the memory address pointed to by the updated SP (which is now one position
higher) is copied to the destination operand specified in the instruction.

For Example:

PUSH A; Push the content of accumulator A (let's assume it's 30H) onto the stack

MOV B, #0; Move the value 0 to register B

POP B; Pop data from the stack and store it in register B

Now, register B will contain the value 30H (which was previously pushed onto the stack).

2.7.3 Subroutine Instructions:

 The 8051 primarily uses the CALL instruction for subroutine calls.
 When a CALL instruction is executed with an address operand, the following happens:
 The current program counter (PC) value, which points to the next instruction after the CALL, is pushed
onto the stack using a PUSH operation.
 This saved PC value acts as the return address, indicating where to resume execution after the subroutine
finishes.
 The program control jumps to the address specified in the CALL instruction, initiating the subroutine
execution.
2.7.4 Return from Subroutine:

 Subroutines typically use the RET (return) instruction to return control back to the calling program.
 The RET instruction performs the following:
 Retrieves the return address from the top of the stack using a POP operation.
 The retrieved address is loaded back into the program counter (PC).
 Program execution resumes from the instruction following the original CALL instruction in the main
program.

i. RET instruction

Operation: RET Function: Return From Subroutine Syntax: RET

Description: RET is used to return from a subroutine previously called by LCALL or ACALL. Program execution
continues at the address that is calculated by popping the topmost 2 bytes off the stack. The most-significant-byte
is popped off the stack first, followed by the least-significant-byte.

ii. RETI instruction

Operation: RETI Function: Return from Interrupt Syntax: RETI

Description: RETI is used to return from an interrupt service routine. RETI first enables interrupts of equal and
lower priorities to the interrupt that is terminating. Program execution continues at the address that is calculated
by popping the topmost 2 bytes off the stack. The most-significant-byte is popped off the stack first, followed by
the least-significant-byte. RETI functions identically to RET if it is executed outside of an interrupt service
routine.

2.8 Some examples in assembly Language