DLD Unit 3 (Spaces)
DLD Unit 3 (Spaces)
The n input binary variables come from an external source; the m output variables are
produced by the internal Combinational logic circuit and go to an external destination.
The first three operations produce a sum of one digit, but when both augend and
addend bits are equal to 1, the binary sum consists of two digits. The higher
significant bit of this result is called a carry. A combinational circuit that performs
the addition of two bits is called a half adder . One that performs the addition of three
bits (two significant bits and a previous carry) is a full adder.
Half adder: A half adder is a digital logic circuit that performs binary addition
of two single-bit binary numbers. It has two inputs, A and B, and two outputs, SUM
and CARRY. The SUM output is the least significant bit (LSB) of the result, while
the CARRY output is the most significant bit (MSB) of the result, indicating whether
there was a carry-over from the addition of the two inputs. The half adder can be
implemented using basic gates such as XOR and AND gates.
P.S.GAJAPATHI RAJU@SPACES
DIGITAL LOGIC DESIGN SPACES DEGREE COLLEGE
The simplified Boolean functions for the two outputs can be obtained directly from
the truth table. The simplified sum-of-products expressions are
Full adder: A full adder is a Combinational circuit that forms the arithmetic
sum of three bits. It consists of three inputs and two outputs. Two of the input
variables, denoted by x and y , represent the two significant bits to be added. The third
input, z , represents the carry from the previous lower significant position. Two
outputs are necessary because the arithmetic sum of three binary digits ranges in value
from 0 to 3, and binary representation of 2 or 3 needs two bits. The two outputs are
designated by the symbols S for sum and C for carry. The binary variable S gives the
value of the least significant bit of the sum.
P.S.GAJAPATHI RAJU@SPACES
DIGITAL LOGIC DESIGN SPACES DEGREE COLLEGE
The logic diagram for the full adder implemented in sum-of-products form is shown
below
P.S.GAJAPATHI RAJU@SPACES
DIGITAL LOGIC DESIGN SPACES DEGREE COLLEGE
It can also be implemented with two half adders and one OR gate, as shown below.
Half subtractor is a combination circuit with two inputs and two outputs that
are different and borrow. It produces the difference between the two binary bits at the
input and also produces an output (Borrow) to indicate if a 1 has been borrowed. In
the subtraction (A-B), A is called a Minuend bit and B is called a Subtrahend bit.
Borrow = A'B
P.S.GAJAPATHI RAJU@SPACES
DIGITAL LOGIC DESIGN SPACES DEGREE COLLEGE
P.S.GAJAPATHI RAJU@SPACES
DIGITAL LOGIC DESIGN SPACES DEGREE COLLEGE
The SOP form can be obtained with the help of K-map as:
The full subtractor logic circuit can be constructed using the 'AND', 'XOR', and NOT
gate with an OR gate.
P.S.GAJAPATHI RAJU@SPACES
DIGITAL LOGIC DESIGN SPACES DEGREE COLLEGE
There are two half adder circuits that are combined using the OR gate. The first half
subtractor has two single-bit binary inputs A and B. As we know that, the half
subtractor produces two outputs, i.e., 'Diff' and 'Borrow'. The 'Diff' output of the first
subtractor will be the first input of the second half subtractor, and the 'Borrow' output
of the first subtractor will be the second input of the second half subtractor. The
second half subtractor will again provide 'Diff' and 'Borrow'. The final outcome of the
Full subtractor circuit is the 'Diff' bit. In order to find the final output of the 'Borrow',
we provide the 'Borrow' of the first and the second subtractor into the OR gate. The
outcome of the OR gate will be the final carry 'Borrow' of full subtractor circuit.
In the above diagram, the control lines of the first Full-Adder is directly coming as its
input(input carry C0). The X0 is the least significant bit of A, which is directly
inputted in the Full-Adder. The result produced by performing the XOR operation of
Y0 and K is the third input of the Binary Adder-Subtractor. The sum/difference(S0)
and carry(C0) are the two outputs produced from the First Full-adder.
In the same way, when the value of K is set to 0, the Y0⨁K produce Y0 as the output.
So the operation would be X+Y0, which is the binary addition of X and Y. It means
when the value of K is 0; the addition operation is performed by the binary Adder-
Subtractor.
P.S.GAJAPATHI RAJU@SPACES
DIGITAL LOGIC DESIGN SPACES DEGREE COLLEGE
The carry/borrow C0 is treated as the carry/borrow input for the second Full-Adder.
The sum/difference S0 defines the least significant bit of the sum/difference of
numbers X and Y. Just like X0, the X1, X2, and X3 are faded directly to the 2nd, 3rd,
and 4th Full-Adder as an input. The outputs after performing the XOR operation of
Y1, Y2, and Y3 inputs with K are the third inputs for 2nd, 3rd, and 4th Full-Adder.
The carry C1, C2 are passed as the input to the Full-Adder. Cout is the output carry of
the sum/difference. To form the final result, the S1, S2, S3 are recorded with s0. We
will use n number of Full-Adder to design the n-bit binary Adder-Subtractor.
Example:
Assume that we have two 3-bit numbers, i.e., X=100 and Y=011, and feed them in
Full-Adder as an input.
X0 = 0 X1 = 0 X2 = 1
Y0 = 1 Y1 = 1 & Y2 = 0
For K=0:
Y0⨁K=Y0 and Cin=K=0
So, from first Full-Adder
S0 = X0+Y0+Cin
S0= 0+1+0
S0=1
C0=0
Similarly,
S1 = X1+Y1+C0
S1 = 0+1+0
S1=1 and C1=0
Similarly,
S2 = X2+Y2+C1
S2 = 1+0+0
S2=1 and C2=0
Thus,
X= 100 =4
Y = 011 = 3
Sum = 0111 = 7
P.S.GAJAPATHI RAJU@SPACES
DIGITAL LOGIC DESIGN SPACES DEGREE COLLEGE
For K=1
Y0⨁K=Y0' and Cin=k=1
So,
S0 = X0+Y0'+Cin
S0 = 0+0+1
S0=1 and C0=0
Similarly,
S1 = X1+Y1'+C0
S1 = 0+0+0
S1=0 and C1=0
Similarly,
S2 = X2+Y2'+C1
S2 = 1+1+0
S2=0 and C2=0
Thus,
X = 010 = 4
Y = 011 = 3
Difference = 001 = 1
P.S.GAJAPATHI RAJU@SPACES