STM32H7S3x8 STM32H7S7x8

STM32H7S3x8 STM32H7S7x8
Arm® Cortex®-M7 32-bit 600 MHz MCU, 64 KB flash, 620 KB RAM, Ethernet,
2x USB, 2x FD-CAN, advanced graphics and security, 2x12-bit ADCs
Datasheet - production data
Features
Includes ST state-of-the-art patented
technology
LQFP100 (14 x 14 mm) LQFP144 (20 x 20 mm) LQFP176 (24 x 24 mm)
UFBGA UFBGA
Core
UFBGA
• 32-bit Arm® Cortex®-M7 CPU with MPU and

UFBGA144 (10 x 10 mm) UFBGA169 (7 x 7 mm) UFBGA176+25 (10 x 10 mm)
DP-FPU, L1 cache: 32+32-Kbyte instruction
and data cache allowing 0-wait state execution TFBGA
TFBGA VFQFPN
from embedded flash memory and external

memories, frequency up to 600 MHz, 1284
DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and WLCSP101 (die) TFBGA100 (8x8 mm) TFBGA225 (13 x 13 mm) VFQFPN68 (10 x 10 mm)
DSP instructions
Security and cryptography
Memories
• PSA level 2 and SESIP level 3 certified (under
• 64 Kbytes of user flash memory that can be
certification)
used for user code and/or external memory
configuration. • Flexible life cycle scheme with debug
authentication based on certificate or password
• SRAM: total 620 Kbytes (548 Kbytes with
(debug reopening/regression support)
optional ECC activated) organized as follows:
– 64+64 Kbytes minimum of instruction and • Root of trust thanks to unique boot entry and
data TCM RAM for critical real time secure hide protection area (HDP)
instructions • Secure firmware installation / update
– 384 Kbytes AXI SRAM (128 Kbytes with (SFI/SFU) thanks to embedded root secure
optional remap to TCM RAM fully activated services (RSS)
– 4 Kbytes of backup SRAM (available in the • Secure data storage with hardware unique key
lowest-power modes) (HUK)
• Flexible external memory controller with up to • 2 AES coprocessors including one with
32-bit data bus: SRAM, PSRAM, FRAM, DPA resistance
SDR/LPSDR SDRAM, NOR/NAND memories • Public key accelerator, DPA resistant
• up to 2x Octo-SPI memory interfaces or 1 octo- • On-the-fly encryption/decryption of serial and
SPI + 1 hexa-SPI with XiP, with support for parallel external memories
serial PSRAM/NAND/NOR, HyperRAM™/
• HASH hardware accelerator
HyperFlash™ frame formats running at up to
200 MHz • True random number generator, NIST
SP800-90B compliant
• 2x SD/SDIO/MMC interfaces
• 96-bit unique ID
2x DMA controllers to offload the CPU
• 1 Kbyte OTP (one-time programmable)
• 2 × dual-port DMAs with FIFO and linked listed
• Active tampers
support
March 2024 DS14359 Rev 2 1/320

This is information on a product in full production. www.st.com
STM32H7Sxx8
• Hardware secure storage (dedicated secure Mathematical acceleration

flash area)
• CORDIC for trigonometric functions
Graphics acceleration
• NeoChrom graphic processor (GPU2D) 23 timers
accelerating any angle rotation, scaling and
• Sixteen 16-bit (including 5 x low power 16-bit
perspective correct texture mapping
timer available in stop mode, one graphic
• Chrom-ART Accelerator (DMA2D) for timer), four 32-bit timers, 2x watchdogs, 1x
enhanced graphic content creation SysTick timer
• Chrom-GRC (GFXMMU) allowing up to 20% of • RTC with sub-second and hardware calendar
graphic resources optimization with calibration (to be verified)
• Hardware JPEG codec
Debug mode
• LCD-TFT controller supporting up to SVGA
• Authenticated debug and flexible device
resolution
lifecycle
• Flexible memory controller FMC8/16 for
• SWD and JTAG interfaces
parallel displays supporting up to WSVGA
• ETM with 2-Kbyte embedded trace buffer
• Digital camera parallel interface with pixel
format conversion and cropping capabilities Up to 35 communication interfaces
Clock, reset and supply management • 3× I2C FM+ (SMBus/PMBus™)
• 1.71 V to 3.6 V application supply and I/O • 1x I3C interface (muxed with one I2C)
• POR, PVD and BOR • Up to 3 USARTs/4 UARTs (ISO7816 interface,
LIN, IrDA, modem control) and 2x LPUART
• Dedicated USB power embedding a 3.3 V
internal regulator to supply the internal PHYs • 6 SPIs with 4 with muxed duplex I2S and 3x
USART configured in synchronous mode
• Embedded regulator LDO to supply the VCORE
(9 SPIs)
and/or external circuitry
• 2x SAI (serial audio interface)
• High power-efficiency SMPS step-down
converter regulator to directly supply VCORE • 2× FD-CAN
and/or external circuitry • 16-bit parallel slave synchronous interface
• Internal oscillators: 64 MHz HSI, 48 MHz • SPDIF-IN interface, HDMI-CEC
HSI48, 4 MHz CSI, 32 kHz LSI
• Ethernet MAC interface with DMA controller
• External oscillators: 4-50 MHz HSE,
• 1 USB Type-C®/USB power delivery controller
32.768 kHz LSE
• 1 USB OTG full-speed with embedded PHY
Low power
• 1 USB OTG high-speed with embedded PHY
• Sleep, Stop, and Standby modes
• VBAT supply for RTC, 32×32-bit backup ECOPACK2 compliant packages
registers Table 1. Device summary
Analog Reference Part numbers
• 2x12-bit ADC, up to 5 MSPS in 12-bit, up to 17 STM32H7S3A8, STM32H7S3I8,
channels STM32H7S3x8 STM32H7S3L8, STM32H7S3R8,
Audio digital filters (ADF) STM32H7S3V8, STM32H7S3Z8
STM32H7S7A8, STM32H7S7I8,
• 2 microphones /1 filter STM32H7S7x8
STM32H7S7L8, STM32H7S7Z8
• Voice activity detector (VAD) support
Up to 152 I/O ports with interrupt

capability
2/320 DS14359 Rev 2

STM32H7Sxx8 Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 Arm Cortex-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.1 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2 Secure access mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.3 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.5.4 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.6 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.7 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.7.1 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.7.2 System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.8 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.9 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.10 General purpose / high-performance direct memory access controller
(GPDMA/HPDMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.11 Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.12 NeoChrom graphic processor (GPU2D) . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.13 Chrom-GRC (GFXMMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.14 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 48
3.15 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 48
3.16 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 49
3.17 CORDIC co-processor (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.18 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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Contents STM32H7Sxx8
3.19 Quad/Octo/Hexa-SPI memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.19.1 XSPI I/O manager (XSPIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.19.2 Extended-SPI interface (XSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.20 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.21 Analog temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.22 Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.23 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.24 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.25 Audio digital filter (ADF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.26 Digital camera interface (DCMIPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.27 Parallel synchronous slave interface (PSSI) . . . . . . . . . . . . . . . . . . . . . . 56
3.28 LCD-TFT display controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.29 JPEG codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.30 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.31 Cryptographic acceleration (CRYP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.31.1 Crypto engines features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.32 Secure AES (SAES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.33 Hash processor (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.34 Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.35 Memory cipher engine (MCE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.35.1 Memory cipher features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.35.2 Memory cipher implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.36 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.36.1 Advanced-control timers (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.36.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.36.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.36.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 63
3.36.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.36.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.36.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.37 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.38 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.39 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.40 Improved inter-integrated circuit (I3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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3.41 Universal synchronous/asynchronous receiver transmitter (USART/UART)

and low-power universal asynchronous receiver transmitter (LPUART) . 66
3.41.1 Universal synchronous/asynchronous receiver transmitter
(USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.41.2 Low-power universal asynchronous receiver transmitter (LPUART) . . . 67
3.42 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 68
3.42.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.42.2 SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.42.3 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.43 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.43.1 SAI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.43.2 SAI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.44 SPDIFRX receiver interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.45 Management data input/output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . . 71
3.46 Secure digital input/output MultiMediaCard interface (SDMMC) . . . . . . . 71
3.47 Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 72
3.48 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 72
3.49 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 73
3.50 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 74
3.51 USB Type-C power delivery controller (UCPD) . . . . . . . . . . . . . . . . . . . . 74
3.52 High-definition multimedia interface - consumer electronics control
(HDMI-CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.53 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.53.1 Serial-wire/JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.53.2 Embedded Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4 Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 76

4.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
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Contents STM32H7Sxx8
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.3.3 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.3.4 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 161
6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . 161
6.3.6 Embedded reference voltage characteristics . . . . . . . . . . . . . . . . . . . . 164
6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.3.8 Wake-up time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . 186
6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 187
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
6.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.3.13 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 202
6.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
6.3.17 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
6.3.18 XSPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
6.3.19 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
6.3.20 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
6.3.21 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 251
6.3.22 Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . 252
6.3.23 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
6.3.24 Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . 253
6.3.25 VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
6.3.26 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
6.3.27 Audio digital filter (ADF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
6.3.28 Digital camera interface (DCMIPP) characteristics . . . . . . . . . . . . . . . 257
6.3.29 Parallel synchronous slave interface (PSSI) characteristics . . . . . . . . 258
6.3.30 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 261
6.3.31 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
6/320 DS14359 Rev 2

6.3.32 Low-power timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

6.3.33 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

7.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
7.2 VFQFPN68 package information (B029) . . . . . . . . . . . . . . . . . . . . . . . . 286
7.3 LQFP100 package information (1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
7.4 TFBGA100 package information (A08Q) . . . . . . . . . . . . . . . . . . . . . . . . 291
7.5 LQFP144 package information (1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
7.6 UFBGA144 package information (A02Y) . . . . . . . . . . . . . . . . . . . . . . . . 298
7.7 UFBGA169 package information (A0YV) . . . . . . . . . . . . . . . . . . . . . . . . 300
7.8 LQFP176 package information (1T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
7.9 WLCSP101 package information (B0FA) . . . . . . . . . . . . . . . . . . . . . . . . 306
7.9.1 Device marking for WLCSP101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
7.10 UFBGA(176+25) package information (A0E7) . . . . . . . . . . . . . . . . . . . . 310
7.11 TFBGA225 package information (B04V) . . . . . . . . . . . . . . . . . . . . . . . . 312
7.12 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
9 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
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List of tables STM32H7Sxx8
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. Security and graphics IP availability per product line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. STM32H7Sxx8 features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. Operating mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 5. Overview of low-power mode monitoring pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. Peripheral clock distribution summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 7. XSPIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 8. XSPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 9. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 10. ADF features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 11. Accelerated cryptographic operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 12. MCE implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 13. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 14. USART, UART and LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 15. Instance implementation on STM32H7Sxx8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 16. SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 17. STM32H7Sxx8 SAI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 18. OTG_FS speeds supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 19. OTG_HS speeds supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 20. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 21. STM32H7Sxx8 pin and ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 22. STM32H7Sxx8 pin alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 23. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 24. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 25. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 26. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 27. Supply voltage and maximum temperature configuration. . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 28. VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 29. Characteristics of SMPS step-down converter external components . . . . . . . . . . . . . . . . 157
Table 30. SMPS step-down converter characteristics for external usage . . . . . . . . . . . . . . . . . . . . 158
Table 31. Inrush current and inrush electric charge characteristics for LDO and SMPS . . . . . . . . . 158
Table 32. Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 33. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 34. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 35. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 36. Typical and maximum current consumption in Run mode, code with data processing running
from ITCM166
from AXISRAM3, cache ON 167
from AXISRAM3, cache OFF 168
from internal flash memory, cache ON169
from internal flash memory, cache OFF170
Table 41. Typical consumption in Run mode and corresponding performance
versus code position171
Table 42. Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . 171
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STM32H7Sxx8 List of tables
Table 43. Typical and maximum current consumption in System Stop mode . . . . . . . . . . . . . . . . . 172
Table 44. Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 172
Table 45. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 172
from Octo flash memory, cache OFF174
from 16-bit memory, cache OFF174
Table 48. Typical and maximum current consumption: data write 50% toggle on 16-bit memory . . 175
Table 49. Typical and maximum current consumption: data write 25% toggle on 16-bit memory . . 175
Table 50. Typical and maximum current consumption: data write 12.5% toggle on 16-bit memory. 176
Table 51. Typical and maximum current consumption: data write 6.25% toggle on 16-bit memory. 176
Table 52. Typical dynamic current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 53. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 54. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 55. Timing for analog HSE input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 56. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 57. Timing for analog LSE input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 58. 4-50 MHz HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 59. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 60. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 61. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 62. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 63. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 64. PLL1 characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 65. PLL1 characteristics (narrow VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 66. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 67. EMI characteristics for fHSE = 8 MHz and fCPU = 600 MHz . . . . . . . . . . . . . . . . . . . . . . . 201
Table 68. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 69. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 70. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 71. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 72. Output voltage characteristics for all I/Os except PC13, PC14, and PC15. . . . . . . . . . . . 206
Table 73. Output voltage characteristics for PC13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 74. Output voltage characteristics for PC14 and PC15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 75. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 76. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 77. Output timing characteristics VDDXSPIx 1.2 V range (HSLV OFF) . . . . . . . . . . . . . . . . . . 213
Table 78. Output timing characteristics VDDXSPIx 1.2 V (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 79. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 80. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 218
Table 81. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 219
Table 82. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 220
Table 83. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 220
Table 84. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 85. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 222
Table 86. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 87. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 224
Table 88. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 89. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 90. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 91. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 92. Switching characteristics for NAND flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
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List of tables STM32H7Sxx8
Table 93. Switching characteristics for NAND flash write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 94. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Table 95. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Table 96. SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 97. LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 98. XSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Table 99. XSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 100. XSPI characteristics in DTR mode (with DQS)/Hyperbus. . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 101. Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 102. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 103. Minimum sampling time vs RAIN (12-bit ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 104. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 105. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 106. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 107. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 108. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 109. Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 110. VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 111. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 112. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 113. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 114. ADF characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Table 115. DCMIPP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Table 116. PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Table 117. PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 118. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Table 119. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Table 120. LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Table 121. I3C open-drain measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 122. I3C push-pull measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 123. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 124. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Table 125. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Table 126. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 127. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Table 128. MDIO slave timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 129. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V . . . . . . . . . . . . . 276
Table 130. Dynamic characteristics: eMMC characteristics VDD = 1.71V to 1.9V. . . . . . . . . . . . . . . 277
Table 131. USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 132. USB OTG_HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Table 133. OTG_HS current consumption characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 134. UCPD electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 135. Dynamic characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . . 281
Table 136. Dynamic characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 282
Table 137. Dynamic characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Table 138. Dynamic JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table 139. Dynamics SWD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Table 140. VFQFPN68 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Table 141. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Table 142. TFBGA100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 143. TFBGA100 - Recommended PCB design rules (0.8 mm pitch BGA) . . . . . . . . . . . . . . . . 293
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STM32H7Sxx8 List of tables
Table 145. UFBGA144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

Table 146. UFBGA144 - Recommended PCB design rules (0.80 mm pitch BGA). . . . . . . . . . . . . . . 299
Table 147. UFBGA169 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Table 148. UFBGA169 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 301
Table 150. WLCSP101 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Table 151. WLCSP101 - recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Table 152. UFBGA(176+25) - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Table 153. UFBGA(176+25) - Recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . 311
Table 154. TFBGA225 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Table 155. TFBGA225 - Recommended PCB design rules (0.8 mm pitch BGA) . . . . . . . . . . . . . . . . 314
Table 156. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Table 157. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
DS14359 Rev 2 11/320

11
List of figures STM32H7Sxx8
List of figures
Figure 1. STM32H7Sxx8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 2. System supply configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 3. Top-level clock tree. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 4. Core and bus clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 5. System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 6. TFBGA100 SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 7. UFBGA144 SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 9. UFBGA144 GFx with SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 10. UFBGA169 GFx with SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 12. UFBGA176 SMPS GFx pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 13. LQFP176 SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 14. LQFP176 GFx with SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 15. WLCSP101 with SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 16. TFBGA225 OCTO with SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 17. TFBGA225 HEXA with SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 18. VFQFPN68 GP pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 19. LQFP100 GP pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 20. LQFP144 GP pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 21. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 22. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 23. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 24. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 25. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 26. External components for SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 27. SMPS efficiency in VOS mode Tj=25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 28. SMPS efficiency in VOS mode Tj=125°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 29. SMPS efficiency in SVOS mode Tj=25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 30. SMPS efficiency in SVOS mode Tj=125°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 31. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 32. Analog HSE input waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 33. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 34. Analog LSE input waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 35. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 36. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 37. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 38. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 39. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 219
Figure 40. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 221
Figure 41. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 42. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 43. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 44. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 45. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 46. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 47. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 234
Figure 48. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
12/320 DS14359 Rev 2

STM32H7Sxx8 List of figures
Figure 49. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 235
Figure 50. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 51. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 52. XSPI DTR (with DQS) write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 53. XSPI DTR (with DQS) read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 54. XSPI DTR clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 55. ADF timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Figure 56. DCMIPP timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Figure 57. PSSI receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Figure 58. PSSI transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Figure 59. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 60. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 61. USART timing diagram in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 62. USART timing diagram in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 63. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Figure 64. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Figure 65. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Figure 66. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 67. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 68. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 69. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 70. MDIO slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Figure 71. SD high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Figure 72. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Figure 73. SDMMC DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Figure 74. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Figure 75. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Figure 76. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Figure 77. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 78. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 79. VFQFPN68 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Figure 80. VFQFPN68 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 81. LQFP100 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 82. LQFP100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Figure 83. TFBGA100 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 84. TFBGA100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 87. UFBGA144 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Figure 88. UFBGA144 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Figure 89. UFBGA169 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Figure 90. UFBGA169 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Figure 93. WLCSP101L - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 94. WLCSP101 - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Figure 95. WLCSP101 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Figure 96. UFBGA(176+25) - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 97. UFBGA(176+25) - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Figure 98. TFBGA225 - Outline(13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Figure 99. TFBGA225 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
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13
Introduction STM32H7Sxx8
1 Introduction
This document provides information on STM32H7Sxx8 microcontrollers, such as

description, functional overview, pin assignment and definition, packaging, and ordering
information.
This document should be read in conjunction with the STM32H7Rx/7Sx reference manual
(RM0477).
For information on the device errata with respect to the datasheet and reference manual, an
errata sheet (ES0596) is available.
For information on the Arm®(a) Cortex®-M7 core, refer to the Cortex®-M7 Technical
Reference Manual, available from the http://www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
14/320 DS14359 Rev 2

STM32H7Sxx8 Description
2 Description
STM32H7Sxx8 devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC
core operating at up to 600 MHz. The Cortex -M7 core features a floating point unit (FPU)
which supports Arm double-precision (IEEE 754 compliant) and single-precision data-
processing instructions and data types. The Cortex -M7 core includes 32 Kbytes of
instruction cache and 32 Kbytes of data cache. STM32H7Sxx8 devices support a full set of
DSP instructions and a memory protection unit (MPU) to enhance application security.
STM32H7Sxx8 devices incorporate high-speed embedded memories, 64 Kbytes of user
flash memory and 128 Kbytes of system flash memory,and up to 620 Kbytes of RAM
(including 128 Kbytes that can be shared between ITCM and AXI, including 64 Kbytes
exclusively ITCM, including 128 Kbyte DTCM, including 64 Kbytes exclusively DTCM,
including 32 Kbytes AHB and 4 Kbytes of backup RAM), as well as an extensive range of
enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB
bus matrix and a multi layer AXI interconnect supporting internal and external memory
access. To improve application robustness, all memories feature error code correction (one
error correction, two error detections).
The devices embed peripherals allowing mathematical/arithmetic function acceleration
(CORDIC coprocessor for trigonometric functions). All the devices offer two ADCs, a low-
power RTC, 4 general-purpose 32-bit timers, 7 general-purpose 16-bit timers including one
PWM timer for motor control, five low-power timers, and a cryptographic acceleration cell
(CRYP), Public key acceleration (PKA), a secure AES coprocessor (SAES) and a memory
cipher engine (MCE) The devices support one digital filter for external sigma-delta
modulators or digital microphone with voice activity detection. They also feature standard
and advanced communication interfaces.
• Standard peripherals:
– Three I2Cs (One shared with I3C)
– Three USARTs, four UARTs and one LPUART
– Six SPIs, four I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S
peripherals can be clocked by a dedicated internal audio PLL or by an external
clock to allow synchronization (note that the five USARTs also provide SPI slave
capability).
– Two SAI serial audio interfaces
– One SPDIFRX interface with four inputs
– One SWPMI (Single Wire Protocol Master Interface)
– Management Data Input/Output (MDIO) slaves
– Two SDMMC interfaces
– A USB OTG high-speed interface with full-speed capability
– A USB OTG full-speed interface
– A USB Type-C/USB Power Delivery interface
– Two FDCANs interface
– An Ethernet interface
– Chrom-ART Accelerator
– HDMI-CEC
DS14359 Rev 2 15/320

18
Description STM32H7Sxx8
• Advanced peripherals including:

– A flexible memory control (FMC) interface
– Two XSPI memory interfaces to support:
a) one or two Octo-SPI memories
b) one octo-SPI and one 16-bit SPI memory
– on-the-fly encryption/decryption (MCE) for Octo-SPI/Hexa-SPI or FMC external
memory. Two type of encryption are supported for best protection or best
performance.
– A camera interface for CMOS sensors
– NeoChrom graphic processor
– An LCD-TFT display controller
– A camera interface for CMOS sensors
Refer to Table 3: STM32H7Sxx8 features and peripheral counts for the list of peripherals
available on each part number.
The device security and graphics features bu product line are shown in Table 2.
T
Table 2. Security and graphics IP availability per product line

STM32H7R3 STM32H7R7 STM32H7S3 STM32H7S7
IP type IP name
GP GFx GP GFx
Neo-Chrom (GPU2D) N Y N Y
Chrom-Art (DMA2D) Y
Chrom-GRC (GFXMMU) Y
Graphics
Hardware codec (JPEG) Y
LCD-TFT N Y N Y
Parallel display (FMC8/16) Y
Life cycle support (TIL0/1/2) Y
Root of trust (ST-iROT) N N Y Y
Debug authentication Y
Secure firmware install (SFI) Y
Security Root secure service (RSS) Y
HASH accelerator and PKA verification Y
Crypto processor (Crypt, PKA, SAES) N N Y Y
On-the-fly encryption/decryption (MCE) N N Y Y
True random number generator (TRNG) Y
To reduce the power consumption some STM32H7Sxx8 devices include an optional step-
down converter that can be used either for internal or external supply, or both.
16/320 DS14359 Rev 2

STM32H7Sxx8 Description
STM32H7Sxx8 devices operate in the –40 to +85°C(a) ambient temperature range from a
1.71 to 3.6 V power supply. The supply voltage can drop down to 1.71 V by using an
external power supervisor the supply voltage must stay above 1.71 V with the embedded
power voltage detector enabled.
Dedicated supply inputs for XSPI and USB are available to allow independent multiple
voltage constraint and greater power supply choice.
A comprehensive set of power-saving modes allows the design of low-power applications.
STM32H7Sxx8 devices are offered in several packages ranging from 68 to 225 pins/balls.
The set of included peripherals changes with the chosen device.
These features make STM32H7Sxx8 microcontrollers suitable for a wide range of
applications:
• Motor drive and application control
• Medical equipment
• Industrial applications: PLC, inverters, circuit breakers
• Printers, and scanners
• Alarm systems, video intercom, and HVAC
• Home audio appliances
• Mobile applications, Internet of Things
• Wearable devices: smart watches.
Figure 1 shows the device block diagram.
a. Under characterization
DS14359 Rev 2 17/320

18
Description STM32H7Sxx8
Figure 1. STM32H7Sxx8 block diagram

Up to 17 analog
inputs Most are MII / RMII
SDI0, DP, DM, DP, DM,
common to MDIO
CCK[1:0] ADC1 & 2 ID, VBUS ID, VBUS
as AF
I-TCM D-TCM D-TCM To

64KB 32KB 32KB AHB1
AHB1
PHY PHY
ETHER
GPDMA OTG_HS OTG_FS
AHBP MAC
ADF ADC1 ADC2
NJTRST,JTMS/SWDIO Arm CPU AXIM AXIAHB 16 Stream DMA DMA DMA
JTDI, JTCK/SWCLK, JTAG/SW
Cortex-M7 FIFOs FIFO FIFO FIFO
JTDO/SWO (AF)
600 MHz
TRACECLK,
ETM
TRACED[3:0] (AF)
I-Cache D-Cache
32KB 32KB 32-bit AHB BUS-MATRIX
AHBS
SRAM1 SRAM2 To To To To AHB1

AHB1
64-bit AXI BUS-MATRIX

16 Stream 16 KB 16 KB RAM I/F AXI AHB4 AHB3 AHB5
HPDMA FIFOs
Backup
RAM CORDIC
Chrom-ART
FIFO 4 KB To
FIFO
(DMA2D) CK, CKIN, CMD, CDIR,
AHB2
@VSW AHB2 SDMMC2 D[7:0], D0DIR, D123DIR
(AF)
Neo-Chrom graphics ICACHE From
processor (GPU2D) FIFO AHB5 PSSI
GFXMMU MCE1 XSPI1 HSPI i/f
xSPIM
CK, CKIN, CMD, CDIR,
D[7:0], D0DIR, D123DIR (AF) SDMMC1 FIFO MCE2 XSPI2 Octo i/f
D[15:0], HSYNC, AHB5
PIXCLK, VSYNC (AF)
DCMIPP CLK, NOE, NWE, NWAIT,
AHB/APB
APB5
MCE3 FMC NE[4:1], NBL[3:0], NL,

AHB5
CLK, HSYNC, VSYNC, DE, D[31:0], A[25:0], TE, (AF)

R[7:0], G[7:0], B[7:0] (AF)
LCD-TFT FIFO From
SRAM4 72 KB shared ECC
AHB1
GFXTIM From
AHB/APB
AHB5 SRAM3 128 KB shared DTCM
D[4:1], FS_[A:B], MCLK_A, MCLK_B,
CK[4:1], SCK_[A:B], SD_A, SD_B (AF) SAI1
SRAM2 128 KB 32b TIM2 CH[4;1], ETR (AF)
D[4:1], FS_[A:B], MCLK_A, MCLK_B,
SAI2
From
AHB
CK[4:1], SCK_[A:B], SD_A, SD_B (AF)

SRAM1 128 KB shared ITCM 16b TIM3 CH[4;1], ETR (AF)
MISO, MOSI, NSS, SCK, RDY (AF) SPI5
16b TIM4 CH[4;1], ETR (AF)
CH[2;1] (AF) TIM9 16b
192 KB flash
CH1, CH1N, BKIN (AF) TIM17 32b TIM5 CH[4;1], ETR (AF)
16b
From
APB2
CH1, CH1N, BKIN (AF) TIM16 AHB/APB TIM12

16b AHB2 TIM6 16b CH[2;1] (AF)
16b
CH[1:2], CH1N, BKIN (AF) TIM15 16b 16b TIM13 CH1 (AF)
TIM7
16b
MISO, MOSI, NSS, SCK, RDY (AF) SPI4 16b TIM14 CH1 (AF)
MISO, MOSI, NSS, SCK, RDY /
SPI1/I2S1 16b LPTIM1 IN1, IN2, ETR, CH1, CH2 (AF)
CK, MCK, SDI, SDO, WS (AF)
RX, TX, CK, CTS, RTS (AF) USART1 WWDG 16b MOSI, MISO, SCK, NSS /
SPI2/I2S2 SDO, SDI, CK, WS, MCK (AF)
CH[1:4]N, CH[1:4], ETR,
BKIN, BKIN2 (AF)
TIM1 (PWM) 16b SPI3/I2S3 MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK (AF)
From SPDIFRX1 IN[1:4] (AF)

GPIO A~H AHB4 From USART2
RNG RX, TX, CK, CTS, RTS, DE (AF)
AHB4
GPIO I~K AHB3

CRC HASH USART3 RX, TX, CK, CTS, RTS (AF)
GPIO M~N
SAES UART4 RX, TX, CTS, RTS (AF)
AHB3
GPIO P RCC CRYPT UART5 RX, TX, CTS, RTS (AF)

PWRCTRL PKA/SRAM
I2C1/SMBUS SCL, SDA, SMBA (AF)
Digital filter
@VDD
BBgen + POWER MNGT VCORE I2C2/SMBUS SCL, SDA, SMBA (AF)
VCAP[4:1], VDDLDO[4:1],
VSSSD, VLXSD,
VDDSD, VFBSD
Voltage regulator I2C3/SMBUS SCL, SDA, SMBA (AF)
3.3 to 1.2V
HDMI-CEC CEC (AF)
VBAT UART7 RX, TX, CTS, RTS (AF)

@VSW
AHB/APB
OSC32_IN XTAL 32 kHz

CRS UART8 RX, TX, CTS, RTS (AF)
OSC32_OUT
APB1
TS, OUT[2:1], REFIN RTC MDIOS MDC, MDIO (AF)
2 KB RAM
APB4
TAMP_IN[8:1], FDCAN1 TX, RX (AF)

FIFO
TAMP_OUT[8:1] (AF)
TAMPER SRAM I/F
FDCAN2 TX, RX (AF)
PHY
CC1, DB1, CC2, DB2

IN1, ETR, OUT (AF) LPTIM5 16b UCPD
IWDG FRSTX1, FRSTX1 as AF
IN1, ETR, OUT (AF) LPTIM4 16b @VDD @VDD
IN1, IN2, ETR, CH1, CH2 (AF) LPTIM3 Temperature sensor
16b PLL1+PLL2+PLL3
XTAL OSC OSC_IN
HSI48 4- 50 MHz OSC_OUT
IN1, IN2, ETR, CH1, CH2 (AF) LPTIM2 HSI48 RC
16b SYSCFG
MISO, MOSI, NSS, SCK, RDY / CSI CSI RC
SPI6/I2S EXTI WKUP @VDD
CK, MCK, SDI, SDO, WS (AF)
LSI LSI RC Supply supervision
POR VDDA, VSSA,
RX, TX, CTS, RTS/DE (AF) LPUART1 VREF POR/PDR/BOR NRESET,
HSI HSI RC Reset
int WKUP[1:4]
PVD
AHB to APB
AHB2 Bus AHB3 Bus AHB4 Bus AHB5 Bus Bridge
V swuitch domain VDD domain From AHB to AXI
MSv55535V6
18/320 DS14359 Rev 2

STM32H7Sxx8
Table 3. STM32H7Sxx8 features and peripheral counts
STM32H7S3L8H6H
STM32H7S7L8H6H
STM32H7S3V8H6
STM32H7S3R8V6
STM32H7S3L8H6
STM32H7S3V8Y6
STM32H7S7L8H6
STM32H7S3V8T6
STM32H7S3Z8T6
STM32H7S3Z8J6
STM32H7S7Z8J6
STM32H7S3A8I6
STM32H7S3I8K6
STM32H7S7A8I6
STM32H7S7I8K6
STM32H7S3I8T6
STM32H7S7I8T6
Peripherals
Flash memory (Kbytes) 64
SRAM on AXI 456

SRAM in Kbytes
SRAM on AHB 32
ITCM RAM (instruction) 64

DS14359 Rev 2
TCM RAM in Kbytes

DTCM RAM (data) 64
Backup SRAM (Kbytes) 4
Display Interface (bit) FMC16 FMC8 FMC16

NOR flash memory/RAM
16 - - 16(1) 32 16 - - 16(2) - - 16(2) 32 16(3)
controller
Multiplexed I/O NOR flash
FMC X(1) - X(1) X(1) X X X(1) - X(4) X(5) X(4) X(4) X X
memory
16-bit NAND flash
X - X X X X - X - - X X X
memory
SDRAM controller 16 - - 16 32 16 - 16 - - 16 32 16
Octo-SPI /Hexa-SPI (6)
- 1/0 2/0 1/1 1/0 1 /0 2/0 2/0 2/0 2/0 2/0 1/1
memories
General-purpose
7/411 7/411 7/411 7/411 7/411 7/411 7/411 7/29 7/18 5/16 6/28 11 10 11 11 11 11
16/32 all
Advanced-control (PWM) 1 1(7) 1
Timers
Basic 2 2
Low-power 5 5 5 5 3 3 3 4 5
Window watchdog /
independent - 1/1
watchdog
Real-time clock
19/320
- 1
(RTC)
Table 3. STM32H7Sxx8 features and peripheral counts (continued)
20/320
STM32H7S3L8H6H
STM32H7S7L8H6H
STM32H7S3V8H6
STM32H7S3R8V6
STM32H7S3V8Y6
STM32H7S3L8H6
STM32H7S7L8H6
STM32H7S3V8T6
STM32H7S3Z8T6
STM32H7S3Z8J6
STM32H7S7Z8J6
STM32H7S3A8I6
STM32H7S3I8K6
STM32H7S7A8I6
STM32H7S7I8K6
STM32H7S3I8T6
STM32H7S7I8T6
Peripherals
Passive 8 8 8 8 8 7 8 3 3 2 2 7 6 8 7 8 7
Tamper pins(8)
Active 4 4 4 4 4 3 4 1 1 1 1 3 3 4 3 4 3
Random number
- 1
generator
Cryptographic
- Yes
accelerator
DS14359 Rev 2
Hash processor
- 1
(HASH)
On-the-fly For external Octo/Hexa-
Yes
encryption/decryption SPI memory and FMC
SPI/I2S 6/4 6/4 5/4 5/4 5/4 4/3 6/4
I2C/I3C (Shared) 3/1
USART/UART/LPUART 3/4/1 3/4/1 3/4/1 3/4/1 3/4/1 3/4/1 3/4/1 3/3/1 2/3/1 2/3/1 3/3/1 3/4/1 3/3/1 3/4/1 3/4/1 3/4/1 3/4/1
SAI/PDM 2/1 1/0 1/0 1/0 1/0 2/1
Communication SPDIFRX 4 inputs 4 inputs 4 inputs 4 inputs 4 inputs 4 inputs 4 inputs - - 1 input - 3 inputs 3 inputs 4 inputs 4 inputs 4 inputs 4 inputs
interfaces
MDIOS 1
1x(4 bit)
SDMMC/EMMC 1 x(4 bit) + 1x 8 bit) 1 x(4 bit) - + 1x(4 bit) 1x(4 bit) and 1x(8 bit)
1x(8 bit)
FDCAN 2
OTG_HS / OTG_FS /
1/1/1 -/1/- -/1/- -/1/- -/1/- -/1/- 1/1/1 1/1/1
UCPD
STM32H7Sxx8
DCMIPP (bits) 16 16 16 16 16 16 16 - - - - 12 8 12 12 16 16
Digital camera
interface/PSSI(9)
PSSI (bits) 16 16 16 16 16 16 16 - - - - 8 8 8 8 16 16
LCD-TFT RGB24
- 0 1 1(10) 1
display controller
STM32H7Sxx8
STM32H7S3L8H6H
STM32H7S7L8H6H
STM32H7S3V8H6
STM32H7S3R8V6
STM32H7S3V8Y6
STM32H7S3L8H6
STM32H7S7L8H6
STM32H7S3V8T6
STM32H7S3Z8T6
STM32H7S3Z8J6
STM32H7S7Z8J6
STM32H7S3A8I6
STM32H7S3I8K6
STM32H7S7A8I6
STM32H7S7I8K6
STM32H7S3I8T6
STM32H7S7I8T6
Peripherals
JPEG codec - 1
ChromART
- 1
Accelerator (DMA2D)
Graphic memory
management unit 1
(GFXMMU)
DS14359 Rev 2
ICACHE - No Yes
HDMI CEC - 1
ADF number of filters - 1 0 1
ADCs (2 x 12bits) Number of channels 17 17 16 18 20 20 16 12 11 11 10 17 16 17 18 20 20
ETH - RMII/MII RMII RMII RMII/MII RMII/MII RMII/MII RMII - - - - RMII/MII RMII RMII RMII/MII RMII/MII RMII/MII
- 119 94 116 122 152 150 98 67 63 65 45 118 93 117 122 152 150
GPIOs
Wakeup pins 4
Maximum CPU
- 600
frequency (MHz)
SMPS step-down
- Yes No Yes No Yes
converter
USB internal
- Yes No Yes
regulator
21/320
DS14359 Rev 2 22/320
Operating
Packages
supply pad
temperatures
Operating voltage
and internal buffer
USB UCPD separate
VREF+ separate pad

Peripherals
-
-
-
-
-
-
LQFP176 STM32H7S3I8T6
UFBGA 144 STM32H7S3Z8J6
UFBGA 169 STM32H7S3A8I6
UFBGA 176+25 STM32H7S3I8K6
TFBGA 225 STM32H7S3L8H6
TFBGA 225 STM32H7S3L8H6H
LQFP144 STM32H7S3Z8T6
LQFP100 STM32H7S3V8T6
1
TFBGA 100 STM32H7S3V8H6

Yes
1.71 to 3.6 V
WLCSP101 STM32H7S3V8Y6
VFQFPN68 STM32H7S3R8V6
Ambient temperature range: -40 to 85 °C
Junction temperature range: -40 to 125 °C(11)

LQFP176 STM32H7S7I8T6
UFBGA 144 STM32H7S7Z8J6
UFBGA 169 STM32H7S7A8I6
UFBGA 176+25 STM32H7S7I8K6
TFBGA 225 STM32H7S7L8H6
TFBGA 225 STM32H7S7L8H6H
STM32H7Sxx8
STM32H7Sxx8
STM32H7S3L8H6H
STM32H7S7L8H6H
STM32H7S3V8H6
STM32H7S3R8V6
STM32H7S3V8Y6
STM32H7S3L8H6
STM32H7S7L8H6
STM32H7S3V8T6
STM32H7S3Z8T6
STM32H7S3Z8J6
STM32H7S7Z8J6
STM32H7S3A8I6
STM32H7S3I8K6
STM32H7S7A8I6
STM32H7S7I8K6
STM32H7S3I8T6
STM32H7S7I8T6
Peripherals
Bootloader - USART, I2C, SPI, USB-DFU, FDCAN
1. No NE4 A24/25.
2. No NBL2/3 A24/25
3. No NBL2/3
DS14359 Rev 2
4. No A24/25
5. No A23/A24/25
6. Quad-SPI support only.
7. No BKIN2, CH4N.
8. A tamper pin can be configured either as passive or active (not both).
9. DCMIPP and PSSI cannot be used simultaneously since they share the same circuitry.
10. RGB 666
11. The junction temperature is limited to 105 °C in the VOS high-voltage range.
23/320
Functional overview STM32H7Sxx8
3 Functional overview
3.1 Arm Cortex-M7 with FPU

The Arm Cortex-M7 with double-precision FPU processor is the latest generation of Arm
processors for embedded systems. It was developed to provide a low-cost platform that
meets the needs of MCU implementation, with a reduced pin count and optimized power
consumption, while delivering outstanding computational performance and low interrupt
latency.
The Cortex-M7 processor is a highly efficient high-performance featuring:
• Six-stage dual-issue pipeline
• Dynamic branch prediction
• Harvard architecture with L1 caches (32 Kbytes of instruction cache, and 32 Kbytes of
data cache)
• 64-bit AXI4 interface
• 64-bit ITCM interface
• 2x32-bit DTCM interfaces
The following memory interfaces are supported:
• Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
• Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM
accesses
• AXI Bus interface to optimize Burst transfers
• Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It also supports single and double precision FPU (floating point unit) speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 1 shows the general block diagram of the STM32H7Sxx8 family.
Note: Cortex-M7 with FPU core is binary compatible with the Cortex-M4 core.
3.2 Memory protection unit (MPU)

The memory protection unit (MPU) manages the CPU access rights and the attributes of the
system resources. It has to be programmed and enabled before use. Its main purposes are
to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by
a privileged task, but also to protect data processes or read-protect memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It
allows defining up to 16 protected regions that can in turn be divided into up to 8
independent subregions, where region address, size, and attributes can be configured. The
protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is
generated.
24/320 DS14359 Rev 2

STM32H7Sxx8 Functional overview
3.3 Memories
3.3.1 Embedded flash memory

The STM32H7Sxx8 devices embed a flash memory organized as follow:
• 64 Kbytes of user flash memory that can be used for storing programs and data.
– The user flash contains 8 user sectors of 8 Kbytes each
– 1 Kbyte of OTP (one-time programmable) memory containing option bytes for user
configuration.
• 128 Kbytes of system flash memory from which the device can boot securely (but not
available for user code).
The flash memory is organized as 137-bit flash words memory. Each word consists of:
• One flash word (4 words, 16 bytes or 128 bits)
• 9 ECC bits.
3.3.2 Secure access mode

In addition to other typical memory protection mechanism, STM32H7Sxx8 devices embed
the Secure access mode, an enhanced security feature. This mode allows developing user-
defined secure services by ensuring, on the one hand code and data protection and on the
other hand code safe execution.
Two types of secure services are available:
• STMicroelectronics Root Secure Services:
These services are embedded in System memory. They provide a secure solution for
firmware and third-party modules installation. These services rely on cryptographic
algorithms based on a device unique private key.
• User-defined secure services:
These services are embedded in user flash memory. Examples of user secure services
are proprietary user firmware update solution, secure flash integrity check or any other
sensitive applications that require a high level of protection.
The secure firmware is embedded in specific user flash memory areas configured
through option bytes.
Secure services are executed just after a reset and preempt all other applications to
guarantee protected and safe execution. Once executed, the corresponding code and data
are no more accessible.
The above secure services are available only for Cortex-M7 core operating in Secure
access mode. The other masters cannot access the option bytes involved in Secure access
mode settings or the flash secured areas.
DS14359 Rev 2 25/320

75
3.3.3 Embedded SRAM

All devices feature:
• 456 Kbytes of AXI-SRAM mapped onto AXI bus matrix split into:
– AXI-SRAM1: 128 Kbytes shared with ITCM
– AXI-SRAM2: 128 Kbytes
– AXI-SRAM3: 128 Kbytes shared with DTCM
– AXI-SRAM4: 72 Kbytes shared with ECC
• 32 Kbytes of AHB-RAM mapped onto AHB bus matrix split into:
– AHB-SRAM1: 16 Kbytes
– AHB-SRAM2: 16 Kbytes
• 4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses, and is
retained in Standby or VBAT mode.
• RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories that are accessible from the
CPU or the HPDMA (even in Sleep mode) through a specific AHB slave of the
CPU(AHBS).
– 64 Kbytes of ITCM-RAM (instruction RAM) which could be increased up to 192
Kbytes using the AXI-SRAM1 with a 32 Kbytes granularity.
This RAM is connected to ITCM 64-bit interface designed for execution of critical
real-times routines by the CPU.
– 64 Kbytes of DTCM-RAM (2x 32 Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
which could be increased up to 192 Kbytes (2x96 Kbytes) using the AXI-SRAM3
with a 2x32 Kbytes granularity.
The DTCM-RAM could be used for critical real-time data, such as interrupt service
routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for
load/store operations) thanks to the Cortex-M7 dual issue capability.
3.4 Boot modes

At startup, the boot memory space is selected by the BOOT0 pin and and the NVSTATE.
For NVSTATE=OPEN the choice is made by the BOOT0 pin. For the NVSTATE=CLOSED
the boot, from the RSS is the in the system flash:
• NVSTATE=OPEN and BOOT0 pin=0, boot from user flash at address 0x8000 0000
• NVSTATE=OPEN and BOOT0 pin=1, boot from bootloader.
• NVSTATE=CLOSED, boot from RSS in system flash memory at address 0x1FF0 0080
The boot loader is located in non-user System flash memory. It is used to reprogram the
flash memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32
microcontroller system memory boot mode application note (AN2606) for details.
26/320 DS14359 Rev 2

3.5 Power supply management
3.5.1 Power supply scheme

• VDD = 1.71 to 3.6 V: external power supply for I/Os, provided externally through VDD
pins.
• VDDLDO = 1.71 to 3.6 V: supply voltage for the internal regulator supplying VCORE
• VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and
PLL.
• VDD33USB and VDD50USB: VDD50USB can be supplied through the USB cable to
generate the VDD33USB via the USB internal regulator. This allows supporting a VDD
supply different from 3.3 V.
The USB regulator can be bypassed to supply directly VDD33USB if VDD = 3.3 V.
• VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present.
• VCAP: VCORE supply, which value depends on voltage scaling (SVOS low, SVOS high,
VOS low, VOS high). It is configured through the VOS bits in the PWR_CSR4 and
PWR_CR1 registers.
• VDDSMPS = 1.71 to 3.6 V: step-down converter power supply
• VLXSMPS = VCORE or 1.8 V: external regulated step-down converter output
• VFBSMPS = VCORE or 1.8 V: external step-down converter feedback voltage sense input
Figure 2 gives the different power supply configurations.
DS14359 Rev 2 27/320

75
Figure 2. System supply configurations
VDDSMPS VDD VDDSMPS
VLXSMPS
VLXSMPS SMPS SMPS
VFBSMPS (off) VFBSMPS (on)
VSSSMPS VSSSMPS
VCAP VCAP
VDD VDDLDO VCORE VDDLDO VCORE

V reg V reg
VSS (on) VSS (off)
1. LDO supply 2. Direct SMPS supply
VDDSMPS VDD VDDSMPS

VDD
VLXSMPS
VLXSMPS
VDD_extern SMPS
SMPS VFBSMPS
VDD_extern VFBSMPS (on)
(on)
VSSSMPS
VSSSMPS
Ext VCAP
VCAP
reg
VCORE VDDLDO VCORE
VDD VDDLDO
V reg
V reg VSS
VSS (off)
(on)
4. External SMPS supply and bypass

3. External SMPS supply, supplies LDO
VDDSMPS
VLXSMPS
SMPS
VFBSMPS (off)
VSSSMPS
External supply VCAP

VDDLDO VCORE
V reg
VSS (off)
DT55556V1
5. Bypass
Note: The features available on the device depend on the package refer to Table 3:
STM32H7Sxx8 features and peripheral counts.
28/320 DS14359 Rev 2

3.5.2 Power supply supervisor

The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry:
• Power-on reset (POR)
The POR supervisor monitors VDD power supply and compares it to a fixed threshold.
The devices remain in reset mode when VDD is below this threshold,
• Power-down reset (PDR)
The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops
below a fixed threshold.
• Brownout reset (BOR)
The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to
2.7 V) can be configured through option bytes. A reset is generated when VDD drops
below this threshold.
• Programmable voltage detector (PVD)
The PVD monitors the VDD power supply by comparing it with a threshold selected
from a set of predefined values.
It can also monitor the voltage level of the PVD_IN pin by comparing it with an internal
VREFINT voltage reference level.
• Analog voltage detector (AVD)
The AVD monitors the VDDA power supply by comparing it with a threshold selected
from a set of predefined values.
• VBAT threshold
The VBAT battery voltage level can be monitored by comparing it with two thresholds
levels.
• Temperature threshold
A dedicated temperature sensor monitors the junction temperature and compare it with
two threshold levels.
3.5.3 Voltage regulator

Voltage regulator output can be adjusted according to application needs through four power
supply levels:
• Run mode (VOS high and VOS low)
– Scale HIGH : high performance
– Scale LOW: optimized performance and low-power consumption
• Stop mode (SVOS high and SVOS low)
– Scale HIGH: peripheral with wakeup from stop mode capabilities (UART, SPI, I2C,
LPTIM) are operational
– Scale LOW where the peripheral with wakeup from Stop mode is disabled
The peripheral functionality is disabled but wakeup from Stop mode is possible
through GPIO or asynchronous interrupt.
DS14359 Rev 2 29/320

75
3.5.4 SMPS step-down converter

The built-in SMPS step-down converter is a highly power-efficient DC/DC non-linear
switching regulator that provides lower power consumption than a conventional voltage
regulator (LDO).
The step-down converter can be used to:
• Directly supply the VCORE domain
– the SMPS step-down converter operating modes follow the device system
operating modes (Run, Stop, Standby).
– the SMPS step-down converter output voltage are set according to the selected
VOS and SVOS bits (voltage scaling)
• Provide an external supply
– The SMPS step-down converter is forced to High-performance mode
– The SMPS step-down converter output equals 1.8 V according to the selected
step-down level
The 1.8 V SMPS step-down converter output voltage imposes a minimum VDDSMPS supply
of 2.3 V to 3.6 V. It defines indirectly the minimum VDD supply and I/O level.
3.6 Low-power modes

There are several ways to reduce power consumption on STM32H7Sxx8:
• Decrease dynamic power consumption by slowing down the system clocks even in
Run mode and individually clock gating the peripherals that are not used.
• Save power consumption when the CPU is idle, by selecting among the available low-
power mode according to the user application needs. This allows achieving the best
compromise between short startup time, low-power consumption, as well as available
wakeup sources. The low-power modes are:
– Sleep (CPU clock stopped and still in RUN mode)
– Stop (System clock stopped)
– Standby (System powered down)
30/320 DS14359 Rev 2

Sleep and Stop low-power modes are entered by the MCU when executing the WFI (Wait
for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of the
Cortex-M7 core is set after returning from an interrupt service routine.
The CPU domain can enter low-power mode (Stop) when the processor, its subsystem and
the peripherals allocated in the domain enter low-power mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared.
Table 4. Operating mode summary

System Peripheral Voltage
System System clock CPU clock
oscillator clock regulator
Run ON ON
ON ON ON (VOS)
Sleep
ON/OFF
Stop ON/OFF OFF ON (SVOS)
OFF
Standby OFF OFF OFF
Some GPIO pins can be used to monitor CPU and domain power states:
Table 5. Overview of low-power mode monitoring pins

Power state monitoring pins Description
PWR_CSLEEP CPU clock OFF

PWR_CSTOP CPU domain in low-power mode
3.7 Reset and clock controller (RCC)

The RCC manages the generation of all the clocks, as well as the clock gating and the
control of the system and peripheral resets. It provides a high flexibility in the choice of clock
sources and allows to apply clock ratios to improve the power consumption. In addition, on
some communication peripherals that are capable to work with two different clock domains
(either a bus interface clock or a kernel peripheral clock), the system frequency can be
changed without modifying the baud rate.
DS14359 Rev 2 31/320

75
Figure 3. Top-level clock tree
RCC
VDD domain
LSION or IWDG activated
lsi_ck
LSI tempo To IWDG
VSW (Backup) RTCSEL

RTCEN
LSEON 0 0
OSC32_IN lse_ck lse_ck rcc_rtc_ck
LSE tempo 1 To RTC/AWU
lsi_ck D
OSC32_OUT 2
CSS hse_rtc_ck
3
RTCPRE MCO1SEL
VDD domain
÷ 2 to 63 hsi_ck
HSEON 0
OSC_IN MCO1PRE
tempo lse_ck 1
HSE hse_ck ÷ 1 to15 MCO1
OSC_OUT hse_ck 2
CSS hse_ker_ck pll1_q_ck 3
hsi48_ck 4
÷1024 hsi_cal_ck
HSIKERON MCO2SEL
HSION HSIDIV
hsi_osc_ck
HSI tempo ÷1,2,4,8 hsi_ck sys_ck 0
pll2_p_ck 1 MCO2PRE
hsi_ker_ck hse_ck 2 ÷ 1 to15 MCO2
CSIKERON pll1_p_ck 3
CSION ÷4 ucpd_ker_ck
csi_ck 4
CSI tempo csi_ck 5
lsi_ck
csi_ker_ck
HSI48ON ÷128 csi_cal_ck
SCGU (System clock generation)
SCEU (System clock enabling)

CRS HSI48 hsi48_ker_ck
Clock SW
recovery CKPERSEL
system hsi_ck 0
hsi_ker_ck 0 csi_ck 1D sys_ck
csi_ker_ck 1 per_ck hse_ck 2 To CPU,
pll1_p_ck busses and
hse_ker_ck 2 3
PLLSRC peripherals
pll_ck
hsi_ck 0 PLL1
ref1_ck
csi_ck 1 ÷ DIVM1
1 to 16 VCO ÷ 2 DIVP
hse_ck 2 MHz pll1_q_ck
DIVN DIVQ
pll[3:1]_q_ck
DIVR
FRACN
PKSU (Peripheral kernel clock selection)
pll[3:2]_p_ck
SSCG DIVS pll1_s_ck
PKEU (Peripheral clock enabling)
pll[3:2]_r_ck
DIVT
sys_ck
PLL2 per_ck
÷ DIVM2 ref2_ck pll2_p_ck hse_ker_ck
VCO ÷ 2 DIVP To
1 to 16 pll2_q_ck hsi_ker_ck
MHz DIVN DIVQ peripherals
pll2_r_ck csi_ker_ck
DIVR
FRACN lsi_ck
SSCG DIVS pll2_s_ck lse_ck
DIVT pll2_t_ck hsi48_ker_ck
ucpd_ker_ck
PLL3
ref3_ck pll3_p_ck
÷ DIVM3 VCO ÷ 2 DIVP
1 to 16
MHz pll3_q_ck
DIVN DIVQ
pll3_r_ck I2S_CKIN
DIVR
FRACN ETH_MII_CK_TX
SSCG DIVS pll3_s_ck ETH_MII_CK_RX/
DIVT ETH_RMII_REF_CLK
ETH_CLK
D The selected input can be changed on-the-fly without spurs on the output signal. x Represents the selected mux input after a system reset.
MSv54104V4
32/320 DS14359 Rev 2

Figure 4. Core and bus clock generation
RCC
System clock generation (SCGU)
trace_ck
÷3 To TPIU
50% Duty-cycle
rcc_cpu_ck
CPU clocks
rcc_fclk
FCPU max
÷8 CPU SysTick clock
sys_cpu_ck
SW FBUS Max rcc_aclk AXI Matrix

CPRE (1) BMPRE (1) AXI peripheral clocks
hsi_ck 0
csi_ck 1D
sys_ck rcc_hclk5
÷ 1,2,4,8,…,512 ÷ 1,2,4,8,…,512 AHB5 peripheral clocks
hse_ck 2 PPRE5 (1)
SCEU (System Clock Enabling)

pll1_p_ck 3
rcc_pclk5
sys_bus_ck
÷ 1,2,4,8,16 APB5 peripheral clocks
FBUS Max / 2
FBUS Max rcc_hclk[4:1] AHB Matrix
AHB1,2,3,4 peripheral clocks
PPRE1 (1)
Phase rcc_pclk1
aligned ÷ 1,2,4,8,16 APB1 peripheral clocks
FBUS Max / 2
PPRE2 (1)
rcc_pclk2 APB2 peripheral clocks

÷ 1,2,4,8,16
FBUS Max / 2
PPRE4 (1)
rcc_pclk4
÷ 1,2,4,8,16 APB4 peripheral clocks
x Represents the selected value after a system reset.
MSv54113V3
DS14359 Rev 2 33/320

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Table 6. Peripheral clock distribution summary

Kernel clock MUX Max Kernel
Type
Peripherals Clock types Clock sources clock freq. (2)(3)
Pos. Control field [MHz] (1)
hclk1 0(4)
pll2_p_ck 1
pll3_p_ck 2
Kernel ADF1SEL FMAX / 2 A
ADF I2S_CKIN 3
csi_ker_ck 4
hsi_ker_ck 5
Bus hclk1 - - FMAX / 2 -
pll2_p_ck 0(4)
Kernel pll3_r_ck 1 ADCSEL 125 A
ADC12
per_ck 2
CORDIC Bus hclk2 - - FMAX / 2 -
CRC Bus hclk4 - - FMAX / 2 -
CRS Bus pclk1 - - FMAX / 4 -
CRYP Bus hclk3 - - FMAX / 2 -
Bus sys_bus_ck - - FMAX / 2 -
DBG
kernel sys_cpu_ck/3 - - FMAX / 3 -
DB_OCSPI1.
DB_OCSPI2
DB_SDMMC1 Bus hclk5 - - FMAX / 2 -
DB_SDMMC2 Bus hclk2 - - FMAX / 2 -
aclk - - FMAX / 2 -
DCMIPP Bus
pclk5 FMAX / 4
GPDMA1 Bus hclk1 - - FMAX / 2 -
hclk5
HPDMA1 Bus - - FMAX / 2 -
aclk
hclk5
DMA2D Bus - - FMAX / 2 -
aclk
34/320 DS14359 Rev 2

Table 6. Peripheral clock distribution summary (continued)

Type
ETH_MII_TX_CLK - - 25 A
ETH_MII_TX_CLK/.
ETH_RMII_REF_CL 0(4)
K
ETH1REFCKSEL 25 A
hse_ker_ck 1
Kernel
ETH1 eth_clk_fb 2
hse_ker_ck 0(4)
ETH1PHYCKSEL 50 A
pll3_s_ck 1
clk_ptp_ref_i FMAX / 2 -
EXTI Bus pclk4 - - FMAX / 4 -
FLASH Bus hclk5 - - FMAX / 2 -
(4)
hse_ker_ck 0
Kernel pll1_q_ck 1 FDCANSEL 125 A
FDCAN
pll2_p_ck 2
Bus pclk1 - - FMAX / 4 -
hclk5 0(4)
pll1_q_ck 1
Kernel FMCSEL FMAX / 2 A
pll2_r_ck 2
FMC
hsi_ker_ck 3
hclk5 -
Bus - FMAX / 2 -
aclk
GPIOA-H. GPIOM-P Bus hclk4 - - FMAX / 2 -
hclk5
GPU2D Bus - - FMAX / 2 -
aclk
hclk5
GFXMMU Bus - - FMAX / 2 -
aclk
GFXTIM Bus pclk5 - - FMAX / 4 -
HASH Bus hclk3 - - FMAX / 2 -
lse_ck 0(4)
Kernel lsi_ck 1 CECSEL 1
HDMI-CEC -
csi_ker_ck/122 2
Bus pclk1 - - FMAX / 4
DS14359 Rev 2 35/320

75

Type
pclk1 0(4)
pll3_r_ck 1
Kernel I2C23SEL FMAX / 4 A
I2C2, I2C3 hsi_ker_ck 2
csi_ker_ck 3
(4)
pclk1 0
pll3_r_ck 1
Kernel I2C1_I3C1SEL FMAX / 4 A
I2C1/I3C1 hsi_ker_ck 2
csi_ker_ck 3
XSPIM Bus hclk5 - - FMAX / 2 -
Kernel lsi_ck - - 1 A
IWDG
JPEG Bus hclk5 - - FMAX / 2 -
pclk1 0(4)
pll2_p_ck 1
pll3_r_ck 2
Kernel LPTIM1SEL FMAX / 4 A
LPTIM1 lse_ck 3
lsi_ck 4
per_ck 5
pclk4 0(4)
pll2_p_ck 1
pll3_r_ck 2
LPTIM2, LPTIM3 lse_ck 3
lsi_ck 4
per_ck 5
36/320 DS14359 Rev 2


Type
pclk4 0(4)
pll2_p_ck 1
pll3_r_ck 2
LPTIM4, LPTIM5 lse_ck 3
lsi_ck 4
per_ck 5
pclk4 0(4)
pll2_q_ck 1
pll3_q_ck 2
Kernel LPUART1SEL FMAX / 4 A
LPUART1 hsi_ker_ck 3
csi_ker_ck 4
lse_ck 5
Kernel pll3_r_ck - 90 A
LTDC pclk5 - - FMAX / 4
Bus -
aclk - FMAX / 2
aclk -
MCE1, MCE2, MCE3 Bus - FMAX / 2 -
hclk5 -
MDIO Bus pclk1 - - FMAX / 4 -
PKA Bus hclk3 - - FMAX / 2 -
PWR Bus hclk4 - - FMAX / 2 -
pll3_r_ck 0(4) -
Kernel PSSISEL 100
PSSI per_ck 1 -
hclk5 0(4)
Kernel pll2_s_ck 1 XSPI1SEL FMAX / 2 A
XSPI1 pll2_t_ck 2
hclk5
Bus - - FMAX / 2 -
aclk
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75

Type
hclk5 0(4)
Kernel pll2_s_ck 1 XSPI2SEL FMAX / 2 A
XSPI2 pll2_t_ck 2
hclk5
Bus - - FMAX / 2 -
aclk
hsi48_ker_ck 0(4)
pll3_q_ck 1
Kernel OTGFSSEL 50 A
OTGFS hse_ker_ck 2
clk48mohci 3
Kernel phy60m_ck - - 60 A
OTGHS
RCC Bus hclk4 - - FMAX / 2 -
Kernel hsi48_ker_ck - - 48 A
RNG
no clock 0(4)
lse_ck 1
Kernel lsi_ck 2 RTCSEL 4 A
RTC/AWU(5)
hse_ker_ck /
3
(RTCDIV+1)
Kernel hclk3 - - FMAX / 2 A
SAES
(4)
pll1_q_ck 0
pll2_p_ck 1
Kernel pll3_p_ck 2 SAI1SEL 133 A
SAI1
I2S_CKIN 3
per_ck 4
38/320 DS14359 Rev 2


Type
pll1_q_ck 0(4)
pll2_p_ck 1
pll3_p_ck 2
Kernel SAI2SEL 133 A
SAI2 I2S_CKIN 3
per_ck 4
spdif_symb_ck 5
SBS Bus pclk4 - - FMAX / 4 -
pll2_s_ck 0(4)
Kernel SDMMC12SEL 200 A
SDMMC1 pll2_t_ck 1
pll2_s_ck 0(4)
Kernel SDMMC12SEL 200 A
SDMMC2 pll2_t_ck 1
(4)
pll1_q_ck 0
pll2_r_ck 1
Kernel SPDIFRXSEL 200 A
SPDIFRX pll3_r_ck 2
hsi_ker_ck 3
pclk4 0(4)
pll2_q_ck 1
pll3_q_ck 2
Kernel SPI6SEL 200 A
SPI/I2S6 hsi_ker_ck 3
csi_ker_ck 4
hse_ker_ck 5
(4)
pll1_q_ck 0
pll2_p_ck 1
Kernel pll3_p_ck 2 SPI1SEL 130 A
SPI/I2S1
I2S_CKIN 3
per_ck 4
DS14359 Rev 2 39/320

75

Type
pclk2 0(4)
pll2_q_ck 1
pll3_q_ck 2
Kernel SPI45SEL 200 A
SPI4, SPI5 hsi_ker_ck 3
csi_ker_ck 4
hse_ker_ck 5
pll1_q_ck 0(4)
pll2_p_ck 1
Kernel pll3_p_ck 2 SPI23SEL 200 A
SPI/I2S3, SPI/I2S2
I2S_CKIN 3
per_ck 4
no clock 0(4)
lse_ck 1
Kernel lsi_ck 2 RTCSEL 4 A
TAMPER
hse_ker_ck/
3
(RTCDIV+1)
Kernel lse_ck - - 10 A
DTS
TIM2, TIM3, TIM4, Kernel timg1_ck - - FMAX / 2 S
TIM5, TIM6, TIM7,
TIM12, TIM13, Bus pclk1 - - FMAX / 4 -
TIM14
TIM1, TIM9, TIM15, Kernel timg2_ck - - FMAX / 2 S

TIM16, TIM17, Bus pclk2 - - FMAX / 4 -
pclk2 0(4)
pll2_q_ck 1
pll3_q_ck 2
Kernel USART1SEL FMAX / 4 A
USART1, hsi_ker_ck 3
csi_ker_ck 4
lse_ck 5
40/320 DS14359 Rev 2


Type
pclk1 0(4)
pll2_q_ck 1
pll3_q_ck 2
USART2, USART3, Kernel UART234578SEL FMAX / 4 A
UART4, UART5, hsi_ker_ck 3
UART7, UART8
csi_ker_ck 4
lse_ck 5
Kernel ucpd_ker_ck - - 25 A
UCPD
(4)
hse_ker_ck 0
USBPHYC Kernel hse_ker_ck / 2 1 USBPHYCSEL 32 A
pll3_q_ck 2
VREFBUF Bus pclk4 - - FMAX / 4 -
WWDG1 Bus pclk1 - - FMAX / 4 -
1. FMAX value depends on the device reference and can be found on the datasheet of the product.
2. 'A' Means that the kernel clock is asynchronous with respect to bus interface clock.
3. ‘S’ Means that the kernel clock is synchronous with respect to bus interface clock.
4. Reset value
5. The RTC switch is in the VSW voltage domain
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3.7.1 Clock management

The devices embed four internal oscillators, two oscillators with external crystal or
resonator, two internal oscillators with fast startup time and three PLLs.
The RCC receives the following clock source inputs:
• Internal oscillators:
– 64 MHz HSI clock (1% accuracy)
– 48 MHz RC oscillator
– 4 MHz CSI clock
– 32 kHz LSI clock
• External oscillators:
– 4-50 MHz HSE clock
– 32.768 kHz LSE clock
The RCC provides three PLLs: one for system clock, two for kernel clocks.
The system starts on the HSI clock. The user application can then select the clock
configuration.
A high precision can be achieved for the 48 MHz clock by using the embedded clock
recovery system (CRS). It uses the USB SOF signal, the LSE or an external signal (SYNC)
to fine tune the oscillator frequency on-the- fly.
3.7.2 System reset sources

Power-on reset initializes all registers while system reset reinitializes the system except for
the debug, part of the RCC, the power controller status registers and part of the SBS, as
well as the backup power domain.
A system reset is generated in the following cases:
• Power-on reset (pwr_por_rst)
• Brownout reset
• Low level on NRST pin (external reset)
• Window watchdog
• Independent watchdog
• Software reset
• Low-power mode security reset
• Exit from Standby
• An option byte reload request from the flash interface (obl_rst)
42/320 DS14359 Rev 2

3.8 General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
as analog, or as peripheral alternate functions. Most of the GPIO pins are shared with digital
or analog alternate functions. All GPIOs are high-current-capable and have speed selection
to better manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs are in Analog mode to reduce power consumption (refer to GPIOs
register reset values in the device reference manual).
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.9 Bus-interconnect matrix

The devices feature an AXI bus matrix, an AHB bus matrices and bus bridges that allow
interconnecting bus masters with bus slaves (see Figure 5).
DS14359 Rev 2 43/320

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Figure 5. System architecture

AHBS
Legend
DTCM0
CPU 32/96 Kbytes
Cortex-M7
DTCM1
32-bit bus AXI AHB APB
32/96 Kbytes 64-bit bus Master interface
I$ D$
32KB 32KB ITCM
64/192 Kbytes
Bus multiplexer Slave interface
AXIM
AHBP
From
GPU ICACHE
AHB SDMMC1 HPDMA1 DCMIPP DMA2D GFXMMMU
ICACHE AXI AXI
domain
To AHB domain
MCE3 FMC
MCE1 XSPI1
MCE2 XSPI2
SRAM4
SRAM3
SRAM2
SRAM1
FLASH
GPV
From CM7_AHBP
From AXI
GPDMA1 ETH1 SDMMC2 OTG_HS
AHB1
SRAM1
16 Kbytes
SRAM2
16 Kbytes
AHB2
AHB3
AHB4
Backup SRAM Reg

AHB6 4 Kbytes
To AXI
AHB5
MSv55520V5
44/320 DS14359 Rev 2

3.10 General purpose / high-performance direct memory access

controller (GPDMA/HPDMA)
The general purpose direct memory access (GPDMA) controller and the high-performance
direct memory access (HPDMA) controller are both bus master and system peripherals.
The GPDMA and HPDMA are used to perform programmable data transfers between
memory-mapped peripherals and/or memories via linked-lists, upon the control of an off-
loaded CPU.
Their main features are:
• Dual bidirectional AXI master for HPDMA and AHB master for GPDMA
• Memory-mapped data transfers from a source to a destination:
– peripheral-to-memory
– memory-to-peripheral
– memory-to-memory
– peripheral-to-peripheral
• Transfers arbitration based on a four-grade programmed priority at a channel level:
– One high-priority traffic class, for time-sensitive channels (queue 3)
– Three low-priority traffic classes, with a weighted round-robin allocation for non
time-sensitive channels (queues 0, 1, 2)
• Per channel event generation, on any of the following events: transfer complete, half
transfer complete, data transfer error, user setting error, link transfer error, completed
suspension, or trigger overrun
• Per channel interrupt generation, with separately programmed interrupt enable per
event
• 16 concurrent DMA channels:
– Per channel FIFO for queuing source and destination transfers
– Intra-channel DMA transfers chaining via programmable linked-list into memory,
supporting two execution modes: run-to-completion and link step mode
– Intra-channel and inter-channel DMA transfers chaining via programmable DMA
input triggers connection to DMA task completion events
• Per linked-list item within a channel:
– Separately programmed source and destination transfers
– Programmable data handling between source and destination: byte-based
reordering, packing or unpacking, padding or truncation, sign extension and
left/right realignment
– Programmable number of data bytes to be transferred from the source, defining
the block level
– linear source and destination addressing: either fixed or contiguously incremented
addressing, programmed at a block level, between successive single transfers
– 2D source and destination addressing: programmable signed address offsets
between successive burst transfers (non-contiguous addressing within a block,
DS14359 Rev 2 45/320

75
combined with programmable signed address offsets between successive blocks,

at a second 2D/repeated block level)
– Support for scatter-gather (multi-buffer transfers), data interleaving and
deinterleaving via 2D addressing
– Programmable DMA request and trigger selection
– Programmable DMA half-transfer and transfer complete events generation
– Pointer to the next linked-list item and its data structure in memory, with automatic
update of the DMA linked-list control registers
• Debug:
– Channel suspend and resume support
– Channel status reporting including FIFO level and event flags
• Privileged/unprivileged support:
– Support for privileged and unprivileged GPDMA transfers, independently at a
channel level
– Privileged-aware AHB slave port.
3.11 Chrom-ART Accelerator (DMA2D)

The Chrom-Art Accelerator (DMA2D) is a graphical accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
• Rectangle filling with a fixed color
• Rectangle copy
• Rectangle copy with pixel format conversion
• Rectangle composition with blending and pixel format conversion
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables. The DMA2D also
supports block based YCbCr to handle JPEG decoder output.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
3.12 NeoChrom graphic processor (GPU2D)

The GPU2D is a dedicated graphics processing unit accelerating numerous 2.5D graphics
applications such as graphical user interface (GUI), menu display or animations.
It works together with an optimized software stack designed for state of the art graphic
rendering.
46/320 DS14359 Rev 2

Main features
• Multi-threaded fragment (pixel) processing core with a VLIW (very-long instruction
word) instruction set
• Fixed point functional units
• Command list based DMAs to minimize CPU overhead
• Two 64-bit AXI master interfaces for texture, command list and framebuffer access
• Dedicated 64-bit AXI master interface for command list
• 32-bit AHB slave interface for register bank access
• Up to 4 general-purpose flags for system-level synchronization
• Texture decompression unit with TSC™4 and TSC™6/TSC™6a support
• 16 Kbyte texture cache (ICACHE)
2D drawing features
• Pixel/line drawing
• Filled rectangles
• Triangles, quadrilateral drawing
• Anti-aliasing 8xMSAA (multi-sample anti-aliasing)
Image transformations
• 3D perspective correct projections
• Texture mapping with bilinear filtering or point sampling
Blit support
• Rotation, mirroring, stretching (independently on x and y axis)
• Source and/or destination color keying
• Pixel format conversions
Text rendering support

• A1, A2, A4, and A8 bitmap anti-aliased
• Subsampled anti-aliased
Main color format

• RGB, grayscale
• 32, 24, 16 and 8 bits with/without alpha
Full alpha blending with hardware blender

• Programmable blending modes
• Source/destination color keying
DS14359 Rev 2 47/320

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3.13 Chrom-GRC (GFXMMU)

The Chrom-GRC is a graphical oriented memory management unit aimed at optimizing
memory usage according to the display shape.
GFXMMU main features:
• Fully programmable display shape to physically store only the visible pixel
• Up to 4 virtual buffers
• Each virtual buffer have 3072 or 4096 bytes per line and 1024 lines
• Each virtual buffer can be physically mapped to any system memory
• Packing and unpacking operation to store 32-bit pixel data into 24-bit packed
• Interrupt in case of buffer overflow (1 per buffer)
• Interrupt in case of memory transfer error
3.14 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller which is able to manage 16
priority levels, and handle up to 140 maskable interrupt channels plus the 16 interrupt lines
of the Cortex-M7 with FPU core.
• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support tail chaining
• Processor context automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.15 Extended interrupt and event controller (EXTI)

The EXTI controller performs interrupt and event management. In addition, it can wake up
the processor from Stop mode.
The EXTI handles up to 61 independent event/interrupt lines split as 27 configurable events
and 34 direct events.
Configurable events have dedicated pending flags, active edge selection, and software
trigger capable.
Direct events provide interrupts or events from peripherals having a status flag.
48/320 DS14359 Rev 2

3.16 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.17 CORDIC co-processor (CORDIC)

The CORDIC co-processor provides hardware acceleration of certain mathematical
functions, notably trigonometric, commonly used in motor control, metering, signal
processing and many other applications. It speeds up the calculation of these functions
compared to a software implementation, allowing a lower operating frequency, or freeing up
processor cycles in order to perform other tasks.
The CORDIC main features are:
• 24-bit CORDIC rotation engine
• Circular and hyperbolic modes
• Rotation and vectoring modes
• Functions: sine, cosine, sinh, cosh, atan, atan2, atanh, modulus, square root, natural
logarithm
• Programmable precision
• Low-latency AHB slave interface
• Results can be read as soon as ready without polling or interrupt
• DMA read and write channels
• Multiple register read/write by DMA
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3.18 Flexible memory controller (FMC)

The FMC controller main features are the following:
• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR flash memory/OneNAND flash memory
– PSRAM (4 memory banks)
– NAND flash memory with ECC hardware to check up to 8 Kbytes of data
• Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
• 8-,16-,32-bit data bus width
• Independent Chip Select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO
• Read FIFO for SDRAM controller
• The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the
FMC kernel clock divided by 2.
50/320 DS14359 Rev 2

3.19 Quad/Octo/Hexa-SPI memory interface
3.19.1 XSPI I/O manager (XSPIM)

The XSPI I/O manager is a low-level interface that enables an efficient XSPI pin assignment
with a full I/O matrix (before alternate function map) and multiplex of
single/dual/quad/octal/16-bit SPI interfaces over the same bus. up to 2 interfaces are
available where one could be up to 16bits depending on the package.
it can support up to two single/dual/quad/octal/16-bit SPI interfaces (depending on the
package option).
Table 7. XSPIM implementation
XSPIM features i/f avaibility
Supports up to two single/dual/quad interfaces Both

Fully I/O multiplexing capability Both
Supports time-multiplexed mode Both
Supports high-speed interface Both
Chip select selection if XSPI provides dual chip select Package dependent
Supports 16-bit data interface and dual-octal mode Only a single i/f, package dependent
3.19.2 Extended-SPI interface (XSPI)

The XSPI supports most external serial memories such as serial PSRAMs, serial NAND and
serial NOR flash memories, HyperRAM™ and HyperFlash™ memories, with the following
functional modes:
• indirect mode: all the operations are performed using the XSPI registers to preset
commands, addresses, data and transfer parameters.
• automatic status-polling mode: the external memory status register is periodically read
and an interrupt can be generated in case of flag setting.
• memory-mapped mode: the external memory is memory mapped and it is seen by the
system as if it was an internal memory, supporting both read and write operations.
The XSPI supports the following protocols with associated frame formats:
• the regular-command frame format with the command, address, alternate byte, dummy
cycles and data phase
• the HyperBus™ frame format
DS14359 Rev 2 51/320

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Table 8. XSPI implementation

Feature XSPI1/2
HyperBus standard compliant X

Xccela standard compliant X
XSPI (JDES251C) standard compliant X
AMBA® AXI compliant data interface X
Asynchronous AHB clock versus kernel clock X
Functional modes: indirect, automatic status-polling, and memory-mapped X
Dual chip select support (NCS1 and NCS2) X
Read and write support in memory-mapped mode X
Dual-quad configuration X
Dual-octal configuration X
SDR (single-data rate) and DTR (double-transfer rate) X
Data strobe (DS, DQS) X
Fully programmable opcode X
Fully programmable frame format X
Integrated FIFO for reception and transmission X
8, 16, and 32-bit data accesses X
Interrupt on FIFO threshold, timeout, operation complete, and access error X
Compliant with dual-XSPI arbiter (communication regulation) X
Extended CSHT timeout X
Memory-mapped write X
Refresh counter X
High-speed interface X
GP/HPDMA interface X
Prefetch disable -
Prefetch hardware software -
52/320 DS14359 Rev 2

3.20 Analog-to-digital converters (ADCs)

The STM32H7Sxx8 devices embed two analog-to-digital converters, which resolution can
be configured to 12, 10, 8, or 6 bits. Each ADC shares up to 19 channels, performing
conversions in the single-shot or scan mode. In scan mode, automatic conversion is
performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
• Simultaneous sample and hold
• Interleaved sample and hold
The ADC can be served by the DMA controller, thus allowing to automatically transfer ADC
converted values to a destination location without any software action.
In addition, an analog watchdog feature can accurately monitor the converted voltage of
one, some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM6 TIM9, TIM12, and TIM15.
3.21 Analog temperature sensor

The temperature sensor generates a voltage VSENSE that varies linearly with temperature.
The temperature sensor is internally connected to the ADC1_INP16 input channel that is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity, but it must be calibrated to obtain a good accuracy of
temperature measurement. As the offset of the temperature sensor varies from chip to chip
due to process variation, the uncalibrated internal temperature sensor is suitable for
applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data is
stored by STMicroelectronics in the system memory area, and is accessible in read-only
mode.
Table 9. Temperature sensor calibration values

Calibration
Description Memory address
value name
Temperature sensor 12-bit raw data acquired by ADC1

TS_CAL1 0x08FF F814 - 0x08FF F815
at 30 °C (± 5 °C), VDDA = VREF+ = 3.3 V (± 10 mV)
Temperature sensor 12-bit raw data acquired by ADC1
TS_CAL2 0x08FF F818 - 0x08FF F819
at 130 °C (± 5 °C), VDDA = VREF+ = 3.3 V (± 10 mV)
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3.22 Digital temperature sensor (DTS)

The STM32H7Sxx8 embeds a sensor that converts the temperature into a square wave
which frequency is proportional to the temperature. The PCLK or the LSE clock can be used
as reference clock for the measurements. A formula given in the product reference manual
(RM0477) allows to calculate the temperature according to the measured frequency stored
in the DTS_DR register.
3.23 VBAT operation

The VBAT power domain contains the RTC, the backup registers and the backup SRAM.
To optimize battery duration, this power domain is supplied by VDD when available or by the
voltage applied on VBAT pin (when VDD supply is not present). VBAT power is switched
when the PDR detects that VDD dropped below the PDR level.
The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or
directly by VDD, in which case, the VDD mode is not functional.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
The devices embed an internal VBAT battery charging circuitry that can be activated when
VDD is present.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
3.24 Voltage reference buffer (VREFBUF)

The built-in voltage reference buffer can be used as voltage reference for ADCs , as well as
voltage reference for external components through the VREF+ pin.
Three different voltages are supported (refer to the reference manual for details).
54/320 DS14359 Rev 2

3.25 Audio digital filter (ADF)

The audio digital filter (ADF) is a high-performance module dedicated to the connection of
external sigma-delta (Σ∆) modulators. The table below lists the set of features implemented
into the ADF.
Table 10. ADF features (1)

Mode or feature ADF1
Number of filters (DFLTx) and serial interfaces (SITFx) 1
ADF_CKI0 connected to pins -
Sound activity detection (SAD) X
RXFIFO depth (number of 24-bit words) 4
ADC connected to ADCITF1 ADC1
ADC connected to ADCITF2 ADC2
Motor dedicated features (SCD, OLD, OEC, INT, snapshot, break) -
Main path with CIC4, CIC5 X
Main path with CIC1,2, 3 or FastSinc -
RSFLT, HPF, SAT, SCALE, DLY, Discard functions X
Autonomous in Stop modes -
1. ‘X’ = supported, ‘-’ = not supported.
3.26 Digital camera interface (DCMIPP)

The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 16-bit parallel interface, to receive video data. The camera
interface can achieve a data transfer rate up to 240 Mbyte/s using a 120 MHz pixel clock. It
features:
• Programmable polarity for the input pixel clock and synchronization signals
• Parallel data communication can be 8-, 10-, 12-, 14- or 16-bit
• Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
• Supports continuous mode or snapshot (a single frame) mode
• Capability to automatically crop the image
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3.27 Parallel synchronous slave interface (PSSI)

The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It
allows the transmitter to send a data valid signal to indicate when the data is valid, and the
receiver to output a flow control signal to indicate when it is ready to sample the data.
The PSSI main features are:
• Slave mode operation
• 8- or 16-bit parallel data input or output
• 8-word (32-byte) FIFO
• Data enable (DE) alternate function input and Ready (RDY) alternate function output.
When enabled, these signals can either allow the transmitter to indicate when the data
is valid or the receiver to indicate when it is ready to sample the data, or both.
The PSSI shares most of the circuitry with the digital camera interface (DCMIPP). It thus
cannot be used simultaneously with the DCMIPP.
3.28 LCD-TFT display controller

The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
• 2 display layers with dedicated FIFO (64x32-bit)
• Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
• Up to 8 input color formats selectable per layer
• Flexible blending between two layers using alpha value (per pixel or constant)
• Flexible programmable parameters for each layer
• Color keying (transparency color)
• Up to 4 programmable interrupt events
• AXI master interface with burst of 16 words
56/320 DS14359 Rev 2

3.29 JPEG codec (JPEG)

The JPEG codec can encode and decode a JPEG stream as defined in the
ISO/IEC10918-1 specification. It provides an fast and simple hardware compressor and
decompressor of JPEG images with full management of JPEG headers.
The JPEG codec main features are as follows:
• 8-bit/channel pixel depths
• Single clock per pixel encoding and decoding
• Support for JPEG header generation and parsing
• Up to four programmable quantization tables
• Fully programmable Huffman tables (two AC and two DC)
• Fully programmable minimum coded unit (MCU)
• Encode/decode support (non simultaneous)
• Single clock Huffman coding and decoding
• Two-channel interface: Pixel/Compress In, Pixel/Compressed Out
• Stallable design
• Support for single greyscale component
• Ability to enable/disable header processing
• Internal register interface
• Fully synchronous design
• Configuration for high-speed decode mode
3.30 Random number generator (RNG)

All the devices embed an RNG that delivers 32-bit random numbers generated by an
integrated analog circuit.
3.31 Cryptographic acceleration (CRYP)

The devices implement state-of-the-art cryptographic algorithms featuring key sizes and
computing protection as recommended by national security agencies. These agencies
include: NIST for the U.S.A, BSI for Germany or ANSSI for France. The algorithms are used
to support privacy, authentication, integrity, entropy and identity attestation.
The crypto engines embedded in STM32 reduce weaknesses in the implementation of
critical cryptographic functions. They prevent, for example, the use of weak cryptographic
algorithms and key sizes. They also enable shorter processing times and lower power
consumption when performing cryptographic operations, by offloading those computations
from Cortex-M7. This is especially true for asymmetric cryptography.
For product certification purposes, ST can provides certified device information on how
these security functions are implemented and validated.
For more information on crypto engine processing times, refer to their respective sections in
the reference manual.
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3.31.1 Crypto engines features

The table below lists the accelerated cryptographic operations available in the devices. Two
AES accelerators are available. One is side-channel attack protected (SAES), while the
second is more performance oriented (CRYP).
Note: Additional operations can be added using firmware.
The PKA can accelerate asymmetric crypto operations (like key pair generation, ECC scalar
multiplication, point on curve check). See Section 40: Public key accelerator (PKA) for more
details.
Table 11. Accelerated cryptographic operations

Algo- Key lengths
Operations Specification Modes
rithm (in bit)
Software and hardware(2)

Get entropy RNG NIST SP800-90B(1) N/A
modes running in parallel
FIPS PUB 197
Encryption, decryption 128, 256 ECB, CBC, CTR(3)
NIST SP800-38A
Authenticated encryption NIST SP800-38C
AES 128, 256 GCM, CCM
or decryption NIST SP800-38D
Cipher-based message
NIST SP800-38D 128, 256 GMAC
authentication code
Checksum SHA-1 N/A Digest 160-bit
FIPS PUB 180-4 SHA-224, SHA-256
Cryptographic hash SHA-2 -
SHA2-384, SHA2-512
Keyed-hashing for FIPS PUB 198-1 Short, long

HMAC -
message authentication IETF RFC 2104 (>64 bytes)
Encryption/decryption IETF RFC 8017

RSA Up to 4160 RSAES-OAEP
key-pair generation(4) NIST SP800-56B
IETF RFC 8017
RSA Up to 4160 PKCS1-v1_5, PSS
FIPS PUB 186-4
(4)
Signature with hashing
ANSI X9.62
Signature verification
ECDSA IETF RFC 7027
Up to 640 -
FIPS PUB 186-4
Key agreement ECDH ANSI X9.42
1. Certifiable using STMicroelectronics reviewed documents.
2. Random numbers distribution to SAES and PKA using a dedicated hardware bus.
3. ECB and CBC chaining modes protected against side-channel and timing attacks in SAES.
4. Private key cryptography protected against side-channel and timing attacks.
Note: Binary curves, Edwards curves and Curve25519 are not supported by the PKA.
58/320 DS14359 Rev 2

3.32 Secure AES (SAES)

The devices provide an on-chip hardware AES encryption and decryption engine, which
implements countermeasures and mitigations against power and electromagnetic side-
channel attacks.
Clocked by the AHB bus clock, the SAES offers very good performance for a DPA resistant
hardware accelerator. The SAES engine supports 128-bit or 256-bit keys in electronic code
book (ECB), cipher block chaining (CBC), (CTR), (GCM), (CCM), (GMAC) modes.
The SAES can be used for extra-secure on-chip storage for sensitive information.
For more information, refer to the Secure AES coprocessor (SAES) section in reference
manual RM0477.
3.33 Hash processor (HASH)

The hash processor is a fully compliant implementation of the secure hash algorithm
(SHA-1, SHA-2 family) and the HMAC (keyed-hash message authentication code)
algorithm. HMAC is suitable for applications requiring message authentication.
The hash processor computes FIPS (Federal Information Processing Standards) approved
digests of length of 160, 224, 256 bits, for messages of any length less than 264 bits (for
SHA-1, SHA-224 and SHA-256) or less than 2128 bits (for SHA-384, SHA-512).
3.34 Public key accelerator (PKA)

The PKA (public key accelerator) is intended for the computation of cryptographic public key
primitives, specifically those related to RSA, Diffie-Hellmann or ECC (elliptic curve
cryptography) over GF(p) (Galois fields). To achieve high performance at a reasonable cost,
these operations are executed in the Montgomery domain.
For a given operation, all needed computations are performed within the accelerator, so no
further hardware/software elaboration is needed to process the inputs or the outputs.
When manipulating secrets, the PKA incorporates a protection against side-channel attacks
(SCA), including differential power analysis (DPA), certified SESIP and PSA security
assurance level 3.
3.35 Memory cipher engine (MCE)

Memory cipher engine (MCE) defines, in a given address space, multiple regions with
specific security setup (encryption, privilege, write). All system bus traffic going through an
encrypted region is managed on-the-fly by the MCE, automatically decrypting reads and
encrypting writes if authorized.
Multiple ciphering option (stream, block, fast block) are available to offer the best security /
performance trade-off.
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3.35.1 Memory cipher features

the MCE embed a system bus in-line encryption (for writes) and decryption (for reads),
based on embedded firewall programming. up to Four encryption modes per region
(maximum 4 regions): no encryption (bypass mode), stream cipher, block cipher and fast
block cipher modes.
The Start and end of regions are defined with 4 kBytes granularity
The block mode with AES cipher is compatible with ECB mode specified in NIST FIPS
publication 197 Advanced encryption standard (AES) (normal or fast).
The stream mode with AES cipher is compliant with CTR mode specified in NIST SP800-
38A Recommendation for Block Cipher Modes of Operation.
It Includes a leakage resilient mode of operation as defense against side channel attacks
(SCA).
When encryption is enabled, support for AXI-64bit INCRx (x=1 to 8) and WRAPx (x=4) write
transactions
3.35.2 Memory cipher implementation
Table 12. MCE implementation

MCE features MCE1 MCE2/3
Number of regions 4
Cipher engines AES x 2 12 rounds Noekeon x2
Derive key function normal, fast
Master key 2
Chaining modes (encryption mode) block, stream block
Cipher context(s) 2 0
Note: When MCE is used in conjunction with XSPI it is mandatory to access the flash memory
using the memory map mode of the flash memory controller.
3.36 Timers and watchdogs

The devices include one advanced-control timers, eleven general-purpose timers, two basic
timers, five low-power timers, two watchdogs and a SysTick timer.
All timer counters can be frozen in Debug mode.
Table 13 compares the features of the advanced-control, general-purpose and basic timers.
60/320 DS14359 Rev 2

Table 13. Timer feature comparison

Capture/ Comple-
Counter Counter Prescaler DMA request
Timer type Timer compare mentary
resolution type factor generation
channels output
Any integer
Advanced- Up, Down,
TIM1 16-bit between 1 and Yes 4 4
control Up/down
65536
Any integer
TIM2,TIM3, Up, Down,
32-bit between 1 and Yes 4 No
TIM4 TIM5 Up/down
65536
Any integer
TIM9,TIM12 16-bit Up between 1 and No 2 No
65536
Any integer
General
TIM13,TIM14 16-bit Up between 1 and No 1 No
purpose
65536
Any integer
TIM15 16-bit Up between 1 and Yes 2 1
65536
Any integer
TIM16, TIM17 16-bit Up between 1 and Yes 1 1
65536
Any integer
Basic TIM6, TIM7 16-bit Up between 1 and Yes 0 No
65536
LPTIM1,
LPTIM2, Up Yes 2 No
Low-power LPTIM3 1, 2, 4, 8, 16,
16-bit
timer 32, 64, 128
LPTIM4,
Up No 0 No
LPTIM5
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3.36.1 Advanced-control timers (TIM1)

The advanced-control timers (TIM1) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability (0 -
100%)
• One-pulse mode output
In Debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled in order to turn off any power switches driven by these outputs.
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 support independent DMA request generation.
3.36.2 General-purpose timers (TIMx)

There are up to elven synchronizable general-purpose timers embedded in the
STM32H7Sxx8 devices (see Table 13: Timer feature comparison for differences).
• TIM2, TIM3, TIM4, TIM5
They are full-featured general-purpose timers with 32-bit auto-reload up/downcounter
and 16-bit prescaler.
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other general-
purpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in Debug mode.
All have independent DMA request generation and support quadrature encoders.
They are capable of handling quadrature (incremental) encoder signals and the digital
outputs from 1 to 3 hall-effect sensors.
• TIM9, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13, TIM14, TIM16 and TIM17 feature one independent channel,
TIM9, TIM12 and TIM15 have two independent channels for input capture/output
compare, PWM or one-pulse mode output. They can be synchronized with the TIM2,
TIM3, TIM4, TIM5 full-featured general-purpose timers or used as simple time bases.
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3.36.3 Basic timers TIM6 and TIM7

These timers are mainly used for waveform generation. They can also be used as a generic
16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
3.36.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)

The devices embed five low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to
wake up the system from Stop mode.
3.36.5 Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 4-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
3.36.6 Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.36.7 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
• A 24-bit downcounter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source.
3.37 Real-time clock (RTC)

The RTC provides an automatic wakeup to manage all low-power modes.
The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-
of-day clock/calendar with programmable alarm interrupts.
The RTC includes also a periodic programmable wakeup flag with interrupt capability.
After backup domain reset, all RTC registers are protected against possible parasitic write
accesses except the one’s configured in privilege mode.
As long as the supply voltage remains in the operating range, the RTC never stops,
regardless of the device status (Run mode, Low-power mode or under reset).
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The RTC unit main features are the following:

• Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of
week), date (day of month), month, and year.
• Daylight saving compensation programmable by software.
• Programmable alarm with interrupt function. The alarm can be triggered by any
combination of the calendar fields.
• Automatic wakeup unit generating a periodic flag that triggers an automatic wakeup
interrupt.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Accurate synchronization with an external clock using the subsecond shift feature.
• Digital calibration circuit (periodic counter correction): 0.95 ppm accuracy, obtained in a
calibration window of several seconds
• Timestamp function for event saving
• Maskable interrupts/events:
– Alarm A
– Alarm B
– Wakeup interrupt
– Timestamp
3.38 Tamper and backup registers (TAMP)

32 x 32-bit backup registers are retained in all low-power modes and also in VBAT mode.
They can be used to store sensitive data as their content is protected by an tamper
detection circuit. 8 tamper pins (8 input or 8 outputs) and 12 internal tampers are available
for anti-tamper detection. The 8 external tamper pins can be configured for edge detection,
edge and level, level detection with filtering, or up to 4 active tamper which increases the
security level by auto checking that the tamper pins are not externally opened or shorted.
TAMP main features
• 32 backup registers:
– the backup registers (TAMP_BKPxR) are implemented in the RTC domain that
remains powered-on by VBAT when the VDD power is switched off.
• 8 external tamper detection events.
– Each external event can be configured to be active (4 Tamper) or passive (8
Tamper).
– External passive tampers with configurable filter and internal pull-up.
• 11 internal tamper events.
• Any tamper detection can generate a RTC timestamp event.
• Any tamper detection erases the backup registers.
• Monotonic counter.
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3.39 Inter-integrated circuit interface (I2C)

The STM32H7Sxx8 embeds three I2C interfaces.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bit rate up to 100 kbit/s
– Fast-mode (Fm), with a bit rate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System management bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power system management protocol (PMBusTM) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
• Wakeup from Stop mode on address match(a)
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
3.40 Improved inter-integrated circuit (I3C)

The I3C interface handles communication between this device and others, such as sensors
and host processor(s) that are connected to an I3C bus.
• The I3C peripheral implements all the required features of the MIPI I3C specification
v1.1. It can control all I3C bus-specific sequencing, protocol, arbitration, and timing. It
acts as a controller (formerly known as master) or as a target (formerly known as
slave).
• The I3C peripheral, acting as controller, improves the features of the I2C interface,
while preserving some backward compatibility; it allows an I2C target to operate on an
I3C bus in legacy I2C fast-mode (Fm) or legacy I2C fast-mode plus (Fm+), provided that
the latter does not perform clock stretching.
• The I3C peripheral can be used with DMA in order to offload the CPU.
Refer to reference manual RM0477 for full details of the I3C controller features versus MIPI
v1.1.
a. Under characterization.
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3.41 Universal synchronous/asynchronous receiver transmitter

(USART/UART)
and low-power universal asynchronous receiver transmitter
(LPUART)
The STM32H7Sxx8 has three embedded universal synchronous receiver transmitters
(USART1, USART2 and USART3) and four universal asynchronous receiver transmitters
(UART4, UART5, UART7 and UART8) and one low-power universal asynchronous receiver
transmitter (LPUART1). Refer to Table 14 for a summary of USARTx UARTx and LPUART
features.
Table 14. USART, UART and LPUART features
Basic feature Low-power
Modes/features(1) Full feature set
set feature set
Hardware flow control for modem X X X

Continuous communication using DMA X X X
Multiprocessor communication X X X
Synchronous mode (master/slave) X - -
Smartcard mode X - -
Single-wire half-duplex communication X X X
IrDA SIR ENDEC block X X -
LIN mode X X -
Dual clock domain X X X
Receiver timeout interrupt X X -
Modbus communication X X -
Auto baud rate detection X X -
Driver Enable X X X
USART data length 7, 8 and 9 bits
Tx/Rx FIFO X X X
Tx/Rx FIFO size (bytes) 16
Wake-up from low-power mode X(2) X(2) X(2)
1. “X” = supported, “-” = not supported.
2. Wake-up supported from Stop mode.
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3.41.1 Universal synchronous/asynchronous receiver transmitter

(USART/UART)
The USART offers a flexible means to perform full-duplex data exchange with external
equipment requiring an industry standard NRZ asynchronous serial data format. A very wide
range of baud rates can be achieved through a fractional baud rate generator.
The USART supports both synchronous one-way and half-duplex single-wire
communications, as well as LIN (local interconnection network), smartcard protocol, IrDA
(infrared data association) SIR ENDEC specifications, and modem operations (CTS/RTS).
Multiprocessor communications are also supported.
High-speed data communications are possible by using the DMA (direct memory access)
for multibuffer configuration.
Table 15. Instance implementation on STM32H7Sxx8

Instance STM32H7Sxx8
USART1 Full
USART2 Full
USART3 Full
UART4 Basic
UART5 Basic
UART7 Basic
UART8 Basic
LPUART1 Low-power
3.41.2 Low-power universal asynchronous receiver transmitter (LPUART)

The LPUART is an UART which enables bidirectional UART communications with a limited
power consumption. Only 32.768 kHz LSE clock is required to enable UART
communications up to 9600 baud. Higher baud rates can be reached when the LPUART is
clocked by clock sources different from the LSE clock.
Even when the microcontroller is in low-power mode, the LPUART can wait for an incoming
UART frame while having an extremely low energy consumption. The LPUART includes all
necessary hardware support to make asynchronous serial communications possible with
minimum power consumption.
It supports half-duplex single-wire communications and modem operations (CTS/RTS). It
also supports multiprocessor communications.
DMA (direct memory access) can be used for data transmission/reception.
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3.42 Serial peripheral interface (SPI)/inter- integrated sound

interfaces (I2S)
3.42.1 Introduction
The device embed six serial peripheral interfaces (SPI) that can be used to communicate
with external devices while using the specific synchronous protocol. The SPI protocol
supports half-duplex, full-duplex and simplex synchronous, serial communication with
external devices.
The interface can be configured as master or slave and can operate in multi-slave or multi-
master configurations. The device configured as master provides communication clock
(SCK) to the slave device. The slave select (SS) and ready (RDY) signals can be applied
optionally just to setup communication with concrete slave and to assure it handles the data
flow properly. The Motorola® data format is used by default, but some other specific modes
are supported as well.
3.42.2 SPI main features

• Full-duplex synchronous transfers on three lines
• Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
• From 4-bit up to 32-bit data size selection or fixed to multiply of 8-bit
• Multi master or multi slave mode capability
• Dual clock domain, the peripheral kernel clock is independent of APB bus clock
• Baud rate prescaler up to kernel frequency/2 or bypass from RCC in Master mode
• Protection of configuration and setting
• Hardware or software management of SS for both master and slave
• Adjustable minimum delays between data and between SS and data flow
• Configurable SS signal polarity and timing, MISO x MOSI swap capability
• Programmable clock polarity and phase
• Programmable data order with MSB-first or LSB-first shifting
• Programmable number of data within a transaction to control SS and CRC
• Dedicated transmission and reception flags with interrupt capability
• SPI Motorola and TI formats support
• Hardware CRC feature can verify integrity of the communication at the end of
transaction by:
– Adding CRC value in Tx mode
– Automatic CRC error checking for Rx mode
• Error detection with interrupt capability in case of data overrun, CRC error, data
underrun, the mode fault and frame error at dependency on the operating mode
• Two multiply of 8-bit embedded Rx and Tx FIFOs (FIFO size depends on instance)
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• Configurable FIFO thresholds (data packing)

• Capability to handle data streams by system DMA controller
• Configurable behavior at slave underrun condition (support of cascaded circular
buffers)
• optional status pin RDY signalizing the slave device ready to handle the data flow
3.42.3 SPI implementation

Table 16 describes the SPI implementation. The instances are applied either with a full set
or a limited set of features.
Table 16. SPI features

SPI2S1, SPI2S2, SPI2S3 and SPI2S6 SPI4 and SPI5
SPI feature
(full feature set instances) (full feature set instances)
Data and CRC size Configurable from 4 to 32- bit Configurable from 4 to 16- bit
CRC polynomial length configurable from 5 CRC polynomial length configurable from 5
CRC computation
to 33- bit to 17- bit
Size of FIFOs 16x8-bit 8x8-bit
Number of data control
Up to 65536 Up to 65536
(TSIZE)
I2S feature Yes No
Autonomous in Stop
modes with wakeup No No
capability
Autonomous in LP-Stop
and Standby modes No No
with wakeup capability
Note: For detailed information about instances capabilities to exit from Stop and Standby modes
refer to SPI wakeup and interrupt requests in reference manual RM0477.
3.43 Serial audio interfaces (SAI)

The devices embed two SAI. Refer to Table 17: STM32H7Sxx8 SAI features for the features
implementation. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
3.43.1 SAI main features

The devices embed 2 SAIs that allow the design of many stereo or mono audio protocols
such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An SPDIF output is available
when the audio block is configured as a transmitter. To bring this level of flexibility and
reconfigurability, the SAI contains two independent audio sub-blocks. Each block has it own
clock generator and I/O line controller.
Audio sampling frequencies up to 192 kHz are supported.
In addition, up to 4 microphones can be supported thanks to an embedded PDM interface.
DS14359 Rev 2 69/320

75
The SAI can work in master or slave configuration. The audio sub-blocks can be either
receiver or transmitter and can work synchronously or asynchronously (with respect to the
other one). The SAI can be connected with other SAIs to work synchronously.
3.43.2 SAI implementation
Table 17. STM32H7Sxx8 SAI features (1)

SAI features SAI1 SAI2
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X

FIFO size 8 words 8 words
SPDIF X X
(2)
PDM X -
1. ‘X’ = supported, ‘-’ = not supported.
2. Only signals D[3:1], and CK[2:1] are available.
3.44 SPDIFRX receiver interface (SPDIFRX)

The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main SPDIFRX features are the following:
• Up to 4 inputs available
• Automatic symbol rate detection
• Maximum symbol rate: 12.288 MHz
• Stereo stream from 32 to 192 kHz supported
• Supports Audio IEC-60958 and IEC-61937, consumer applications
• Parity bit management
• Communication using DMA for audio samples
• Communication using DMA for control and user channel information
• Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal is available, the SPDIFRX resamples the incoming signal, decode the
Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that is used to compute the exact sample rate for clock drift algorithms.
70/320 DS14359 Rev 2

3.45 Management data input/output (MDIO) slaves

The devices embed an MDIO slave interface it includes the following features:
• 32 MDIO register addresses, each of which is managed using separate input and
output data registers:
– 32 x 16-bit firmware read/write, MDIO read-only output data registers
– 32 x 16-bit firmware read-only, MDIO write-only input data registers
• Configurable slave (port) address
• Independently maskable interrupts/events:
– MDIO register write
– MDIO register read
– MDIO protocol error
• Able to operate in and wake up from STOP mode
3.46 Secure digital input/output MultiMediaCard interface

(SDMMC)
Two secure digital input/output MultiMediaCard interfaces (SDMMC) provide an interface
between the AHB bus and SD memory cards, SDIO devices and e.MMC devices.
The SDMMC features include the following:
• Full compliance with MultiMediaCard System Specification Version 5.1.
Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit.
(HS200 speed limited by maximum allowed I/O speed, HS400 is not supported)
• Full compatibility with previous versions of MultiMediaCards (backward compatibility).
• Full compliance with SD memory card specifications version 6.0.
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported).
• Full compliance with SDIO card specification version 4.0.
Card support for two different databus modes: 1-bit (default) and 4-bit.
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported).
• Data transfer up to 208 Mbyte/s for the 8-bit mode. (depending maximum allowed I/O
speed).
• Data and command output enable signals to control external bidirectional drivers.
• The SDMMC host interface embeds a dedicated DMA controller allowing high-speed
transfers between the interface and the SRAM.
• IDMA linked list support
Each SDMMC is coupled with a delay block (DLYB) allowing support of an external data
frequency above 100 MHz.
DS14359 Rev 2 71/320

75
3.47 Controller area network (FDCAN1, FDCAN2)

The controller area network (CAN) subsystem consists of two CAN module, a shared
message RAM memory and a configuration block.
The modules (FDCAN) are compliant with ISO 11898-1: 2015 (CAN protocol specification
version 2.0 part A, B) and CAN FD protocol specification version 1.0.
A 2 Kbyte message RAM implements filters, receives FIFOs, transmits event FIFOs and
transmits FIFOs.
The FDCAN main features are:
• Conform with CAN protocol version 2.0 part A, B and ISO 11898-1: 2015, -4
• CAN FD with maximum 64 data bytes supported
• CAN error logging
• AUTOSAR and J1939 support
• Improved acceptance filtering
• 2 receive FIFOs of three payloads each (up to 64 bytes per payload)
• Separate signaling on reception of high priority messages
• Transmit FIFO / queue of three payload (up to 64 bytes per payload)
• Configurable transmit Event FIFO
• Programmable loop-back test mode
• Maskable module interrupts
• Two clock domains: APB bus interface and CAN core kernel clock
• Power-down support
3.48 Universal serial bus on-the-go full-speed (OTG_FS)

The main features support both host-mode and device-mode.It is compliant with the
Universal Serial Bus Specification Rev 2.0. it includes an on-chip full-speed PHY.
It includes full support (PHY) for the optional On-The-Go (OTG) protocol detailed in the On-
The-Go Supplement Rev 2.0 specification. it support the A-B device identification (ID line) .It
supports OTG monitoring of VBUS levels with internal comparators and the SOF pulse on
PAD ALT function.
• SOF pulse internal connection to timer (TIM2 and.TIM5)
It includes power saving features such as system stop during USB suspend, switch-off of
clock domains internal to the digital core, PHY and DFIFO power management. it includes a
dedicated RAM of 1.25 Kbytes with advanced FIFO control as configurable partitioning of
RAM space into different FIFOs for flexible and efficient use of RAM
It supports charging port detection as described in Battery Charging Specification Revision
1.2.
Table 18. OTG_FS speeds supported

Mode HS (480 Mbit/s) FS (12 Mbit/s) LS (1.5 Mbit/s)
Host mode - X X
Device mode - X -
72/320 DS14359 Rev 2

3.49 Universal serial bus on-the-go high-speed (OTG_HS)

The devices embed one USB High Speed host/device (up to 480 Mbit/s) with one physical
port. OTG_HS supports both low-speed, full-speed as well as high-speed modes. It
integrates a physical interface (PHY) which can be used for either low-speed (1.5 Mbit/s),
full-speed (12 Mbit/s) or high-speed operation (480 Mbit/s). it includes the SOF pulse on
PAD ALT function.
• SOF pulse internal connection to timer (TIM2 and TIM5)
It includes power saving features such as system stop during USB suspend, switch-off of
clock domains internal to the digital core, PHY and DFIFO power management. it includes a
dedicated RAM of 1.25 Kbytes with advanced FIFO control as configurable partitioning of
RAM space into different FIFOs for flexible and efficient use of RAM
It supports charging port detection as described in Battery Charging Specification Revision
1.2.
The OTG_HS uses a dedicaded digital power supply, DVDD. This should be connected to
VCAP when used, and to GND when not used.
Table 19. OTG_HS speeds supported

Mode HS (480 Mbit/s) FS (12 Mbit/s) LS (1.5 Mbit/s)
Host mode X X X
Device mode X X -
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75
3.50 Ethernet MAC interface with dedicated DMA controller (ETH)

The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, and so on). The PHY is connected to the device MII port using 21 signals for MII or 12
signals for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
The devices include the following features:
• Supports 10 and 100 Mbit/s rates
• Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
• Tagged MAC frame support (VLAN support)
• Half-duplex (CSMA/CD) and full-duplex operation
• MAC control sublayer (control frames) support
• 32-bit CRC generation and removal
• Several address filtering modes for physical and multicast address (multicast and
group addresses)
• 32-bit status code for each transmitted or received frame
• Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
• Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
• Triggers interrupt when system time becomes greater than target time
3.51 USB Type-C power delivery controller (UCPD)

The devices embed one controllers compliant with USB Type-C Rev.2.1 and USB Power
Delivery Rev. 3.1 specifications.
The controllers use specific I/Os supporting the USB Type-C and USB Power Delivery
requirements, featuring the USB Type-C pull-up (Rp, current source) and pull-down (Rd,
resistors) and the USB Power Delivery message transmission and reception
The digital controller handles embed the USB Type-C level detection with de-bounce,
generating interrupts and FRS detection, generating an interrupt
The interface offers low-power operation compatible with Stop mode, maintaining the
capacity to detect incoming USB Power Delivery messages and FRS signaling.
3.52 High-definition multimedia interface - consumer electronics

control (HDMI-CEC)
The device embeds a HDMI-CEC controller that provides hardware support for the
consumer electronics control (CEC) protocol (supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
74/320 DS14359 Rev 2

overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wake up the MCU from Stop mode on data reception.
3.53 Development support
3.53.1 Serial-wire/JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded and is a combined JTAG and serial-wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using two pins only instead of five required by the JTAG (JTAG pins can
be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.53.2 Embedded Trace Macrocell

The Arm Embedded Trace Macrocell (ETM) provides a greater visibility of the instruction
and data flow inside the CPU core by streaming compressed data at a very high rate from
the devices through a small number of ETM pins to an external hardware trace port analyzer
(TPA) device.
Real-time instruction and data flow activity be recorded and then formatted for display on
the host computer that runs the debugger software. TPA hardware is commercially available
from common development tool vendors.
The ETM operates with third party debugger software tools.
DS14359 Rev 2 75/320

75
Pinouts, pin description and alternate functions STM32H7Sxx8
4 Pinouts, pin description and alternate functions
Figure 6. TFBGA100 SMPS pinout(a)
1 2 3 4 5 6 7 8 9 10
A PB8 PB6 PB3 BOOT0 PM14 PM12 PM9 PM6 PM8 PM2
PC14-
B PB9 PB7 PB4 PM13 PM11 DVDD PM5 PM3 PM1
OSC32_IN
PC15-
C VSS VBAT VCAP4 VSS VDD50USB VSS PM0 PA14 PA15
OSC32_OUT
D VDDSMPS VSSSMPS PC13 PB5 VDD VSSUSB VDD33USB VCAP3 PA12 PA13
E VFBSMPS VLXSMPS VDD VSS VDDLDO VDDLDO VDD PA8 PA10 PA11
PH1-
F PH0-OSC_IN NRST VREFM PB0 VSS VDDLDO VSS PB14 PA9
OSC_OUT
G PC0 PA1 VSSA VDD PB2 VDDXSPI1 VDD VCAP2 PB12 PB15
H PC1 VDDA PA5 VSS VDDXSPI1 VSS VDDXSPI1 PO0 PB10 PB13
J VREFP PA2 PA7 PO1 PP2 PO5 PP5 PP6 PP7 PB11
K PA0 PA4 PA6 PB1 PP4 PP3 PO4 PP0 PO2 PP1
MSv55547V3
a. The above figure shows the package top view.
76/320 DS14359 Rev 2

STM32H7Sxx8 Pinouts, pin description and alternate functions
Figure 7. UFBGA144 SMPS pinout(a)
1 2 3 4 5 6 7 8 9 10 11 12
VDD33U VDD50U
A VSS PB8 PB6 PB5 PD7 BOOT0 PM11 PM9 PM6
SB SB
VSS
B VBAT PC13 PE1 PE0 PB3 PD5 PM12 PM8 PM5 PM2 PM3 PD4
PC14- PC15-
C OSC32_I OSC32_ PB9 PE2 PB4 PD6 PM14 DVDD VSS PM1 PD2 PC12
N OUT
D PE5 VSS PE3 PB7 VSS VDD VSS VSSUSB VDD PD3 PC10 PA15
VSSSMP
E S
PE6 PE4 VDD VCAP4 PM13 VSS PM0 PC11 PA14 PA12 PA13
VLXSMP VDDSMP VFBSMP

F S S S
NRST VSS VDDLDO VDDLDO VCAP3 VDD PA8 PA10 PA11
PH0-
G VSS
OSC_IN
PC0 VDD PC1 VDDLDO VDDLDO VSS PC7 PC9 PC8 PA9
PH1-
H OSC_OU PC3 VSSA VSS VREFM VCAP1 VSS VCAP2 PB14 PB12 PD14 PC6
T
J PC2 PA1 VDDA PA5 VDD PO1 PO0 PD8 VDD PB10 PB13 PB15
VDDXSPI VDDXSPI VDDXSPI

K PA0 PA3 VREFP PA7
1
VSS
1
VSS
1
VSS PD12 PB11
L PA2 PA4 PC4 PB0 PB2 PP2 PO5 PP0 PO2 PP1 PD11 PD13
M VSS PA6 PC5 PB1 PP4 PP3 PO4 PP5 PP6 PP7 PD10 VSS
MSv55548V3
DS14359 Rev 2 77/320

91
1 2 3 4 5 6 7 8 9 10 11 12 13
A PB8 PB6 PE0 PB3 PF1 PD7 PD5 PM11 PM6 PM5 PM2 PM3 PG1
VDD50U
B VBAT PB7 PE2 PB5 PF2 PD6 PM14 PM12 VSS
SB
PM1 PD4 PE13
PC15- PC14-
VDD33U
C OSC32_ OSC32_I VDD VSS VDD VSS PM9
SB
VSS VDD PD3 PE12 PE11
OUT N
VDDSMP VSSSMP
D S S
PE3 PB9 PE1 PF0 PM13 VSSUSB PM8 PG0 VSS PD2 PD1
VFBSMP VLXSMP
E S S
PE4 PC13 VCAP4 PB4 BOOT0 DVDD PM0 PD0 VDD PC11 PC12
F PF5 PF6 VSS PE6 PE5 VDDLDO VSS VDDLDO VCAP3 PA10 VSS PA14 PC10
PH0-
G PF8
OSC_IN
VDD PF7 PF9 VSS VSS VSS PC9 PC7 VDD PA12 PA15
PH1-
H OSC_OU PC2 PC0 NRST PC1 VDDLDO VSS VDDLDO VCAP2 PC6 VSS PA8 PA13
T
J PC3 VSS VREFM VSSA PA3 VCAP1 PE9 PB12 PB14 PD15 PC8 PA9 PA11
VDDXSPI
K PA0 VDD VREFP VDDA PB0 PE7 PO1
1
PO0 VDD VSS PB15 PD14
VDDXSPI VDDXSPI
L PA1 PA4 PA5 PC5 VDD VSS
1
VSS
1
VSS PD12 PB10 PB13
M PA2 PA7 PB1 PF11 PE10 PP2 PO5 PP5 PP6 PP7 PD10 PD13 PB11
MSv55553V3
N PA6 PC4 PB2 PE8 PP4 PP3 PO4 PP0 PO2 PP1 PD8 PD9 PD11
78/320 DS14359 Rev 2

Figure 9. UFBGA144 GFx with SMPS pinout(a)
1 2 3 4 5 6 7 8 9 10 11 12
VDD50U
A VSS PB8 PB6 PD7 PD5 PM12
SB
PD4 PC10 PA15 PA9 VSS
VDD33U
B VBAT PB9 PE1 PB5 PD6 PM11
SB
PD3 PD0 PA13 PA12 PC8
PC14- PC15-
C OSC32_I OSC32_ PC13 PB7 PB3 BOOT0 VSS PG1 PD2 PA14 PA8 PC6
N OUT
D PE5 VSS PE3 VDD PE2 PM13 VDD PG0 PC11 PA10 PC9 PC7
VSSSMP VDDXSPI
E S
PE6 PE4 VSS VCAP4 PB4 PM14 VSS PA11
2
PN3 PN11
VLXSMP VDDSMP VFBSMP

F S S S
VDD VSS VDDLDO VDDLDO VCAP3 VDD VSS PN0 PN10
PH0- VDDXSPI
G VSS
OSC_IN
PC0 NRST VSS VDDLDO VDDLDO VSS PN1
2
PN2 PN9
PH1-
H OSC_OU PC3 VDDA VREFM PC1 VCAP1 VSS VCAP2 VDD VSS PN7 PN6
T
VDDXSPI
J PC2 PA0 VSSA VDD VSS PB1 PO1 PO0 PB10
2
PN4 PN5
VDDXSPI VDDXSPI VDDXSPI

K PA1 PA3 VREFP PC4
1
VSS
1
VSS
1
PB12 PB14 PN8
L PA2 PA5 PA7 PB0 PB2 PP2 PO5 PP0 PO2 PP1 PB15 PB13
M VSS PA4 PA6 PC5 PP4 PP3 PO4 PP5 PP6 PP7 PB11 VSS
MSv55543V3
a. The above figure shows the package top view
DS14359 Rev 2 79/320

91
Figure 10. UFBGA169 GFx with SMPS pinout(a)
1 2 3 4 5 6 7 8 9 10 11 12 13
VDD50U
A PB8 PB6 PE0 PB3 PF1 PD7 PD5 PM11
SB
PE13 PE11 PC10 PA15
B VBAT PB7 PE2 PB5 PF2 PG2 PD6 PM12 PG1 PD4 PD1 PD0 PA13
PC15- PC14-
VDD33U
C OSC32_ OSC32_I VDD VSS VDD VSS PM14
SB
VSS VDD PC12 PA14 PA11
OUT N
VDDSMP VSSSMP
D S S
PE3 PB9 PE1 PF0 PM13 PG0 PD3 PE14 VSS PA12 PA9
VFBSMP VLXSMP
E S S
PE4 PC13 VCAP4 PB4 BOOT0 PE12 PD2 PC11 VDD PA10 PA8
F PF8 PF6 VSS PE6 PE5 VDDLDO VSS VDDLDO VCAP3 PC9 VSS PC8 PC6
PH1-
PH0- VDDXSPI
G OSC_OU
OSC_IN
VDD PF7 PF9 VSS VSS VSS PC7 PN1
2
PN11 PN3
T
VDDXSPI
H PC3 PC2 PC0 NRST PC1 VDDLDO VSS VDDLDO VCAP2
2
VSS PN10 PN0
VDDXSPI
J PA0 VSS VREFM VSSA PA3 VCAP1 PD8 PB12 PB14 PN12
2
PN9 PN2
VDDXSPI
K PA2 VDD VREFP VDDA PB0 PE7 PO1
1
PO0 VDD VSS PN7 PN6
VDDXSPI VDDXSPI
L PA1 PA4 PA5 PB2 VDD VSS
1
VSS
1
VSS PB10 PN4 PN5
M PA6 PA7 PB1 PE8 PE9 PP2 PO5 PP5 PP6 PP7 PD10 PB13 PN8
MSv55554V3
N PC4 PC5 PF11 PE10 PP4 PP3 PO4 PP0 PO2 PP1 PD9 PB11 PB15
80/320 DS14359 Rev 2


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A VSS PB6 PB5 PF3 PF1 PD7 PD5 PM12 PM14 PM6 PM8 PM3 PD4 PE15 VSS
VDD50US
B PB8 PE1 PE2 PB3 PF4 PF0 PD6 PM11 PM9 PM5
B
PM1 PG0 PE13 PE11
C VBAT PB9 PB7 PE0 PB4 PF2 BOOT0 PM13 DVDD VSSUSB PM2 PM0 PE14 PE12 PD1
PC14-
VDD33US
D OSC32_I VSS PC13 VDD VSS VSS VDD VSS
B
VDD VSS PD3 PD2 PD0 PC12
N
PC15-
E VSS OSC32_O VSS VSS VSS PC11 PC10 PA15
UT
F PE5 PE3 PE4 VSS VCAP4 VSS VSS VSS VSS VDD PA14 PA12 PA13
VSSSMP
G S
VLXSMPS PE6 VDD VSS VDDLDO VSS VDDLDO VCAP3 VSS PA10 PA8 PA11
VFBSMP VDDSMP
H S S
PF5 VSS VSS VSS VDDLDO VSS VSS VSS VSS PC9 PA9
J PF6 PF8 PF7 VSS VSS VDDLDO VSS VDDLDO VSS VDD PC6 PC7 PC8
VDDXSPI
K PF10 PF9 VSS VDD VSS VCAP1 VSS
1
VCAP2 VSS PD14 PD15 PB15
PH0-
L VSS
OSC_IN
VSS VSSA VDD PB12 PB14 PB13
PH1-
VDDXSPI VDDXSPI
M OSC_OU NRST VREFP VDDA PA4 VDD VSS
1
VSS
1
VSS VDD PD12 PB10 PB11
T
N PC0 PC3 VREFM PA3 PA7 PB0 PF12 PE9 PE10 VSS PP5 PD8 PD10 PD11 PD13
P PC1 PC2 PA1 PA5 PC4 PB2 PF13 PE7 PO1 PP2 PO5 PP6 PP7 PO0 PD9
R VSS PA0 PA2 PA6 PC5 PB1 PF11 PE8 PP4 PP3 PO4 PP0 PO2 PP1 VSS
MSv55550V3
DS14359 Rev 2 81/320

91
Figure 12. UFBGA176 SMPS GFx pinout(a)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A VSS PB6 PB5 PF3 PF1 PG3 PD7 PD5 PM14 PM11 PD4 PE15 PE11 PD1 VSS
B PB8 PE1 PE2 PB3 PF4 PF0 PD6 BOOT0 PM13 PM12 PG0 PE13 PE12 PD0 PC12
VDD50US
C VBAT PB9 PB7 PE0 PB4 PF2 PG2 VSS
B
PG1 PD3 PE14 PD2 PC11 PA15
PC14-
VDD33US
D OSC32_I VSS PC13 VDD VSS VSS VDD VSS
B
VDD VSS VSS PC10 PA13 PA11
N
PC15-
E VSS OSC32_O VSS VSS VSS PA14 PA12 PA9
UT
F PE5 PE3 PE4 VSS VCAP4 VSS VSS VSS VSS VDD PA10 PA8 PC8
VSSSMP
G S
VLXSMPS PE6 VDD VSS VDDLDO VSS VDDLDO VCAP3 VSS PC9 PC7 PC6
VFBSMP VDDSMP VDDXSPI

H S S
PF5 VSS VSS VSS VDDLDO VSS
2
VSS VSS PN1 PN3
VDDXSPI
J PF6 PF8 PF7 VSS VSS VDDLDO VSS VDDLDO VSSUSB 2
PN10 PN11 PN0
VDDXSPI
K PF10 PF9 DVDD VDD VSS VCAP1 VSS
1
VCAP2 VSS PB14 PN9 PN2
PH0- VDDXSPI
L VSS
OSC_IN
VSS VSSA
2
PB12 PN7 PN6
PH1-
VDDXSPI VDDXSPI
M OSC_OU NRST VREFP VDDA PA4 VDD VSS
1
VSS
1
VSS VDD PB15 PN4 PN5
T
N PC0 PC3 VREFM PA3 PA7 PB0 PF12 PE9 PE10 VSS PP5 PD8 PB10 PB13 PN8
P PC1 PC2 PA1 PA5 PC4 PB2 PF13 PE7 PO1 PP2 PO5 PP6 PP7 PO0 PB11
R VSS PA0 PA2 PA6 PC5 PB1 PF11 PE8 PP4 PP3 PO4 PP0 PO2 PP1 VSS
MSv55544V3
82/320 DS14359 Rev 2

Figure 13. LQFP176 SMPS pinout(a)
VDD33USB
VDD50USB
VDDLDO
VSSUSB
BOOT0
VCAP4
DVDD
PM13
PM14
PM12
PM11
VDD
VDD
PM9
PM8
VDD
VDD
PM6
PM5
PM3
PM2
PM1
PM0
PD7
PD6
PD5
VSS
PB9
PB8
PB7
PB6
PE2
PE1
PE0
PD4
PD3
PB5
PB4
PB3
PF4
PF3
PF2
PF1
PF0
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VBAT 1 132 VSS
PC13 2 131 PE15
PC14-OSC32_IN 3 130 PE14
PC15-OSC32_OUT 4 129 PE13
VDD 5 128 PE12
VSS 6 127 PE11
PE3 7 126 PD2
PE4 8 125 PD1
PE5 9 124 PD0
PE6 10 123 PC12
VSS 11 122 PC11
VDD 12 121 PC10
VSSSMPS 13 120 VDD
VLXSMPS 14 119 VDDLDO
VDDSMPS 15 118 VSS
VFBSMPS 16 117 VCAP3
PF5 17 116 PA15
PF6 18 115 PA14
PF7 19 114 PA13
PF8 20 113 PA12
PF9 21 112 PA11
PF10 22 111 PA10
PH0-OSC_IN 23 LQFP176 110 PA9
PH1-OSC_OUT 24 109 PA8
NRST 25 108 VSS
VSS 26 107 VDD
VDD 27 106 PC9
PC0 28 105 PC8
PC1 29 104 PC7
PC2 30 103 PC6
PC3 31 102 PD15
VSSA 32 101 PD14
VREFM 33 100 VDD
VREFP 34 99 VDDLDO
VDDA 35 98 VSS
PA0 36 97 VCAP2
PA1 37 96 PB15
PA2 38 95 PB14
PA3 39 94 PB13
VSS 40 93 PB12
VDD 41 92 PB11
PA4 42 91 PB10
PA5 43 90 PD13
PA6 44 89 PD12
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
PC4
PC5
PB0
PB1
PB2
VDD
VSS
PE7
PE8
PE9
PE10
VDD
VDDLDO
VSS
VCAP1
PO1
VDDXSPI1
VSS
PP4
PP2
PP3
VSS
VDDXSPI1
PO5
PO4
PP5
PP0
VSS
VDDXSPI1
PP6
PO2
PP7
PP1
VSS
VDDXSPI1
PO0
PD8
PD9
PD10
VDD
VSS
PA7
PF11
PD11
MSv55551V3
DS14359 Rev 2 83/320

91
Figure 14. LQFP176 GFx with SMPS pinout(a)
VDD33USB
VDD50USB
VDDLDO
BOOT0
VCAP4
PM13
PM14
PM12
PM11
PE15
PE14
PE13
PE12
PE11
VDD
VDD
VDD
PG2
PG1
PD7
PD6
PD5
VSS
PG0
VSS
PB9
PB8
PB7
PB6
PE2
PE1
PE0
PD4
PD3
PD2
PD1
PB5
PB4
PB3
PF4
PF3
PF2
PF1
PF0
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VBAT 1 132 PD0
PC13 2 131 PC12
PC14-OSC32_IN 3 130 PC11
PC15-OSC32_OUT 4 129 PC10
VDD 5 128 VDD
VSS 6 127 VDDLDO
PE3 7 126 VSS
PE4 8 125 VCAP3
PE5 9 124 PA15
PE6 10 123 PA14
VSS 11 122 PA13
VDD 12 121 PA12
VSSSMPS 13 120 PA11
VLXSMPS 14 119 PA10
VDDSMPS 15 118 PA9
VFBSMPS 16 117 PA8
PF5 17 116 VDD
PF6 18 115 PC9
PF7 19 114 PC8
PF8 20 113 PC7
PF9 21 112 PC6
PF10 22 111 PN1
PH0-OSC_IN 23 LQFP176 110 VDDXSPI2
PH1-OSC_OUT 24 109 PN3
NRST 25 108 PN11
VSS 26 107 PN0
VDD 27 106 PN10
PC0 28 105 VDDXSPI2
PC1 29 104 VSS
PC2 30 103 PN2
PC3 31 102 PN9
VSSA 32 101 PN6
VREFM 33 100 PN7
VREFP 34 99 VDDXSPI2
VDDA 35 98 VSS
PA0 36 97 PN5
PA1 37 96 PN4
PA2 38 95 PN8
PA3 39 94 VSS
VSS 40 93 VDDXSPI2
VDD 41 92 VDD
PA4 42 91 VDDLDO
PA5 43 90 VSS
PA6 44 89 VCAP2
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
PC4
PC5
PB0
PB1
PB2
VDD
VSS
PE7
PE8
PE9
PE10
VDD
VDDLDO
VSS
VCAP1
PO1
VDDXSPI1
VSS
PP4
PP2
PP3
VSS
VDDXSPI1
PO5
PO4
PP5
PP0
VSS
VDDXSPI1
PP6
PO2
PP7
PP1
VSS
VDDXSPI1
PO0
PB10
PB12
PB13
PB14
PB15
PA7
PF11
PB11
MSv55545V3
84/320 DS14359 Rev 2

Figure 15. WLCSP101 with SMPS pinout(a)
2 4 6 8 10
1 3 5 7 9 11
A VDD50USB PM5 PM12 VDD VCAP4
PC14-
B VDD VDD3USB PM6 PM11 VSS
OSC32_IN
C VSS VSSUSB PM9 PD7 VDDLDO
PC15-
D VCAP3 PM0 DVDD PM13 PB5 OSC32_O
UT
E VDDLDO PM1 PM8 PB3 VSS
F PA15 PC10 PM3 BOOT0 PB6 VDD
G PA14 PC11 PM14 PB7 PC13
H PA10 PA13 PM2 PB4 VBAT VSSSMPS
J PA9 PA12 PA5 PB8 VLXSMPS
K PA8 PA11 PB11 PA1 NRST VDDSMPS
L PB14 PB12 PB1 PC1 VFBSMPS
PH0-
M PB15 PB10 PD12 PA6 PC0
OSC_IN
N PO0 PP5 PB2 PA4 VREFM
PH1-
P VDD PP0 PO4 PO1 PA0
OSC_OUT
R PP7 VSS PP2 PB0 VSSA
T VSS PP6 PO5 VSS PA7 VDDA
U PP1 VDDXSPI1 PP4 VDDLDO VREFP
V VDDXSPI1 PO2 PP3 VDDXSPI1 VSS PA2
W VCAP1 VDD
MSv55555V3
DS14359 Rev 2 85/320

91
Figure 16. TFBGA225 OCTO with SMPS pinout(a)(b)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A VSS PE0 PF3 PF2 PG3 BOOT0 PM12 VSS PM6 PM3 VSS PD3 PE14 PD2 VSS
B PB8 PE2 PB5 PF4 PF0 PD7 PM11 PM9 PM5 PM2 PG0 PE13 PD1 PC10 PC11
C VBAT PB9 PE1 PB3 PF1 PG2 PM13 PM14 PM8 PM1 PD4 PE11 PD0 PA12 PA11
PC15- PC14-
VDD50US
D OSC32_O OSC32_I VSS PB7 PB4 VSS PD5 DVDD
B
PM0 PE15 PC12 PA14 PA9 PC8
UT N
E PE6 PE4 VSS PC13 PB6 VCAP4 PD6 VSSUSB VSS PG1 PE12 PA13 PA10 PC9 PC6
VDD33US
F PG14 PG12 PG11 PE5 PE3 VSS VDD
B
VDD VDD VCAP3 PA8 PC7 PN1 VSS
VFBSMP
G VLXSMPS
S
PF5 PG15 PG13 VDD VDDLDO VSS VDDLDO VSS PA15 VSS PN3 PN0 PN11
VDDSMP VSSSMP VDDXSPI

H S S
PF8 PF7 PF6 VDD VSS VSS VSS VDD VSS
2
PN10 PN9 PN2
VDDXSPI
J VSS PF9 PF10 NRST VSSA VDDA VDDLDO VSS VDDLDO VSS
2
VSS PN7 PN6 VSS
PH1-
PH0- VDDXSPI
K OSC_IN
OSC_OU PC0 VREFM VREFP VDD VSS VDD VSS VDD VCAP2
2
PN8 PN4 PN5
T
VDDXSPI VDDXSPI
L PC1 PC2 PC3 PA2 PC4 VSS VCAP1
1
VDD
1
VSS PB12 PD15 PD14 PN12
VDDXSPI
M PA0 PA1 PA4 PA7 PF11 PE7 PG6 VSS VSS
1
PD8 PD11 PB14 PB15 VSS
N PA3 PA5 PC5 PB2 PF15 PG4 PG7 PP2 PP3 PP0 PP7 PO0 PD12 PB11 PB13
P PA6 PB0 PF13 PF14 PE9 PG5 PG8 PO1 VSS PP5 PO2 PP1 PD9 PD13 PB10
R VSS PB1 PF12 PE8 PE10 VSS PG9 PP4 PO5 PO4 PP6 VSS PG10 PD10 VSS
MSv55542V4

b. The above figure shows the package top view
86/320 DS14359 Rev 2

Figure 17. TFBGA225 HEXA with SMPS pinout(a)(b)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A VSS PE0 PF3 PF2 PG3 BOOT0 PM12 VSS PM6 PM3 VSS PD3 PE14 PD2 VSS
B PB8 PE2 PB5 PF4 PF0 PD7 PM11 PM9 PM5 PM2 PG0 PE13 PD1 PC10 PC11
C VBAT PB9 PE1 PB3 PF1 PG2 PM13 PM14 PM8 PM1 PD4 PE11 PD0 PA12 PA11
PC15- PC14-
VDD50US
D OSC32_O OSC32_I VSS PB7 PB4 VSS PD5 DVDD
B
PM0 PE15 PC12 PA14 PA9 PC8
UT N
E PE6 PE4 VSS PC13 PB6 VCAP4 PD6 VSSUSB VSS PG1 PE12 PA13 PA10 PC9 PC6
VDD33US
F PG14 PG12 PG11 PE5 PE3 VSS VDD
B
VDD VDD VCAP3 PA8 PC7 PN1 VSS
VFBSMP
G VLXSMPS
S
PF5 PG15 PG13 VDD VDDLDO VSS VDDLDO VSS PA15 VSS PN3 PN0 PN11
VDDSMP VSSSMP VDDXSPI

H S S
PF8 PF7 PF6 VDD VSS VSS VSS VDD VSS
2
PN10 PN9 PN2
VDDXSPI
J VSS PF9 PF10 NRST VSSA VDDA VDDLDO VSS VDDLDO VSS
2
VSS PN7 PN6 VSS
PH1-
PH0- VDDXSPI
K OSC_IN
OSC_OU PC0 VREFM VREFP VDD VSS VDD VSS VDD VCAP2
2
PN8 PN4 PN5
T
VDDXSPI VDDXSPI
L PC1 PC2 PC3 PA2 PC4 VSS VCAP1
1
VDD
1
VSS PB12 PD15 PD14 PN12
VDDXSPI VDDXSPI
M PA0 PA1 PA4 PA7 PF11 PE7 VSS
1
VSS
1
PO3 PP10 PB14 PB15 VSS
N PA3 PA5 PC5 PB2 PF15 PP12 PP14 VSS PP2 PP5 PO2 PP1 PD12 PB11 PB13
P PA6 PB0 PF13 PF14 PE9 PP11 PO1 PP15 PP3 PO5 PP0 PP7 PP8 PD13 PB10
R VSS PB1 PF12 PE8 PE10 VSS PP13 PP4 VSS PO4 PP6 VSS PO0 PP9 VSS
MSv55541V4

b. The above figure shows the package top view
DS14359 Rev 2 87/320

91
Figure 18. VFQFPN68 GP pinout(a)
VDD33USB
BOOT0
VCAP4
PM13
PM14
PM12
PM11
VDD
VDD
VSS
VSS
PB9
PB8
PB7
PB5
PB4
PB3
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
VBAT 1 51 VCAP3
PC13 2 50 PA15
PC14-OSC32_IN 3 49 PA14
PC15-OSC32_OUT 4 48 PA13
PH0-OSC_IN 5 47 PA12
NRST 7 45 PA10
VSS 8 44 PA9
VDD 9 VFQFPN68 43 PA8
VSSA 10 42 VDD
VREFP 11 41 VSS
VDDA 12 40 VCAP2
PA0 13 39 PB15
PA1 14 38 PB14
PA2 15 37 PB12
PA3 16 36 PB11
PA4 17 35 PB10
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
VDD
PB0
PB1
PB2
PP2
PP3
VSS
VDDXSPI1
PO4
PP0
PP1
VSS
VDDXSPI1
PO0
PA5
PA6
PA7
MSv55546V3
88/320 DS14359 Rev 2

Figure 19. LQFP100 GP pinout(a)
VDD50USB
VDD33USB
VSSUSB
BOOT0
VCAP4
DVDD
PM12
PM14
PM13
PM11
VDD
VDD
PM3
PM5
PM6
PM8
PM9
VSS
PB3
PB4
PB5
PB6
PB7
PB8
PB9
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VBAT 1 75 PM2
PC13 2 74 PM1
PC14-OSC32_IN 3 73 PM0
PH0-OSC_IN 5 71 PC11
PH1-OSC_OUT 6 70 PC10
NRST 7 69 VDD
VSS 8 68 VSS
VDD 9 67 VCAP3
PC0 10 66 PA15
PC1 11 65 PA14
VSSA 12 64 PA13
VREFM 13 LQFP100 63 PA12
VREFP 14 62 PA11
VDDA 15 61 PA10
PA0 16 60 PA9
PA1 17 59 PA8
PA2 18 58 VDD
PA3 19 57 VSS
VSS 20 56 VCAP2
PA4 21 55 PB15
PA5 22 54 PB14
VDD 23 53 PB13
PA6 24 52 PB12
PA7 25 51 PB11
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PB10
PO0
VDDXSPI1
VSS
PP1
PP7
PO2
VDDXSPI1
PP6
VSS
PP0
PP5
PO4
PO5
VDDXSPI1
VSS
PP3
PP2
PP4
VSS
VDDXSPI1
PO1
PB2
PB1
PB0
MSv55552V3
DS14359 Rev 2 89/320

91
Figure 20. LQFP144 GP pinout(a)
VDD33USB
VDD50USB
VSSUSB
BOOT0
VCAP4
DVDD
PM13
PM14
PM12
PM11
VDD
VDD
VDD
PM9
PM8
PM6
PM5
PM3
PM2
PM1
PM0
VSS
VSS
PD7
PD6
PD5
PD4
PD3
PB7
PB6
PE2
PE1
PE0
PB5
PB4
PB3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
109
119
118
117
116
115
114
113
112
110
111
PB8 1 108 VDD
PB9 2 107 VSS
VBAT 3 106 PD2
PC13 4 105 PD1
PC14-OSC32_IN 5 104 PD0
VDD 7 102 PC11
VSS 8 101 PC10
PE3 9 100 VDD
PE4 10 99 VSS
PE5 11 98 VCAP3
PE6 12 97 PA15
PH0-OSC_IN 13 96 PA14
NRST 15 94 PA12
VSS 16 93 PA11
VDD 17 92 PA10
PC0 18 91 PA9
PC1 19 LQFP144 90 PA8
PC2 20 89 VSS
PC3 21 88 VDD
VSSA 22 87 PC9
VREFM 23 86 PC8
VREFP 24 85 PC7
VDDA 25 84 PC6
PA0 26 83 PD15
PA1 27 82 PD14
PA2 28 81 VDD
PA3 29 80 VSS
VSS 30 79 VCAP2
VDD 31 78 PB15
PA4 32 77 PB14
PA5 33 76 PB13
PA6 34 75 PB12
PA7 35 74 PB11
PC4 36 73 PB10
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PC5
PB0
PB1
PB2
VDD
VSS
VCAP1
PO1
VDDXSPI1
VSS
PP4
PP2
PP3
VSS
VDDXSPI1
PO5
PO4
PP5
PP0
VSS
VDDXSPI1
PP6
PO2
PP7
PP1
VSS
VDDXSPI1
PO0
PD8
PD9
VDD
VSS
PD10
PD12
PD13
PD11
MSv55540V4
90/320 DS14359 Rev 2

4.1 Pin description

Table 20. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function during
Pin name
and after reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input/output pin
FT 5V-tolerant I/O
TT 3.6V-tolerant I/O
B Dedicated BOOT pin
Bidirectional reset pin with embedded weak pull-up
RST
resistor
Option for TT or FT I/Os(1)
_a I/O, with analog switch function supplied by VDDA
I/O structure
_f I/O, Fm+ capable
_h I/O with high-speed low-voltage mode (HSLV)
_s I/O supplied only by VDDIOx(2)
_t I/O with tamper function functional in VBAT mode
_c I/O power delivery
_d I/O i/o dead battery
_u I/O USB
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after
Notes
reset.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in the table below are a concatenation of various options. Examples: FT_hat, FT_fs, TT_a.
2. VDDIOx represents VDD or VDDXSPIx.
DS14359 Rev 2 91/320

91
STM32H7Sxx8
Table 21. STM32H7Sxx8 pin and ball descriptions
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
(function Alternate functions
functions
after reset)
TIM17_CH1, TIM4_CH4,
DS14359 Rev 2
I2C1_SDA/I3C1_SDA,
SPI2_NSS/I2S2_WS,
PSSI_D7, SDMMC1_CDIR, TAMP_IN2/
B2 C3 B2 D4 D4 C2 176 176 C2 - C2 C2 68 100 2 PB9 I/O FT_h -
UART4_TX, FDCAN1_TX, TAMP_OUT1
SDMMC2_D5,
SDMMC1_D5, DCMIPP_D7,
EVENTOUT
C3 B1 B1 B1 B1 C1 1 1 C1 H9 C1 C1 1 1 3 VBAT S - - - -
C1 A1 A1 C4 B9 A1 - - A1 B9 A1 A1 - - - VSS S - - - -
TAMP_IN1/
TAMP_OUT2,
D3 B2 C3 E4 E4 D3 2 2 D3 G10 E4 E4 2 2 4 PC13 I/O - - EVENTOUT RTC_OUT1/
92/320
RTC_TS,
WKUP3
Table 21. STM32H7Sxx8 pin and ball descriptions (continued)
93/320 Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
C5 A12 A12 C6 C4 A15 - - A15 C2 A8 A8 - - - VSS S - - - -

DS14359 Rev 2
PC14-
B1 C1 C1 C2 C2 D1 3 3 D1 B11 D2 D2 3 3 5 OSC32_IN( I/O - - EVENTOUT OSC32_IN
OSC32_IN)
PC15-
OSC32_OU
C2 C2 C2 C1 C1 E2 4 4 E2 D11 D1 D1 4 4 6 I/O - - EVENTOUT OSC32_OUT
T(OSC32_O
UT)
D5 D6 D4 C3 C3 D4 5 5 D4 F11 F7 F7 - - 7 VDD S - - - -
C7 C9 C7 C9 C6 D2 6 6 C8 E10 A11 A11 - - 8 VSS S - - - -
TRACED0, LPTIM5_ETR,
TIM15_BKIN, SAI1_SD_B,
- D3 D3 D3 D3 F2 7 7 F2 - F5 F5 - - 9 PE3 I/O FT_h - ETH_MII_RXD3, -
FMC_D12/FMC_AD12,
EVENTOUT
TRACED1, SAI1_D2,
ADF1_SDI0, TIM15_CH1N,
STM32H7Sxx8
SPI4_NSS, SAI1_FS_A,
- E3 E3 E3 E3 F3 8 8 F3 - E2 E2 - - 10 PE4 I/O FT_h - -
PSSI_D4,
FMC_D13/FMC_AD13,
DCMIPP_D4, EVENTOUT
STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
TRACED2, ADF1_CCK1,
SAI1_CK2, TIM15_CH1,
DS14359 Rev 2
SPI4_MISO, SAI1_SCK_A,
- D1 D1 F5 F5 F1 9 9 F1 - F4 F4 - - 11 PE5 I/O FT_h - -
PSSI_D6,
FMC_D14/FMC_AD14,
DCMIPP_D6, EVENTOUT
TRACED3, TIM1_BKIN2,
SAI1_D1, ADF1_SDI0,
TIM15_CH2, SPI4_MOSI,
- E2 E2 F4 F4 G3 10 10 G3 - E1 E1 - - 12 PE6 I/O FT_h - SAI1_SD_A, PSSI_D7, -
SAI2_MCLK_B,
FMC_D15/FMC_AD15,
DCMIPP_D7, EVENTOUT
E3 D9 D7 C5 - D7 - - D7 - F9 F9 - - - VDD S - - - -
E4 D2 D2 D11 C9 D5 - - D2 R4 A15 A15 - - - VSS S - - - -
LPTIM1_IN2,
SPI1_SCK/I2S1_CK,
SPDIFRX_IN0, PSSI_D3,
- - - - - - - - - - F3 F3 - - - PG11 I/O FT_h - SDMMC2_D2, -
ETH_MII_TX_EN/ETH_RMII
_TX_EN, FMC_D28,
DCMIPP_D3, EVENTOUT
94/320
95/320 Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
LPTIM1_IN1,
SPI6_MISO/I2S6_SDI,
DS14359 Rev 2
SPDIFRX_IN1,
- - - - - - - - - - F2 F2 - - - PG12 I/O FT_h - SDMMC2_D3, -
ETH_MII_TXD1/ETH_RMII_
TXD1, FMC_D29, LCD_G1,
EVENTOUT
TRACED0, LPTIM1_CH1,
SPI6_SCK/I2S6_CK,
SDMMC2_D6,
- - - - - - - - - - G5 G5 - - - PG13 I/O FT_h - -
TXD0, FMC_D30, LCD_CLK,
EVENTOUT
TRACED1, LPTIM1_ETR,
SPI6_MOSI/I2S6_SDO,
SDMMC2_D7,
- - - - - - - - - - F1 F1 - - - PG14 I/O FT_h - -
TXD1, FMC_D31, LCD_B1,
EVENTOUT
STM32H7Sxx8
LPTIM1_CH2, PSSI_D13,
- - - - - - - - - - G4 G4 - - - PG15 I/O FT_h - FMC_NBL3, DCMIPP_D13, -
EVENTOUT
F6 D5 E4 F3 D11 D6 11 11 D5 T1 D3 D3 - - - VSS S - - - -
STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
E7 E4 F4 C10 C5 D10 12 12 D10 - F10 F10 - - - VDD S - - - -

DS14359 Rev 2
D2 E1 E1 D2 D2 G1 13 13 G1 H11 H2 H2 - - - VSSSMPS S - - - -
E2 F1 F1 E2 E2 G2 14 14 G2 J10 G1 G1 - - - VLXSMPS S - - - -
D1 F2 F2 D1 D1 H2 15 15 H2 K11 H1 H1 - - - VDDSMPS S - - - -
E1 F3 F3 E1 E1 H1 16 16 H1 L10 G2 G2 - - - VFBSMPS S - - - -
DCMIPP_D15,
UCPD_FRSTX1, PSSI_D15,
- - - - F1 H3 17 17 H3 - G3 G3 - - - PF5 I/O FT_h - -
FMC_CLE, ETH_MII_RXD2,
FMC_A16, EVENTOUT
TIM16_CH1, SPI5_NSS,
SAI1_SD_B, UART7_RX,
- - - F2 F2 J1 18 18 J1 - H5 H5 - - - PF6 I/O FT_h - -
FMC_ALE, FMC_A17,
EVENTOUT
TIM17_CH1, SPI5_SCK,
SAI1_MCLK_B, UART7_TX,
- - - G4 G4 J3 19 19 J3 - H4 H4 - - - PF7 I/O FT_h - -
FMC_A18, LCD_G0,
EVENTOUT
96/320
97/320 Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
TIM16_CH1N,
DCMIPP_PIXCLK,
DS14359 Rev 2
SPI5_MISO, SAI1_SCK_B,
- - - F1 G1 J2 20 20 J2 - H3 H3 - - - PF8 I/O FT_h - -
UART7_RTS, PSSI_PDCK,
TIM13_CH1, FMC_A19,
LCD_G1, EVENTOUT
TIM17_CH1N, SPI5_MOSI,
SAI1_FS_B, UART7_CTS,
- - - G5 G5 K2 21 21 K2 - J2 J2 - - - PF9 I/O FT_h - -
TIM14_CH1, FMC_A21,
LCD_R0, EVENTOUT
TIM16_BKIN, SAI1_D3,
DCMIPP_D15, PSSI_D15,
- - - - - K1 22 22 K1 - J3 J3 - - - PF10 I/O FT_h - PSSI_D11, FMC_A22, -
DCMIPP_D11, LCD_R1,
EVENTOUT
PH0-
F1 G2 G2 G2 G2 L2 23 23 L2 M11 K1 K1 5 5 13 OSC_IN(PH I/O FT_h - EVENTOUT OSC_IN
0)
PH1-
STM32H7Sxx8
F2 H1 H1 G1 H1 M1 24 24 M1 P11 K2 K2 6 6 14 OSC_OUT( I/O FT_h - EVENTOUT OSC_OUT
PH1)
F3 F4 G4 H4 H4 M2 25 25 M2 K9 J4 J4 7 7 15 NRST I/O RST - - -
F8 D7 E8 F7 F3 D8 - - D6 T7 D6 D6 - - - VSS - - - - -
STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
H4 E7 F5 F11 F7 D11 26 26 D8 V9 E3 E3 8 8 16 VSS S - - - -

DS14359 Rev 2
W1
G4 F9 F9 E11 C10 F12 27 27 F12 G6 G6 9 9 17 VDD S - - - -
0
G7 G4 H9 G3 E11 G4 - - G4 - H6 H6 - - - VDD - - - - -
GFXTIM_FCKCAL,
SAI2_FS_B, FMC_NBL1,
G1 G3 G3 H3 H3 N1 28 28 N1 M9 K3 K3 - 10 18 PC0 I/O FT_h - ADC12_INP10
GFXTIM_LCKCAL,
EVENTOUT
TRACED0, SAI1_D1,
ADF1_SDI0, ADC12_INP11,
SPI2_MOSI/I2S2_SDO, ADC12_INN10,
H1 G5 H5 H5 H5 P1 29 29 P1 L8 L1 L1 - 11 19 PC1 I/O FT_h - SAI1_SD_A, FMC_A16, TAMP_IN7/TAM
SDMMC2_CK, ETH_MDC, P_OUT8,
FMC_A0, MDIOS_MDC, WKUP4
EVENTOUT
TIM1_CH1,
SPI2_MISO/I2S2_SDI, ADC12_INP12,
- J1 J1 H2 H2 P2 30 30 P2 - L2 L2 - - 20 PC2 I/O FT_h -
FMC_A17, ETH_MII_TXD2, ADC12_INN11
FMC_A1, EVENTOUT
98/320
99/320 Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
TIM1_CH2,
SPI2_MOSI/I2S2_SDO,
DS14359 Rev 2
ADC12_INP13,
- H2 H2 H1 J1 N2 31 31 N2 - L3 L3 - - 21 PC3 I/O FT_h - FMC_A18,
ADC12_INN12
ETH_MII_TX_CLK, FMC_A2,
EVENTOUT
G3 H3 J3 J4 J4 L4 32 32 L4 R10 J5 J5 10 12 22 VSSA S - - - -
F4 H5 H4 J3 J3 N3 33 33 N3 N10 K4 K4 - 13 23 VREFM S - - - -
J1 K3 K3 K3 K3 M3 34 34 M3 U10 K5 K5 11 14 24 VREFP S - - - -
H2 J3 H3 K4 K4 M4 35 35 M4 T11 J6 J6 12 15 25 VDDA S - - - -
TIM2_CH1, TIM5_CH1,
TIM9_CH1, TIM15_BKIN,
SPI6_NSS/I2S6_WS,
USART2_CTS/USART2_NS ADC12_INP0,
K1 K1 J2 J1 K1 R2 36 36 R2 P9 M1 M1 13 16 26 PA0 I/O FT_h - S, UART4_TX, ADC12_INN1,
SDMMC2_CMD, WKUP1
SAI2_SD_B,
FMC_AD7/FMC_D7,
LCD_G3, EVENTOUT
STM32H7Sxx8
STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
TIM2_CH2, TIM5_CH2,
LPTIM3_IN1, TIM15_CH1N,
DS14359 Rev 2
DCMIPP_D0, PSSI_D0,
USART2_RTS, UART4_RX,
G2 J2 K1 L1 L1 P3 37 37 P3 K7 M2 M2 14 17 27 PA1 I/O FT_h - SAI2_MCLK_B, ADC12_INP1
ETH_MII_RX_CLK/ETH_RMI
I_REF_CLK,
FMC_AD6/FMC_D6,
LCD_G2, EVENTOUT
TIM2_CH3, TIM5_CH3,
LPTIM3_IN2, TIM15_CH1,
USART2_TX, SAI2_SCK_B,
ADC12_INP14,
J2 L1 L1 K1 M1 R3 38 38 R3 V11 L4 L4 15 18 28 PA2 I/O FT_h - ETH_MDIO,
WKUP2
FMC_AD5/FMC_D5,
LCD_B7, MDIOS_MDIO,
EVENTOUT
TIM2_CH4, TIM5_CH4,
LPTIM3_CH1, TIM15_CH2,
I2S6_MCK, SPI4_RDY,
USART2_RX,
- K2 K2 J5 J5 N4 39 39 N4 - N1 N1 16 19 29 PA3 I/O FT_h - GFXTIM_LCKCAL, ADC12_INP15
SPI5_RDY, SPI1_RDY,
ETH_MII_COL,
100/320
GFXTIM_FCKCAL, LCD_DE,
TIM1_CH3, EVENTOUT
101/320 Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
- G1 G1 G7 G6 E3 40 40 D12 - F6 F6 - 20 30 VSS S - - - -
DS14359 Rev 2
- J5 J4 K2 G3 J12 41 41 K4 - H10 H10 - - 31 VDD S - - - -

TIM5_ETR, LPTIM3_CH2,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK,
K2 L2 M2 L2 L2 M5 42 42 M5 N8 M3 M3 17 21 32 PA4 I/O FT_h - SPI6_NSS/I2S6_WS, ADC1_INP18
PSSI_DE, OTG_HS_SOF,
ETH_MDIO, LCD_R3,
DCMIPP_HSYNC,
EVENTOUT
PWR_CSTOP, TIM2_CH1,
TIM2_ETR, TIM9_CH2,
SPI1_SCK/I2S1_CK,
H3 J4 L2 L3 L3 P4 43 43 P4 J6 N2 N2 18 22 33 PA5 I/O FT_h - PSSI_D8, ADC2_INP18
SPI6_SCK/I2S6_CK,
FMC_NOE, DCMIPP_D8,
LCD_CLK, EVENTOUT
- G8 G5 G8 G7 E4 - - E1 - F15 F15 - - - VSS S - - - -
STM32H7Sxx8
- J9 - K10 G11 K4 - - M6 - K6 K6 19 23 - VDD S - - - -
STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
PWR_CSLEEP, TIM1_BKIN,
TIM3_CH1, LPTIM3_ETR,
DS14359 Rev 2
SPI1_MISO/I2S1_SDI,
PSSI_PDCK,
K3 M2 M3 M1 N1 R4 44 44 R4 M7 P1 P1 20 24 34 PA6 I/O FT_h - ADC12_INP3
SPI6_MISO/I2S6_SDI,
TIM13_CH1, MDIOS_MDC,
LCD_B7, DCMIPP_PIXCLK,
LCD_HSYNC, EVENTOUT
TIM1_CH1N, TIM3_CH2,
SPI1_MOSI/I2S1_SDO,
SPI6_MOSI/I2S6_SDO,
ADC12_INP7,
J3 K4 L3 M2 M2 N5 45 45 N5 T9 M4 M4 21 25 35 PA7 I/O FT_h - TIM14_CH1, LCD_R4,
ADC12_INN3
ETH_MII_RX_DV/ETH_RMII
_CRS_DV, FMC_INT,
LCD_B1, EVENTOUT
I2S1_MCK, FMC_A19,
SPDIFRX_IN2,
- L3 K4 N1 N2 P5 46 46 P5 - L5 L5 - - 36 PC4 I/O FT_h - ADC12_INP4
ETH_MII_RXD0/ETH_RMII_
RXD0, FMC_A3, EVENTOUT
SAI1_D3, DCMIPP_D15,
PSSI_D15, FMC_A21,
ADC12_INP8,
- M3 M4 N2 L4 R5 47 47 R5 - N3 N3 - - 37 PC5 I/O FT_h - SPDIFRX_IN3,
ADC12_INN4
102/320
RXD1, FMC_A5, EVENTOUT

103/320 Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
TIM9_CH1,
DS14359 Rev 2
SPI1_SCK/I2S1_CK,
UART4_CTS, ADC12_INP9,
F5 L4 L4 K5 K5 N6 48 48 N6 R8 P2 P2 22 26 38 PB0 I/O FT_h -
ETH_MII_TXD0/ETH_RMII_ ADC12_INN5
TXD0, GFXTIM_TE,
[RNG_S1], LCD_VSYNC,
EVENTOUT
TIM9_CH2, FDCAN2_TX,
LCD_G2,
K4 M4 J6 M3 M3 R6 49 49 R6 L6 R2 R2 23 27 39 PB1 I/O FT_h - ADC12_INP5
TXD1, FMC_NOE,
[RNG_S2], EVENTOUT
RTC_OUT2, SAI1_D1,
ADF1_SDI0, SAI1_SD_A,
G5 L5 L5 L4 N3 P6 50 50 P6 N6 N4 N4 24 28 40 PB2 I/O FT_h - SPI3_MOSI/I2S3_SDO, -
LCD_B2, FMC_NWE,
EVENTOUT
STM32H7Sxx8
M1
- - - L5 K2 L12 51 51 - K8 K8 - - 41 VDD S - - - -
2
- H4 G8 H7 G8 E12 52 52 E3 - G8 G8 - - - VSS S - - - -
STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
SPI5_MOSI, PSSI_D12,
SAI2_SD_B, FMC_A23,
DS14359 Rev 2
- - - N3 M4 R7 53 53 R7 - M5 M5 - - - PF11 I/O FT_h - ADC1_INP2

DCMIPP_D12, LCD_B0,
EVENTOUT
USART1_RX, SPI5_MISO, ADC1_INP6,

- - - - - N7 - - N7 - R3 R3 - - - PF12 I/O FT_h -
FMC_D19, EVENTOUT ADC1_INN2
USART1_TX, SPI5_NSS,
- - - - - P7 - - P7 - P3 P3 - - - PF13 I/O FT_h - PSSI_D10, FMC_D20, ADC2_INP2
DCMIPP_D10, EVENTOUT
USART1_CTS, SPI5_MOSI,
ADC2_INP6,
- - - - - - - - - - P4 P4 - - - PF14 I/O FT_h - FMC_A24, LCD_G0,
ADC2_INN2
EVENTOUT
USART1_RTS, SPI5_SCK,
- - - - - - - - - - N5 N5 - - - PF15 I/O FT_h - FMC_A25, LCD_G1, -
EVENTOUT
TIM1_ETR, UART7_RX,
- - - K6 K6 P8 54 54 P8 - M6 M6 - - - PE7 I/O FT_h - FMC_A20, SAI2_SD_B, -
FMC_A4, EVENTOUT
TIM1_CH1N, UART7_TX,
- - - M4 N4 R8 55 55 R8 - R4 R4 - - - PE8 I/O FT_h - -
FMC_A12, EVENTOUT
104/320
105/320 Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
TIM1_CH1, UART7_RTS,
- - - M5 J7 N8 56 56 N8 - P5 P5 - - - PE9 I/O FT_h - FMC_A14, FMC_BA0, -
DS14359 Rev 2
EVENTOUT
TIM1_CH2N, UART7_CTS,
- - - N4 M5 N9 57 57 N9 - R5 R5 - - - PE10 I/O FT_h - FMC_A15, FMC_BA1, -
EVENTOUT
- - - - K10 M6 58 58 - - K10 K10 - - 41 VDD S - - - -
- G6 G6 H6 H6 J7 59 59 J7 U8 J7 J7 - - - VDDLDO S - - - -
- H7 H7 H11 H7 F4 60 60 E4 - G10 G10 - - 42 VSS S - - - -
- H6 H6 J6 J6 K7 61 61 K7 W8 L7 L7 - - 43 VCAP1 S - - - -
TIM1_BKIN2,
- - - - - - - - - - N6 - - - - PG4 I/O FT_h - -
RXD0, FMC_D22,
EVENTOUT
TIM1_ETR,
- - - - - - - - - - P6 - - - - PG5 I/O FT_h - -
RXD1, FMC_D23,
STM32H7Sxx8
EVENTOUT
TIM17_BKIN, PSSI_D12,
- - - - - - - - - - M7 - - - - PG6 I/O FT_h - ETH_MDC, FMC_NBL2, -
STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
SAI1_MCLK_A, PSSI_D13,
- - - - - - - - - - N7 - - - - PG7 I/O FT_h - FMC_D24, DCMIPP_D13, -
DS14359 Rev 2
EVENTOUT
SPI6_NSS/I2S6_WS,
SPDIFRX_IN2,
- - - - - - - - - - P7 - - - - PG8 I/O FT_h - -
ETH_PPS_OUT, FMC_D25,
LCD_G0, EVENTOUT
SPI1_MISO/I2S1_SDI,
SPDIFRX_IN3, PSSI_RDY,
SAI2_FS_B, SDMMC2_D0,
- - - - - - - - - - R7 - - - - PG9 I/O FT_h - -
FMC_D26,
DCMIPP_VSYNC,
EVENTOUT
- - - - - - - - - U4 - L8 - - - VDDXSPI1 S - - - -
- - - - - - - - - - - H7 - - - VSS S - - - -
- - - - - - - - - - - N6 - - - PP12 I/O FT_h - XSPIM_P1_IO12 -
- - - - - - - - - - - P6 - - - PP11 I/O FT_h - XSPIM_P1_IO11 -

- - - - - - - - - - - N7 - - - PP14 I/O FT_h - XSPIM_P1_IO14 -
- - - - - - - - - - - R7 - - - PP13 I/O FT_h - XSPIM_P1_IO13 -

106/320
J4 J6 J7 K7 K7 P9 62 62 P9 P7 P8 P7 - 29 44 PO1 I/O FT_h - XSPIM_P1_NCS2 -

107/320 Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
G6 K5 K5 K8 K8 K9 63 63 K9 V1 L8 L10 - 30 45 VDDXSPI1 S - - - -
DS14359 Rev 2
- K8 J5 K11 J2 F8 64 64 F4 - H7 H8 - 31 46 VSS S - - - -
K5 M5 M5 N5 N5 R9 65 65 R9 U6 R8 R8 - 32 47 PP4 I/O FT_h - XSPIM_P1_IO4 -
J5 L6 L6 M6 M6 P10 66 66 P10 R6 N8 N9 25 33 48 PP2 I/O FT_h - XSPIM_P1_IO2 -
K6 M6 M6 N6 N6 R10 67 67 R10 V5 N9 P9 26 34 49 PP3 I/O FT_h - XSPIM_P1_IO3 -
- K10 K6 L6 K11 F9 68 68 F7 - H8 H9 27 35 50 VSS S - - - -
H5 K7 K7 L7 L7 M8 69 69 M8 V7 L10 M8 28 36 51 VDDXSPI1 S - - - -
J6 L7 L7 M7 M7 P11 70 70 P11 T5 R9 P10 - 37 52 PO5 I/O FT_h - XSPIM_P1_NCLK -
K7 M7 M7 N7 N7 R11 71 71 R11 P5 R10 R10 29 38 53 PO4 I/O FT_h - XSPIM_P1_CLK -
J7 M8 M8 M8 M8 N11 72 72 N11 N4 P10 N10 - 39 54 PP5 I/O FT_h - XSPIM_P1_IO5 -
K8 L8 L8 N8 N8 R12 73 73 R12 P3 N10 P11 30 40 55 PP0 I/O FT_h - XSPIM_P1_IO0 -
- M1 K8 L8 L6 F10 74 74 F8 - H9 H11 - 41 56 VSS S - - - -
STM32H7Sxx8
M1 M1 M1 M1
H7 K9 K9 L9 L9 75 75 - - 42 57 VDDXSPI1 S - - - -
0 0 0 0
J8 M9 M9 M9 M9 P12 76 76 P12 T3 R11 R11 - 43 58 PP6 I/O FT_h - XSPIM_P1_IO6 -
K9 L9 L9 N9 N9 R13 77 77 R13 V3 P11 N11 - 44 59 PO2 I/O FT_h - XSPIM_P1_DQS0 -

STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
M1 M1 M1 M1
J9 P13 78 78 P13 R2 N11 P12 - 45 60 PP7 I/O FT_h - XSPIM_P1_IO7 -
0 0 0 0
DS14359 Rev 2
K10 L10 L10 N10 N10 R14 79 79 R14 U2 P12 N12 31 46 61 PP1 I/O FT_h - XSPIM_P1_IO1 -
M1
- M1 L10 L8 G6 80 80 F9 - H11 J1 32 47 62 VSS S - - - -
2
- - - - - - 81 81 - - - - 33 48 63 VDDXSPI1 S - - - -
H8 J7 J8 K9 K9 P14 82 82 P14 N2 N12 R13 34 49 64 PO0 I/O FT_h - XSPIM_P1_NCS1 -
- - - - - - - - - - - M11 - - - PO3 I/O FT_h - XSPIM_P1_DQS1 -
- - - - - - - - - - - R14 - - - PP9 I/O FT_h - XSPIM_P1_IO9 -
M1
- - - - - - - - - - - - - - PP10 I/O FT_h - XSPIM_P1_IO10 -
2
- - - - - - - - - - - J8 - - - VSS S - - - -
SPI1_NSS/I2S1_WS,
PSSI_D2, SAI2_SD_B,
- - - - - - - - - - R13 - - - - PG10 I/O FT_h - -
SDMMC2_D1, FMC_D27,
DCMIPP_D2, EVENTOUT
108/320
109/320 Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
USART3_TX, SPDIFRX_IN1,
ETH_MII_TX_EN/ETH_RMII
DS14359 Rev 2
- J8 - J7 N11 N12 83 - N12 - M11 - - - 65 PD8 I/O FT_h - -

_TX_EN, FMC_NBL0,
LCD_R0, EVENTOUT
USART3_RX, FMC_SDCLK,
- - - N11 N12 P15 84 - - - P13 - - - 66 PD9 I/O FT_h - -
LCD_R1, EVENTOUT
TIM1_CH4, DCMIPP_D4,
SPI4_RDY, USART3_CK,
TAMP_IN8/TAM
- M11 - M11 M11 N13 85 - - - R14 - - - 67 PD10 I/O FT_h - PSSI_D4, SPI5_RDY,
P_OUT7
SPI1_RDY, FMC_CLK,
LCD_B0, EVENTOUT
TIM1_ETR, LPTIM2_IN2,
DCMIPP_D6,
M1
- L11 - - N13 N14 86 - - - - - - 68 PD11 I/O FT_h - USART3_CTS/USART3_NS -
2
S, PSSI_D6, SAI2_SD_A,
FMC_D16, EVENTOUT
M1
- - - - L5 87 - - P1 L9 L9 - - 69 VDD S - - - -
2
STM32H7Sxx8
M1
- - - L10 G8 88 - F10 - J1 J10 - - 70 VSS S - - - -
2
STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
LPTIM1_IN1, TIM4_CH1,
LPTIM2_IN1, USART3_RTS,
DS14359 Rev 2
M1
- K11 - - L11 89 - - M5 N13 N13 - - 71 PD12 I/O FT_h - PSSI_D12, SAI2_FS_A, -
3
FMC_NE1, DCMIPP_D12,
LCD_DE, EVENTOUT
UCPD_FRSTX2,
M1
- L12 - - N15 90 - - - P14 P14 - - 72 PD13 I/O FT_h - SAI2_SCK_A, PSSI_D13, -
2
FMC_INT, DCMIPP_D13,
EVENTOUT
TIM2_CH3, LPTIM2_IN1,
I2C2_SCL,
SPI2_SCK/I2S2_CK,
M1
H9 J10 J9 L11 L12 91 83 N13 M3 P15 P15 35 50 73 PB10 I/O FT_h - USART3_TX, -
4
ETH_MII_RX_ER,
FMC_D11/FMC_AD11,
LCD_G7, EVENTOUT
I2C2_SDA, USART3_RX,
M1 M1 ETH_MII_TX_EN/ETH_RMII
J10 K12 M11 N12 92 84 P15 K5 N14 N14 36 51 74 PB11 I/O FT_h - -
3 5 _TX_EN,
FMC_D10/FMC_AD10,
LCD_G6, EVENTOUT
110/320
111/320 Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
TIM1_BKIN, LPTIM2_IN2,
I2C2_SMBA,
DS14359 Rev 2
SPI2_NSS/I2S2_WS,
G9 H10 K10 J8 J8 L13 93 85 L13 L4 L12 L12 37 52 75 PB12 I/O FT_h - USART3_CK, FDCAN2_RX, -
FMC_D9/FMC_AD9,
LCD_G5, UART5_RX,
EVENTOUT
TIM1_CH1N, LPTIM2_CH1,
SPI2_SCK/I2S2_CK,
SDMMC1_D0,
USART3_CTS/USART3_NS
M1
H10 J11 L12 L13 L15 94 86 N14 - N15 N15 - 53 76 PB13 I/O FT_h - S, PSSI_D2, FDCAN2_TX, -
2
LCD_G4, ETH_MII_RXD3,
FMC_D8/FMC_AD8,
DCMIPP_D2, UART5_TX,
EVENTOUT
LPTIM2_CH2, USART1_TX,
M1 M1 SPI2_MISO/I2S2_SDI,
F9 H9 K11 J9 J9 L14 95 87 K13 L2 38 54 77 PB14 I/O FT_h - -
3 3 USART3_RTS, UART4_RTS,
STM32H7Sxx8
SDMMC2_D0, FMC_NE1,
LCD_DE, EVENTOUT
STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
RTC_REFIN, TIM1_CH3N,
TIM12_CH2, USART1_RX,
DS14359 Rev 2
M1 M1 M1 SPI2_MOSI/I2S2_SDO,
G10 J12 L11 N13 K12 K15 96 88 M1 39 55 78 PB15 I/O FT_h - PVD_IN
3 4 4 UART4_CTS, SDMMC2_D1,
LCD_G7, FMC_A20,
EVENTOUT
G8 H8 H8 H9 H9 K10 97 89 K10 - K11 K11 40 56 79 VCAP2 S - - - -
- - - - - G12 98 90 G6 - J8 J12 41 57 80 VSS S - - - -
F7 G7 G7 H8 H8 H8 99 91 H8 - J9 J9 - - - VDDLDO S - - - -
- - - - - - 100 92 - - - - 42 58 81 VDD S - - - -
LPTIM2_CH1, DCMIPP_D7,
- H11 - - K13 K13 101 - - - L14 L14 - - 82 PD14 I/O FT_h - UCPD_FRSTX1, -
UART8_CTS, PSSI_D7,
FMC_D17, EVENTOUT
TIM4_CH4, LPTIM5_OUT,
DCMIPP_D9,
- - - - J10 K14 102 - - - L13 L13 - - 83 PD15 I/O FT_h - UCPD_FRSTX2, -
UART8_RTS, PSSI_D9,
FMC_D18, EVENTOUT
112/320
- - - J10 - - - - - - L15 L15 - - - PN12 I/O FT_h - XSPIM_P2_NCS2 -
- - E10 G11 - - - 93 H10 - H12 H12 - - - VDDXSPI2 S - - - -

113/320 Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
- - - - - H6 - 94 G12 - J12 K7 - - - VSS S - - - -

DS14359 Rev 2
M1 XSPIM_P2_IO4,
- - K12 - - - 95 N15 - K13 K13 - - - PN8 I/O FT_h - -
3 FMC_D4/FMC_AD4
M1 XSPIM_P2_IO2,
- - J11 L12 - - - 96 - K14 K14 - - - PN4 I/O FT_h - -
4 FMC_D2/FMC_AD2
M1 XSPIM_P2_IO3,
- - J12 L13 - - - 97 - K15 K15 - - - PN5 I/O FT_h - -
5 FMC_D3/FMC_AD3
- - - - - H7 - 98 H4 - J15 K9 - - - VSS S - - - -
- - G10 H10 - - - 99 J12 - J11 J11 - - - VDDXSPI2 S - - - -
XSPIM_P2_NCLK,
- - H11 K12 - - - 100 L14 - J13 J13 - - - PN7 I/O FT_h - -
FMC_CLK
XSPIM_P2_CLK,
- - H12 K13 - - - 101 L15 - J14 J14 - - - PN6 I/O FT_h - -
FMC_SDCLK
XSPIM_P2_IO5,
- - G12 J12 - - - 102 K14 - H14 H14 - - - PN9 I/O FT_h - -
FMC_D5/FMC_AD5
XSPIM_P2_IO0,
STM32H7Sxx8
- - G11 J13 - - - 103 K15 - H15 H15 - - - PN2 I/O FT_h - -
FMC_D0/FMC_AD0
- - - - - H9 - 104 H6 - K7 L6 - - - VSS S - - - -
- - J10 J11 - - - 105 L12 - K12 K12 - - - VDDXSPI2 S - - - -

STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
XSPIM_P2_IO6,
- - F12 H12 - - - 106 J13 - H13 H13 - - - PN10 I/O FT_h - -
FMC_D6/FMC_AD6
DS14359 Rev 2
XSPIM_P2_DQS0,
- - F11 H13 - - - 107 J15 - G14 G14 - - - PN0 I/O FT_h - -
FMC_NE4
XSPIM_P2_IO7,
- - E12 G12 - - - 108 J14 - G15 G15 - - - PN11 I/O FT_h - -
FMC_D7/FMC_AD7
XSPIM_P2_IO1,
- - E11 G13 - - - 109 H15 - G13 G13 - - - PN3 I/O FT_h - -
FMC_D1/FMC_AD1
- - - - - H10 - - H7 - K9 L11 - - - VSS S - - - -
- - - - - - - 110 - - - - - - - VDDXSPI2 S - - - -
XSPIM_P2_NCS1,
- - G9 G10 - - - 111 H14 - F14 F14 - - - PN1 I/O FT_h - -
FMC_NBL0
TIM3_CH1, TIM9_CH1,
I2S2_MCK,
SDMMC1_D0DIR, PSSI_D0,
- H12 C12 F13 H10 J13 103 112 G15 - E15 E15 - - 84 PC6 I/O FT_h - -
SDMMC2_D6,
EVENTOUT
114/320
115/320 Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
TRGIO, TIM3_CH2,
TIM9_CH2, I2S3_MCK,
DS14359 Rev 2
SDMMC1_D123DIR,
- G9 D12 G9 G10 J14 104 113 G14 - F13 F13 - - 85 PC7 I/O FT_h - -
PSSI_D1, SDMMC2_D7,
EVENTOUT
TRACED1, TIM3_CH3,
I2C3_SMBA, UART5_RTS,
- G11 B12 F12 J11 J15 105 114 F15 - D15 D15 - - 86 PC8 I/O FT_h - -
PSSI_D2, SDMMC1_D0,
DCMIPP_D2, EVENTOUT
MCO2, TIM3_CH4,
I2C3_SDA, I2S_CKIN,
- G10 D11 F10 G9 H14 106 115 G13 - E14 E14 - - 87 PC9 I/O FT_h - UART5_CTS, PSSI_D3, -
EVENTOUT
- - - - - - 107 116 - - - - - - 88 VDD S - - - -
- - - - - H12 108 - H9 - L6 M7 - - 89 VSS S - - - -

MCO1, TIM1_CH1,
STM32H7Sxx8
I2C3_SCL, USART1_CK,
E8 F10 C11 E13 H12 G14 109 117 F14 K1 F12 F12 43 59 90 PA8 I/O FT_h - OTG_FS_SOF, UART7_RX, -
FMC_AD4/FMC_D4,
LCD_B6, EVENTOUT
STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
TIM1_CH2, LPUART1_TX,
I2C3_SDA,
DS14359 Rev 2
SPI2_SCK/I2S2_CK,
F10 G12 A11 D13 J12 H15 110 118 E15 J2 D14 D14 44 60 91 PA9 I/O FT_h - PSSI_D0, USART1_TX, -
FMC_AD3/FMC_D3,
DCMIPP_D0, LCD_B5,
EVENTOUT
TIM1_CH3, LPUART1_RX,
PSSI_D1, USART1_RX,
MDIOS_MDIO,
E9 F11 D10 E12 F10 G13 111 119 F13 H1 E13 E13 45 61 92 PA10 I/O FT_h - -
FMC_AD2/FMC_D2,
DCMIPP_D1, LCD_B4,
EVENTOUT
TIM1_CH4, LPUART1_CTS,
SPI2_NSS/I2S2_WS,
UART4_RX,
E10 F12 E9 C13 J13 G15 112 120 D15 K3 C15 C15 46 62 93 PA11 I/O FT_h - USART1_CTS/USART1_NS -
S, FDCAN1_RX,
FMC_AD1/FMC_D1,
LCD_B3, EVENTOUT
116/320
117/320 Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
TIM1_ETR, LPUART1_RTS,
SPI2_SCK/I2S2_CK,
DS14359 Rev 2
UART4_TX, USART1_RTS,
D9 E11 B11 D12 G12 F14 113 121 E14 J4 C14 C14 47 63 94 PA12 I/O FT_h - -
SAI2_FS_B, FDCAN1_TX,
FMC_AD0/FMC_D0,
LCD_B2, EVENTOUT
PA13(JTMS/
D10 E12 B10 B13 H13 F15 114 122 D14 H3 E12 E12 48 64 95 I/O FT_h - JTMS-SWDIO, EVENTOUT -
SWDIO)
PA14(JTCK/
C9 E10 C10 C12 F12 F13 115 123 E13 G2 D13 D13 49 65 96 I/O FT_h - JTCK-SWCLK, EVENTOUT -
SWCLK)
JTDI, TIM2_CH1,
TIM2_ETR, HDMI_CEC,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
C10 D12 A10 A13 G13 E15 116 124 C15 F1 G11 G11 50 66 97 PA15(JTDI) I/O FT_h - -
SPI6_NSS/I2S6_WS,
UART4_RTS, UART7_TX,
FMC_D15/FMC_AD15,
LCD_R5, EVENTOUT
D8 F8 F8 F9 F9 G10 117 125 G10 D1 F11 F11 51 67 98 VCAP3 S - - - -
STM32H7Sxx8
- - - - - H13 118 126 H12 - L11 M9 52 68 99 VSS S - - - -
E6 F7 F7 F8 F8 G9 119 127 G9 E2 G9 G9 - - - VDDLDO S - - - -
- - - - - - 120 128 - B1 - - 53 69 100 VDD S - - - -

STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
TIM1_BKIN,
SPI3_SCK/I2S3_CK,
DS14359 Rev 2
- D11 A9 A12 F13 E14 121 129 D13 F3 B14 B14 - 70 101 PC10 I/O FT_h - USART3_TX, UART4_TX, -
PSSI_D14, SDMMC1_D2,
SPI3_MISO/I2S3_SDI,
USART3_RX, UART4_RX,
- E9 D9 E10 E12 E13 122 130 C14 G4 B15 B15 - 71 102 PC11 I/O FT_h - -
PSSI_D4, SDMMC1_D3,
DCMIPP_D4, EVENTOUT
TRACED3, TIM1_CH4,
TIM15_CH1,
SPI6_SCK/I2S6_CK,
- C12 - C11 E13 D15 123 131 B15 - D12 D12 - 72 103 PC12 I/O FT_h - SPI3_MOSI/I2S3_SDO, -
USART3_CK, UART5_TX,
PSSI_D9, SDMMC1_CK,
DCMIPP_D9, EVENTOUT
PSSI_DE, FMC_A22,
UART4_RX, FDCAN1_RX,
- - B9 B12 E10 D14 124 132 B14 - C13 C13 - - 104 PD0 I/O FT_h - -
FMC_A6, DCMIPP_HSYNC,
EVENTOUT
FMC_A23, UART4_TX,
- - - B11 D13 C15 125 133 A14 - B13 B13 - - 105 PD1 I/O FT_h - FDCAN1_TX, FMC_A7, -
118/320
EVENTOUT
119/320 Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
TRACED2, TIM1_ETR,
TIM3_ETR, TIM15_BKIN,
DS14359 Rev 2
- C11 C9 E9 D12 D13 126 134 C13 - A14 A14 - - 106 PD2 I/O FT_h - PSSI_D11, UART5_RX, -
SDMMC1_CMD,
- - - - - J6 - - J4 - M9 N8 - - - VSS S - - - -
TIM1_CH2, SPI4_NSS,
- - - A11 C13 B15 127 135 A13 - C12 C12 - - - PE11 I/O FT_h - SAI2_SD_B, LCD_VSYNC, -
FMC_SDNWE, EVENTOUT
TIM1_CH3N, SPI4_SCK,
- - - E8 C12 C14 128 136 B13 - E11 E11 - - - PE12 I/O FT_h - SAI2_SCK_B, -
FMC_SDNRAS, EVENTOUT
TIM1_CH3, SPI4_MISO,
- - - A10 B13 B14 129 137 B12 - B12 B12 - - - PE13 I/O FT_h - SAI2_FS_B, FMC_SDNCAS, -
EVENTOUT
TIM1_CH4,
GFXTIM_FCKCAL,
SPI4_MOSI, SAI2_MCLK_B,
STM32H7Sxx8
- - - D10 - C13 130 138 C12 - A13 A13 - - - PE14 I/O FT_h - -
FMC_SDNE0,
GFXTIM_LCKCAL,
EVENTOUT
STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
TIM1_BKIN,
GFXTIM_LCKCAL,
DS14359 Rev 2
- - - - - A14 131 139 A12 - D11 D11 - - - PE15 I/O FT_h - FMC_SDCKE0, -
GFXTIM_FCKCAL,
EVENTOUT
M1
- - - - - J8 132 140 J6 - R1 - - 107 VSS S - - - -
5
- - - - - - 133 141 - - - - - - 108 VDD S - - - -

TIM1_CH3N,
SPI2_SCK/I2S2_CK,
PSSI_D5,
- D10 B8 D9 C11 D12 134 142 C11 - A12 A12 - - 109 PD3 I/O FT_h - USART2_CTS/USART2_NS -
S, FMC_NWAIT,
DCMIPP_D5, LCD_B1,
EVENTOUT
DCMIPP_HSYNC, PSSI_DE,
USART2_RTS, TAMP_IN6/TAM
- B12 A8 B10 B12 A13 135 143 A11 - C11 C11 - - 110 PD4 I/O FT_h -
ETH_PHY_INTN, FMC_NL, P_OUT3
EVENTOUT
TIM1_CH4N, LCD_R7,
- - D8 D8 D10 B13 - 144 B11 - B11 B11 - - - PG0 I/O FT_h - -
EVENTOUT
120/320
- - C8 B9 A13 - - 145 C10 - E10 E10 - - - PG1 I/O FT_h - LCD_R6, EVENTOUT -
121/320 Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
C8 E8 - - E9 C12 136 - - D3 D10 D10 - 73 111 PM0 I/O FT_c - - UCPD_CC1

DS14359 Rev 2
B10 C10 - - B11 B12 137 - - E4 C10 C10 - 74 112 PM1 I/O FT_c - - UCPD_CC2
A10 B10 - - A11 C11 138 - - H5 B10 B10 - 75 113 PM2 I/O FT_d - - UCPD_DB1
B9 B11 - - A12 A12 139 - - F5 A10 A10 - 76 114 PM3 I/O FT_d - - UCPD_DB2
- - - - - J10 - - J8 - P9 R6 - - - VSS S - - - -
C6 A11 A7 A9 B10 B11 140 146 C9 A2 D9 D9 - 77 115 VDD50USB S - - - -
- - - - - - 141 147 - - - - 54 78 116 VDD33USB S - - - -
D6 D8 - - D8 C10 142 - J10 C4 E8 E8 - 79 117 VSSUSB S - - - -
B8 B9 - - A10 B10 143 - - A4 B9 B9 - 80 118 PM5 I/O FT_u - - OTG_HS_DM
A8 A9 - - A9 A10 144 - - B5 A9 A9 - 81 119 PM6 I/O FT_u - - OTG_HS_DP
B7 C8 - - E8 C9 145 - K3 D5 D8 D8 - 82 120 DVDD S - - - -
UART7_RX,
A9 B8 - - D9 A11 146 - - E6 C9 C9 - 83 121 PM8 I/O FT_u - -
OTG_HS_VBUS
A7 A8 - - C7 B9 147 - - C6 B8 B8 - 84 122 PM9 I/O FT_u - UART7_TX, OTG_HS_ID -
STM32H7Sxx8
- - - - - - 148 - - A8 - - - 85 123 VDD S - - - -
- - - - - K3 - - K6 - R1 R9 - - - VSS S - - - -
A6 B7 A6 B8 B8 A8 149 148 B10 A6 A7 A7 55 86 124 PM12 I/O FT_u - SPI5_NSS OTG_FS_DM

STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
B6 A7 B6 A8 A8 B8 150 149 A10 B7 B7 B7 56 87 125 PM11 I/O FT_u - SPI5_SCK OTG_FS_DP

DS14359 Rev 2
A5 C7 E7 C7 B7 A9 151 150 A9 G6 C8 C8 57 88 126 PM14 I/O FT_u - SPI5_MISO, OTG_FS_VBUS -

B5 E6 D6 D7 D7 C8 152 151 B9 D7 C7 C7 58 89 127 PM13 I/O FT_u - SPI5_MOSI, OTG_FS_ID -
A4 A6 C6 E7 E7 C7 153 152 B8 F7 A6 A6 59 90 128 BOOT0 I B - - [VPP]
TIM1_CH4N,
DCMIPP_PIXCLK,
TAMP_IN5/TAM
- B6 A5 A7 A7 A7 154 153 A8 - D7 D7 - - 129 PD5 I/O FT_h - PSSI_PDCK, USART2_TX,
P_OUT4
FMC_NCE, FMC_NE2,
EVENTOUT
SAI1_D1, ADF1_SDI0,
ETH_CLK,
SPI3_MOSI/I2S3_SDO,
- C6 B5 B7 B6 B7 155 154 B7 - E7 E7 - - 130 PD6 I/O FT_h - SAI1_SCK_A, USART2_RX, -
PSSI_D10, FMC_INT,
SDMMC2_CK, FMC_NE3,
122/320
123/320 Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
I_REF_CLK,
DS14359 Rev 2
SPI1_MOSI/I2S1_SDO,
PSSI_D2, USART2_CK,
- A5 A4 A6 A6 A6 156 155 A7 C8 B6 B6 - - 131 PD7 I/O FT_h - -
SPDIFRX_IN0,
SDMMC2_CMD,
FMC_D8/FMC_AD8,
DCMIPP_D2, EVENTOUT
- - - B6 - - - 156 C7 - C6 C6 - - - PG2 I/O FT_h - LCD_HSYNC, EVENTOUT -
DCMIPP_HSYNC, PSSI_DE,
- - - - - - - - A6 - A5 A5 - - - PG3 I/O FT_h - ETH_PPS_OUT, FMC_D21, -
EVENTOUT
- - - - - K6 - - K8 - R6 R12 - - 132 VSS S - - - -
- - - - - - 157 157 - - - - - - 133 VDD S - - - -

I2C2_SDA, LCD_R2,
- - - D6 D6 B6 158 158 B6 - B5 B5 - - - PF0 I/O FT_h - -
FMC_A8, EVENTOUT
I2C2_SCL, FMC_A9,
- - - A5 A5 A5 159 159 A5 - C5 C5 - - - PF1 I/O FT_h - -
STM32H7Sxx8
EVENTOUT
I2C2_SMBA, DCMIPP_D14,
- - - B5 B5 C6 160 160 C6 - A4 A4 - - - PF2 I/O FT_h - PSSI_D14, FMC_A10, -
EVENTOUT
STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
DCMIPP_D9, PSSI_D9,
- - - - - A4 161 161 A4 - A3 A3 - - - PF3 I/O FT_h - ETH_MII_CRS, FMC_A11, -
DS14359 Rev 2
EVENTOUT
DCMIPP_D8, PSSI_D8,
- - - - - B5 162 162 B5 - B4 B4 - - - PF4 I/O FT_h - ETH_MII_TX_ER, FMC_A13, -
EVENTOUT
JTDO-SWO, TIM2_CH2,
LPTIM4_IN1,
DCMIPP_HSYNC,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
PB3(JTDO/T
A3 B5 C5 A4 A4 B4 163 163 B4 E8 C4 C4 60 91 134 I/O FT_h - SPI6_SCK/I2S6_CK, -
RACESWO)
SDMMC2_D2, CRS_SYNC,
UART7_RX,
FMC_D14/FMC_AD14,
LCD_R4, PSSI_DE,
EVENTOUT
124/320
125/320 Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
NJTRST, TIM16_BKIN,
DS14359 Rev 2
DCMIPP_VSYNC,
SPI1_MISO/I2S1_SDI,
SPI3_MISO/I2S3_SDI,
PB4(NJTRS
B4 C5 E6 E6 E6 C5 164 164 C5 H7 D5 D5 61 92 135 I/O FT_h - SPI2_NSS/I2S2_WS, -
T)
SPI6_MISO/I2S6_SDI,
SDMMC2_D3, UART7_TX,
FMC_D13/FMC_AD13,
LCD_R3, PSSI_RDY,
EVENTOUT
TIM17_BKIN, TIM3_CH2,
LPTIM4_OUT, I2C1_SMBA,
SPI1_MOSI/I2S1_SDO,
PSSI_D10,
SPI3_MOSI/I2S3_SDO,
D4 A4 B4 B4 B4 A3 165 165 A3 D9 B3 B3 62 93 136 PB5 I/O FT_h - SPI6_MOSI/I2S6_SDO, -
FDCAN2_RX, LCD_R2,
ETH_PPS_OUT,
FMC_D12/FMC_AD12,
STM32H7Sxx8
DCMIPP_D10, UART5_RX,
EVENTOUT
C4 E5 E5 E5 E5 F6 166 166 F6 A10 E6 E6 63 94 137 VCAP4 S - - - -
- - - - - K8 167 167 K12 - R12 R15 64 95 138 VSS S - - - -

STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
E5 F6 F6 F6 F6 G7 168 168 G7 C10 G7 G7 - - - VDDLDO S - - - -

DS14359 Rev 2
- - - - - - 169 169 - - - - 65 96 139 VDD S - - - -

LPTIM1_ETR, TIM4_ETR,
LPTIM2_ETR, UART8_RX,
TAMP_IN4/TAM
- B4 - A3 A3 C4 170 170 C4 - A2 A2 - - 140 PE0 I/O FT_h - PSSI_D2, SAI2_MCLK_A,
P_OUT5
FMC_D9/FMC_AD9,
DCMIPP_D2, EVENTOUT
LPTIM1_IN2, LPTIM2_CH2,
UART8_TX, PSSI_D3, TAMP_IN3/TAM
- B3 B3 D5 D5 B2 171 171 B2 - C3 C3 - - 141 PE1 I/O FT_h -
FMC_D10/FMC_AD10, P_OUT6
DCMIPP_D3, EVENTOUT
TRACECLK, ADF1_CCK0,
SAI1_CK1, LPTIM5_IN1,
SPI4_SCK, SAI1_MCLK_A,
- C4 D5 B3 B3 B3 172 172 B3 - B2 B2 - - 142 PE2 I/O FT_h - -
ETH_MII_TXD3,
FMC_D11/FMC_AD11,
TIM1_CH2N, EVENTOUT
126/320
127/320 Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
I2C1_SCL/I3C1_SCL,
DS14359 Rev 2
HDMI_CEC, PSSI_D5,
USART1_TX, LPUART1_TX,
A2 A3 A3 A2 A2 A2 173 173 A2 F9 E5 E5 - 97 143 PB6 I/O FT_h - FDCAN2_TX, -
I_REF_CLK, FMC_SDNE1,
DCMIPP_D5, UART5_TX,
EVENTOUT
I2C1_SDA/I3C1_SDA,
DCMIPP_D1, PSSI_RDY,
USART1_RX, LPUART1_RX,
B3 D4 C4 B2 B2 C3 174 174 C3 G8 D4 D4 66 98 144 PB7 I/O FT_h - PSSI_D1, -
TXD1, FMC_SDCKE1,
DCMIPP_VSYNC,
UART5_TX, EVENTOUT
STM32H7Sxx8
STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
TIM16_CH1, TIM4_CH3,
USART3_CK,
DS14359 Rev 2
I2C1_SCL/I3C1_SCL,
PSSI_D6, SDMMC1_CKIN,
UART4_RX, FDCAN1_RX,
A1 A2 A2 A1 A1 B1 175 175 B1 J8 B1 B1 67 99 1 PB8 I/O FT_h - -
SDMMC2_D4,
ETH_MII_TXD3,
FMC_D9/FMC_AD9,
EVENTOUT
- - - - - J9 - - J9 - - - - - - VDDLDO S - - - -
D7 A10 B7 C8 C8 D9 - - D9 B3 F8 F8 - - - VDD33USB S - - - -
- - - - - K12 - - L1 - R15 - - - - VSS S - - - -
M1
- - - - - J4 - - H13 - M8 - - - VSS S - - - -
5
- - - - - H4 - - G8 - J10 J15 - - - VSS S - - - -
- K6 H10 J2 H11 F7 - - E12 - G12 G12 - - - VSS S - - - -
H6 F5 F10 G6 F11 E1 - - D11 - E9 E9 - - - VSS - - - - -
- - - - - R15 - - R15 - - - - - - VSS S - - - -

128/320
- - - - - R1 - - R1 - - - - - - VSS S - - - -
STM32H7Sxx8
Pin number
TFBGA225 OCTO SMPS
TFBGA225 HEXA SMPS

UFBGA144 SMPS GFx
UFBGA169 SMPS GFx
UFBGA176 SMPS GFx
WLCSP101 SMPS GP
UFBGA144 SMPS GP
UFBGA169 SMPS GP
UFBGA176 SMPS GP
TFBGA100 SMPS GP
LQFP176 SMPS GFx

LQFP176 SMPS GP
I/O structure
VFQFPN68 GP
Pin type
Pin name
LQFP100 GP
LQFP144 GP
Notes
Additional
functions
after reset)
- - - - - N10 - - N10 - - - - - - VSS S - - - -

DS14359 Rev 2
- - - - - M11 - - M11 - - - - - - VSS S - - - -

- - - - - M9 - - M9 - - - - - - VSS S - - - -
- - - - - M7 - - M7 - - - - - - VSS S - - - -
- - - - - L3 - - L3 - - - - - - VSS S - - - -
- - - - - L1 - - - - - - - - - VSS S - - - -
129/320
STM32H7Sxx8
Table 22. STM32H7Sxx8 pin alternate functions
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
FDCAN1
FMC/SD GFXTIM/
CEC/DC /2/FMC/ CRS/FM
PSSI_/S MMC1/S LPUART
ADF1/L CEC/DC MIPP/SP OCTOS C/LCD/
GFXTIM/ AI1/SDM PI2/I2S2 1/PSSI_/ ETH/LC FMC/LC
Port ADF1/L PTIM2/3/ MIPP/ET I1/I2S1/ PIM_P1/ OTG1_F FMC/GF
PDM_S MC1/SPI /SPI3/I2 SAI2/SD D/MDIO DCMIPP D/MDIO
PTIM1/T 4/5/LPU H/I2C/I3 SPI2/I2S 2/PSSI_/ S/OTG1 XTIM/LC
SYS AI1/TIM 3/I2S3/S S3/SPI6/ MMC1/S S/SDMM /GFXTIM S/PSSI_/ SYS
IM1/2/16 ART1/TI C/I2C2/3 2/SPI3/I SDMMC _HS/SAI D/SDMM
2/3/4/5/1 PI4/UAR I2S6/UA PDIFRX/ C1/2/UA /LCD TIM1/UA
/17 M9/USA /TIM15/ 2S3/SPI 2/SPDIF 2/SDMM C1
2/15 T4/UCP RT7/US SPI6/I2S RT7 RT5
RT3 USART1 4/5/SPI6 RX/SPI5 C2/SPI1/
D ART1/2/ 6/UART
/I2S6 /TIM13/1 I2S1
3 4/5/8
4
USART2
SPI6_N FMC_A
TIM2_C TIM5_C TIM9_C TIM15_ _CTS/U UART4_ SDMMC SAI2_S EVENT
PA0 - SS/I2S6 - - D7/FMC LCD_G3 -
H1 H1 H1 BKIN SART2_ TX 2_CMD D_B OUT
_WS _D7
NSS
ETH_MII
_RX_CL FMC_A
TIM2_C TIM5_C LPTIM3_ TIM15_ DCMIPP PSSI_D USART2 UART4_ SAI2_M EVENT
PA1 - - K/ETH_ D6/FMC LCD_G2 -
H2 H2 IN1 CH1N _D0 0 _RTS RX CLK_B OUT
RMII_RE _D6
DS14359 Rev 2
F_CLK
FMC_A
TIM2_C TIM5_C LPTIM3_ TIM15_ USART2 SAI2_S ETH_M MDIOS_ EVENT
PA2 - - - - D5/FMC LCD_B7
H3 H3 IN2 CH1 _TX CK_B DIO MDIO OUT
_D5
GFXTIM GFXTIM
TIM2_C TIM5_C LPTIM3_ TIM15_ I2S6_M SPI4_R USART2 SPI5_R SPI1_R ETH_MII TIM1_C EVENT
PA3 - _LCKCA _FCKCA LCD_DE
H4 H4 CH1 CH2 CK DY _RX DY DY _COL H3 OUT
L L
Port A
SPI1_N SPI3_N SPI6_N
TIM5_E LPTIM3_ USART2 PSSI_D OTG_H ETH_M DCMIPP EVENT
PA4 - - - SS/I2S1 SS/I2S3 SS/I2S6 LCD_R3 -
TR CH2 _CK E S_SOF DIO _HSYNC OUT
_WS _WS _WS
SPI1_S SPI6_S
PWR_CSTO TIM2_C TIM2_E TIM9_C PSSI_D FMC_N DCMIPP LCD_CL EVENT
PA5 - CK/I2S1 - CK/I2S6 - - -
P H1 TR H2 8 OE _D8 K OUT
_CK _CK
SPI1_MI SPI6_MI DCMIPP

PWR_CSLE TIM1_B TIM3_C LPTIM3_ PSSI_P TIM13_ MDIOS_ LCD_HS EVENT
PA6 - SO/I2S1 - SO/I2S6 - LCD_B7 _PIXCL
EP KIN H1 ETR DCK CH1 MDC YNC OUT
_SDI _SDI K
ETH_MII
SPI1_M SPI6_M _RX_DV
TIM1_C TIM3_C TIM14_ FMC_IN EVENT
PA7 - - - OSI/I2S1 - - OSI/I2S6 LCD_R4 /ETH_R LCD_B1 -
H1N H2 CH1 T OUT
_SDO _SDO MII_CRS
_DV
130/320
Table 22. STM32H7Sxx8 pin alternate functions (continued)
131/320 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
FDCAN1
FMC/SD GFXTIM/
D ART1/2/ 6/UART
/I2S6 /TIM13/1 I2S1
3 4/5/8
4
FMC_A
TIM1_C I2C3_SC USART1 OTG_FS UART7_ EVENT
PA8 MCO1 - - - - - - D4/FMC LCD_B6 -
H1 L _CK _SOF RX OUT
_D4
SPI2_S FMC_A
TIM1_C LPUART I2C3_SD PSSI_D USART1 DCMIPP EVENT
PA9 - - CK/I2S2 - - - - D3/FMC LCD_B5
H2 1_TX A 0 _TX _D0 OUT
_CK _D3
FMC_A
TIM1_C LPUART PSSI_D USART1 MDIOS_ DCMIPP EVENT
PA10 - - - - - - D2/FMC LCD_B4
H3 1_RX 1 _RX MDIO _D1 OUT
DS14359 Rev 2
_D2
USART1
SPI2_N FMC_A
TIM1_C LPUART UART4_ _CTS/U FDCAN1 EVENT
PA11 - - - SS/I2S2 - - - D1/FMC LCD_B3 -
H4 1_CTS RX SART1_ _RX OUT
Port A _WS _D1
NSS
SPI2_S FMC_A
TIM1_E LPUART UART4_ USART1 SAI2_FS FDCAN1 EVENT
PA12 - - - CK/I2S2 - - D0/FMC LCD_B2 -
TR 1_RTS TX _RTS _B _TX OUT
_CK _D0
JTMS- EVENT
PA13 - - - - - - - - - - - - - -
SWDIO OUT
JTCK- EVENT
PA14 - - - - - - - - - - - - - -
SWCLK OUT
SPI1_N SPI3_N SPI6_N FMC_D1

TIM2_C TIM2_E HDMI_C UART4_ UART7_ EVENT
PA15 JTDI - SS/I2S1 SS/I2S3 SS/I2S6 - - 5/FMC_ LCD_R5 -
H1 TR EC RTS TX OUT
_WS _WS _WS AD15
STM32H7Sxx8
STM32H7Sxx8
FDCAN1
FMC/SD GFXTIM/
D ART1/2/ 6/UART
/I2S6 /TIM13/1 I2S1
3 4/5/8
4
ETH_MII
SPI1_S
TIM1_C TIM3_C TIM9_C UART4_ _TXD0/E GFXTIM LCD_VS EVENT
PB0 - - CK/I2S1 - - - - -
H2N H3 H1 CTS TH_RMII _TE YNC OUT
_CK
_TXD0
ETH_MII
TIM1_C TIM3_C TIM9_C FDCAN2 _TXD1/E FMC_N EVENT
PB1 - - - - - - LCD_G2 - -
H3N H4 H2 _TX TH_RMII OE OUT
_TXD1
DS14359 Rev 2
SPI3_M
ADF1_S SAI1_S FMC_N EVENT
PB2 RTC_OUT2 - SAI1_D1 - - OSI/I2S3 - - LCD_B2 - -
DI0 D_A WE OUT
_SDO
SPI1_S SPI3_S SPI6_S FMC_D1

TIM2_C LPTIM4_ DCMIPP SDMMC CRS_SY UART7_ PSSI_D EVENT
PB3 JTDO-SWO - CK/I2S1 CK/I2S3 - CK/I2S6 4/FMC_ LCD_R4
H2 IN1 _HSYNC 2_D2 NC RX E OUT
_CK _CK _CK AD14
SPI1_MI SPI3_MI SPI2_N SPI6_MI FMC_D1

TIM16_B TIM3_C LPTIM4_ DCMIPP SDMMC UART7_ PSSI_R EVENT
PB4 NJTRST SO/I2S1 SO/I2S3 SS/I2S2 SO/I2S6 - 3/FMC_ LCD_R3
Port B KIN H1 ETR _VSYNC 2_D3 TX DY OUT
_SDI _SDI _WS _SDI AD13
SPI1_M SPI3_M SPI6_M FMC_D1

TIM17_B TIM3_C LPTIM4_ I2C1_S PSSI_D FDCAN2 ETH_PP DCMIPP UART5_ EVENT
PB5 - OSI/I2S1 OSI/I2S3 OSI/I2S6 LCD_R2 2/FMC_
KIN H2 OUT MBA 10 _RX S_OUT _D10 RX OUT
_SDO _SDO _SDO AD12
ETH_MII
I2C1_SC _RX_CL
TIM16_ TIM4_C HDMI_C PSSI_D USART1 LPUART FDCAN2 FMC_S DCMIPP UART5_ EVENT
PB6 - - L/I3C1_ - K/ETH_
CH1N H1 EC 5 _TX 1_TX _TX DNE1 _D5 TX OUT
SCL RMII_RE
F_CLK
ETH_MII
I2C1_SD
TIM17_ TIM4_C DCMIPP PSSI_R USART1 LPUART PSSI_D _TXD1/E FMC_S DCMIPP UART5_ EVENT
PB7 - - A/I3C1_ -
CH1N H2 _D1 DY _RX 1_RX 1 TH_RMII DCKE1 _VSYNC TX OUT
SDA
_TXD1
I2C1_SC FMC_D9
TIM16_ TIM4_C USART3 PSSI_D SDMMC UART4_ FDCAN1 SDMMC ETH_MII SDMMC DCMIPP EVENT
PB8 - L/I3C1_ - /FMC_A
CH1 H3 _CK 6 1_CKIN RX _RX 2_D4 _TXD3 1_D4 _D6 OUT
132/320
SCL D9
FDCAN1
FMC/SD GFXTIM/
D ART1/2/ 6/UART
/I2S6 /TIM13/1 I2S1
3 4/5/8
4
I2C1_SD SPI2_N
TIM17_ TIM4_C PSSI_D SDMMC UART4_ FDCAN1 SDMMC SDMMC DCMIPP EVENT
PB9 - - A/I3C1_ SS/I2S2 -
CH1 H4 7 1_CDIR TX _TX 2_D5 1_D5 _D7 OUT
SDA _WS
SPI2_S FMC_D1
TIM2_C LPTIM2_ I2C2_SC USART3 ETH_MII EVENT
PB10 - - CK/I2S2 - - - - 1/FMC_ LCD_G7 -
H3 IN1 L _TX _RX_ER OUT
_CK AD11
ETH_MII
_TX_EN/ FMC_D1
TIM2_C LPTIM2_ I2C2_SD USART3 EVENT
DS14359 Rev 2
PB11 - - - - - - - ETH_R 0/FMC_ LCD_G6 -

H4 ETR A _RX OUT
MII_TX_ AD10
EN
SPI2_N FMC_D9
Port B TIM1_B LPTIM2_ I2C2_S USART3 FDCAN2 UART5_ EVENT
PB12 - - SS/I2S2 - - - - /FMC_A LCD_G5
KIN IN2 MBA _CK _RX RX OUT
_WS D9
USART3
SPI2_S FMC_D8
TIM1_C LPTIM2_ SDMMC _CTS/U PSSI_D FDCAN2 ETH_MII DCMIPP UART5_ EVENT
PB13 - - - CK/I2S2 LCD_G4 /FMC_A
H1N CH1 1_D0 SART3_ 2 _TX _RXD3 _D2 TX OUT
_CK D8
NSS
SPI2_MI
TIM1_C TIM12_ LPTIM2_ USART1 USART3 UART4_ SDMMC FMC_N EVENT
PB14 - SO/I2S2 - - - LCD_DE -
H2N CH1 CH2 _TX _RTS RTS 2_D0 E1 OUT
_SDI
SPI2_M
TIM1_C TIM12_ USART1 UART4_ SDMMC FMC_A2 EVENT
PB15 RTC_REFIN - OSI/I2S2 - - LCD_G7 - - -
H3N CH2 _RX CTS 2_D1 0 OUT
_SDO
GFXTIM GFXTIM
SAI2_FS FMC_N EVENT
PC0 - - _FCKCA - - - - - - - - _LCKCA -
_B BL1 OUT
L L
STM32H7Sxx8
SPI2_M
ADF1_S SAI1_S FMC_A1 SDMMC ETH_M MDIOS_ EVENT
Port C PC1 TRACED0 - SAI1_D1 - OSI/I2S2 - - FMC_A0 -
DI0 D_A 6 2_CK DC MDC OUT
_SDO
SPI2_MI
TIM1_C FMC_A1 ETH_MII EVENT
PC2 - - - - SO/I2S2 - - - - FMC_A1 - -
H1 7 _TXD2 OUT
_SDI
STM32H7Sxx8
FDCAN1
FMC/SD GFXTIM/
D ART1/2/ 6/UART
/I2S6 /TIM13/1 I2S1
3 4/5/8
4
SPI2_M ETH_MII
TIM1_C FMC_A1 EVENT
PC3 - - - - OSI/I2S2 - - - - _TX_CL FMC_A2 - -
H2 8 OUT
_SDO K
ETH_MII
_RXD0/
I2S1_M FMC_A1 SPDIFR EVENT
PC4 - - - - - - - - ETH_R FMC_A3 - -
CK 9 X_IN2 OUT
MII_RXD
0
DS14359 Rev 2
ETH_MII
_RXD1/
DCMIPP PSSI_D FMC_A2 SPDIFR EVENT
PC5 - - SAI1_D3 - - - - ETH_R FMC_A5 - -
_D15 15 1 X_IN3 OUT
MII_RXD
1
SDMMC
TIM3_C TIM9_C I2S2_M PSSI_D SDMMC SDMMC DCMIPP EVENT
PC6 - - - - - 1_D0DI - -
H1 H1 CK 0 2_D6 1_D6 _D0 OUT
R
Port C SDMMC
TIM3_C TIM9_C I2S3_M PSSI_D SDMMC SDMMC DCMIPP EVENT
PC7 TRGIO - - - - 1_D123 - -
H2 H2 CK 1 2_D7 1_D7 _D1 OUT
DIR
TIM3_C I2C3_S UART5_ PSSI_D SDMMC DCMIPP EVENT

PC8 TRACED1 - - - - - - - -
H3 MBA RTS 2 1_D0 _D2 OUT
TIM3_C I2C3_SD I2S_CKI UART5_ PSSI_D SDMMC DCMIPP EVENT

PC9 MCO2 - - - - - - -
H4 A N CTS 3 1_D1 _D3 OUT
SPI3_S
TIM1_B USART3 UART4_ PSSI_D SDMMC DCMIPP EVENT
PC10 - - - - - CK/I2S3 - - -
KIN _TX TX 14 1_D2 _D14 OUT
_CK
SPI3_MI
USART3 UART4_ PSSI_D SDMMC DCMIPP EVENT
PC11 - - - - - SO/I2S3 - - -
_RX RX 4 1_D3 _D4 OUT
_SDI
SPI6_S SPI3_M
TIM1_C TIM15_ USART3 UART5_ PSSI_D SDMMC DCMIPP EVENT
PC12 TRACED3 - - CK/I2S6 OSI/I2S3 - - -
134/320
H4 CH1 _CK TX 9 1_CK _D9 OUT

_CK _SDO
FDCAN1
FMC/SD GFXTIM/
D ART1/2/ 6/UART
/I2S6 /TIM13/1 I2S1
3 4/5/8
4
EVENT
PC13 - - - - - - - - - - - - - - -
OUT
EVENT
Port C PC14 - - - - - - - - - - - - - - -
OUT
EVENT
PC15 - - - - - - - - - - - - - - -
OUT
PSSI_D FMC_A2 UART4_ FDCAN1 DCMIPP EVENT

PD0 - - - - - - - - FMC_A6 -
DS14359 Rev 2
E 2 RX _RX _HSYNC OUT
FMC_A2 UART4_ FDCAN1 EVENT

PD1 - - - - - - - - - FMC_A7 - -
3 TX _TX OUT
TIM1_E TIM3_E TIM15_B PSSI_D UART5_ SDMMC DCMIPP EVENT

PD2 TRACED2 - -
TR TR KIN 11 RX 1_CMD _D11 OUT
USART2
SPI2_S
TIM1_C PSSI_D _CTS/U FMC_N DCMIPP EVENT
PD3 - - - - CK/I2S2 - - - LCD_B1
H3N 5 SART2_ WAIT _D5 OUT
_CK
NSS
DCMIPP PSSI_D USART2 ETH_PH EVENT

Port D PD4 - - - - - - - FMC_NL - -
_HSYNC E _RTS Y_INTN OUT
DCMIPP
TIM1_C PSSI_P USART2 FMC_N FMC_N EVENT
PD5 - - - - _PIXCL - - - -
H4N DCK _TX CE E2 OUT
K
SPI3_M
ADF1_S ETH_CL SAI1_S USART2 PSSI_D FMC_IN SDMMC FMC_N DCMIPP EVENT
PD6 - - SAI1_D1 OSI/I2S3 - -
DI0 K CK_A _RX 10 T 2_CK E3 _D10 OUT
_SDO
ETH_MII
STM32H7Sxx8
_RX_CL SPI1_M FMC_D8
PSSI_D USART2 SPDIFR SDMMC DCMIPP EVENT
PD7 - - - - K/ETH_ OSI/I2S1 - /FMC_A -
2 _CK X_IN0 2_CMD _D2 OUT
RMII_RE _SDO D8
F_CLK
STM32H7Sxx8
FDCAN1
FMC/SD GFXTIM/
D ART1/2/ 6/UART
/I2S6 /TIM13/1 I2S1
3 4/5/8
4
ETH_MII
_TX_EN/
USART3 SPDIFR FMC_N EVENT
PD8 - - - - - - - - - ETH_R LCD_R0 -
_TX X_IN1 BL0 OUT
MII_TX_
EN
USART3 FMC_S EVENT

PD9 - - - - - - - - - - - LCD_R1 -
_RX DCLK OUT
TIM1_C DCMIPP SPI4_R USART3 PSSI_D SPI5_R SPI1_R FMC_CL EVENT

PD10 - - - - - LCD_B0 -
DS14359 Rev 2
H4 _D4 DY _CK 4 DY DY K OUT
USART3
Port D TIM1_E LPTIM2_ DCMIPP _CTS/U PSSI_D SAI2_S FMC_D1 EVENT
PD11 - - - - - - - -
TR IN2 _D6 SART3_ 6 D_A 6 OUT
NSS
LPTIM1_ TIM4_C LPTIM2_ USART3 PSSI_D SAI2_FS FMC_N DCMIPP EVENT

PD12 - - - - - - LCD_DE
IN1 H1 IN1 _RTS 12 _A E1 _D12 OUT
LPTIM1_ TIM4_C UCPD_F SAI2_S PSSI_D FMC_IN DCMIPP EVENT

PD13 - - - - - - -
CH1 H2 RSTX2 CK_A 13 T _D13 OUT
LPTIM1_ TIM4_C LPTIM2_ DCMIPP UCPD_F UART8_ PSSI_D FMC_D1 EVENT

PD14 - - - - - - -
CH2 H3 CH1 _D7 RSTX1 CTS 7 7 OUT
TIM4_C LPTIM5_ DCMIPP UCPD_F UART8_ PSSI_D FMC_D1 EVENT

PD15 - - - - - - - -
H4 OUT _D9 RSTX2 RTS 9 8 OUT
136/320
FDCAN1
FMC/SD GFXTIM/
D ART1/2/ 6/UART
/I2S6 /TIM13/1 I2S1
3 4/5/8
4
FMC_D9
LPTIM1_ TIM4_E LPTIM2_ UART8_ PSSI_D SAI2_M DCMIPP EVENT
PE0 - - - - - - /FMC_A -
ETR TR ETR RX 2 CLK_A _D2 OUT
D9
FMC_D1
LPTIM1_ LPTIM2_ UART8_ PSSI_D DCMIPP EVENT
PE1 - - - - - - - - 0/FMC_ -
IN2 CH2 TX 3 _D3 OUT
AD10
FMC_D1
ADF1_C SAI1_C LPTIM5_ SPI4_S SAI1_M ETH_MII TIM1_C EVENT
PE2 TRACECLK - - - - 1/FMC_ -
CK0 K1 IN1 CK CLK_A _TXD3 H2N OUT
DS14359 Rev 2
AD11
FMC_D1
LPTIM5_ TIM15_B SAI1_S ETH_MII EVENT
PE3 TRACED0 - - - - - - 2/FMC_ - -
ETR KIN D_B _RXD3 OUT
AD12
FMC_D1
ADF1_S TIM15_ SPI4_N SAI1_FS PSSI_D DCMIPP EVENT
PE4 TRACED1 - SAI1_D2 - - - 3/FMC_ -
DI0 CH1N SS _A 4 _D4 OUT
AD13
FMC_D1
Port E ADF1_C SAI1_C TIM15_ SPI4_MI SAI1_S PSSI_D DCMIPP EVENT
PE5 TRACED2 - - - 4/FMC_ -
CK1 K2 CH1 SO CK_A 6 _D6 OUT
AD14
FMC_D1
TIM1_B ADF1_S TIM15_ SPI4_M SAI1_S PSSI_D SAI2_M DCMIPP EVENT
PE6 TRACED3 SAI1_D1 - - - 5/FMC_ -
KIN2 DI0 CH2 OSI D_A 7 CLK_B _D7 OUT
AD15
TIM1_E UART7_ FMC_A2 SAI2_S EVENT

PE7 - - - - - - - - FMC_A4 - -
TR RX 0 D_B OUT
TIM1_C UART7_ FMC_A1 EVENT

PE8 - - - - - - - - - - - -
H1N TX 2 OUT
TIM1_C UART7_ FMC_A1 FMC_BA EVENT

PE9 - - - - - - - - - - -
STM32H7Sxx8
H1 RTS 4 0 OUT
TIM1_C UART7_ FMC_A1 FMC_BA EVENT

PE10 - - - - - - - - - - -
H2N CTS 5 1 OUT
TIM1_C SPI4_N SAI2_S LCD_VS FMC_S EVENT

PE11 - - - - - - - - - -
H2 SS D_B YNC DNWE OUT
STM32H7Sxx8
FDCAN1
FMC/SD GFXTIM/
D ART1/2/ 6/UART
/I2S6 /TIM13/1 I2S1
3 4/5/8
4
TIM1_C SPI4_S SAI2_S FMC_S EVENT

PE12 - - - - - - - - - - -
H3N CK CK_B DNRAS OUT
TIM1_C SPI4_MI SAI2_FS FMC_S EVENT

PE13 - - - - - - - - - - -
H3 SO _B DNCAS OUT
Port E GFXTIM GFXTIM

TIM1_C SPI4_M SAI2_M FMC_S EVENT
PE14 - _FCKCA - - - - - - - _LCKCA -
H4 OSI CLK_B DNE0 OUT
L L
DS14359 Rev 2
GFXTIM GFXTIM
TIM1_B FMC_S EVENT
PE15 - _LCKCA - - - - - - - - - _FCKCA -
KIN DCKE0 OUT
L L
I2C2_SD EVENT
PF0 - - - - - - - - - - LCD_R2 FMC_A8 - -
A OUT
Port F
I2C2_SC EVENT
PF1 - - - - - - - - - - FMC_A9 - -
L OUT
138/320
FDCAN1
FMC/SD GFXTIM/
D ART1/2/ 6/UART
/I2S6 /TIM13/1 I2S1
3 4/5/8
4
I2C2_S DCMIPP PSSI_D FMC_A1 EVENT

PF2 - - - - - - - - - - -
MBA _D14 14 0 OUT
DCMIPP PSSI_D ETH_MII FMC_A1 EVENT

PF3 - - - - - - - - - - -
_D9 9 _CRS 1 OUT
DS14359 Rev 2
DCMIPP PSSI_D ETH_MII FMC_A1 EVENT

PF4 - - - - - - - - - - -
_D8 8 _TX_ER 3 OUT
DCMIPP UCPD_F PSSI_D FMC_CL ETH_MII FMC_A1 EVENT

Port F PF5 - - - - - - - - -
_D15 RSTX1 15 E _RXD2 6 OUT
TIM16_ SPI5_N SAI1_S UART7_ FMC_AL FMC_A1 EVENT

PF6 - - - - - - - -
CH1 SS D_B RX E 7 OUT
TIM17_ SPI5_S SAI1_M UART7_ FMC_A1 EVENT

PF7 - - - - - - - - LCD_G0 -
CH1 CK CLK_B TX 8 OUT
STM32H7Sxx8
DCMIPP
TIM16_ SPI5_MI SAI1_S UART7_ PSSI_P TIM13_ FMC_A1 EVENT
PF8 - - - _PIXCL - - LCD_G1 -
CH1N SO CK_B RTS DCK CH1 9 OUT
K
STM32H7Sxx8
FDCAN1
FMC/SD GFXTIM/
D ART1/2/ 6/UART
/I2S6 /TIM13/1 I2S1
3 4/5/8
4
TIM17_ SPI5_M SAI1_FS UART7_ TIM14_ FMC_A2 EVENT

PF9 - - - - - - - LCD_R0 -
CH1N OSI _B CTS CH1 1 OUT
TIM16_B DCMIPP PSSI_D PSSI_D FMC_A2 DCMIPP EVENT

PF10 - SAI1_D3 - - - - - - LCD_R1
KIN _D15 15 11 2 _D11 OUT
DS14359 Rev 2
SPI5_M PSSI_D SAI2_S FMC_A2 DCMIPP EVENT

PF11 - - - - - - - - - LCD_B0
OSI 12 D_B 3 _D12 OUT
USART1 SPI5_MI FMC_D1 EVENT

Port F PF12 - - - - - - - - - - - -
_RX SO 9 OUT
USART1 SPI5_N PSSI_D FMC_D2 DCMIPP EVENT

PF13 - - - - - - - - - -
_TX SS 10 0 _D10 OUT
USART1 SPI5_M FMC_A2 EVENT

PF14 - - - - - - - - - - LCD_G0 -
_CTS OSI 4 OUT
USART1 SPI5_S FMC_A2 EVENT

PF15 - - - - - - - - - - LCD_G1 -
_RTS CK 5 OUT
140/320
FDCAN1
FMC/SD GFXTIM/
D ART1/2/ 6/UART
/I2S6 /TIM13/1 I2S1
3 4/5/8
4
TIM1_C EVENT
PG0 - - - - - - - - - - - - LCD_R7 -
H4N OUT
EVENT
PG1 - - - - - - - - - - - - - LCD_R6 -
OUT
LCD_HS EVENT
PG2 - - - - - - - - - - - - - -
YNC OUT
DCMIPP PSSI_D ETH_PP FMC_D2 EVENT

PG3 - - - - - - - - - -
DS14359 Rev 2
_HSYNC E S_OUT 1 OUT
ETH_MII
_RXD0/
TIM1_B FMC_D2 EVENT
PG4 - - - - - - - - - - ETH_R - -
KIN2 2 OUT
MII_RXD
0
ETH_MII
_RXD1/
TIM1_E FMC_D2 EVENT
Port G PG5 - - - - - - - - - - ETH_R - -
TR 3 OUT
MII_RXD
1
TIM17_B PSSI_D ETH_M FMC_N DCMIPP EVENT

PG6 - - - - - - -
KIN 12 DC BL2 _D12 OUT
SAI1_M PSSI_D FMC_D2 DCMIPP EVENT

PG7 - - - - - - - - - -
CLK_A 13 4 _D13 OUT
SPI6_N
SPDIFR ETH_PP FMC_D2 EVENT
PG8 - - - - - SS/I2S6 - - - - LCD_G0 -
X_IN2 S_OUT 5 OUT
_WS
SPI1_MI
SPDIFR PSSI_R SAI2_FS SDMMC FMC_D2 DCMIPP EVENT
STM32H7Sxx8
PG9 - - - - - SO/I2S1 - - -
X_IN3 DY _B 2_D0 6 _VSYNC OUT
_SDI
SPI1_N
PSSI_D SAI2_S SDMMC FMC_D2 DCMIPP EVENT
PG10 - - - - - SS/I2S1 - - -
2 D_B 2_D1 7 _D2 OUT
_WS
STM32H7Sxx8
FDCAN1
FMC/SD GFXTIM/
D ART1/2/ 6/UART
/I2S6 /TIM13/1 I2S1
3 4/5/8
4
ETH_MII
SPI1_S _TX_EN/
LPTIM1_ SPDIFR PSSI_D SDMMC FMC_D2 DCMIPP EVENT
Port G PG11 - - - - CK/I2S1 - - ETH_R -
IN2 X_IN0 3 2_D2 8 _D3 OUT
_CK MII_TX_
EN
EVENT
PH0 - - - - - - - - - - - - - - -
OUT
Port H
EVENT
PH1 - - - - - - - - - - - - - - -
DS14359 Rev 2
OUT
UCPD_
PM0 - - - - - - - - - - - - - - -
CC1
UCPD_
PM1 - - - - - - - - - - - - - - -
CC2
UCPD_
PM2 - - - - - - - - - - - - - - -
DB1
UCPD_
PM3 - - - - - - - - - - - - - - -
DB2
OTG_H
PM5 - - - - - - - - - - - - - - -
S_DM
Port M
OTG_H
PM6 - - - - - - - - - - - - - - -
S_DP
UART7_ OTG_H
PM8 - - - - - - - - - - - - - -
RX S_VBUS
UART7_ OTG_H
PM9 - - - - - - - - - - - - - -
TX S_ID
SPI5_S OTG_FS
PM11 - - - - - - - - - - - - - -
CK _DP
SPI5_N OTG_FS
142/320
PM12 - - - - - - - - - - - - - -
SS _DM
FDCAN1
FMC/SD GFXTIM/
D ART1/2/ 6/UART
/I2S6 /TIM13/1 I2S1
3 4/5/8
4
SPI5_M OTG_FS
PM13 - - - - - - - - - - - - - -
OSI _ID
Port M
SPI5_MI OTG_FS
PM14 - - - - - - - - - - - - - -
SO _VBUS
XSPIM_
FMC_N
PN0 - - - - - - - - - P2_DQS - - - - -
E4
0
DS14359 Rev 2
XSPIM_
FMC_N
PN1 - - - - - - - - - P2_NCS - - - - -
BL0
1
FMC_D0
XSPIM_
PN2 - - - - - - - - - - - /FMC_A - - -
P2_IO0
D0
FMC_D1
XSPIM_
PN3 - - - - - - - - - - - /FMC_A - - -
P2_IO1
D1
FMC_D2
Port N XSPIM_
PN4 - - - - - - - - - - - /FMC_A - - -
P2_IO2
D2
FMC_D3
XSPIM_
PN5 - - - - - - - - - - - /FMC_A - - -
P2_IO3
D3
XSPIM_ FMC_S
PN6 - - - - - - - - - - - - - -
P2_CLK DCLK
XSPIM_
FMC_CL
PN7 - - - - - - - - - P2_NCL - - - - -
K
STM32H7Sxx8
K
FMC_D4
XSPIM_
PN8 - - - - - - - - - - - /FMC_A - - -
P2_IO4
D4
STM32H7Sxx8
FDCAN1
FMC/SD GFXTIM/
D ART1/2/ 6/UART
/I2S6 /TIM13/1 I2S1
3 4/5/8
4
FMC_D5
XSPIM_
PN9 - - - - - - - - - - - /FMC_A - - -
P2_IO5
D5
FMC_D6
XSPIM_
PN10 - - - - - - - - - - - /FMC_A - - -
P2_IO6
D6
Port N
FMC_D7
XSPIM_
PN11 - - - - - - - - - - - /FMC_A - - -
P2_IO7
DS14359 Rev 2
D7
XSPIM_
PN12 - - - - - - - - - P2_NCS - - - - - -
2
XSPIM_
PO0 - - - - - - - - - P1_NCS - - - - - -
1
XSPIM_
PO1 - - - - - - - - - P1_NCS - - - - - -
2
XSPIM_
PO2 - - - - - - - - - P1_DQS - - - - - -
Port O 0
XSPIM_
PO3 - - - - - - - - - P1_DQS - - - - - -
1
XSPIM_
PO4 - - - - - - - - - - - - - - -
P1_CLK
XSPIM_
PO5 - - - - - - - - - P1_NCL - - - - - -
K
144/320
FDCAN1
FMC/SD GFXTIM/
D ART1/2/ 6/UART
/I2S6 /TIM13/1 I2S1
3 4/5/8
4
XSPIM_
PP0 - - - - - - - - - - - - - - -
P1_IO0
XSPIM_
PP1 - - - - - - - - - - - - - - -
P1_IO1
XSPIM_
PP2 - - - - - - - - - - - - - - -
P1_IO2
XSPIM_
PP3 - - - - - - - - - - - - - - -
DS14359 Rev 2
P1_IO3
XSPIM_
PP4 - - - - - - - - - - - - - - -
P1_IO4
XSPIM_
PP5 - - - - - - - - - - - - - - -
P1_IO5
XSPIM_
PP6 - - - - - - - - - - - - - - -
P1_IO6
Port P
XSPIM_
PP7 - - - - - - - - - - - - - - -
P1_IO7
XSPIM_
PP8 - - - - - - - - - - - - - - -
P1_IO8
XSPIM_
PP9 - - - - - - - - - - - - - - -
P1_IO9
XSPIM_
PP10 - - - - - - - - - - - - - - -
P1_IO10
XSPIM_
PP11 - - - - - - - - - - - - - - -
P1_IO11
STM32H7Sxx8
XSPIM_
PP12 - - - - - - - - - - - - - - -
P1_IO12
XSPIM_
PP13 - - - - - - - - - - - - - - -
P1_IO13
STM32H7Sxx8
FDCAN1
FMC/SD GFXTIM/
D ART1/2/ 6/UART
/I2S6 /TIM13/1 I2S1
3 4/5/8
4
XSPIM_
PP14 - - - - - - - - - - - - - - -
P1_IO14
Port P
XSPIM_
PP15 - - - - - - - - - - - - - - -
P1_IO15
DS14359 Rev 2
146/320
STM32H7Sxx8 Memory mapping
5 Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
DS14359 Rev 2 147/320

147
Electrical characteristics STM32H7Sxx8
6 Electrical characteristics
The STM32H7Sxx8 uses a static voltage trimming mechanism to ensure that the maximum
frequency is reached with the minimum power consumption.
This mechanism is automatically selected when using a internal power supply. The static
voltage-trimming setting is die dependent, and cannot be modified. All values given in this
document are derived and guaranteed for an internal supply with LDO or SMPS only, and
not when a bypass mechanism is used.
6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with a junction temperature at TJ = 25 °C and TJ = TJmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus four times the
standard deviation (mean ±4σ).
6.1.2 Typical values

Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.0 V (for the
1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±4σ).
6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 21.
6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 22.
148/320 DS14359 Rev 2

STM32H7Sxx8 Electrical characteristics
Figure 21. Pin loading conditions Figure 22. Pin input voltage
MCU pin MCU pin
C = 50 pF VIN
MS19011V2 MS19010V2
DS14359 Rev 2 149/320

284
6.1.6 Power supply scheme
Figure 23. Power supply scheme
VDDSMPS
VLXSMPS Step
VFBSMPS Down
Converter
VSSSMPS
VCAP
Core domain (VCORE)
Voltage
VDDLDO
regulator
VSS
Level shifter
(CPU, System logic,

IO EXTI, Peripherals,
IOs
logic RAM)
VSS
VDD domain
HSI, CSI,
VDD HSI48, Power
VBAT HSE, PLLs switch
Backup domain
charging
VSW Backup VBKP
VBAT regulator
Power switch
LSI, LSE, RTC,

Wakeup logic, Backup
BKUP IO backup RAM
IOs logic registers, Reset
VSS
VDD50USB VSS
USB regulator
VDD33USB
DVDD
USB
FS, HS, UCPD
IOs
VDDA Analog domain
REF_BUF ADCs
VREF+ Temp.
VREF+
sensor
VREF- VREF-
VSSA
MSv53475V3
150/320 DS14359 Rev 2

6.1.7 Current consumption measurement
Figure 24. Current consumption measurement scheme
IDD_VBAT IDD_VBAT
VBAT VBAT
IDD IDD
VDD VDD
VDDLDO VDDSMPS
VDDA VDDA
DS14359 Rev 2 151/320

284
6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 23: Voltage characteristics,
Table 24: Current characteristics, and Table 25: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rat ing conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are
available on demand.
Table 23. Voltage characteristics

Symbols Ratings Min Max Unit
External main supply voltage (including

VDDX-VSS(1) VDD(2)(3)(4), VDDSMPS, VDDA, VDDUSB, -0.3 4.0
VDDXSPIx(2)(3)(4), VBAT, VREF+)
I/O supply when HSLV= 0 -0.3 4.0
VDDX-VSS(3)
I/O supply when HSLV= 1 - 2.8
V
MIN (MIN (VDD, VDDA, VDDUSB,
Input voltage on FT_xxx pins VSS−0.3
VBAT) + 4.0 V)(6)(7)
VIN(5) Input voltage on TT_xx pins VSS−0.3 4.0

Input voltage on BOOT0 pin VSS 9.0
Input voltage on any other pins VSS-0.3 4.0
Variations between different VDDX
|∆VDDX| - 50.0 mV
power pins of the same domain
Variations between all the different
|VSSX-VSS| - 50.0 mV
ground pins
Allowed voltage difference for Vref+ >
Vref-VDDA - 0.4 V
VDDA
1. All main power (VDD, VDDA, VDD33USB, VDDSMPS, VBAT) and ground (VSS, VSSA) pins must always be connected to the
external power supply, in the permitted range.
2. If HSLV = 0.
3. VDD, VDDXSP1, or VDDXSP2.
4. HSLV = High-speed low-voltage mode. Refer to General-purpose I/Os (GPIO) section of RM0477.
5. VIN maximum must always be respected. Refer to Table xx: Current characteristics for the maximum allowed injected
current values.
6. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
7. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
152/320 DS14359 Rev 2

Table 24. Current characteristics

Symbols Ratings Max Unit
ΣIVDD Total current into sum of all VDD power lines (source)(1) 620
(1)
ΣIVSS Total current out of sum of all VSS ground lines (sink) 620
(1)
IVDD Maximum current into each VDD power pin (source) 100
IVSS Maximum current out of each VSS ground pin (sink)(1) 100
Output current sunk or sourced by any I/O and control pin, except
IIO 20 mA
Pxy_C
Total output current sunk by sum of all I/Os and control pins(2) 140
ΣI(PIN)
(2)
Total output current sourced by sum of all I/Os and control pins 140
(3)(4)
IINJ(PIN) Injected current on FT_xxx, TT_xx, RST and B pins -5/+0
ΣIINJ(PIN) Total injected current (sum of all I/Os and control pins)(5) ±25
1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 23: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 25. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range -65 to +150

Maximum junction °C
TJ Industrial temperature range 6 125(1)
temperature
1. The junction temperature is limited to 105 °C in the VOS high voltage range.
DS14359 Rev 2 153/320

284
6.3 Operating conditions
6.3.1 General operating conditions
Table 26. General operating conditions

Symbol Parameter Operating conditions Min Typ Max Unit
(1)
Standard operating HSLV=0 1.71 - 3.6
VDD
voltage HSLV=1 1.71(1) - 2.7
Supply voltage for the
VDDLDO 1.71(1) - 3.6
internal regulator.
Supply voltage for the -
(2)
VDDSMPS internal SMPS step- 1.71(1) - 3.6
down converter
Octo and HexaSPI HSLV=0 1.71 - 3.6

VDDXSPIx
supply HSLV=1 1.08 - 2.7
USB regulator ON 4.0 5.0 5.5
VDD50USB(2) USB suply voltage
USB regulator OFF VDD33USB
USB used 3.0 - 3.6
VDD33USB USB suply voltage
USB not used 0 - 3.6
ADC used 1.62 -
Analog operating VREFBUF used 2.10 -
VDDA 3.6
voltage V
ADC, VREFBUF not
0 -
used
Supply voltage for
VBAT - 1.2(3) - 3.6
backup domain
BOOT0 -0.3 - 9.0
MIN (VDD,
VDDA,
VIN I/O Input voltage VDD33USB,
All IOs except BOOT0 -0.3 -
VDDXSPIx,
3.6 V)
<, 5.5 V(4)(5)
Internal regulator ON VOS low 1.1 1.21 1.26

(LDO or SMPS)(6) VOS high 1.1 1.36 1.4
Regulator OFF: VOS low 1.2 - 1.26

VCORE
external VCORE VOS high 1.37 - 1.4
voltage must be (7)
supplied from external SVOS low 0.7 0.74 0.8
regulator on VCAP pins SVOS high (7)
0.95 1 1.05
154/320 DS14359 Rev 2

Table 26. General operating conditions (continued)

Symbol Parameter Operating conditions Min Typ Max Unit
VOS low - - 400

fCPU CPU clock frequency
VOS high - - 600
VOS low - - 200
fACLK AXI clock frequency
VOS high - - 300
MHz
VOS low - - 200
fHCLK AHB clock frequency
VOS high - - 300
VOS low - - 100
Fpclk APB clock frequency
VOS high - - 150
Ambient temperature
Maximum power
TA for temperature -40 - 85
dissipation °C
range(8)
TJ Junction temperature VOS high -40 - 105
1. When RESET is released, functionality is guaranteed down to BOR level 0 minimum voltage.
2. Not available on every package.
3. VBAT minimum value can be reduced to 0 V if VDD is present.
4. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. Maximum
I/O input voltage is the smallest value between Min (VDD, VDDA, VDD33USB, VDDXSPIx) + 3.6 V < 5.5 V.
5. For operation with voltage higher than Min (VDD, VDDA, VDDUSB, and VDDXSPIx) +0.3 V, the internal Pull-up and Pull-Down
resistors must be disabled.
6. These values are factory trimmed per die.
7. Values for Regulator ON or OFF
8. The device junction temperature must be kept below maximum TJ indicated in Table 27: Supply voltage and maximum
temperature configuration and Section 7.12: Package thermal characteristics).
Table 27. Supply voltage and maximum temperature configuration

Power scale VCORE source Max. TJ (°C) Min. VDD(V) Min. VDDLDO (V)
LDO 1.71 1.71

VOS high 105
External (Bypass) 1.71 -
LDO 1.71 1.71
VOS low 125
External (Bypass) - -
125 2 2
SVOS high/SVOS LDO
105 1.71 1.71
low
External (Bypass) 125 1.71 -
DS14359 Rev 2 155/320

284
6.3.2 VCAP external capacitor

Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to
the VCAP pin. CEXT is specified in Table 28. Two external capacitors can be connected to
VCAP pins.
Figure 25. External capacitor CEXT
ESR
R Leak
MS19044V2
1. Legend: ESR is the equivalent series resistance.
Table 28. VCAP operating conditions(1)

Symbol Parameter Conditions
CEXT Capacitance of external capacitor 2.2 µF(2)(3)

ESR ESR of external capacitor < 100 mΩ
1. When bypassing the voltage regulator, the three 2.2 µF VCAP capacitors are not required and should be
replaced by three 100 nF decoupling capacitors.
2. This value corresponds to CEXT typical value. A variation of ±20% is tolerated.
3. If a fourth VCAP pin is available on the package, it must be connected to the other VCAP pins, but no
additional capacitor is required.
6.3.3 SMPS step-down converter

The devices embed a high power efficiency SMPS step-down converter. SMPS
characteristics for external usage are given in Table 30. The SMPS step-down converter
requires external components that are fully described in AN5935 “STM32H7R3/7S3 and
STM32H7R7/7S7 MCU hardware development”. The components used for datasheet
characterization are specified in Figure 26 and Table 29.
156/320 DS14359 Rev 2

Figure 26. External components for SMPS step-down converter
VDD VDDSMPS VDD VDDSMPS
Cin L VLXSMPS Cin L VLXSMPS
SMPS SMPS
VFBSMPS Cfilt VFBSMPS Cfilt
(ON) VVDD_ (ON)
DD_
External
External
Cout1 VSSSMPS 2xCout1 VSSSMPS
VCAP VCAP
VDDLDO VVCORE
CORE VDDLDO VVCORE
CORE
Voltage Vdd_external Voltage

Cout2 regulator Cout2 regulator
VSS (OFF) VSS (ON)
Direct SMPS supply External SMPS supply, LDO supplied by SMPS
MSv55526V2
Table 29. Characteristics of SMPS step-down converter external components

Capacitance of external capacitor on VDDSMPS 4.7 µF

Cin
ESR of external capacitor 100 mΩ
Cfilt Capacitance of external capacitor on VLXSMPS pin 220 pF
Capacitance of external capacitor on VFBSMPS pin 2x10 µF
COUT
ESR of external capacitor 20 mΩ
L Inductance of external Inductor on VLXSMPS pin 2.2 µH
- Serial DC resistor 150 mΩ
ISAT DC current at which the inductance drops 30% from its value without current. 1.7 A
Average current for a 40 °C rise: rated current for which the temperature of the
IRMS 1.4 A
inductor is raised 40°C by DC current
DS14359 Rev 2 157/320

284
Table 30. SMPS step-down converter characteristics for external usage

Parameters Conditions Min Typ Max Unit
VOUT = 1.8 V(2) 2.3 - 3.6

VDDSMPS(1)
VOUT = 2.5 V (2)
3 - 3.6
V
2.25 2.5 2.75
VOUT(3) Iout=600 mA
1.62 1.8 1.98
IOUT (4)
External usage only - - 600 mA
RDSON - - 100 120 mΩ
IDDSMPS_Q Quiescent current - 220 - µA
VOUT = 1.8 V - 270 405
TSMPS_START µs
VOUT = 2.5 V - 360 540
1. The switching frequency is 2.4 MHz±10%.
2. Only for bypass mode.
3. Including line transient and load transient.
4. These characteristics are given for SMPSEXTHP bit is set in the PWR_CR3 register.
Table 31. Inrush current and inrush electric charge characteristics for LDO and SMPS(1)(2)
Symbol Parameter Conditions Min Typ Max Unit
Inrush current on voltage on VDDLDO(3) - - 55 96(4)

regulator power-on (POR SMPS supplies the
or wakeup from Standby) on VDDSMPS(5) - 100 420(6)
VDDCORE
IRUSH SMPS supplies external mA
Inrush current on voltage - 100 320(6)
circuit, VOUT = 1.8 V(7)
regulator power-on on VDDSMPS(5)
(POR) SMPS supplies external
- - 240(6)
Inrush charge on voltage on VDDLDO(3) - - 4.4 5.3(4)

regulator power-on (POR SMPS supplies the
or wakeup from Standby) on VDDSMPS(5) - 7.3 18(6)
VDDCORE
QRUSH SMPS supplies external µC
Inrush charge on voltage - 13.7(6)
regulator power-on on VDDSMPS(5) 7.3
(POR) SMPS supplies external
- 10.5(6)
1. The typical values are given for VDDLDO = VDDSMPS = 3.3 V and for typical decoupling capacitor values of CEXT and COUT.
2. The product consumption (on VDDCORE) is not taken into account in the inrush current and inrush electric charges.
3. The inrush current and inrush electric charge on VDDLDO are not present in Bypass mode or when the SMPS supplies the
VDDCORE.
4. The maximum value is given for the maximum decoupling capacitor CEXT.
5. The inrush current and inrush electric charges on VDDSMPS are not present if the external component (L or COUT) is not
present that is if the SMPS is not used.
6. The maximum value is given for the maximum decoupling capacitor COUT and the minimum VDDSMPS voltage.
7. The inrush current due to transition from 1.2 V to the final VOUT Value (1.8 V or 2.5 V) is not taken into account.
158/320 DS14359 Rev 2

Typical SMPS efficiency versus load current and temperature
Figure 27. SMPS efficiency in VOS mode Tj=25°C
MSv58400V1
Figure 28. SMPS efficiency in VOS mode Tj=125°C
MSv58401V1
DS14359 Rev 2 159/320

284
Figure 29. SMPS efficiency in SVOS mode Tj=25°C
MSv58402V1
Figure 30. SMPS efficiency in SVOS mode Tj=125°C
MSv58403V1
160/320 DS14359 Rev 2

6.3.4 Operating conditions at power-up / power-down

These figures are subject to general operating conditions for TA.
Table 32. Operating conditions at power-up/power-down

Symbol Parameter Min Max Unit
VDD rise time rate 0 ∞

tVDD
VDD fall time rate 10 ∞
VDDA rise time rate 0 ∞
tVDDA
VDDA fall time rate 10 ∞
µs/V
VDDUSB rise time rate 0 ∞
tVDDUSB
VDDUSB fall time rate 10 ∞
VCORE rise time rate(2) 0 285
tVCORE(1)
VCORE fall time rate 10 ∞
1. tVCORE should be achieved when VCORE is provided by an external supply voltage (bypass with
VDDLDO = VCORE).
2. VCORE rising slope must respect the above constraints. There are no constraints on the delay between VDD
rising and VCORE rising.
6.3.5 Embedded reset and power control block characteristics

The parameters given in Table 33 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 26: General operating
conditions.
DS14359 Rev 2 161/320

284
Table 33. Reset and power control block characteristics

Reset temporization
tRSTTEMPO(1) - - 377 550 µs
after BOR0 released
Power-on/power-down reset Rising edge(1) 1.62 1.67 1.71

VBOR0/POR/PDR
threshold Falling edge 1.58 1.62 1.68
Rising edge 2.04 2.10 2.15
VBOR1 Brown-out reset threshold 1
Falling edge 1.95 2.00 2.06
Rising edge 2.34 2.41 2.47
Rising edge 2.63 2.70 2.78
Programmable Voltage Rising edge 1.90 1.96 2.01

VPVD0
Detector threshold 0 Falling edge 1.81 1.86 1.91

VPVD1 V

VPVD2

VPVD3

VPVD4

VPVD5

VPVD6
Detector threshold 6 Falling edge in Run mode 2.69 2.76 2.83
Hysteresis voltage for
Vhyst_POR_PDR Power-on/power-down reset - 43 -
(including BOR0) Hysteresis in Run mode mV
Hysteresis voltage for BOR
Vhyst_BOR_PVD - 100 -
(except BOR0)
BOR and PVD consumption
IDD_BOR_PVD(1) - - - 0.63
from VDD
µA
POR and PVD consumption
IDD_POR_PVD - 0.8 - 1.2
from VDD
162/320 DS14359 Rev 2

Table 33. Reset and power control block characteristics (continued)

Analog voltage detector for Rising edge 1.66 1.71 1.76

VAVM_0
VDDA threshold 0 Falling edge 1.56 1.61 1.66

VAVM_1
V
VAVM_2

VAVM_3
Hysteresis of VDDA voltage
Vhyst_VDDA - - 100 - mV
detector
PVM consumption from
IDD_PVM - - - 0.25 µA
VDD(1)
Voltage detector
IDD_VDDA Resistor bridge - - 2.5 µA
consumption on VDDA(1)
1. Specified by design – not tested in production.
DS14359 Rev 2 163/320

284
6.3.6 Embedded reference voltage characteristics

The parameters given in Table 34 are derived from tests performed under ambient
conditions.
Table 34. Embedded reference voltage

VREFINT Internal reference voltages -40°C < TJ < TJmax 1.18 1.216 1.255 V
ADC sampling time when
tS_vrefint(1)(2)(3) reading the internal reference - 4.3 - -
voltage
VBAT sampling time when
µs
tS_vbat(2) reading the internal VBAT - 9 - -
reference voltage
Start time of reference voltage
tstart_vrefint(2) - - - 4.4
buffer when ADC is enable
Reference Buffer consumption
Irefbuf(2) VDD = 3.3 V 9 13.5 23 µA
for ADC
Internal reference voltage
ΔVREFINT(2) spread over the temperature -40°C < TJ < TJmax - 5 15 mV
range
Average temperature Average temperature
Tcoeff(2) - 20 70 ppm/°C
coefficient coefficient
VDDcoeff(2) Average Voltage coefficient 3.0 V < VDD < 3.6 V - 10 1370 ppm/V
VREFINT_DIV1 1/4 reference voltage - - 25 -
VREFINT_DIV2 1/2 reference voltage - - 50 - % VREFINT
VREFINT_DIV3 3/4 reference voltage - - 75 -
1. The shortest sampling time for the application can be determined by multiple iterations.
2. Guaranteed by design.
3. Guaranteed by design. and tested in production at 3.3 V.
Table 35. Internal reference voltage calibration values

Symbol Parameter Memory address
VREFIN_CAL Raw data acquired at temperature of 30 °C, VDDA = 3.3 V 0x08FF F810 - 0x08FF F811
164/320 DS14359 Rev 2

6.3.7 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 24: Current consumption
measurement scheme.
All the Run-mode current consumption measurements given in this section are performed
with a CoreMark code.
Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode.
• All peripherals are disabled except when explicitly mentioned.
• The flash memory access time is adjusted with the minimum wait states number,
depending on the fACLK frequency (refer to the table “Number of wait states according to
CPU clock (frcc_c_ck) frequency and VCORE range” available in the reference manual).
• When the peripherals are enabled, the AHB clock frequency is the CPU frequency
divided by 2 and the APB clock frequency is AHB clock frequency divided by 2.
• For typical values, the power supply is 3 V unless otherwise specified.
• For maximum values, the power supply is 3.6 V unless otherwise specified.
The parameters given in the below tables are derived from tests performed at supply
voltage conditions summarized in Table 26: General operating conditions, and at ambient
temperature unless otherwise specified.
DS14359 Rev 2 165/320

284
Table 36. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM(1)
Max(2) LDO
frcc_c_ck Typ Typ
Symbol Parameter Conditions Unit
(MHz) LDO SMPS TJ = TJ = TJ = TJ =
25°C 85°C 105°C 125°C
600 125.0 65.5 135.0 235.0 310.0 -

VOS high
400 84.5 45.0 95.0 195.0 275.0 -
All
VOS
peripherals 400 90.0 48.0 100.0 200.0 280.0 -
high(3)
disabled
400 73.5 36.5 91.5 190.0 260.0 405.0
VOS low
Supply 300 57.0 29.0 75.0 170.0 245.0 390.0
IDD current in mA
Run mode 600 175.0 90.0 180.0 280.0 355.0 -
VOS high
400 115.0 62.5 130.0 230.0 305.0 -
All
VOS
peripherals 400 125.0 65.5 135.0 235.0 310.0 -
high(3)
enabled
400 105.0 50.5 125.0 220.0 290.0 435.0
VOS low
300 79.5 39.5 98.0 195.0 265.0 410.0
1. Data are in DTCM for best computation performance, cache has no influence on consumption in this case.
2. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for
the SMPS maximum consumption.
3. ECC is enabled.
166/320 DS14359 Rev 2

running from AXISRAM3, cache ON (1)
Max(2) LDO
frcc_c_ck Typ Typ
25°C 85°C 105°C 125°C
VOS 600 130.0 69.0 140.0 240.0 315.0 -

high 400 89.5 47.5 99.5 200.0 275.0 -
All
VOS
peripherals 400 92.0 49.0 105.0 205.0 280.0 -
high(3)
disabled
400 77.5 38.5 96.0 195.0 265.0 410.0
VOS low
Supply 300 60.5 30.5 78.5 175.0 245.0 395.0
IDD current in mA
Run mode VOS 600 180.0 94.5 190.0 285.0 360.0 -
high 400 125.0 65.5 135.0 235.0 310.0 -
All
VOS
peripherals 400 125.0 67.0 135.0 235.0 310.0 -
high(3)
enabled
400 105.0 52.5 130.0 225.0 295.0 440.0
VOS low
300 82.5 41.0 105.0 200.0 270.0 415.0
3. ECC is enabled.
DS14359 Rev 2 167/320

284
running from AXISRAM3, cache OFF (1)
Max(2) LDO
frcc_c_ck Typ Typ
25°C 85°C 105°C 125°C
VOS 600 96.0 51.0 110.0 210.0 285.0 -

high 400 66.5 35.5 82.5 180.0 255.0 -
All
VOS
peripherals 400 70.5 37.5 87.0 185.0 260.0 -
high(3)
disabled
VOS 400 57.5 28.5 79.5 175.0 245.0 390.0
Supply low 300 46.0 23.5 66.5 160.0 235.0 380.0
IDD current in mA
Run mode VOS 600 145.0 77.5 160.0 255.0 330.0 -
high 400 99.5 53.0 115.0 215.0 290.0 -
All
VOS
peripherals 400 105.0 55.5 120.0 215.0 290.0 -
high(3)
enabled
VOS 400 87.0 43.0 110.0 205.0 275.0 420.0
low 300 68.0 34.0 89.0 185.0 255.0 405.0
3. ECC is enabled.
168/320 DS14359 Rev 2

running from internal flash memory, cache ON(1)
Max(2) LDO
frcc_c_ck Typ Typ
25°C 85°C 105°C 125°C
600 130.0 67.5 140.0 235.0 315.0 -

VOS high
400 87.0 46.5 97.0 200.0 275.0 -
All
VOS
peripherals 400 89.5 48.0 99.5 200.0 280.0 -
high(3)
disabled
400 75.5 37.0 93.5 190.0 265.0 410.0
VOS low
Supply 300 58.5 29.5 76.5 175.0 245.0 395.0
IDD current in mA
Run mode 600 175.0 92.5 185.0 285.0 360.0 -
VOS high
400 120.0 64.0 130.0 230.0 305.0 -
All
VOS
peripherals 400 125.0 65.5 135.0 235.0 310.0 -
high(3)
enabled
400 105.0 51.5 125.0 220.0 295.0 440.0
VOS low
300 81.0 40.5 99.5 195.0 270.0 415.0
3. ECC is enabled.
DS14359 Rev 2 169/320

284
running from internal flash memory, cache OFF(1)
Max(2) LDO
frcc_c_ck Typ Typ
25°C 85°C 105°C 125°C
600 78.5 43.5 91.5 195.0 270.0 -

VOS high
400 59.0 33.0 73.5 175.0 250.0 -
All
VOS
peripherals 400 60.5 34.0 75.0 175.0 250.0 -
high(3)
disabled
400 49.5 26.5 68.5 165.0 235.0 385.0
VOS low
Supply 300 41.5 22.5 60.5 155.0 230.0 375.0
IDD current in mA
Run mode 600 130.0 69.5 140.0 240.0 315.0 -
VOS high
400 92.5 51.0 105.0 205.0 280.0 -
All
VOS
peripherals 400 94.0 52.0 110.0 205.0 280.0 -
high(3)
enabled
400 78.5 40.5 98.5 195.0 265.0 415.0
VOS low
300 64.0 33.0 83.0 180.0 250.0 400.0
3. ECC is enabled.
170/320 DS14359 Rev 2

Table 41. Typical consumption in Run mode and corresponding performance

versus code position
Conditions
frcc_c_ck Typ Typ LDO IDD SMPS IDD
Symbol Parameter Coremark Unit Unit
(MHz) LDO SMPS CoreMark CoreMark
Peripheral Code
All
peripherals ITCM 600 2976 125.0 65.5 42.0 22.2
disabled
All AXI
600 2976 130.0 69.0 43.7 23.2
Supply peripherals SRAM3
µA/
current in disabled,
IDD Internal mA Core-
Run cache ON 600 2976 130.0 67.5 43.7 22.7
flash Mark
mode
All AXI
600 1284 96.0 51.0 74.8 39.7
peripherals SRAM3
disabled, Internal
cache OFF flash 600 564 78.5 43.5 139.2 77.1
Table 42. Typical and maximum current consumption in Sleep mode

Max(1) LDO
frcc_c_ck Typ Typ
25°C 85°C 105°C 125°C
VOS 600 34.5 20.0 49.0 150.0 225.0 -

high 400 24.5 14.5 39.5 140.0 215.0 -
Supply
All
current in VOS
IDD(Sleep) peripherals 400 24.5 14.5 40.0 140.0 220.0 - mA
Sleep high(2)
disabed
mode
VOS 400 20.5 11.5 38.0 135.0 205.0 345.0
low 9.9
300 17.5 34.5 130.0 205.0 340.0
2. ECC is enabled.
DS14359 Rev 2 171/320

284
Table 43. Typical and maximum current consumption in System Stop mode
Max(1) LDO
Typ Typ
Symbol Parameter Conditions TJ = TJ = Unit
LDO SMPS TJ = TJ =
105 ° 125 °
25 °C 85 °C
C C
Flash memory SVOS

1.450 0.700 11.0 66.5 115.0 200.0
in low-power high
mode SVOS low 0.605 0.265 4.3 32.5 56.0 105.0
IDD(Stop) Stop mA
Flash memory SVOS
1.500 0.705 11.0 66.5 115.0 200.0
in normal high
mode SVOS low 0.605 0.265 4.3 32.5 56.0 105.0
Table 44. Typical and maximum current consumption in Standby mode

Conditions Typ Max (3.6 V)(1)
Smbol Parameter RTC Unit

Backup TJ = TJ = TJ = TJ =
and 1.8 V 2.4 V 3V 3.3 V
SRAM 25 °C 85 °C 105 °C 125 °C
LSE(2)
Supply OFF OFF 2.4 2.6 2.8 3.0 5.4 15.5 31.5 84.5
current in ON OFF 3.9 4.2 4.5 4.7 8.6 40.5 97.0 160.0
IDD
Standby µA
(Standby) OFF ON 3.0 3.1 3.5 3.7 - - - -
mode,
IWDG OFF ON ON 4.2 4.6 5.0 5.3 - - - -
1. Guaranteed by characterization results.
2. The LSE is in Low-drive mode.
Table 45. Typical and maximum current consumption in VBAT mode

Conditions Typ Max (3.6 V)(1)
Sym-bol Parameter RTC Unit

Backup TJ = TJ = TJ = TJ =
and 1.62 V 2.4 V 3V 3.3 V
SRAM 25 °C 85 °C 105 °C 125 °C
LSE(2)
OFF OFF 0.009 0.013 0.021 0.037 0.22 3.40 8.70 27.00
Supply ON OFF 1.5 1.8 1.8 1.9 2.85 19.00 41.00 87.00
IDD
current in µA
(VBAT) VBAT mode OFF ON 0.4 0.5 0.7 0.8 1.10 4.25 9.55 28.50
ON ON 1.9 2.1 2.4 2.5 3.70 19.50 41.50 89.00
2. The LSE is in Low-drive mode.
172/320 DS14359 Rev 2

XSPI current consumption

All XSPI current consumption measurements given in this section are performed using the
TFBGA225 SMPS HEXA product, which supports both 16-bit SPI and OCTO-SPI
memories. A 16-bit SPI memory is connected to Port 1, while an Octo-SPI memory is
connected to port 2.
The MCU is put under the following conditions:
• The external Octo and HexaSPI power supply (VDDXSPI1, VDDXSPI2) is 1.8 V
• All I/O pins of Hexa and Octo dedicated Power rail (XSPIM1 rail, XSPIM2 rail) are
configured in HSLV mode .
• The Memory clock frequency is the CPU frequency divided by 2
• The MCU power supply is 3 V unless otherwise specified.
The parameters given in the below tables are derived from tests performed with :
• CoreMark code running from Octo SPI memory (Table 46), and 16-bit SPI memory
(Table 47).
• Data write on 16-bit memory with 50%, 25%,12.5%, or 6.25% of toggling (Table 48 to
Table 51).
DS14359 Rev 2 173/320

284
running from Octo flash memory(1), cache OFF(2)
Memory
frcc_c_ck Max(3)
Symbol Parameter Conditions frequency( Typ Unit
(MHz) TJ = 105°C
MHz)
380 190 9.00 9.5

320 160 7.10 7.7
266 133 5.80 6.3
XSPI current VDDXSPIx =
IDD_XSPI 200 100 4.50 4.9 mA
in Run mode 1.8 V
180 90 4.05 4.5
120 60 2.70 3.0
60 30 1.35 1.5
1. MACRONIX_MX66UW1G45G.
running from 16-bit memory(1), cache OFF(2)
Memory
frcc_c_ck Max(3)
(MHz) TJ = 105°C
MHz)
380 190 4.55 5.0

320 160 3.70 4.1
266 133 3.10 3.4
IDD_XSPI 200 100 2.35 2.6 mA
in Run mode 1.8 V
180 90 2.10 2.4
120 60 1.45 1.6
60 30 0.76 0.8
1. AP_Memory_Hexa-SPI_PSRAM_APS256XXN OBR-BG.
174/320 DS14359 Rev 2

Table 48. Typical and maximum current consumption: data write 50% toggle on 16-bit memory(1)
Memory
frcc_c_ck Max(2)
(MHz) TJ = 105°C
MHz)
380 190 48.0 52.0

320 160 38.0 42.0
266 133 32.0 35.5
IDD_XSPI 200 100 25.0 27.5 mA
in Run mode 1.8 V
180 90 22.5 25.0
120 60 15.0 17.0
60 30 7.6 8.5
1. AP_Memory_Hexa-SPI_PSRAM_APS256XXN OBR-BG
Table 49. Typical and maximum current consumption: data write 25% toggle on 16-bit memory(1)
Memory
frcc_c_ck Max(2)
(MHz) TJ = 105°C
MHz)
380 190 26.50 29.0

320 160 21.50 23.5
266 133 18.00 20.0
IDD_XSPI 200 100 14.00 15.5 mA
in Run mode 1.8 V
180 90 12.50 14.0
120 60 8.50 9.4
60 30 4.25 4.8
DS14359 Rev 2 175/320

284
Table 50. Typical and maximum current consumption: data write 12.5% toggle on 16-bit memory(1)
Memory
frcc_c_ck Max(2)
(MHz) TJ = 105°C
MHz)
380 190 16.00 17.5

320 160 13.00 14.0
266 133 11.00 12.0
IDD_XSPI 200 100 8.35 9.3 mA
in Run mode 1.8 V
180 90 7.55 8.4
120 60 5.10 5.7
60 30 2.55 2.9
Table 51. Typical and maximum current consumption: data write 6.25% toggle on 16-bit memory(1)
Memory
frcc_c_ck Max(2)
Symbol Parameter Conditions frequency Typ Unit
(MHz) TJ = 105°C
(MHz)
380 190 10.50 11.5

320 160 8.55 9.5
266 133 7.35 8.0
IDD_XSPI 200 100 5.60 6.2 mA
in Run mode 1.8 V
180 90 5.05 5.6
120 60 3.40 3.8
60 30 1.70 1.9
176/320 DS14359 Rev 2

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as input with pull-up or pull-down generate a current consumption when
the pin is externally held to the opposite level.
The value of this current consumption can be simply computed by using the pull-up/pull-
down resistors values given in Table 71: I/O static characteristics.
For the output pins, any internal or external pull-up or pull-down and external load must also
be considered to estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption, the I/Os used by an application
also contribute to the current consumption. When an I/O pin switches, it uses the current
from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the
capacitive load (internal and external) connected to the pin:
I SW = V DDx × f SW × C L
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDx is the MCU supply voltage
fSW is the I/O switching frequency
CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
DS14359 Rev 2 177/320

284
On-chip peripheral current consumption

The MCU is placed under the following conditions:
• At startup, all I/O pins are in analog input configuration.
• All peripherals are disabled unless otherwise mentioned.
• The I/O compensation cell is enabled.
• frcc_c_ck is the CPU clock. fPCLK = frcc_c_ck/4, and fHCLK = frcc_c_ck/2.
The given value is calculated by measuring the difference of current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
• The ambient operating temperature is 25 °C and VDD=3 V
178/320 DS14359 Rev 2

Table 52. Typical dynamic current consumption of peripherals

LDO SMPS
Bus Peripheral Unit
VOS high VOS low VOS high VOS low
ADC1/2 registers 2.57 1.89 1.34 1.00

ADC1/2 kernel 0.55 0.49 0.35 0.34
ADF1 registers 1.19 1.06 0.59 0.52
ADF1 kernel 2.45 2.18 1.23 1.09
ETHERNET MAC
11.44 9.56 6.05 4.90
registers
ETHERNET MAC kernel 2.38 2.12 1.19 1.06
AHB1 ETHERNETRX 0.44 0.39 0.22 0.20

ETHERNETTX 0.50 0.44 0.25 0.22
GPDMA1 1.27 0.99 0.62 0.45
OTG_FS registers 7.06 5.97 3.82 3.07
OTG_FS kernel 0.27 0.24 0.14 0.12
OTG_HS 15.46 13.37 8.33 6.85
µA/MHz
USBPHYC registers 0.23 0.20 0.08 0.07
USBPHYC kernel 1.10 0.98 0.40 0.36
CORDIC 0.33 0.29 0.21 0.19
PSSI registers 1.85 1.69 1.05 0.85
PSSI kernel 0.43 0.33 0.20 0.18
AHB2
SDMMC2 7.63 6.76 4.19 3.43
SRAM1 0.37 0.33 0.25 0.22
SRAM2 0.46 0.42 0.30 0.27
CRYP 0.89 0.77 0.54 0.44
HASH 1.10 0.95 0.64 0.55
AHB3 PKA 4.79 4.20 2.64 2.20
RNG 0.82 0.69 0.46 0.38
SAES 6.83 6.07 4.28 3.80
DS14359 Rev 2 179/320

284
Table 52. Typical dynamic current consumption of peripherals (continued)

LDO SMPS
Bus Peripheral Unit
BKPRAM 1.34 1.17 0.84 0.75

CRC 0.25 0.22 0.13 0.10
GPIOA 0.14 0.12 0.09 0.07
GPIOB 0.14 0.14 0.10 0.08
GPIOC 0.16 0.14 0.12 0.10
GPIOD 0.12 0.11 0.07 0.06
GPIOE 0.12 0.11 0.07 0.06
AHB4 µA/MHz
GPIOF 0.16 0.14 0.08 0.06
GPIOG 0.13 0.12 0.09 0.08
GPIOH 0.15 0.13 0.08 0.07
GPIOM 0.17 0.16 0.09 0.08
GPION 0.17 0.15 0.09 0.08
GPIOO 0.31 0.28 0.21 0.18
GPIOP 0.30 0.27 0.22 0.19
180/320 DS14359 Rev 2


LDO SMPS
Bus Peripheral Unit
DMA2D 1.29 1.15 0.78 0.65

FMC/MCE3 registers 2.47 2.21 1.39 1.13
FMC/MCE3 kernel 4.71 4.21 2.58 2.15
GFXMMU 0.63 0.59 0.41 0.29
GPU2D 6.00 5.37 3.37 2.73
HPDMA1 0.91 0.84 0.51 0.42
JPEG 1.47 1.38 0.86 0.68
SDMMC1 6.88 6.13 3.82 3.15
XSPI1/MCE1 registers 0.86 0.77 0.49 0.43
AHB5
XSPI1/MCE1 kernel 1.02 0.99 0.57 0.51
XSPI2/MCE2 registers 0.74 0.71 0.46 0.37
XSPI2/MCE2 kernel 1.03 0.93 0.54 0.48
XSPIM 0.22 0.20 0.11 0.10
Flash 13.75 12.19 7.58 6.19
µA/MHz
DTCM1 0.69 0.62 0.43 0.34
DTCM2 0.50 0.44 0.31 0.27
ITCM 0.72 0.64 0.44 0.37
AXI SRAM 10.02 8.95 5.56 4.52
HDMI-CEC register 0.90 0.80 0.34 0.30
HDMI-CEC kernel 8.65 7.69 4.33 3.85
CRS 7.32 6.14 3.9 3.06
FDCAN1/2 register 6.53 5.54 3.4 2.75
FDCAN1/2 kernel 3.64 3.25 1.87 1.54
APB1
I2C1 register 1.34 1.19 0.59 0.52
I2C1 kernel 4.54 4.01 2.53 2.04
I2C2 register 1.27 1.13 0.49 0.44
I2C2 kernel 1.65 1.52 0.89 0.79
I2C3 register 1.36 1.21 0.51 0.45
DS14359 Rev 2 181/320

284

LDO SMPS
Bus Peripheral Unit
I2C3 kernel 2.14 1.87 1.22 0.96

LPTIM1 registers 1.33 1.18 0.63 0.50
LPTIM1 kernel 3.38 2.93 1.83 1.50
MDIOS 2.83 2.52 1.35 1.04
SPDIF-RX registers 0.99 0.71 0.37 0.33
SPDIF-RX kernel 2.34 2.21 1.33 1.10
SPI2 registers 1.84 1.35 0.87 0.67
SPI2 kernel 2.14 1.92 0.99 0.88
APB1 µA/MHz
SPI3 registers 1.79 1.41 0.84 0.62
SPI3 kernel 1.91 1.78 1.07 0.98
TIM12 1.90 1.52 0.92 0.72
TIM13 1.39 1.04 0.59 0.42
TIM14 1.49 1.1 0.64 0.51
TIM2 3.40 2.97 1.83 1.49
TIM3 3.56 3.04 1.87 1.50
TIM4 3.58 3.11 1.85 1.49
182/320 DS14359 Rev 2


LDO SMPS
Bus Peripheral Unit
TIM5 3.48 3.01 1.81 1.45

TIM6 1.02 0.86 0.51 0.45
TIM7 0.91 0.74 0.45 0.4
UART4 registers 2.12 1.63 1.07 0.78
UART4 kernel 3.53 3.05 1.95 1.55
UART5 registers 2.13 1.59 1.10 0.98
UART5 kernel 3.62 3.14 1.94 1.61
UART7 registers 2.24 1.68 1.14 1.01
APB1 UART7 kernel 3.43 3.02 1.95 1.54 µA/MHz
UART8 registers 2.27 1.71 1.16 1.03
UART8 kernel 3.61 3.17 1.96 1.58
UCPD1 2.61 2.21 1.25 1.06
USART2 registers 2.32 1.87 1.12 0.86
USART2 kernel 3.41 3.03 1.89 1.55
USART3 registers 2.07 1.66 1.04 0.79
USART3 kernel 4.02 3.60 2.20 1.82
WWDG 1.25 1.11 0.57 0.46
DS14359 Rev 2 183/320

284

LDO SMPS
Bus Peripheral Unit
SAI1 registers 1.17 1.01 0.56 0.41

SAI1 kernel 1.56 1.38 0.87 0.68
SAI2 registers 1.19 1.02 0.64 0.57
SAI2kernel 1.41 1.22 0.73 0.64
SPI1 registers 1.29 1.14 0.68 0.54
SPI1 kernel 2.15 1.87 1.08 0.95
SPI4 registers 1.25 1.11 0.66 0.53
SPI4 kernel 1.48 1.35 0.88 0.69
APB2 SPI5 registers 1.3 1.22 0.60 0.52 µA/MHz
SPI5kernel 1.69 1.42 0.91 0.69
TIM1 4.50 3.97 2.43 1.98
TIM15 2.25 2.02 1.25 0.99
TIM16 1.54 1.45 0.88 0.69
TIM17 1.60 1.42 0.87 0.74
TIM9 1.39 1.24 0.67 0.58
USART1 registers 1.50 1.33 0.78 0.62
USART1 kernel 4.03 3.47 2.20 1.77
184/320 DS14359 Rev 2


LDO SMPS
Bus Peripheral Unit
DTS 2.10 1.63 1.01 0.89

LPTIM2 registers 1.24 1.1 0.57 0.49
LPTIM2 kernel 3.17 2.78 1.78 1.46
LPTIM3 registers 1.23 0.97 0.61 0.51
LPTIM3 kernel 3.35 2.99 1.84 1.5
LPTIM4 registers 0.69 0.56 0.35 0.26
LPTIM4 kernel 1.90 1.79 1.08 0.87
LPTIM5 registers 0.73 0.58 0.36 0.31
APB4
LPTIM5 kernel 2.24 1.92 1.25 1.04
µA/MHz
LPUART1 registers 1.39 1.07 0.68 0.64
LPUART1 KERNEL 2.46 2.25 1.40 1.12
RTCAPB 1.85 1.51 0.93 0.80
SBS 0.71 0.63 0.33 0.29
SPI6 registers 1.58 1.16 0.74 0.68
SPI6 kernel 1.69 1.55 0.91 0.77
VREF 0.27 0.24 0.12 0.11
DCMIPP 5.71 5.03 3.14 2.60
APB5 GFXTIM 1.12 1.03 0.67 0.56
LTDC 3.42 3.03 1.87 1.55
DS14359 Rev 2 185/320

284
6.3.8 Wake-up time from low-power modes

The wake-up times given in Table 53 are measured starting from the wake-up event trigger
up to the first instruction executed by the CPU:
• For Stop or Sleep modes: the wake-up event is WFE.
• WKUP (PC1) pin is used to wake-up from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD=3 V.
Table 53. Low-power mode wakeup timings
Symbol Parameter Conditions Typ(1) Max(1)(2)(3) Unit
CPU
Wakeup from
tWUSLEEP(4) - 15 16 clock
Sleep
cycles
SVOS low, HSI, Flash memory in
42.5 46.0
normal mode
SVOS low, HSI, Flash memory in
42.5 46.0
low-power mode
SVOS high, HSI, Flash memory in
16.0 17.5
normal mode
SVOS high, HSI, Flash memory in
20.0 21.0
Wakeup from low-power mode
tWUDSTOP(4)
Stop SVOS low, CSI, Flash memory in
65.0 71.0 µs
normal mode
SVOS low, CSI, Flash memory in
71.5 77.5
low power mode
SVOS high, CSI, Flash memory in
32.0 35.0
normal mode
SVOS high, CSI, Flash memory in
48.5 54.0
low-power mode
Wakeup from
tWUSTDBY(4) - 280.0 535.0
Standby mode
2. Measurements are made at -40°C under worst-case conditions.
3. Maximum values are for the LDO configuration.
4. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
instruction..
186/320 DS14359 Rev 2

6.3.9 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.
The external clock signal has to respect the Table 71: I/O static characteristics. However,
the recommended clock input waveform is shown in Figure 31.
Table 54. High-speed external user clock characteristics(1)

User external clock External digital/

fHSE_ext 4 25 50 MHz
source frequency analog clock
Digital OSC_IN
External digital
VHSEH input high-level 0.7 VDD - VDD
clock
voltage
V
Digital OSC_IN
External digital
VHSEL input low-level VSS - 0.3 VDD
cwlock
voltage
OSC_IN high or low External digital
tW(HSE)(2) 7 - - ns
time(2) clock
Analog low swing
VlswHSE External Analog
OSC_IN peak-to- 0.2 - 2/3 VDD V
(VHSEH -VHSEL)(3) Low Swing Clock
peak amplitud(3)e
Analog low swing External analog
DuCyHSE 45 50 55 %
OSC_IN duty cycle low-swing clock
Analog low swing External analog
trHSE/tfHSE OSC_IN rise and low -swing clock 0.05 / fHSE_ext - 0.3 / fHSE_ext ns
fall time(3) 10% to 90%
2. No specified rise and fall time for a digital input signal but the VHSEH and VHSEL conditions must be fulfilled.
3. The DC component of the signal must insure that the signal peaks are located between VDD and VSS.
DS14359 Rev 2 187/320

284
Figure 31. High-speed external clock source AC timing diagram
VHSEH
90 %
10 %
VHSEL
tr(HSE) tf(HSE) tW(HSE) tW(HSE) t
THSE
External fHSE_ext
IL
clock source OSC_IN
STM32
ai17528b
Table 55. Timing for analog HSE input

Parameter Comment Min Typ Max KHz
IO power supply VDDIO 1.71 3.30 3.60 V

Temperature - -40 25 125 °C
Absolute input range - 0.000 - VDDIO V
Input peak-to peak amplitude V pp 0.2(1) - 2/3.VDDIO V
VDDIO power consumption - - 150(2) 500(3) µA
(4)
Input frequency - 4 - 50 MHz
Input duty cycle Square wave 45 50 55
%
Duty cycle deterioration - 0 ±10(5) ±10(6)
Time to start - 1 - 10(7) µs
10% to 90% threshold levels
Rise and fall time of the input peak-to-peak 0.05 / freq - 0.3 / freq -
amplitude
1. 200 mV is the minimum peak-to-peak amplitude @25°C (0.1 V< Vdc < VDD IO -0.1 V where Vdc is the DC component of the
input signal).
2. Power consumption with a sine wave signal at the input @25°C (VDD IO = 3.3 V / V pp = 400 mV / V dc = 0.4 V).
3. Power consumption with a sine wave signal at the input @125°C (VDD IO = 3.6 V / V pp = 800 mV / V dc =1.8 V).
4. The IP is functional up to 50 MHz for RMII applications.
5. Guaranteed by design with a square wave @25°C / VDD IO =3.3 V / V pp = 400 mV / Vdc =1 V.
6. Guaranteed by design with a square wave @25°C / VDD IO =1.6 V / V pp = 200 mV / Vdc =0.8 V.
7. Maximum start-up time value (slow corner @125°C with 200 mV peak-to-peak amplitude).
188/320 DS14359 Rev 2

Figure 32. Analog HSE input waveform

VDDIO (V)
VDDIO max
freq=1T Signal 1
Signal 2
90%
Vdc
Vpp
10%
0 t (s)
Signal 1 Signal 2
rise time rise time
MSv55527V1
DS14359 Rev 2 189/320

284
Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 71: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 33.
Table 56. Low-speed external user clock characteristics(1)

User external clock External digital /

fLSE_ext - 32.768 1000 kHz
source frequency analog clock
Digital OSC_IN input
VLSEH External digital clock 0.7 VDD - VDD V
high level
OSC32_IN input pin
VLSEL External digital clock VSS - 0.3 VDD V
low level voltage
OSC32_IN high or low
tw(LSEH)/tw(LSEL) External digital clock 250 - - ns
time
Analog low-swing External analog low
Vlsw_H 0.6 1.225 V
OSC_IN high level swing clock
Analog low-swing External Analog low
Vlsw_L 0.35 0.8 V
OSC_IN low level swing clock
Analog low-swing
VlswLSE External analog low
OSC_IN peak-to-peak 0.2 0.875 V
(VLSEH - VLSEL) swing clock
amplitude
Analog low-swing External analog low
DuCyLSE 45 50 55 %
OSC_IN duty cycle swing clock
Analog low -swing External analog low
trLSE/tfLSE OSC_IN rise and fall swing clock 10% to - 100 200 ns
time 90%
1. Specified by design - not tested in production.
Figure 33. Low-speed external clock source AC timing diagram
VLSEH
90%
10%
VLSEL
tr(LSE) tf(LSE) tW(LSE) tW(LSE) t
TLSE
External fLSE_ext
OSC32_IN IL
clock source
STM32
ai17529b
190/320 DS14359 Rev 2

Table 57. Timing for analog LSE input

Parameter Comment Min Typ Max Unit
Input frequency Fundamental frequency 32.768 32.768 32.768 kHz

(1)
Input peak-to-peak amplitude Vpp 0.3 - VSW
V
Absolute input range - - - VSW
1. 300 mV is the minimum peak-to-peak amplitude @25°C (0.1V<Vdc < VDDIO -0.1V where Vdc is the DC component of the
input signal).
Figure 34. Analog LSE input waveform

VDDIO (V)
VDDIO max
Frequency=32.768 kHz Sine wave
Square wave
90%
Vdc
Vpp
10%
0 t (s)
Trise Tfall
MSv55528V1
DS14359 Rev 2 191/320

284
High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 50 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 58. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 58. 4-50 MHz HSE oscillator characteristics(1)

Operating
Symbol Parameter Min Typ Max Unit
conditions(2)
F Oscillator frequency - 4 - 50 MHz

RF Feedback resistor - - 200 - kΩ
During startup(3) - - 10
VDD=3 V, Rm=20 Ω
- 0.44 -
CL=10 pF at 4 MHz
VDD=3 V, Rm=20 Ω
- 0.44 -
CL=10 pF at 8 MHz
IDD(HSE) HSE current consumption VDD=3 V, Rm=20 Ω mA
- 0.55 -
CL=10 pF at 16 MHz
VDD=3 V, Rm=20 Ω
- 0.67 -
CL=10 pF at 32 MHz
VDD=3 V, Rm=20 Ω
- 1.17 -
CL=10 pF at 48 MHz
Gmcritmax Maximum critical crystal gm Startup - - 1.5 mA/V
tSU(4) Start-up time VDD is stabilized - 2 - ms
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Note: For information on selecting the crystal, refer to application note AN2867 “Oscillator design
guide for STM8AF/AL/S, STM32 MCUs and MPUs” available from the ST website
www.st.com.
192/320 DS14359 Rev 2

Figure 35. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
CL1
OSC_IN fHSE
Bias
8 MHz RF controlled
resonator
gain
REXT(1) OSC_OU T STM32

CL2
ai17530b
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 59. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 59. Low-speed external user clock characteristics(1)

Symbol Parameter Operating conditions(2) Min Typ Max Unit
F Oscillator frequency - - 32.768 - kHz

LSEDRV[1:0] = 00,
- 246 -
Low drive capability
LSEDRV[1:0] = 01,
- 333 -
Medium Low drive capability
IDD LSE current consumption nA
LSEDRV[1:0] = 10,
- 462 -
Medium high drive capability
LSEDRV[1:0] = 11,
- 747 -
High drive capability
LSEDRV[1:0] = 00,
- - 0.5
Low drive capability
LSEDRV[1:0] = 01,
- - 0.75
Medium Low drive capability
Gmcritmax Maximum critical crystal gm µA/V
LSEDRV[1:0] = 10,
- - 1.7
Medium high drive capability
LSEDRV[1:0] = 11,
- - 2.7
High drive capability
tSU(3) Startup time VDD is stabilized - 2 - s
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
STM8AF/AL/S, STM32 MCUs and MPUs”.
3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
DS14359 Rev 2 193/320

284
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for STM8AF/AL/S, STM32 MCUs and MPUs” available from the ST website
www.st.com.
Figure 36. Typical application with a 32.768 kHz crystal

Resonator with
integrated capacitors CL1
OSC32_IN fHSE
Bias
32.768 kHz
RF controlled
resonator
gain
OSC32_OUT
STM32
CL2
ai17531c
1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
194/320 DS14359 Rev 2

6.3.10 Internal clock source characteristics

The parameters given in Table 60 to Table 62 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 26: General
operating conditions.
48 MHz high-speed internal RC oscillator (HSI48)
Table 60. HSI48 oscillator characteristics

VDD=3.3 V,
fHSI48 HSI48 frequency 47.5(1) 48 48.5(1) MHz
TJ=30 °C
TRIM(2) USER trimming step - - 0.175 0.250 %
USER TRIM
USER trimming coverage ± 32 steps ±4.70 ±5.6 - %
COVERAGE(3)
DuCy(HSI48)(2) Duty cycle - 45 - 55 %
Accuracy of the HSI48 oscillator
ACCHSI48_REL(3)(4) TJ=-40 to 125 °C -4.5 - 3.5 %
over temperature (factory calibrated)
VDD=3 to 3.6 V - 0.025 0.05
HSI48 oscillator frequency drift with
ΔVDD(HSI48)(2)(4) VDD=1.62 V to %
VDD(5) (the reference is 3.3 V) - 0.05 0.1
3.6 V
tsu(HSI48)(2) HSI48 oscillator start-up time - - 2.1 4.0 µs
IDD(HSI48)(2) HSI48 oscillator power consumption - - 350 400 µA
Next transition jitter
NT jitter(2) - - ± 0.15 - ns
Accumulated jitter on 28 cycles(6)
Paired transition jitter
PT jitter(2) - - ± 0.25 - ns
Accumulated jitter on 56 cycles(6)
1. Guaranteed by test in production.
3. Guaranteed by characterization.
4. ΔfHSI = ACCHSI48_REL + ΔVDD.
5. These values are obtained by using the formula: (Freq(3.6 V) - Freq(3.0 V)) / Freq(3.0 V) or (Freq(3.6 V) - Freq(1.62 V)) /
Freq(1.62 V).
6. Jitter measurements are performed without clock source activated in parallel.
DS14359 Rev 2 195/320

284
64 MHz high-speed internal RC oscillator (HSI)
Table 61. HSI oscillator characteristics(1)

fHSI HSI frequency VDD=3.3 V, TJ=30 °C 63.7(2) 64 64.3(2) MHz

Trimming is not a multiple
- 0.24 0.32
of 32
Trimming is 128, 256 and
-5.2 -1.8 -
384
TRIM HSI user trimming step Trimming is 64, 192, 320 %

-1.4 -0.8 -
and 448
Other trimming are a
multiple of 32 (not
-0.6 -0.25 -
including multiple of 64
and 128)
DuCy(HSI) Duty cycle - 45 - 55 %
HSI oscillator frequency drift over
ΔVDD (HSI) VDD=1.71 to 3.6 V -0.12 - 0.03 %
VDD (the reference is 3.3 V)
HSI oscillator frequency drift over TJ=-20 to 105 °C -1(3) - 1(3)
ΔTEMP(HSI) temperature (the reference is %
64 MHz) TJ=-40 to TJmax °C -2(3) - 1(3)
tsu(HSI) HSI oscillator start-up time - - 1.4 2

at 1% of target frequency - 4 8 µs
tstab(HSI) HSI oscillator stabilization time
at 5% of target frequency - - 4
IDD(HSI) HSI oscillator power consumption - - 300 400 µA
1. Guaranteed by design unless otherwise specified.
3. Guaranteed by characterization.
196/320 DS14359 Rev 2

4 MHz low-power internal RC oscillator (CSI)
Table 62. CSI oscillator characteristics(1)

fCSI CSI frequency VDD=3.3 V, TJ=30 °C 3.96(2) 4 4.04(2) MHz

Trimming is not a
- 0.40 0.75
multiple of 16
Trimming is a multiple
-4.75 -2.75 0.75
of 32
TRIM CSI trimming step %
Other trimming values
not multiple of 16
-0.43 0.00 0.75
(excluding multiple of
32)
DuCy(CSI) Duty cycle - 45 - 55 %
CSI oscillator frequency drift over TJ = 0 to 85 °C -3.7(3) - 4.5(3)

ΔTEMP (CSI) %
temperature TJ = -40 to 125 °C -11(3) - 7.5(3)
CSI oscillator frequency drift over
ΔVDD (CSI) VDD = 1.71 to 3.6 V -0.06 - 0.06 %
VDD
tsu(CSI) CSI oscillator startup time - - 1 2 µs
CSI oscillator stabilization time
tstab(CSI) - - - 4 cycle
(to reach ± 3% of fCSI)
IDD(CSI) CSI oscillator power consumption - - 23 30 µA
1. Guaranteed by design, unless otherwise specified.
Low-speed internal (LSI) RC oscillator
Table 63. LSI oscillator characteristics

VDD = 3.3 V, TJ = 25 °C 31.4(1) 32 32.6(1)

TJ = –40 to 110 °C,
29.76(2) - 33.6(2)
fLSI LSI frequency VDD = 1.62 to 3.6 V kHz
TJ = –40 to 125 °C,
29.4(2) - 33.6(2)
VDD = 1.71 to 3.6 V
tsu(LSI)(3) LSI oscillator startup time - - 80 130
LSI oscillator stabilization time µs
tstab(LSI)(3) - - 120 170
(5% of final value)
IDD(LSI)(3) LSI oscillator power consumption - - 130 280 nA
DS14359 Rev 2 197/320

284
6.3.11 PLL characteristics

The parameters given in Table 64 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 26: General operating conditions.
Table 64. PLL1 characteristics (wide VCO frequency range)(1)

PLL input clock - 2 - 16 MHz

fPLL_IN
PLL input clock duty cycle - 10 - 90 %
(2)
PLL multiplier output clock VOS high 1.5 - 600
fPLL_P_OUT
P, Q, R, S, T VOS low 1.5 - 400(2) MHz
fVCO_OUT PLL VCO output - 192 - 836(3)
Normal mode 15 50 150(3)
tLOCK PLL lock time µs
Sigma-delta mode (CKIN ≥ 8 MHz) 25 65 170
Cycle-to-cycle jitter fVCO_OUT = 192 MHz - 35 -
multiplier output clock P,
Q, R, S, T fVCO_OUT = 836 MHz - 15 -
±ps
Period jitter multiplier fVCO_OUT = 192 MHz - 32 -
Jitter (RMS) output clock P, Q, R, S, T fVCO_OUT = 836 MHz - 10 -
Normal mode (FPLL IN= 2 MHz),
- ±0.18 -
Long term jitter multiplier fVCO_OUT = 192 MHz
%(4)
output clock P, Q, R, S, T Normal mode (FPLL IN= 16 MHz),
- ±0.5 -
fVCO_OUT = 192 MHz
VDDA - 390 548
fVCO_OUT = 192 MHz
VCORE - 590 3800
IDD(PLL) PLL power consumption µA
VDDA - 1000 1100
fVCO_OUT = 836 MHz
VCORE - 3500 9020
2. This value must be limited to the maximum frequency due to the product limitation.
4. Given as percent of input clock period.
198/320 DS14359 Rev 2

Table 65. PLL1 characteristics (narrow VCO frequency range)(1)

PLL input clock - 1 - 2 MHz

fPLL_IN
PLL input clock duty cycle - 10 - 90 %
PLL multiplier output clock VOS high 1.17 - 210

fPLL_P_OUT
P, Q, R, S, T VOS low 1.17 - 210 MHz
fVCO_OUT PLL VCO output - 150 - 420
Normal mode - 60(2) 100(2)
tLOCK PLL lock time µs
Sigma-delta mode Forbidden
Cycle-to-cycle jitter fVCO_OUT = 150 MHz - 20 -
multiplier output clock P,
Q, R, S, T fVCO_OUT = 420 MHz - 12 -
±ps
Period jitter multiplier fVCO_OUT = 150 MHz - 15 -
Jitter (RMS) output clock P, Q, R, S, T fVCO_OUT = 420 MHz - 8 -
Normal mode (FPLL_IN = 2 MHz)
- ±0.35 - %(3)
Long-term jitter multiplier fVCO_OUT = 150 MHz
output clock P, Q, R, S, T Normal mode (FPLL_IN = 2 MHz)
- ±0.55 -
fVCO_OUT = 420 MHz
VDDA - 200 290
fVCO_OUT = 192 MHz
VCORE - 625 4880
IDD(PLL) PLL power consumption µA
VDDA - 460 510
fVCO_OUT = 836 MHz
VCORE - 1690 640
2. This value must be limited to the maximum frequency due to the product limitation.
3. Given as percent of input clock period.
DS14359 Rev 2 199/320

284
6.3.12 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 66. They are based on the EMS levels and classes
defined in AN1709 “EMC design guide for STM8, STM32 and Legacy MCUs”.
Table 66. EMS characteristics

Level/
Class
VDD = 3.3 V, TA = 25 °C,

Voltage limits to be applied on any I/O pin to fHCLK = 600 MHz,
VFESD 1B
induce a functional disturbance BGA225 Hexa package
conforming to IEC 61000-4-2
VDD = 3.3 V, TA = 25 °C,
Fast transient voltage burst limits to be
f = 600 MHz,
VFTB applied through 100 pF on VDD and VSS pins HCLK 5A
BGA225 Hexa package
to induce a functional disturbance
conforming to IEC 61000-4-4
As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as

possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical data corruption (such as control registers)
200/320 DS14359 Rev 2

Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST or on the oscillator pins for 1 s.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015 “Software
techniques for improving microcontrollers EMC performance”).
Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 67. EMI characteristics for fHSE = 8 MHz and fCPU = 600 MHz
Max vs.
Monitored frequency [fHSE/fCPU]
band
8/600 MHz
0.1 to 30 MHz 10
30 to 130 MHz 30
Peak level(1) V = 3.6 V, T = 25 °C, BGA225 dBµV
SEMI DD A 130 MHz to 1 GHz 22
package, compliant with IEC61967-2
1 GHz to 2 GHz 9
Level(2) 0.1 MHz to 2 GHz 4.0 -
1. Refer to AN1709 EMI radiated test chapter.
2. Refer to AN1709 EMI level classification chapter.
DS14359 Rev 2 201/320

284
6.3.13 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each
sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC
JS-001 and ANSI/ESDA/JEDEC JS-002 standards.
Table 68. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Packages Class Unit
value(1)
Electrostatic
TA = +25 °C conforming to
VESD(HBM) discharge voltage All packages(2) 2 2000
ANSI/ESDA/JEDEC JS-001
(human body model)
Electrostatic V
discharge voltage TA = +25 °C conforming to
VESD(CDM) All packages(2) C2B 750
(charge device ANSI/ESDA/JEDEC JS-002
model)
1. Evaluated by characterization – not tested in production.
2. WLCSP not yet available.
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.
Table 69. Electrical sensitivities

Symbol Parameter Conditions Class
LU Static latchup class Conforming to JESD78, TJ = TJMax II level A
202/320 DS14359 Rev 2

6.3.14 I/O current injection characteristics

As a general rule, a current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during the normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when an abnormal injection accidentally happens, susceptibility
tests are performed on a sample basis during the device characterization.
Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
The following tables are the compilation of the SIC1/SIC2 and functional ESD results.
Negative induced A negative induced leakage current is caused by negative injection and
positive induced leakage current by positive injection.
Table 70. I/O current injection susceptibility(1)

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection
Injected current on pins: PB2, PC14, PC15, PF15, PM0, PM1,

IINJ 0 0
PM5 and PM6 mA
- Injected current on all other pins 5 NA
1. Evaluated by characterization results.
6.3.15 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 71 are derived from tests
performed under the conditions summarized in Table 26: General operating conditions. All
I/Os are CMOS and TTL compliant (except for BOOT0).
Note: For information on GPIO configuration, refer to AN4899 “STM32 GPIO configuration for
hardware settings and low-power consumption”, available from the ST website www.st.com.
DS14359 Rev 2 203/320

284
Table 71. I/O static characteristics(1)

Symbol Parameter Condition Min Typ Max Unit
I/O input low level voltage

- - 0.3 VDDIOx(2)
except BOOT0
I/O input low level voltage
VIL 1.08 V < VDD < 3.6 V - - 0.4 VDDIOx - 0.1(3) V
except BOOT0
BOOT0 I/O input low level
- - 0.19 VDDIOx + 0.1(3)
voltage
I/O input high level
0.7 VDDIOx(2) - -
voltage except BOOT0
I/O input high level 0.52 VDDIOx +
VIH 1.08 V < VDD < 3.6 V - - V
voltage except BOOT0 0.18(3)
BOOT0 I/O input high 0.17 VDDIOx +
- -
level voltage 0.6(3)
TT_xx, FT_xxx and NRST
1.08 V < VDD < 3.6 V - 250 -
I/O input hysteresis
VHYS(3) mV
BOOT0 I/O input
1.71 V < VDD < 3.6 V - 200 -
hysteresis
0 < VIN ≤
- - ±250
Max(VDDXXX)(7)
Max(VDDXXX) <
FT_xx Input leakage
VIN ≤ Max(VDDXXX)+ - - 2500
current(3)
1 V) (5)(7) nA
Ileak(4)
Max(VDDXXX) < VIN ≤
- - 750
5.5 V (5)(7)
TT_xx Input leakage 0< VIN ≤ Max(VDDXXX)
(7) - - ±250
current
BOOT0 0< VIN ≤ VDDOX - - 15 µA
Weak pull-up
RPU VIN = VSS 30 40 50
equivalent resistor(6)
kΩ
Weak pull-down
RPD VIN = VDD(7) 30 40 50
equivalent resistor(6)
CIO I/O pin capacitance - - 5 - pF
1. VDDIOx represents VDD or VDDXSPIx.
2. Compliant with CMOS requirements.
3. Specified by design - Not tested in production.
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ieak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).
5. VIN must be less than Max(VDDXXX) + 3.6 V.
6. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10%).
7. Max(VDDXXX) is the maximum value of all the I/O supplies.
204/320 DS14359 Rev 2

All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 37.
Figure 37. VIL/VIH for all I/Os except BOOT0

3
2.5
Minimum required
logic level 1 zone
TTL standard requirement VIHmin = 2V
2
xV DDIO
= 0.7
V IHmin
ment)
d re quire
VIN (V) ndar
S sta
1.5 (CMO
duction
d in pro IO +
0.18
Teste 0.52 VDD
lation VIHmin = Undefined input range
on simu
Based
1
VDDIO - 0.1
VILmax = 0.4
simulation = 0.3 VDDIO TTL standard requirement VILmax = 0.8V
Based on ment) VILmax
dard require
(CMOS stan
0.5 Tested in production
Minimum required
logic level 0 zone
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Device characteristics VDDIO (V)

Tested thresholds MSv47925V1
Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins that can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2: Absolute maximum ratings. In
particular:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 24).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 24).
DS14359 Rev 2 205/320

284
Output voltage levels

Unless otherwise specified, the parameters given in Table 72 and Table 73 are derived from
tests performed under ambient temperature and VDD supply voltage conditions summarized
in Table 26: General operating conditions. All I/Os are CMOS and TTL compliant.
Table 72. Output voltage characteristics for all I/Os except PC13, PC14, and PC15
Symbol Parameter Conditions(1) Min Max Unit
CMOS port(2)
VOL Output low level voltage IIO = 8 mA - 0.4
2.7 V≤ VDD ≤ 3.6 V
CMOS port(2)
VOH Output high level voltage IIO = -8 mA VDD- 0.4 -
2.7 V≤ VDD ≤ 3.6 V
TTL port(2)
VOL(3) Output low level voltage IIO = 8 mA - 0.4
2.7 V≤ VDD ≤ 3.6 V
TTL port(2)
VOH (3) Output high level voltage IIO = -8 mA 2.4 -
2.7 V≤ VDD ≤ 3.6 V
IIO = 20 mA
VOL(3) Output low level voltage - 1.3
2.7 V ≤ VDD ≤ 3.6 V
IIO = -20 mA
VOH(3) Output high level voltage VDD - 1.3 -
2.7 V ≤ VDD ≤ 3.6 V V
IIO = 4 mA
1.71 V ≤ VDD ≤ 3.6 V
IIO = -4 mA
VOH (3) Output high level voltage VDD - 0.4 -
1.71 V ≤ VDD <3.6 V
IIO = 2 mA 0.3 VDDXSPIx

VOL(3) Output low level voltage -
1.08 V ≤ VDD ≤ 1.32 V 0.3
IIO = -2 mA
VOH (3) Output high level voltage 0.7 VDDXSPIx -
1.71 V ≤ VDD < 1.32 V
IIO = 20 mA
- 0.4
2.3 V≤ VDD ≤3.6 V
Output low level voltage for an IIO = 10 mA
VOLFM+(3) - 0.4
FTf I/O pin in (FT I/O with “f” option) 1.71 V ≤ VDD ≤ 3.6 V
IIO = 4.5 mA
- 0.4
1.08 V ≤ VDD ≤ 3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 24, and
the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute
maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
206/320 DS14359 Rev 2

Table 73. Output voltage characteristics for PC13(1)

CMOS port(2) IIO = 3 mA

VOL Output low level voltage - 0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2) IIO = -3 mA
VOH Output high level voltage VDD - 0.4 -
2.7 V≤ VDD ≤3.6 V
TTL port(2) IIO = 3 mA
2.7 V≤ VDD ≤3.6 V
V
TTL port(2) IIO = -3 mA
VOH(3) Output high level voltage 2.4 -
2.7 V≤ VDD ≤3.6 V
IIO = 1.5 mA
1.71 V≤ VDD ≤ 3.6 V
IIO = −1.5 mA
1.71 V≤ VDD ≤ 3.6 V
Table 74. Output voltage characteristics for PC14 and PC15(1)

CMOS port(2) IIO = 0.5 mA

VOL Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
CMOS port(2) IIO = -0.5 mA
VOH Output high level voltage VDD - 0.4 -
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2) IIO = 0.5 mA
2.7 V ≤ VDD ≤ 3.6 V
V
TTL port(2) IIO = -0.5 mA
VOH(3) Output high level voltage 2.4 -
2.7 V ≤ VDD ≤ 3.6 V
IIO = 0.25 mA
1.71 V ≤ VDD ≤ 3.6 V
IIO = -0.25 mA
1.71 V ≤ VDD ≤ 3.6 V
DS14359 Rev 2 207/320

284
Output buffer timing characteristics (HSLV option disabled)

The HSLV bit of GPIOx_HSLVR register can be used to optimize the I/O speed when the
product voltage is below 2.7 V.
Table 75. Output timing characteristics (HSLV OFF)(1)

Speed Symbol Parameter Conditions Min Max Unit
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 8

C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 5
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 10
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 5
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 12
Fmax(2)(3) Maximum frequency MHz
C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 5
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 14
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 5
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 16
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 5
00
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 18.0
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 36.0
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 17.0
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 34.0
Output high to low level C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 15.5
tr/tf(4)(5) fall time and output low ns
to high level rise time C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 32.0
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 14.2
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 30.0
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 12.2
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 27
208/320 DS14359 Rev 2

Table 75. Output timing characteristics (HSLV OFF)(1) (continued)

C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V 40

C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 12
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 45
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 14
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 50
Fmax(2)(3) Maximum frequency MHz
C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 16
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 55
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 18
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 60
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 20
01
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 6.2
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 11.4
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 5.7
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 10.5
tr/tf(4)(5) fall time and output low ns
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 4.5
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V 8.4
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V 3.7
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V 7.0
DS14359 Rev 2 209/320

284

C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 80

C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 30
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 90
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 35
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 100
Fmax(2)(3)(6) Maximum frequency MHz
C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 40
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 110
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 45
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 133
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 50
10
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 3.8
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 7.5
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 3.4
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 6.6
tr/tf(4)(5)(6) fall time and output low ns
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 2.5
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 4.7
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 1.9
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 3.7
210/320 DS14359 Rev 2


C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 100

C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 40
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 120
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 50
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 140
Fmax(2)(3)(6) Maximum frequency MHz
C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 60
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 166
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 70
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 200
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 80
11
C = 50 pF, 2.7 V≤ VDD ≤ 3.6 V - 3.3
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 6.3
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 2.8
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 5.5
tr/tf(4)(5)(6) fall time and output low ns
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 1.9
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 3.7
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 1.4
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 3
2. The maximum frequency is defined with the conditions (tr + tf) ≤ 2/3 T, Skew ≤ 1/20 T, and 45% < Duty cycle < 55%.
3. When 2 V < VDD < 2.7 V the maximum frequency is between values given for VDD = 1.98 V and VDD = 2.7 V.
4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
5. When 2 V<VDD<2.7 V maximum frequency is between values given for VDD=1.98 V and VDD=2.7 V.
6. When 2 V<VDD<2.7 V Max Trise/Tfall is between values given for VDD=1.98 V and Vdd=2.7 V.
DS14359 Rev 2 211/320

284
Output buffer timing characteristics (HSLV option enabled)
Table 76. Output timing characteristics (HSLV ON)(1)

C = 50 pF, 1.71 V ≤ VDD≤2 V - 8

C = 40 pF, 1.71 V ≤ VDD≤2 V - 10
Fmax(2) Maximum frequency C = 30 pF, 1.71 V ≤ VDD≤2 V - 12 MHz
C = 20 pF, 1.71 V ≤ VDD≤2 V - 14
C = 10 pF, 1.71 V ≤ VDD≤2 V - 16
00
C = 50 pF, 1.71 V ≤ VDD≤2 V - 17.8
C = 40 pF, 1.71 V ≤ VDD≤2 V - 15.8
Output high to low level
tr/tf(3) fall time and output low C = 30 pF, 1.71 V ≤ VDD≤2 V - 14.4 ns
to high level rise time
C = 20 pF, 1.71 V ≤ VDD≤2 V - 13.1
C = 10 pF, 1.71 V ≤ VDD≤2 V - 11.4
C = 50 pF, 1.71 V ≤ VDD≤2 V - 40
C = 40 pF, 1.71 V ≤ VDD≤2 V - 45
Fmax(2) Maximum frequency C = 30 pF, 1.71 V ≤ VDD≤2 V - 50 MHz
C = 20 pF, 1.71 V ≤ VDD≤2 V - 55
C = 10 pF, 1.71 V ≤ VDD≤2 V - 60
01
C = 50 pF, 1.71 V ≤ VDD≤2 V - 7.2
C = 40 pF, 1.71 V ≤ VDD≤2 V - 6.5
tr/tf(3)(4) fall time and output low C = 30 pF, 1.71 V ≤ VDD≤2 V - 5.6 ns
C = 20 pF, 1.71 V ≤ VDD≤2 V - 4.8
C = 10 pF, 1.71 V ≤ VDD≤2 V - 3.8
C = 50 pF, 1.71 V ≤ VDD≤2 V - 60
C = 40 pF, 1.71 V ≤ VDD≤2 V - 70
(2)(4)
Fmax Maximum frequency C = 30 pF, 1.71 V ≤ VDD≤2 V - 90 MHz
C = 20 pF, 1.71 V ≤ VDD≤2 V - 110
C = 10 pF, 1.71 V ≤ VDD≤2 V - 140
10
C = 50 pF, 1.71 V ≤ VDD≤2 V - 5.3
C = 40 pF, 1.71 V ≤ VDD≤2 V - 4.6
(3)(4)
tr/tf fall time and output low C = 30 pF, 1.71 V ≤ VDD≤2 V - 3.8 ns
C = 20 pF, 1.71 V ≤ VDD≤2 V - 3.0
C = 10 pF, 1.71 V ≤ VDD≤2 V - 2.2
212/320 DS14359 Rev 2

Table 76. Output timing characteristics (HSLV ON)(1) (continued)

C = 50 pF, 1.71 V ≤ VDD≤2 V - 67

C = 40 pF, 1.71 V ≤ VDD≤2 V - 100
(2)(4)
Fmax Maximum frequency C = 30 pF, 1.71 V ≤ VDD≤2 V - 120 MHz
C = 20 pF, 1.71 V ≤ VDD≤2 V - 155
C = 10 pF, 1.71 V ≤ VDD≤2 V - 200
11
C = 50 pF, 1.71 V ≤ VDD≤2 V - 5.0
C = 40 pF, 1.71 V ≤ VDD≤2 V - 4.1
tr/tf(3)(4) fall time and output low C = 30 pF, 1.71 V ≤ VDD≤2 V - 3.3 ns
C = 20 pF, 1.71 V ≤ VDD≤2 V - 2.5
C = 10 pF, 1.71 V ≤ VDD≤2 V - 1.8
2. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45% < Duty cycle < 55%
3. The fall and rise times are defined, respectively, between 90 and 10% and between 10 and 90% of the output waveform.
4. Compensation system enabled.
Table 77. Output timing characteristics VDDXSPIx 1.2 V range (HSLV OFF)(1)
Speed Symbol Parameter conditions Min Max Unit
C = 50 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 1

C = 40 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 1
Fmax(2) Maximum frequency C = 30 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 1 MHz
C = 20 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 1
C = 10 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 1
00
C = 50 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 83.0
Output high to low C = 40 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 79.0
level fall time and
tr/tf(3) C = 30 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 46.0 ns
output low to high level
rise time C = 20 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 72.0
C = 10 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 68.0
DS14359 Rev 2 213/320

284
Table 77. Output timing characteristics VDDXSPIx 1.2 V range (HSLV OFF)(1) (continued)
C = 50 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 5

C = 40 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 5
C = 20 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 5
C = 10 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 5
01
C = 50 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 24.5
level fall time and
C = 10 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 15.0
C = 50 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 10
C = 40 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 10
C = 20 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 10
C = 10 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 10
10
C = 50 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 16.2
level fall time and
C = 10 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 7.9
C = 50 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 20
C = 40 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 23
Fmax(2)(4) Maximum frequency C = 30 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 25 MHz
C = 20 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 28
C = 10 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 30
11
C = 50 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 14.0
level fall time and
tr/tf(3)(4) C = 30 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 10.0 ns
C = 10 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 6.0
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45% < Duty cycle < 55%
214/320 DS14359 Rev 2

Table 78. Output timing characteristics VDDXSPIx 1.2 V (HSLV ON)(1)

C = 50 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 5

C = 40 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 5
Fmax (2)
Maximum frequency C = 30 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 5 MHz
C = 20 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 5
C = 10 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 5
00
C = 50 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 32.5
C = 40 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 30.0
tr/tf(3) fall time and output low C = 30 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 27.5 ns
C = 20 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 25.0
C = 10 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 22.5
C = 50 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 15.0
C = 40 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 17.5
(2)
Fmax Maximum frequency C = 30 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 20.0 MHz
C = 20 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 22.5
C = 10 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 25.0
01
C = 50 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 14.6
C = 40 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 12.9
tr/tf(3) fall time and output low C = 30 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 11.2 ns
C = 20 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 9.3
C = 10 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 7.3
C = 50 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 25
C = 40 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 30
Fmax (2)(4)
Maximum frequency C = 30 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 33 MHz
C = 20 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 44
C = 10 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 55
10
C = 50 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 11.6
C = 40 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 9.7
tr/tf(3)(4) fall time and output low C = 30 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 7.8 ns
C = 20 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 6.1
C = 10 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 4.3
DS14359 Rev 2 215/320

284
Table 78. Output timing characteristics VDDXSPIx 1.2 V (HSLV ON)(1) (continued)
C = 50 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 30

C = 40 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 35
(2)(4)
Fmax Maximum frequency C = 30 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 44 MHz
C = 20 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 55
C = 10 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 77
11
C = 50 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 11.1
C = 40 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 9.2
tr/tf(3)(4) fall time and output low C = 30 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 7.2 ns
C = 20 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 5.4
C = 10 pF, 1.08 V ≤ VDDXSPIx≤1.32 V - 3.6
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
216/320 DS14359 Rev 2

6.3.16 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 71: I/O static characteristics).
Unless otherwise specified, the parameters in Table 79 are derived from tests performed
under the ambient temperature and VDD supply voltage conditions summarized in Table 23:
Voltage characteristics.
Table 79. NRST pin characteristics

RPU(2) Weak pull-up equivalent resistor(1) VIN = VSS 30 40 50 kΩ

VF(NRST) (2) NRST input filtered pulse 1.71 V < VDD < 3.6 V - - 50
ns
VNF(NRST)(2) NRST input not filtered pulse 1.71 V < VDD < 3.6 V 350 - -
1. The pull-up is designed with a true resistance in series with a switchable PMOS. The PMOS contribution to
the series resistance is minimum (~10 % order).
Figure 38. Recommended NRST pin protection
VDD
External
reset circuit (1)
RPU
NRST (2) Internal Reset
Filter
0.1 μF
STM32
ai14132d
1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 71, otherwise the reset is not taken into account by the device.
6.3.17 FMC characteristics

Unless otherwise specified, the parameters given in Table 80 to Table 93 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 26: General operating conditions,
with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5VDD
• IO Compensation cell activated.
• HSLV activated when VDD ≤ 2.7 V
• VOS level set to VOS high.
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics.
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284
Asynchronous waveforms and timings

Figure 39 through Figure 41 represent asynchronous waveforms and Table 80 through
Table 87 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
• BusTurnAroundDuration = 0x0
• Capacitive load CL = 30 pF
In all timing tables, the TKERCK is the fmc_ker_ck clock period.
Table 80. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)

tw(NE) FMC_NE low time 3Tfmc_ker_ck –1 3Tfmc_ker_ck+1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 1
tw(NOE) FMC_NOE low time 2Tfmc_ker_ck –1 2Tfmc_ker_ck+1
FMC_NOE high to FMC_NE high
th(NE_NOE) Tfmc_ker_ck -
hold time
tv(A_NE) FMC_NEx low to FMC_A valid - 1
Address hold time after
th(A_NOE) 2Tfmc_ker_ck-1 -
FMC_NOE high
Data to FMC_NEx high setup ns
tsu(Data_NE) Tfmc_ker_ck+12.5 -
time
Data to FMC_NOEx high setup
tsu(Data_NOE) 12.5 -
time
Data hold time after FMC_NOE
th(Data_NOE) 0 -
high
Data hold time after FMC_NEx
th(Data_NE) 0 -
high
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 1
tw(NADV) FMC_NADV low time - Tfmc_ker_ck+1
218/320 DS14359 Rev 2

Table 81. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT

timings(1)(2)
tw(NE) FMC_NE low time 8Tfmc_ker_ck–1 8Tfmc_ker_ck+1

tw(NOE) FMC_NOE low time 7Tfmc_ker_ck–1 7Tfmc_ker_ck +1
tw(NWAIT) FMC_NWAIT low time Tfmc_ker_ck -
ns
FMC_NWAIT valid before FMC_NEx
tsu(NWAIT_NE) 5Tfmc_ker_ck +12 -
high
FMC_NEx hold time after
th(NE_NWAIT) 4Tfmc_ker_ck+12 -
FMC_NWAIT invalid
2. NWAIT pulse width is equal to 1 fmc_ker_ck cycle.
Figure 39. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
tw(NE)
FMC_NE
tv(NOE_NE) t w(NOE) t h(NE_NOE)
FMC_NOE
FMC_NWE
tv(A_NE) t h(A_NOE)
FMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)
FMC_NBL[1:0]
t h(Data_NE)
t su(Data_NOE) th(Data_NOE)
t su(Data_NE)
FMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
DS14359 Rev 2 219/320

284
Table 82. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)

tw(NE) FMC_NE low time 3Tfmc_ker_ck –1 3Tfmc_ker_ck + 1

tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck–1 Tfmc_ker_ck+0.5
tw(NWE) FMC_NWE low time Tfmc_ker_ck –0.5 Tfmc_ker_ck+0.5
FMC_NWE high to FMC_NE high
th(NE_NWE) Tfmc_ker_ck+1 -
hold time
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
Address hold time after FMC_NWE
th(A_NWE) Tfmc_ker_ck -
high ns
tv(BL_NE) FMC_NEx low to FMC_BL valid - 1
FMC_BL hold time after FMC_NWE
th(BL_NWE) Tfmc_ker_ck +0.5 -
high
tv(Data_NE) Data to FMC_NEx low to Data valid - Tfmc_ker_ck+ 0.5
th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck + 2 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0.5
tw(NADV) FMC_NADV low time - Tfmc_ker_ck+ 0.5
Table 83. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT

timings(1)(2)

tw(NWE) FMC_NWE low time 6Tfmc_ker_ck –1 6Tfmc_ker_ck+1
FMC_NWAIT valid before FMC_NEx ns
tsu(NWAIT_NE) 5Tfmc_ker_ck+13 -
high
th(NE_NWAIT) 4Tfmc_ker_ck+13 -
FMC_NWAIT invalid
220/320 DS14359 Rev 2

Figure 40. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

tw(NE)
FMC_NEx
FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)
FMC_NWE
tv(A_NE) th(A_NWE)
FMC_A[25:0] Address
tv(BL_NE) th(BL_NWE)
FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)
FMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
DS14359 Rev 2 221/320

284
Table 84. Asynchronous multiplexed PSRAM/NOR read timings(1)

tw(NE) FMC_NE low time 4Tfmc_ker_ck –1 4Tfmc_ker_ck +1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 2Tfmc_ker_ck –1 2Tfmc_ker_ck +1
ttw(NOE) FMC_NOE low time Tfmc_ker_ck –1 Tfmc_ker_ck+1
FMC_NOE high to FMC_NE high hold
th(NE_NOE) Tfmc_ker_ck -
time
tv(A_NE) FMC_NEx low to FMC_A valid - 1
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1
tw(NADV) FMC_NADV low time Tfmc_ker_ck –1 Tfmc_ker_ck +1
ns
FMC_AD(address) valid hold time
th(AD_NADV) Tfmc_ker_ckk –3 -
after FMC_NADV high)
Address hold time after FMC_NOE
th(A_NOE) 2Tfmc_ker_ck –1 -
high
tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck +12 -
tsu(Data_NOE) Data to FMC_NOE high setup time 12 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
Table 85. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)

tw(NE) FMC_NE low time 9Tfmc_ker_ck –1 9Tfmc_ker_ck +1

tw(NOE) FMC_NWE low time 6Tfmc_ker_ck –1 6Tfmc_ker_ck +1
FMC_NWAIT valid before ns
FMC_NEx high
th(NE_NWAIT) 4Tfmc_ker_ck +13 -
FMC_NWAIT invalid
222/320 DS14359 Rev 2

Figure 41. Asynchronous multiplexed PSRAM/NOR read waveforms

tw(NE)
FMC_ NE
tv(NOE_NE) t h(NE_NOE)
FMC_NOE
t w(NOE)
FMC_NWE
tv(A_NE) th(A_NOE)
FMC_ A[25:16] Address

tv(BL_NE) th(BL_NOE)
FMC_ NBL[1:0] NBL

th(Data_NE)
tsu(Data_NE)
t v(A_NE) tsu(Data_NOE) th(Data_NOE)
FMC_ AD[15:0] Address Data
t v(NADV_NE) th(AD_NADV)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
DS14359 Rev 2 223/320

284
Table 86. Asynchronous multiplexed PSRAM/NOR write timings(1)


tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck –0.5 Tfmc_ker_ck +0.5
tw(NWE) FMC_NWE low time 2Tfmc_ker_ck –0.5 2Tfmc_ker_ck +0.5
FMC_NWE high to FMC_NE high hold
th(NE_NWE) Tfmc_ker_ck +1 -
time
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5
tw(NADV) FMC_NADV low time Tfmc_ker_ck –0.5 Tfmc_ker_ck + 0.5
ns
FMC_AD(adress) valid hold time after
th(AD_NADV) Tfmc_ker_ck –1.5 -
FMC_NADV high)
Address hold time after FMC_NWE
th(A_NWE) Tfmc_ker_ck -
high
FMC_BL hold time after FMC_NWE
th(BL_NWE) Tfmc_ker_c + 0.5 -
high
tv(BL_NE) FMC_NEx low to FMC_BL valid - 1
tv(Data_NADV) FMC_NADV high to Data valid - Tfmc_ker_ck +0.5
th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck+ 2 -
Table 87. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)

tw(NE) FMC_NE low time 9Tfmc_ker_ck –1 9Tfmc_ker_ck + 1

tw(NWE) FMC_NWE low time 7Tfmc_ker_ck –1 7Tfmc_ker_ck +1
FMC_NWAIT valid before FMC_NEx ns
high
th(NE_NWAIT) 4Tfmc_ker_ck +13 -
FMC_NWAIT invalid
224/320 DS14359 Rev 2

Synchronous waveforms and timings

Figure 44 through Figure 43 represent synchronous waveforms and Table 90 through
Table 89 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable
• MemoryType = FMC_MemoryType_CRAM
• WriteBurst = FMC_WriteBurst_Enable
• CLKDivision = 1
• DataLatency = 1 for NOR flash, DataLatency = 0 for PSRAM, CL = 30 pF
In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following
FMC_CLK maximum values:
• For 2.7 V<VDD<3.6 V: maximum FMC_CLK = 125 MHz at CL = 20 pF
Note: At VOS low, the performance can be degraded by up to 7% compared to VOS high.
Table 88. Synchronous non-multiplexed NOR/PSRAM read timings(1)

Symbol Parameter Min Max(2) Unit
tw(CLK) FMC_CLK period 2Tfmc_ker_ck –0.5 -

FMC_CLK low to FMC_NEx low
t(CLKL-NExL) - 2
(x=0..2)
FMC_CLK high to FMC_NEx high
td(CLKH-NExH) Tfmc_ker_ck+1 -
(x= 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 -
FMC_CLK low to FMC_Ax valid
td(CLKL-AV) - 2
(x=16…25)
FMC_CLK high to FMC_Ax invalid
td(CLKH-AIV) Tfmc_ker_ck -
(x=16…25) ns
td(CLKL-NOEL) FMC_CLK ow to FMC_NOE low - 2
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck -
FMC_D[15:0] valid data before
tsu(DV-CLKH) 2.5 -
FMC_CLK high
FMC_D[15:0] valid data after
th(CLKH-DV) 1.5 -
FMC_CLK high
FMC_NWAIT valid before
t(NWAIT-CLKH) 2.5 -
FMC_CLK high
FMC_NWAIT valid after FMC_CLK
th(CLKH-NWAIT) 1 -
high
2. At VOS Low, these values are degraded by up to 7%.
DS14359 Rev 2 225/320

284
Figure 42. Synchronous non-multiplexed NOR/PSRAM read timings
tw(CLK) tw(CLK)
FMC_CLK
td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
td(CLKL-AV) td(CLKH-AIV)
FMC_A[25:0]
td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)
FMC_D[15:0] D1 D2
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) t h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
MS32759V1
226/320 DS14359 Rev 2

Table 89. Synchronous non-multiplexed PSRAM write timings(1)

t(CLK) FMC_CLK period 2Tfmc_ker_ck –0.5 -

td(CLKL-NExL) - 2
(x=0..2)
t(CLKH-NExH) Tfmc_ker_ck+1 -
(x= 0…2)
FMC_CLK low to FMC_NADV
td(CLKL-NADVL) - 2
low
FMC_CLK low to FMC_NADV
td(CLKL-NADVH) 1 -
high
td(CLKL-AV) - 2
(x=16…25)
FMC_CLK high to FMC_Ax
invalid (x=16…25) ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1
FMC_CLK high to FMC_NWE
td(CLKH-NWEH) Tfmc_ker_ck -
high
FMC_D[15:0] valid data after
td(CLKL-Data) - 2
FMC_CLK low
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
FMC_CLK high to FMC_NBL
td(CLKH-NBLH) Tfmc_ker_ck+0.5 -
high
FMC_NWAIT valid before
tsu(NWAIT-CLKH) 2.5 -
FMC_CLK high
FMC_NWAIT valid after
th(CLKH-NWAIT) 1 -
FMC_CLK high
DS14359 Rev 2 227/320

284
Figure 43. Synchronous non-multiplexed PSRAM write timings

tw(CLK) tw(CLK)
FMC_CLK
Data latency = 0
FMC_NEx
FMC_NADV
FMC_A[25:0]
td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE
td(CLKL-Data) td(CLKL-Data)
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH)
th(CLKH-NWAITV)
FMC_NBL
MS32760V1
228/320 DS14359 Rev 2

Table 90. Synchronous multiplexed NOR/PSRAM read timings(1)

tw(CLK) FMC_CLK period 2Tfmc_ker_ck –0.5 -

td(CLKL-NExL) - 2
(x=0..2)
td(CLKH_NExH) Tfmc_ker_ck+1 -
(x= 0…2)
td(CLKL-AV) - 2
(x=16…25)
FMC_CLK high to FMC_Ax invalid
(x=16…25)
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 2
ns
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck -
FMC_CLK low to FMC_AD[15:0]
td(CLKL-ADV) - 2.5
valid
FMC_CLK low to FMC_AD[15:0]
td(CLKL-ADIV) 0 -
invalid
FMC_A/D[15:0] valid data before
tsu(ADV-CLKH) 2.5 -
FMC_CLK high
FMC_A/D[15:0] valid data after
th(CLKH-ADV) 1.5 -
FMC_CLK high
FMC_NWAIT valid before FMC_CLK
tsu(NWAIT-CLKH) 2.5 -
high
FMC_NWAIT valid after FMC_CLK
th(CLKH-NWAIT) 1 -
high
DS14359 Rev 2 229/320

284
Figure 44. Synchronous multiplexed NOR/PSRAM read timings
tw(CLK) tw(CLK) BUSTURN = 0
FMC_CLK
Data latency = 0
FMC_NEx
t d(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
FMC_A[25:16]
td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE
td(CLKL-ADIV) th(CLKH-ADV)
t d(CLKL-ADV) tsu(ADV-CLKH) tsu(ADV-CLKH) th(CLKH-ADV)
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32757V1
230/320 DS14359 Rev 2

Table 91. Synchronous multiplexed PSRAM write timings(1)

tw(CLK) FMC_CLK period, VDD = 2.7 to 3.6 V 2Tfmc_ker_ck –0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x =0..2) - 2
td(CLKH-NExH) Tfmc_ker_ck +1 -
(x = 0…2)
FMC_CLK low to FMC_Ax valid (x
td(CLKL-AV) - 2
=16…25)
FMC_CLK high to FMC_Ax invalid (x
=16…25)
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1 ns
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck -
td(CLKL-ADV) FMC_CLK low to to FMC_AD[15:0] valid - 2
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
FMC_A/D[15:0] valid data after
td(CLKL-DATA) - 2
FMC_CLK low
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck +0.5 -
FMC_NWAIT valid before FMC_CLK
tsu(NWAIT-CLKH) 2 -
high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 -
DS14359 Rev 2 231/320

284
Figure 45. Synchronous multiplexed PSRAM write timings
tw(CLK) tw(CLK) BUSTURN = 0
FMC_CLK
Data latency = 0
FMC_NEx
FMC_NADV
FMC_A[25:16]
td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE
td(CLKL-ADIV) td(CLKL-Data)
td(CLKL-ADV) td(CLKL-Data)
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)
td(CLKH-NBLH)
FMC_NBL
MS32758V1
232/320 DS14359 Rev 2

NAND controller waveforms and timings

Figure 46 through Figure 49 represent synchronous waveforms, and Table 92 and Table 93
provide the corresponding timings. The results shown in this table are obtained with the
following FMC configuration and a capacitive load (CL) of 30 pF:
• COM.FMC_SetupTime = 0x01
• COM.FMC_WaitSetupTime = 0x03
• COM.FMC_HoldSetupTime = 0x02
• COM.FMC_HiZSetupTime = 0x01
• ATT.FMC_SetupTime = 0x01
• ATT.FMC_WaitSetupTime = 0x03
• ATT.FMC_HoldSetupTime = 0x02
• ATT.FMC_HiZSetupTime = 0x01
• Bank = FMC_Bank_NAND
• MemoryDataWidth = FMC_MemoryDataWidth_16b
• ECC = FMC_ECC_Enable
• ECCPageSize = FMC_ECCPageSize_512Bytes
• TCLRSetupTime = 0
• TARSetupTime = 0
In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.
Table 92. Switching characteristics for NAND flash read cycles(1)

tw(N0E) FMC_NOE low width 4Tfmc_ker_ck – 0.5 4Tfmc_ker_ck+0.5

FMC_D[15-0] valid data before
tsu(D-NOE) 12.5 -
FMC_NOE high
FMC_D[15-0] valid data after ns
th(NOE-D) 0 -
FMC_NOE high
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3Tfmc_ker_ck +0.5
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 4Tfmc_ker_ck –1 -
DS14359 Rev 2 233/320

284
Figure 46. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
td(ALE-NOE) th(NOE-ALE)
FMC_NOE (NRE)
tsu(D-NOE) th(NOE-D)
FMC_D[15:0]
MS32767V1
Figure 47. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) th(NOE-ALE)
FMC_NWE
tw(NOE)
FMC_NOE
tsu(D-NOE) th(NOE-D)
FMC_D[15:0]
MS32769V1
Table 93. Switching characteristics for NAND flash write cycles(1)

tw(NWE) FMC_NWE low width 4Tfmc_ker_ck – 0.5 4Tfmc_ker_ck +0.5

FMC_NWE low to FMC_D[15-0]
tv(NWE-D) 0 -
valid
FMC_NWE high to FMC_D[15-0]
th(NWE-D) 2Tfmc_ker_ck +1 -
invalid
ns
FMC_D[15-0] valid before
td(D-NWE) 5Tfmc_ker_ck – 2 -
FMC_NWE high
FMC_ALE valid before FMC_NWE
td(ALE-NWE) - 3Tfmc_ker_ck -1
low
th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 2Tfmc_ker_ck + 1.5 -
234/320 DS14359 Rev 2

Figure 48. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NWE) th(NWE-ALE)
FMC_NWE
FMC_NOE (NRE)
tv(NWE-D) th(NWE-D)
FMC_D[15:0]
MS32768V1
Figure 49. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) tw(NWE) th(NOE-ALE)
FMC_NWE
FMC_N OE
td(D-NWE)
tv(NWE-D) th(NWE-D)
FMC_D[15:0]
MS32770V1
DS14359 Rev 2 235/320

284
SDRAM waveforms and timings

In all timing tables, Tfmc_ker_ck is the fmc_ker_ck clock period, with the following
FMC_SDCLK maximum values:
• For 2.7 V<VDD<3.6 V: maximum FMC_CLK = 95 MHz at 20 pF
• For 1.71 V<DD<1.9 V: maximum FMC_CLK = 95 MHz at 15 pF
Note: At VOS low, the performance can be degraded by up to 7 % compared to VOS high.
Table 94. SDRAM read timings(1)

tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 0.5 2Tfmc_ker_ck +0.5

tsu(SDCLKH _Data) Data input setup time 2.5 -
th(SDCLKH_Data) Data input hold time 0.5 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL- SDNE) Chip select valid time - 1
ns
th(SDCLKL_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1.5
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1.5
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
Table 95. LPSDR SDRAM read timings(1)

tW(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 0.5 2Tfmc_ker_ck+0.5

tsu(SDCLKH_Data) Data input setup time 2 -
th(SDCLKH_Data) Data input hold time 1 -
td(SDCLKL_SDNE) Chip select valid time - 1
ns
th(SDCLKL_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS SDNRAS valid time - 1.5
td(SDCLKL_SDNCAS) SDNCAS valid time - 1.5
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
236/320 DS14359 Rev 2

Figure 50. SDRAM read access waveforms (CL = 1)
FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)
FMC_A[12:0] Row n Col1 Col2 Coli Coln
th(SDCLKL_AddC)
td(SDCLKL_SNDE) th(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)
FMC_SDNRAS
td(SDCLKL_NCAS) th(SDCLKL_NCAS)
FMC_SDNCAS
FMC_SDNWE
tsu(SDCLKH_Data) th(SDCLKH_Data)
FMC_D[31:0] Data1 Data2 Datai Datan
Table 96. SDRAM Write timings(1)

tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 0.5 2Tfmc_ker_ck+0.5

td(SDCLKL _Data) Data output valid time - 1.5
th(SDCLKL _Data) Data output hold time 0 -
td(SDCLKL_SDNWE) SDNWE valid time - 1.5
th(SDCLKL_SDNWE) SDNWE hold time 0.5 -
ns
td(SDCLKL_ SDNE) Chip select valid time - 1
th(SDCLKL-_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1
td(SDCLKL_SDNCAS) SDNCAS valid time - 1
td(SDCLKL_SDNCAS) SDNCAS hold time 0 -
DS14359 Rev 2 237/320

284
Table 97. LPSDR SDRAM Write timings(1)

tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 0.5 2Tfmc_ker_ck+0.5

td(SDCLKL _Data) Data output valid time - 1.5
th(SDCLKL _Data) Data output hold time 0 -
td(SDCLKL-SDNWE) SDNWE valid time - 1.5
th(SDCLKL-SDNWE) SDNWE hold time 0.5 -
ns
td(SDCLKL- SDNE) Chip select valid time - 1
th(SDCLKL- SDNE) Chip select hold time 0 -
td(SDCLKL-SDNRAS) SDNRAS valid time - 1
th(SDCLKL-SDNRAS) SDNRAS hold time 0 -
td(SDCLKL-SDNCAS) SDNCAS valid time - 1
td(SDCLKL-SDNCAS) SDNCAS hold time 0 -
238/320 DS14359 Rev 2

Figure 51. SDRAM write access waveforms
FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)
FMC_A[12:0] Row n Col1 Col2 Coli Coln
th(SDCLKL_AddC)
td(SDCLKL_SNDE) th(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)
FMC_SDNRAS
td(SDCLKL_NCAS) th(SDCLKL_NCAS)
FMC_SDNCAS
td(SDCLKL_NWE) th(SDCLKL_NWE)
FMC_SDNWE
td(SDCLKL_Data)
FMC_D[31:0] Data1 Data2 Datai Datan
td(SDCLKL_NBL) th(SDCLKL_Data)
FMC_NBL[3:0]
MS32752V2
DS14359 Rev 2 239/320

284
6.3.18 XSPI interface characteristics

Unless otherwise specified, the parameters given in Table 98 and Table 100 for XSPI are
derived from tests performed under the ambient temperature, fHCLK frequency and VDD
supply voltage conditions summarized in Table 26: General operating conditions, with the
following configuration:
• VOS level set to VOS high
Table 98. XSPI characteristics in SDR mode(1)

Symbol Parameter Conditions Min Typ Max(2) Unit
2.7 V < VDD < 3.6 V,

2.7 V<VDDXSPI1/2<3.6 V, - - 180(3)
CLOAD = 15 pF
F(CLK) XSPI clock frequency MHz
1.71 V < VDD < 3.6 V,
1.62 V<VDDXSPI1/2<3.6 - - 145(3)
V, CLOAD =15 pF
tw(CLKH) XSPI clock high and low PRESCALER[7:0] = n = t(CLK)/2 - t(CLK)/2+1
tw(CLKL) time, even division 0,1,3,5 t(CLK)/2–1 - t(CLK)/2
(n/2)*t(CLK)/ (n/2)*t(CLK)/
tw(CLKH) -
XSPI clock high and low PRESCALER[7:0] = n = (n+1) (n+1)+1
time, odd division 2,4,6,8 (n/2+1)*t(CLK)/ (n/2+1)*t(CLK)/
tw(CLKL) - ns
(n+1)–1 (n+1)
ts(IN) Data input setup time - 2.0 - -
th(IN) Data input hold time - 2.5 - -
tv(OUT) Data output valid time - - 0.5 1
th(OUT) Data output hold time - 0 - -
1. Guaranteed by characterizatin results.
3. Tuning COARSE[4:0] and FINE[6:0] of the XSPI_CALMR register is required to achieve this frequency
240/320 DS14359 Rev 2

Table 99. XSPI characteristics in DTR mode (no DQS)(1)

1.71 V < VDD < 3.6 V,

F(CLK) XSPI clock frequency 1.62 V<VDDXSPI1/2<3.6 - - 135(3) MHz
V, CLOAD = 15 pF
tw(CLKH) XSPI clock high and PRESCALER[7:0] = t(CLK)/2 - t(CLK)/2+1
tw(CLKL) low time, even division n = 0,1,3,5 t(CLK)/2–1 - t(CLK)/2
(n/2)*t(CLK)/ (n/2)*t(CLK)/
tw(CLKH) -
XSPI clock high and PRESCALER[7:0] = (n+1) (n+1)+1
low time, odd division n = 2,4,6,8 (n/2+1)*t(CLK) (n/2+1)*
tw(CLKL) -
/(n+1) – 1 t(CLK)/(n+1)
tsr(IN)
Data input setup time - 2.0 - -
tsf(IN)
ns
thr(IN)
Data input hold time - 2.5 - -
thf(IN)
- t(CLK)/4+ 0.5 t(CLK)/4+1.5
tvr(OUT)
Data output valid time Prescaler = 0, -
tvf(OUT) 5 7
F(CLK)<60 MHz
- t(CLK)/4 - 0.5
thr(OUT)
Data output hold time Prescaler = 0, - -
thf(OUT) 3.5
F(CLK)<60 MHz
3. Tuning COARSE[4:0] and FINE[6:0] of the XSPI_CALMR register is required to achieve this frequency.
DS14359 Rev 2 241/320

284
Table 100. XSPI characteristics in DTR mode (with DQS)/Hyperbus(1)

1.71 V < VDD < 3.6 V,

1.62 V<VDDXSPI1/2<3.6 V, - - 190
CLOAD = 10 pF
F(CLK) XSPI clock frequency MHz
1.71 V < VDD < 3.6 V,
1.62 V<VDDXSPI1/2<3.6 V, - - 185
CLOAD = 15 pF
tw(CLKH) XSPI clock high and PRESCALER[7:0] = t(CLK)/2 - t(CLK)/2+1
ns
tw(CLKL) low time, even division n = 0,1,3,5 t(CLK)/2–1 - t(CLK)/2
(n/2)*t(CLK)/ (n/2)*t(CLK)/
tw(CLKH) -
XSPI clock high and PRESCALER[7:0] = (n+1) (n+1)+1
low time, odd division n = 2,4,6,8 (n/2+1)*t(CLK (n/2+1)*t(CLK
tw(CLKL) - ns
)/(n+1)–1 )/(n+1)
tv(CK) Clock valid time - - - t(CLK)+1

th(CK) Clock hold time - t(CLK)/2 - -
CK,CK crossing level VDD=VDDXSPI1
VODr(CK) 1024 - 1353
on CK rising edge =VDDXSPI2=1.8 V
mV
CK,CK crossing level VDD=VDDXSPI1
VODf(CK) 907 - 1229
on CK falling edge =VDDXSPI2=1.8 V
tw(CS) Chip select high time - 3*t(CLK) - -
tv(DQ) Data input vallid time - 0 - -
Data strobe input valid
tv(DS) - 0 - -
time
Data strobe input hold
th(DS) - 0 - -
time
Data strobe output
tv(RWDS) - - - 3 x t(CLK)
valid time
tsr(DQ), - 1.5 - t(CLK)/4

Data input setup time - - ns
tsf(DQ) F(CLK) < 60 MHz -3
thr(DQ), - 1.5 + t(ClK)/4

Data input hold time - -
thf(DQ) F(CLK) < 60 MHz 7.5
- - t(ClK)/4+0.5 t(ClK)/4+1.5
tvr(OUT),
Data output valid time Prescaler = 0,
tvf(OUT) 5 7
F(CLK) < 60 MHz
- t(ClK)/4-1
thr(OUT),
Data output hold time Prescaler = 0, -
thf(OUT) 3.5
F(CLK) < 60 MHz
242/320 DS14359 Rev 2

Figure 52. XSPI DTR (with DQS) write timing diagram
NCS
Read write recovery Access latency

tv(CLK) th(CLK)
CLK, NCLK
tv(RWDS) High = 2x latency count tv(OUT) th(OUT)

Low = 1x latency count
DQS[1:0]
Latency count
tv(OUT) th(OUT) tv(OUT) th(OUT)
Dn Dn Dn+1 Dn+1
IO[7:0] 47:40 39:32 31:24 23:16 15:8 7:0
A B A B
Command address
tv(OUT) th(OUT)
Dn Dn Dn+1 Dn+1
IO[15:8] A B A B
MSv69142V2
Figure 53. XSPI DTR (with DQS) read timing diagram
NCS
tv(CLK) tACC = initial access th(CLK)
CLK, NCLK
tv(RWDS) tv(DS) th(DS)
DQS0
tv(OUT) th(OUT) Latency count tv(DQ)
47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1

IO[7:0] A B A B
tv(RWDS) tv(DS) th(DS)

Command address
DQS1
tv(DQ)
Dn Dn Dn+1 Dn+1
IO[15:8] A B A B
MSv69141V2
Figure 54. XSPI DTR clock timing diagram

t(CLK) tw(CLKH) tw(CLKL)
t(NCLK) tw(NCLKL) tw(NCLKH)
CLK
VOD(CLK)
NCLK
MSv69140V2
DS14359 Rev 2 243/320

284
6.3.19 Delay block (DLYB) characteristics

Unless otherwise specified, the parameters given in Table 101 for the delay block are
supply voltage summarized in Table 26: General operating conditions, with the following
configuration:
Table 101. Delay block characteristics

tinit Initial delay - 2400 2500 3000

ps
tΔ Unit Delay - 41 48 57
244/320 DS14359 Rev 2

6.3.20 ADC characteristics

Unless otherwise specified, the parameters given in Table 102, Table 103 and Table 104 are
derived from tests performed under the ambient temperature and VDDA supply voltage
conditions summarized in Table 26: General operating conditions. In Table 102, Table 103
and Table 104, fADC refers to fadc_ker_ck.
Table 102. ADC characteristics(1)(2)

Paramete
Symbol Conditions Min Typ Max Unit
r
Analog
power
VDDA - 1.62 - 3.6
supply for
ADC ON
Positive
V
VREF+ reference - 1.62 - VDDA
voltage
Negative
VREF- reference - VSSA
voltage
ADC clock
fADC 1.62 V ≤ VDDA ≤ 3.6 V 1.5 - 75 MHz
frequency
1.8 V≤VDD fADC=

- 5.00 -
Continuou A≤3.6 V 75 MHz
s mode
1.6 V≤VDD fADC=
- 4.66
Resolutio A≤3.6 V 70 MHz
-40°C ≤ TJ
n = 12 SMP=2.5
2.4 V≤VDD ≤ 130°C
bits fADC=
- 4.00 -
Single or A≤3.6V 60 MHz
discontinu
ous mode 1.6 V≤VDD fADC=
- 3.33 -
A≤3.6 V 50 MHz
Sampling
rate for fast Continuou 1.6V≤VDDA fADC=
- 5.77 -
channels s Mode ≤3.6 V 75 MHz
(VIN[0:5]) Resolutio
2.4 V≤VDD -40°C ≤ TJ fADC=
n = 10 SMP=2.5 5.77 -
Single or A≤3.6 V ≤ 130°C 75 MHz
bits discontinu
fS(3) with ous mode 1.6 V≤VDD fADC=
5.00 -
RAIN=47Ω A≤3.6 V 65 MHz
MSPS
and
CPCB=22 pF Resolutio 1.6 V≤VDD -40°C ≤ TJ fADC=
All modes - 6.82 -
n = 8 bits A≤3.6V ≤ 130°C 75 MHz
SMP=2.5
Resolutio 1.6 V≤VDD -40°C ≤ TJ fADC=
All modes - 8.33 -
n = 6 bits A≤3.6V ≤ 130°C 75 MHz
Resolutio
fADC=
n = 12 - 2.30 -
35MHz
bits
Resolutio
Sampling fADC=
n = 10 - 2.70 -
1.6 V≤VDD -40°C ≤ TJ 35MHz
rate for slow bits All modes SMP=2.5
channels A≤3.6 V ≤ 130°C
Resolutio fADC=
- 4.50 -
n = 8 bits 50MHz
Resolutio fADC=
- 5.50 -
n = 6 bits 50MHz
External
tTRIG trigger Resolution = 12 bits - - 15 1/fADC
period
DS14359 Rev 2 245/320

284
Table 102. ADC characteristics(1)(2) (continued)

Paramete
r
Conversion
VAIN(2) voltage - 0 - VREF+
range
V
Common VREF/
VREF/ VREF/2
VCMIV mode input - 2−
2 + 10%
voltage 10%
Resolution = 12 bits, TJ = 140°C (Tolerance 4 LSBs) - - 321
Resolution = 12 bits, TJ = 125°C - - 220

External
RAIN(4) input Resolution = 10 bits, TJ = 125°C - - 2100 Ω
impedance
Internal
sample and
CADC - - 3 - pF
hold
capacitor
tADCVREG_ ADC LDO

- - 5 10 µs
STUP startup time
ADC power- Conversion

tSTAB LDO already started 1 - -
up time cycles
Offset
tOFF_CAL calibration - 1335
time
Trigger CKMODE = 00 1.5 2 2.5

conversion
latency for CKMODE = 01 - - 2.5
regular and
tLATR injected CKMODE = 10 2.5
channels
without
aborting the CKMODE = 11 2.25
conversion
Trigger CKMODE = 00 2.5 3 3.5

conversion
latency for CKMODE = 01 - - 3.5 fADC clock
regular and cycles
injected CKMODE = 10 - - 3.5
tLATRINJ
channels
when a
regular CKMODE = 11 - - 3.25
conversion
is aborted
Sampling
tS - 2.5 - 640.5
time
Total
conversion
tS +
time
tCONV N-bits resolution 0.5 +
(including
N
sampling
time)
246/320 DS14359 Rev 2

Table 102. ADC characteristics(1)(2) (continued)

Paramete
r
ADC fs= 5 MSPS - 600 -
consumption
on fs= 1 MSPS - 190 -
IDDA_D(ADC) VDDA and
VREF,
Differential fs= 0.1 MSPS - 50 -
mode
ADC fs= 5 MSPS - 500 -

consumption
on VDDA fs= 1 MSPS - 150 -
IDDA_SE(ADC)
and VREF
Single- fs= 0.1 MSPS - 50 - µA
ended mode
fADC=75 MHz - 265 -
fADC=50 MHz 175 -
ADC fADC=25 MHz - 90 -

IDD(ADC) consumption
on VDD fADC=12.5 MHz - 45 -
fADC=6.25 MHz - 22 -
fADC=3.125 MHz - 11 -
2. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches).
3. These values are valid on BGA packages
4. The tolerance is 2 LSBs for 12-bit, 10-bit and 8-bit resolutions, unless otherwise specified.
DS14359 Rev 2 247/320

284
Table 103. Minimum sampling time vs RAIN (12-bit ADC)(1)(2)

Minimum sampling time (s)
Resolution RAIN (Ω)
Fast channels(3) Slow channels(4)
47 3.75E-08 6.12E-08
68 3.94E-08 6.25E-08
100 4.36E-08 6.51E-08
150 5.11E-08 7.00E-08
12 bits
220 6.54E-08 7.86E-08
330 8.80E-08 9.57E-08
470 1.17E-07 1.23E-07
680 1.60E-07 1.65E-07
47 3.19E-08 5.17E-08
68 3.35E-08 5.28E-08
100 3.66E-08 5.45E-08
150 4.35E-08 5.83E-08
220 5.43E-08 6.50E-08
330 7.18E-08 7.89E-08
10 bits
470 9.46E-08 1.00E-07
680 1.28E-07 1.33E-07
1000 1.81E-07 1.83E-07
1500 2.63E-07 2.63E-07
2200 3.79E-07 3.76E-07
3300 5.57E-07 5.52E-07
248/320 DS14359 Rev 2

Table 103. Minimum sampling time vs RAIN (12-bit ADC)(1)(2) (continued)

Minimum sampling time (s)
Resolution RAIN (Ω)
Fast channels(3) Slow channels(4)
47 2.64E-08 4.17E-08
68 2.76E-08 4.24E-08
100 3.02E-08 4.39E-08
150 3.51E-08 4.66E-08
220 4.27E-08 5.13E-08
330 5.52E-08 6.19E-08
470 7.17E-08 7.72E-08
680 9.68E-08 1.00E-07
8 bits
1000 1.34E-07 1.37E-07
1500 1.93E-07 1.94E-07
2200 2.76E-07 2.74E-07
3300 4.06E-07 4.01E-07
4700 5.73E-07 5.62E-07
6800 8.21E-07 7.99E-07
10000 1.20E-06 1.17E-06
15000 1.79E-06 1.74E-06
47 2.14E-08 3.16E-08
68 2.23E-08 3.21E-08
100 2.40E-08 3.31E-08
150 2.68E-08 3.52E-08
220 3.13E-08 3.87E-08
330 3.89E-08 4.51E-08
470 4.88E-08 5.39E-08
680 6.38E-08 6.79E-08
6 bits
1000 8.70E-08 8.97E-08
1500 1.23E-07 1.24E-07
2200 1.73E-07 1.73E-07
3300 2.53E-07 2.49E-07
4700 3.53E-07 3.45E-07
6800 5.04E-07 4.90E-07
10000 7.34E-07 7.11E-07
15000 1.09E-06 1.05E-06
2. Data valid up to 130 °C, with a 22 pF PCB capacitor and VDDA = 1.6 V.
DS14359 Rev 2 249/320

284
3. Fast channels correspond to ADCx_INP0 to _INP5, and for ADCx_ INN0 to _INN5.
4. Slow channels correspond to all ADC inputs except for the Fast channels.
Table 104. ADC accuracy(1)(2)

Fast and slow Single ended - ±3.5 ±12

ET Total unadjusted error
channels Differential - ±2.5 ±7.5
- Single ended - ±3 ±5.5
EO Offset error
- Differential - ±2 ±3.5
- Single ended - ±3.5 ±11
EG Gain error LSB
- Differential - ±2.5 ±7
- Single ended ±0.75 +2/-1
ED Differential linearity error
- Differential - ±0.75 +2/-1
Fast and slow Single ended - ±2 ±6.5

EL Integral linearity error
channels Differential - ±1 ±4
Single ended - 10.8 -
ENOB Effective number of bits bits
Differential - 11.5 -
Signal-to-noise and Single ended - 68 -

SINAD
distortion ratio Differential - 71 -
Single ended - 70 -
SNR Signal-to-noise ratio dB
Differential - 72 -
Single ended - -70 -
THD Total harmonic distortion
Differential - -80 -
1. Data guaranteed by characterization for BGA packages. The values for LQFP packages might differ.
2. ADC DC accuracy values are measured after internal calibration in continuous mode.
250/320 DS14359 Rev 2

6.3.21 Voltage reference buffer characteristics
Table 105. VREFBUF characteristics(1)

VRS = 000 2.8 3.3 3.6
Normal mode,
VRS = 001 2.4 - 3.6
VDDA = 3.3 V
VRS = 010 2.1 - 3.6
VDDA Analog supply voltage
VRS = 000 1.62 - 2.80
Degraded mode(2) VRS = 001 1.62 - 2.40
VRS = 010 1.62 - 2.10
VRS = 000 2.4980(3) 2.5000 2.5035(3)
Normal mode at V
30 °C, VRS = 001 2.0460 2.0490 2.0520
Iload = 100 µA
VRS = 010 1.8010 1.8040 1.8060
Voltage reference VDDA-
VREFBUF_ VRS = 000 - VDDA
buffer output, at 30 °C, 150 mV
OUT Iload= 100 µA
VDDA-
Degraded mode(2) VRS = 001 - VDDA
150 mV
VDDA-
VRS = 010 - VDDA
150 mV
TRIM Trim step resolution - - - ±0.05 ±0.1 %
CL Load capacitor - - 0.5 1 1.50 µF
Equivalent Serial
esr - - - - 2 Ω
Resistor of CL
ILOAD Static load current - - - - 4 mA
2.8 V ≤ VDDA ≤ Iload = 500 µA - 200 -

Iline_reg Line regulation ppm/V
3.6 V Iload = 4 mA - 100 -
500 µA ≤ ILOAD ≤ ppm/
Iload_reg Load regulation Normal mode - 50 -
4 mA mA
Tcoeff
Temperature ppm/
Tcoeff -40 °C < TJ < +125 °C - - VREFINT
coefficient °C
+ 100
DC - 60 -
PSRR Power supply rejection dB
100 KHz - 40 -
CL=0.5 µF - 300 -
tSTART Start-up time CL=1 µF - 500 - µs
CL=1.5 µF - 650 -
Control of maximum
DC current drive on
IINRUSH - - 8 - mA
VREFBUF_OUT during
startup phase(4)
DS14359 Rev 2 251/320

284
Table 105. VREFBUF characteristics(1) (continued)

ILOAD = 0 µA - 15 25
VREFBUF
IDDA
consumption from ILOAD = 500 µA - 16 30 µA
(VREFBUF) V
DDA
ILOAD = 4 mA - 32 50
2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA- drop voltage).
3. Evaluated in characterization not tested in production.
4. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be
in the range of 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VRS = 010, 001 and 000, respectively.
6.3.22 Analog temperature sensor characteristics
Table 106. Temperature sensor characteristics

VSENSE linearity with temperature (from Vsensor voltage) - - 3

TL(1) °C
VSENSE linearity with temperature (from ADC counter) - - 3
Average slope (from VSENSE voltage) - 2 -
Avg_Slope(2) mV/°C
Average slope (from ADC counter) - 2 -
V30(3) Voltage at 30°C ± 5 °C - 0.62 - V
tstart_run Startup time in Run mode (buffer startup) - - 25.2
µs
(1)
tS_temp ADC sampling time when reading the temperature 9 - -
Isens(1) Sensor consumption - 0.18 0.31
µA
Isensbuf(1) Sensor buffer consumption - 3.8 6.5
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1
byte.
Table 107. Temperature sensor calibration values

Symbol Parameter Memory address
Temperature sensor raw data acquired value at

TS_CAL1 0x08FF F814 - 0x08FF F815
30 °C, VDDA=3.3 V
Temperature sensor raw data acquired value at
TS_CAL2 0x08FF F818 - 0x08FF F819
130 °C, VDDA=3.3 V
252/320 DS14359 Rev 2

6.3.23 Voltage booster for analog switch
Table 108. Voltage booster for analog switch characteristics(1)

VDD Supply voltage - 1.71 2.6 3.6 V

tSU(BOOST) Booster startup time - - - 50 µs
1.71 V ≤ VDD ≤ 2.7 V - - 125
IDD(BOOST) Booster consumption µA
2.7 V < VDD < 3.6 V - - 250
1. Evaluated by characterization - Not tested in production.
6.3.24 Digital temperature sensor characteristics
Table 109. Digital temperature sensor characteristics(1)

fDTS(2) Output clock frequency 500 750 1150 kHz

VDD_CORE =
Temperature linearity 1.19 V(3)
TLC(2) 1660 2100 2750 Hz/°C
coefficient
TJ = -40°C to
-13 - 4
Temperature offset 30°C
TTOTAL_ERROR(2) °C
measurement, all VOS TJ = 30°C to
-7 - 2
130°C
Additional error due to
TVDD_CORE - -1 - 1 °C
supply variation
tTRIM Calibration time - - - 2 ms
Wake-up time from off
tWAKE_UP state until DTS ready bit - - 67 116.00 µs
is set
DTS consumption on
IDDCORE_DTS - 8.5 30 70.0 µA
VDD_CORE
2. Evaluated by characterization - Not tested in production.
3. The characterization is done at VDD_CORE = 1.19 V for Typ/Min/Max.
6.3.25 VCORE monitoring characteristics
Table 110. VCORE monitoring characteristics

ADC sampling time when

ts_vcore - 1 - - µs
reading the VCORE voltage
DS14359 Rev 2 253/320

284
6.3.26 Temperature and VBAT monitoring
Table 111. VBAT monitoring characteristics

R Resistor bridge for VBAT - 4x26 - kΩ

Q Ratio on VBAT measurement - 4 - -
(1)
Er Error on Q -10 - +10 %
tS_vbat(1) ADC sampling time when reading VBAT input 9 - - µs
VBAThigh High supply monitoring - 3.575 -
V
VBATlow Low supply monitoring - 1.36 -
IVBATbuf(1) Sensor buffer consuption - 3.8 6.5 µA
Table 112. VBAT charging characteristics

VBRS in PWR_CR3= 0 - 5 -
RBC Battery charging resistor kΩ
VBRS in PWR_CR3= 1 1.5 -
Table 113. Temperature monitoring characteristics

TEMPhigh High temperature monitoring - 126 -

°C
TEMPlow Low temperature monitoring - -37 -
254/320 DS14359 Rev 2

6.3.27 Audio digital filter (ADF)

Unless otherwise specified, the parameters given in for ADF are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
conditions summarized in Table 26: General operating conditions, with the following
configuration:
• Voltage scale is set to VOS high
Refer to Table 6.3.15: I/O port characteristics for more details on the input/output alternate
Table 114. ADF characteristics(1)

Symbol Parameter Conditions Min Typ Max Units
Input clock frequency via the

FCCKI ADF_CCK[1:0] pin, in 1.71<VDD<3.6 V - - 25 MHz
SLAVE_SPI mode
Output clock frequency in
FCCKO 1.71<VDD<3.6 V - - 25 MHz
MASTER_SPI
Output clock frequency in
FCCKOLF 1.71<VDD<3.6 V - - 5 MHz
LF_MASTER_SPI
Input symbol rate in
FSYMB 1.71<VDD<3.6 V - - 20 MHz
MANCHESTER mode
ADF_CCK[1:0] input clock
THCCKI, TLCCKI In SLAVE_SPI mode 2 x Tadf_proc_ck - - ns
high and low time
ADF_CCK[1:0] output clock In MASTER_SPI
THCCKO, TLCCKO 2 x Tadf_proc_ck - - ns
high and low time mode
THCCKOLF, ADF_CCK[1:0] output clock In LF_MASTER_SPI
Tadf_proc_ck - - ns
TLCCKOLF high and low time mode
Data setup time w.r.t. In SLAVE_SPI mode:
TSUCCKI 2.5 - - ns
ADF_CCK[1:0] input ADF_CCK[1:0]
configured in input,
Data hold time w.r.t. measured on rising
THDCCKI 0.5 - - ns
ADF_CCK[1:0] input and falling edge
Data setup time w.r.t. In MASTER_SPI
TSUCCKO 3 - - ns
ADF_CCK[1:0] output mode: ADF_CCK[1:0]
configured in output,
THDCCKO 1 - - ns
ADF_CCK[1:0] output and falling edge
Data setup time w.r.t. In LF_MASTER_SPI
TSUCCKOLF 13 - - ns
ADF_CCK[1:0] output mode: ADF_CCK[1:0]
configured in output,
THDCCKOLF 0 - - ns
ADF_CCK[1:0] output and falling edge
DS14359 Rev 2 255/320

284
Figure 55. ADF timing diagram

FCCKI, FCCKO, FCCKOLF,
TSUCCKI THDCCKI TSUCCKI THDCCKI
TSUCCKO THDCCKO TSUCCKO THDCCKO
TLCCKI, THCCKI,
TSUCCKOLF THDCCKOLF TSUCCKOLF THDCCKOLF
TLCCKO, TLCCKOLF THCCKO, TLCCKOLF
ADF_CCK (IO)
ADF_SDIx (I)
MSv55575V1
256/320 DS14359 Rev 2

6.3.28 Digital camera interface (DCMIPP) characteristics

Unless otherwise specified, the parameters given in Table xx for DCMIPP are derived from
tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 24 General operating conditions,, with the following configuration:
• DCMIPP_PIXCLK polarity: falling
• DCMIPP_VSYNC and DCMIPP_HSYNC polarity: high
• Data formats: 16 bits
• Capacitive load C=30pF
Table 115. DCMIPP characteristics(1)

DCMIPP_PIXCLK Pixel Clock input - 120 MHz
Dpixel Pixel Clock input duty cycle 30 70 %
tsu(DATA) Data input setup time 3 -
th(DATA) Data hold time 1 -
tsu(HSYNC), ns
DCMI_HSYNC/ DCMI_VSYNC input setup time 2.5 -
tsu(VSYNC)
th(HSYNC),
DCMI_HSYNC/ DCMI_VSYNC input hold time 1 -
th(VSYNC)
1. Evaluated By characterization – Not tested in production.
2. At VOS low, these values are degraded by up to 7%.
Figure 56. DCMIPP timing diagram
1/DCMIPP_PIXCLK
DCMIPP_PIXCLK
tsu(HSYNC) th(HSYNC)
DCMIPP_HSYNC
tsu(VSYNC) th(HSYNC)
DCMIPP_VSYNC
tsu(DATA) th(DATA)
DATA[15:0]
MSv73149V1
DS14359 Rev 2 257/320

284
6.3.29 Parallel synchronous slave interface (PSSI) characteristics

Unless otherwise specified, the parameters given in Table 116 and Table 117 for PSSI are
supply voltage summarized in Table 26: General operating conditions with the following
configuration:
• PSSI_PDCK polarity: falling
• PSSI_RDY and PSSI_DE polarity: low
• Bus width: 16 lines
• Data width: 32 bits
• Measurement points done at CMOS levels: 0.5*VDD
• I/O compensation cell activated
Table 116. PSSI transmit characteristics(1)

Symbol Parameter Conditions Min Max(2) Unit
- Frequency ratio PSSI_PDCK/fHCLK - - 0.4 -

PSSI_PDCK PSSI Clock input 1.71 V<VDD<3.6 V - 80(3) MHz
Dpixel PSSI Clock input duty cycle - 30 70 %
tov(DATA) Data output valid time - 12.5
toh(DATA) Data output hold time 5.5 -
tov((DE) DE output valid time - 12
1.71 V<VDD<3.6 V ns
toh(DE) DE output hold time 5.5 -
tsu(RDY) RDY input setup time 0 -
th(RDY) RDY input hold time 5.5 -
3. This maximum frequency does not consider receiver setup and hold timings.
258/320 DS14359 Rev 2

Table 117. PSSI receive characteristics(1)

- Frequency ratio PSSI_PDCK/fHCLK - - 0.4 -

PSSI_PDCK PSSI Clock input 1.71 V<VDD<3.6 V - 100 MHz
Dpixel PSSI Clock input duty cycle - 30 70 %
tsu(DATA) Data input setup time 1 -
th(DATA) Data input hold time 1.5 -
tsu((DE) DE input setup time 1 -
1.71 V<VDD<3.6 V ns
th(DE) DE input hold time 1.5 -
tov(RDY) RDY output valid time - 11.5
toh(RDY) RDY output hold time 5.5 -
Figure 57. PSSI receive timing diagram
tc(PDCK)
tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK)

PSSI_PDCK
CKPOL=0
(input)
CKPOL=1
ts(DATA)
th(DATA)
PSSI D[15:0]
Invalid data IN Valid data IN Invalid data IN
(input)
ts(DE)
th(DE)
DEPOL=0
PSSI_DE
(input)
DEPOL=1
tv(RDY) tho(RDY)
PSSI_RDY
RDYPOL=0
(output)
RDYPOL=1
MSv63436V1
DS14359 Rev 2 259/320

284
Figure 58. PSSI transmit timing diagram

tc(PDCK)
tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK)

PSSI_PDCK
CKPOL=0
(input)
CKPOL=1
tv(DATA) tho(DATA)
PSSI D[15:0]
Invalid data OUT Valid data OUT Invalid data OUT
(output)
tv(DE) tho(DE)
DEPOL=0
PSSI_DE
(output)
DEPOL=1
ts(RDY) th(RDY)
PSSI_RDY
RDYPOL=0
(input)
RDYPOL=1
MSv63437V1
260/320 DS14359 Rev 2

6.3.30 LCD-TFT controller (LTDC) characteristics

Unless otherwise specified, the parameters given in Table 118 for LCD-TFT are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 26: General operating conditions, with the following
configuration:
• LCD_CLK polarity: high
• LCD_DE polarity: low
• LCD_VSYNC and LCD_HSYNC polarity: high
• Pixel formats: 24 bits
• Capacitive load CL=30 pF
Table 118. LTDC characteristics(1)

LTDC clock
1.71<VDD<3.
fCLK output - 90 MHz
6 V, 30 pF
frequency
DCLK LTDC clock output duty cycle 45 55 %
tw(CLKH),
Clock High time, low time tw(CLK)//2-0.5 tw(CLK)/2+0.5
tw(CLKL)
tv(DATA) Data output valid time - 3.5
th(DATA) Data output hold time 0.5 -
tv(HSYNC), ns
HSYNC/VSYNC/DE output
tv(VSYNC), - 3.0
valid time
tv(DE)
th(HSYNC),
HSYNC/VSYNC/DE output
th(VSYNC), 0.5 -
hold time
th(DE)
DS14359 Rev 2 261/320

284
Figure 59. LCD-TFT horizontal timing diagram
tCLK
LCD_CLK
LCD_VSYNC
tv(HSYNC) tv(HSYNC)
LCD_HSYNC
tv(DE) th(DE)
LCD_DE
tv(DATA)
LCD_R[0:7]
LCD_G[0:7] Pixel Pixel Pixel
1 2 N
LCD_B[0:7]
th(DATA)
HSYNC Horizontal Active width Horizontal

width back porch back porch
One line
MS32749V1
Figure 60. LCD-TFT vertical timing diagram
tCLK
LCD_CLK
tv(VSYNC) tv(VSYNC)
LCD_VSYNC
LCD_R[0:7]
LCD_G[0:7] M lines data
LCD_B[0:7]
VSYNC Vertical Active width Vertical

width back porch back porch
One frame
MS32750V1
262/320 DS14359 Rev 2

6.3.31 Timer characteristics

The parameters given in Table 119 are guaranteed by design.
Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 119. TIMx characteristics(1)(2)

AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK = 1 - tTIMxCLK
300 MHz
tres(TIM) Timer resolution time
AHB/APBx
prescaler>4, fTIMxCLK = 1 - tTIMxCLK
150 MHz
Timer external clock
fEXT 0 fTIMxCLK/2 MHz
frequency on CH1 to CH4 f
TIMxCLK = 240 MHz
ResTIM Timer resolution - 16/32 bit
Maximum possible count 65536 ×
tMAX_COUNT - - tTIMxCLK
with 32-bit counter 65536
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
3. The maximum timer frequency on APB1 or APB2 is up to 300 MHz, by setting the TIMPRE bit in the
RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x
Frcc_pclkx1 or TIMxCLK = 4x Frcc_pclkx2.
6.3.32 Low-power timer characteristics

The parameters given in Table 120 are guaranteed by design.
Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 120. LPTIMx characteristics(1)(2)

tres(TIM) Timer resolution time 1 - tTIMxCLK
fLPTIMxCLK Timer kernel clock 0 150

Timer external clock frequency on Input1 and MHz
fEXT 0 fLPTIMxCLK/2
Input2
ResTIM Timer resolution - 16 bit
tMAX_COUNT Maximum possible count - 65536 tTIMxCLK
1. LPTIMx is used as a general term to refer to the LPTIM1 to LPTIM5 timers.

DS14359 Rev 2 263/320

284
6.3.33 Communication interfaces

I3C interface characteristics
The I3C interface meets the timings requirements of the MIPI® I3C specification v1.1.
The I3C peripheral supports:
• I3C SDR-only as controller
• I3C SDR-only as target
• I3C SCL bus clock frequency up to 12.5 MHz
The parameters given in Table 121 are obtained with the following configuration:
• I/O compensation cell activated
The timings are in line with the MIPI specification, except for those given in Table 121 and
Table 122. For tSU_OD and tSU_PP this can be mitigated by increasing the corresponding
SCL low duration in the I3C_TIMINGR0 register. For further details refer to AN5879.
Table 121. I3C open-drain measured timing(1)

I3C open drain mode
(specification) Timing
measurements
Min Max
SDA data setup time Controller

tSU_OD 3 - 16 ns
during open drain mode 1.71 V < VDD < 3.6 V
Table 122. I3C push-pull measured timing(1)

I3C open drain mode
(specification) Timing
measurements
Min Max
SDA signal data setup in Controller

tSU_PP 3 - 14.5 ns
push-pull mode 1.71 V < VDD < 3.6 V
I2C interface characteristics

The I2C interface meets the timings requirements of the I2C-bus specification and user
manual revision 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The parameters given in Table 123 are obtained with the following configuration:
264/320 DS14359 Rev 2


The I2C timing requirements are specified by design, and not tested in production, when the
I2C peripheral is properly configured (refer to the product reference manual):
The SDA and SCL I/O requirements are met with the following restrictions: The SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIOx is disabled, but is still present. Only FT_f I/O
pins support Fm+ low level output current maximum requirement. Refer to Section 6.3.15:
I/O port characteristics for the I2C I/O characteristics:
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog fil-
ter characteristics:
Table 123. I2C analog filter characteristics(1)(2)

Maximum pulse width of spikes that

tAF 50(4) 165(5) ns
are suppressed by analog filter
2. Measurement points are done at 50% VDD.
3. At VOS low, the performance can be degraded by up to 7% compared to VOS high.
4. Spikes with widths below tAF(min) are filtered.
5. Spikes with widths above tAF(max) are not filtered.
USART interface characteristics

Unless otherwise specified, the parameters given in Table 124 for USART are derived from
tests performed under the ambient temperature, fPCLK frequency and VDD supply voltage
configuration:
function characteristics (NSS, CK, TX, RX for USART).
DS14359 Rev 2 265/320

284
Table 124. USART characteristics(1)

Master mode,
15.5
1.71 V ≤ VDD ≤ 3.6 V
- -
Slave receiver mode,
41.5
1.71 V ≤ VDD ≤ 3.6 V
fCK USART clock frequency Slave transmitter MHz

mode, 40.0
1.71 V ≤ VDD ≤ 3.6 V
- -
Slave transmitter
mode, 41.5
2.7 V ≤ VDD ≤ 3.6 V
tsu(NSS) NSS setup time Slave mode tker+2 - -
th(NSS) NSS hold time Slave mode 0.5 - -
tw(CKH), 1/fCK/2-
CK high and low time Master mode 1/fCK/2 1/fCK/2+1
tw(CKL) 1
Master mode 11.5 - -
tsu(RX) Data input setup time
Slave mode 1.5 - -
Master mode 0 - -
th(RX) Data input hold time
Slave mode 0.5 - - ns
Slave mode, ,
- 8.0 10.5
2.7 V ≤ VDD ≤ 3.6 V
tv(TX) Data output valid time Slave mode, ,
- 8.0 12.5
1.71 V ≤ VDD ≤ 3.6 V
Master mode - 1 2
Slave mode 6 - -
th(TX) Data output hold time
Master mode 0.5 - -
266/320 DS14359 Rev 2

Figure 61. USART timing diagram in master mode

1/fCK
tw(CKH)
CPHA=0
CK output
CPOL=0
CPHA=0
CPOL=1
tw(CKL)
CPHA=1
CK output
CPOL=0
CPHA=1
CPOL=1
tsu(RX) th(RX)
RX input MSB IN BIT6 IN LSB IN
TX output MSB OUT BIT1 OUT LSB OUT
tv(TX) th(TX) MSv65386V6
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
Figure 62. USART timing diagram in slave mode
NSS input
1/fCK th(NSS)
tsu(NSS) tw(CKH)
CPHA=0
CPOL=0
CK input
CPHA=0
CPOL=1
tw(CKL) tv(TX) th(TX)
TX output First bit OUT Next bits OUT Last bit OUT
tsu(RX) th(RX)
RX input First bit IN Next bits IN Last bit IN
MSv65387V6
DS14359 Rev 2 267/320

284
SPI interface characteristics

Unless otherwise specified, the parameters given in Table 125 for SPI are derived from tests
performed under the ambient temperature, fPCLK frequency and VDD supply voltage
configuration:
function characteristics (SS, SCK, MOSI, MISO for SPI).
Table 125. SPI characteristics(1)

Master mode,
90
1.71 V < VDD < 3.6 V
Master mode,
2.7 V < VDD < 3.6 V, SPI2, 3, 4, 133
5, 6
Master mode,
130
2.7 V < VDD < 3.6 V, SPI1
fSCK SPI clock frequency - - MHz
2.7 V < VDD < 3.6 V, SPI2, 3, 4, 140
5, 6
130
1.71 V < VDD < 3.6 V, SPI1
Slave mode transmitter/full
45
duplex, 2.7 V < VDD < 3.6 V
Slave mode transmitter/full
38
duplex, 1.71 V < VDD < 3.6 V
tsu(NSS) NSS setup time Slave mode 2.5 - -
th(NSS) NSS hold time Slave mode 1 - -
ns
tw(SCKH),
SCK high and low time Master mode, prescaler = 2 tSCK-1 tSCK tSCK+1
tw(SCKL)
268/320 DS14359 Rev 2

Table 125. SPI characteristics(1) (continued)

tsu(MI) Master mode 1.5 - -

Data input setup time
tsu(SI) Slave mode 2 - -
th(MI) Master mode 1.5 - -
Data input hold time
th(SI) Slave mode 1.5 - -
ta(SO) Data output access time Slave mode 10 11.5 15.5
tdis(SO) Data output disable time Slave mode 7.5 8 12
Slave mode, ns
- 9 11
2.7 V < VDD < 3.6 V
tv(SO)
Slave mode,
Data output valid time - 9 13
1.71 V < VDD < 3.6 V
Master mode,
tv(MO) - 0.5 1
1.71 V < VDD < 3.6 V
th(SO) Slave mode 6.5 - -
Data output hold time
th(MO) Master mode 0 - -
Figure 63. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK) th(NSS)
tsu(NSS) tw(SCKH)
CPHA=0
SCK input
CPOL=0
CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41658V2
DS14359 Rev 2 269/320

284
Figure 64. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK) th(NSS)
tsu(NSS) tw(SCKH)
CPHA=1
SCK input
CPOL=0
CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41659V2
Figure 65. SPI timing diagram - master mode
High
NSS input
tc(SCK)
tw(SCKH)
CPHA=0
SCK output
CPOL=0
CPHA=0
CPOL=1
tw(SCKL)
CPHA=1
SCK output
CPOL=0
CPHA=1
CPOL=1
tsu(MI) th(MI)
MISO input First bit IN Next bits IN Last bit IN
MOSI output First bit OUT Next bits OUT Last bit OUT
tv(MO) th(MO) ai14136e
270/320 DS14359 Rev 2

I2S Interface characteristics

Unless otherwise specified, the parameters given in Table 126 for I2S are derived from tests
configuration:
function characteristics (CK,SD,WS).
Table 126. I2S dynamic characteristics(1)

- - 50
Master transmitter - 50
fMCK I2S main clock output Master receiver - 28 MHz
Slave transmitter - 23
Slave receiver - 50
tv(WS) WS valid time - 1.5
Master mode
th(WS) WS hold time 0.5 -
tsu(WS) WS setup time 3 -
Slave mode
th(WS) WS hold time 1 -
tsu(SD_MR) Master receiver 1.5 -
tsu(SD_SR) Slave receiver 1.5 -
th(SD_MR) Master receiver 2 -
th(SD_SR) Slave receiver 1 - ns
Slave transmitter (after enable

tv(SD_ST) - 13
edge)
Data output valid time
Master transmitter (after
tv(SD_MT) - 2
enable edge)
Slave transmitter (after enable
th(SD_ST) 7.5 -
edge)
Data output hold time
Master transmitter (after
th(SD_MT) 0.5 -
enable edge)
DS14359 Rev 2 271/320

284
Figure 66. I2S slave timing diagram (Philips protocol)(1)
ai14881c
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 67. I2S master timing diagram (Philips protocol)(1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
272/320 DS14359 Rev 2

SAI characteristics
Unless otherwise specified, the parameters given in Table 127 for SAI are derived from tests
configuration:
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output
alternate function characteristics (SCK,SD,WS).
Table 127. SAI characteristics(1)

Symbol Parameter Conditions Min Max (2) Unit
fMCK SAI Main clock output - - 50

Master transmitter - 34
Master receiver - 38 MHz
fCK SAI clock frequency(3)
Slave transmitter - 35
Slave receiver - 50
Master mode, 2.7 V ≤ VDD ≤ 3.6 V - 12
tv(FS) FS valid time
Master mode, 1.71 V ≤ VDD ≤ 3.6 V - 13
tsu(FS) FS setup time Slave mode 3 -
Master mode 7 -
th(FS) FS hold time
Slave mode 1 -
tsu(SD_A_MR) Master receiver 2.5 -
tsu(SD_B_SR) Slave receiver 1.5 - ns
th(SD_A_MR) Master receiver 2 -
th(SD_B_SR) Slave receiver 1 -
tv(SD_B_ST) Data output valid time Slave transmitter (after enable edge) - 14
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 7.5 -
tv(SD_A_MT) Data output valid time Master transmitter (after enable edge) - 14.5
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 7 -
3. APB clock frequency must be at least twice SAI clock frequency.
DS14359 Rev 2 273/320

284
Figure 68. SAI master timing waveforms

1/fSCK
SAI_SCK_X
(CKSTR = 0)
SAI_SCK_X
(CKSTR = 1)
th(FS)
SAI_FS_X
(output)
tv(FS) tv(SD_MT) th(SD_MT)
SAI_SD_X
(transmit) Slot n Slot n+2
tsu(SD_MR) th(SD_MR)
SAI_SD_X
(receive) Slot n
MS32771V2
Figure 69. SAI slave timing waveforms

1/fSCK
SAI_SCK_X
(CKSTR = 0)
SAI_SCK_X
(CKSTR = 1)
tw(CKH_X) tw(CKL_X) th(FS)
SAI_FS_X
(input)
tsu(FS) tv(SD_ST) th(SD_ST)
SAI_SD_X Slot n Slot n+2

(transmit)
tsu(SD_SR) th(SD_SR)
SAI_SD_X
Slot n
(receive)
MS32772V2
274/320 DS14359 Rev 2

MDIO characteristics
Unless otherwise specified, the parameters given in Table 128 for the MDIO are derived
from tests performed under the ambient temperature, fPCLK frequency and VDD supply
voltage conditions summarized in Table 26: General operating conditions, with the following
configuration:
• I/O Compensation cell activated.
Table 128. MDIO slave timing parameters(1)

Symbol Parameter Min Typ Max(2) Unit
FMDC Management Data Clock - - 30 MHz

td(MDIO) Management Data Iput/output output valid time 6 8.5 13
tsu(MDIO) Management Data Iput/output setup time 2.5 - - ns
th(MDIO) Management Data Iput/output hold time 0.5 - -
Figure 70. MDIO slave timing diagram

tMDC)
td(MDIO)
tsu(MDIO) th(MDIO)
MSv40460V1
DS14359 Rev 2 275/320

284
SD/SDIO MMC card host interface (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 129 and Table 130 for SDIO are
supply voltage summarized in Table 26: General operating conditions, with the following
configuration:
characteristics.
Table 129. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V(1)
Clock frequency in data transfer

fPP - 0 - 120(3) MHz
mode
tW(CKL) Clock low time 8.5 9.5 -
fPP =52MHz ns
tW(CKH) Clock high time 8.5 9.5 -
CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) mode
tISU Input setup time HS - 2.5 - -

tIH Input hold time HS - 1.5 - - ns
(4)
tIDW Input valid window (variable window) - 3.5 - -
CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(5)/DDR(5) mode
tOV Output valid time HS - - 6 6.5

ns
tOH Output hold time HS - 4 - -
CMD, D inputs (referenced to CK) in SD default mode
tISUD Input setup time SD - 2.5 -

ns
tIHD Input hold time SD - 1.5 -
CMD, D outputs (referenced to CK) in SD default mode
tOVD Output valid default time SD - - 1 1.5

ns
tOHD Output hold default time SD - 0 - -
3. With capacitive load CL = 20 pF.
4. For SD 1.8 V support, an external voltage converter is needed.
5. Minimum window of time where the data needs to be stable for proper sampling in tuning mode.
276/320 DS14359 Rev 2

Table 130. Dynamic characteristics: eMMC characteristics VDD = 1.71V to 1.9V(1)

Clock frequency in data transfer

fPP - - - 130(3) MHz
mode
tW(CKL) Clock low time 8.5 9.5 -
fPP =52 MHz ns
tW(CKH) Clock high time 8.5 9.5 -
CMD, D inputs (referenced to CK) in eMMC mode
tISU Input setup time HS - 2 - -

tIH Input hold time HS - 1.5 - -
ns
Input valid window (variable
tIDW(4) - 3 - -
window)
CMD, D outputs (referenced to CK) in eMMC mode
tOVD Output valid time HS - - 6 6.5

ns
tOHD Output hold time HS - 4 - -
3. CL = 20 pF.
4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
Figure 71. SD high-speed mode
Figure 72. SD default mode
CK
tOVD tOHD
D, CMD
(output)
ai14888
DS14359 Rev 2 277/320

284
Figure 73. SDMMC DDR mode
tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)
Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)
Data output IO0 IO1 IO2 IO3 IO4 IO5
tsf(IN) thf(IN) tsr(IN) thr(IN)
Data input IO0 IO1 IO2 IO3 IO4 IO5

MSv36879V3
USB OTG_FS characteristics
Table 131. USB OTG_FS electrical characteristics(1)

USB transceiver operating

VDD33USB - 3.0(1) - 3.6 V
voltage
Embedded USB_DP pull-up
RPUI - 900 1250 1600
value during idle
Embedded USB_DP pull-up
RPUR - 1400 2300 3200 Ω
value during reception
Driver high
ZDRV Output driver impedance(2) 28 36 44
and low
1. The USB functionality is ensured down to 2.7 V. However, not all USB electrical characteristics are
degraded in the 2.7 to 3.0 V voltage range.
2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.
278/320 DS14359 Rev 2

USB OTG_HS characteristics

The OTG_HS controller complies with the following specifications:
• USB On-The-Go supplement, revision 2.0
• Universal Serial Bus revision 2.0 specification
• Battery charging specification, revision 1.2
The parameters given in Table 132 and Table 133 are derived from tests performed under
conditions.
Table 132. USB OTG_HS DC electrical characteristics(1)

USB transceiver
VDDUSB - 3.12(2) - 3.6 V
operating voltage
fHCLK value to guarantee
fHCLK proper operation of the - 30(3) - - MHz
OTG_HS interface
Embedded USB_DP pull-
RPUI - 900 1250 1575
up value during idle
Embedded USB_DP pull-
RPUR - 1425(3) 2250 3090(3)
up value during reception
Ω
Embedded USB_DP and
RPD - 14250 - 24800
USB_DM pull-down value
Output driver
ZDRV Driving high or low 40.5(3) 45 49.5(3)
impedance(4)
tlr Rise time CL < 5 pF 0.5(3) - -
ns
tlf Fall time CL < 5 pF 0.5(3) - -
tlrfm Rise/fall time matching - 80(3) - 125(3) %
1. Evaluated by characterization. Not tested in production, unless otherwise specified.
2. The USB functionality is ensured down to 3 V but not the full USB electrical characteristics
which are degraded in 3.0 to 3.12 V voltage range.
3. Specified by design. Not tested in production.
4. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-). The
matching impedance is already included in the embedded driver.
DS14359 Rev 2 279/320

284
Table 133. OTG_HS current consumption characteristics(1)

Full Speed Transmit(2) - 5.65 6.02

USB (PLL and PHY)
(2)
IDD(OTG_HS) current consumption on High Speed Idle - 5.66 6 mA
VDDUSB (2)
High Speed Transmit - 14.6 14.92
Full Speed Transmit(2) - 6.00 10.59
USB (PLL and PHY)
IDD11(OTG_HS) (2)
current consumption on High Speed Idle - 5.93 10.51 mA
VDD11USB (2)
High Speed Transmit - 6.87 11.98
1. Evaluated by characterization. Not tested in production.
2. Suspend when operating in Device mode with no far-side host termination on DP/DM during
measurements.
UCPD characteristics
The UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0
specifications.
Table 134. UCPD electrical characteristics

UCPD operating supply

VDD - 3.0 3.3 3.6 V
voltage
280/320 DS14359 Rev 2

Ethernet interface characteristics

Unless otherwise specified, the parameters given in Table 135, Table 136 and Table 137 for
SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK
frequency and VDD supply voltage conditions summarized in Table 26: General operating
conditions, with the following configuration:
Due to timing constraint Pxy_C I/Os cannot be used as ethernet signals.
characteristics:
Table 135. Dynamic characteristics: Ethernet MAC signals for SMI(1)

tMDC MDC cycle time( 2.5 MHz) 400 400 400

Td(MDIO) Write data valid time 0 1 1.5
ns
tsu(MDIO) Read data setup time 12.5 - -
th(MDIO) Read data hold time 0 - -
Figure 74. Ethernet SMI timing diagram

tMDC
ETH_MDC
td(MDIO)
ETH_MDIO(O)
tsu(MDIO) th(MDIO)
ETH_MDIO(I)
MS31384V1
DS14359 Rev 2 281/320

284
Table 136. Dynamic characteristics: Ethernet MAC signals for RMII (1)
tsu(RXD) Receive data setup time 2.5 - -

tih(RXD) Receive data hold time 1 - -
tsu(CRS) Carrier sense setup time 1.5 - -
ns
tih(CRS) Carrier sense hold time 0.5 - -
td(TXEN) Transmit enable valid delay time 7 9.5 14
td(TXD) Transmit data valid delay time 7 10.5 14.5
Figure 75. Ethernet RMII timing diagram
RMII_REF_CLK
td(TXEN)
td(TXD)
RMII_TX_EN
RMII_TXD[1:0]
tsu(RXD) tih(RXD)
tsu(CRS) tih(CRS)
RMII_RXD[1:0]
RMII_CRS_DV
ai15667b
Table 137. Dynamic characteristics: Ethernet MAC signals for MII(1)

tsu(RXD) Receive data setup time 2.5 - -

tih(RXD) Receive data hold time 1 - -
tsu(DV) Data valid setup time 1 - -
tih(DV) Data valid hold time 0.5 - -
ns
tsu(ER) Error setup time 2 - -
tih(ER) Error hold time 0.5 - -
td(TXEN) Transmit enable valid delay time 6.5 9 13
td(TXD) Transmit data valid delay time 6.5 10 14.5
282/320 DS14359 Rev 2

Figure 76. Ethernet MII timing diagram
MII_RX_CLK
tsu(RXD) tih(RXD)
tsu(ER) tih(ER)
tsu(DV) tih(DV)
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
MII_TX_CLK
td(TXEN)
td(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668b
JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in Table 138 and Table 139 for
JTAG/SWD are derived from tests performed under the ambient temperature, fHCLK
frequency and VDD supply voltage summarized in Table 26: General operating conditions,
with the following configuration:
characteristics: (1)
Table 138. Dynamic JTAG characteristics
2.7 V ≤ VDD≤ 3.6 V - - 50

FTCK TCK clock frequency MHz
1.71 ≤ VDD ≤ 3.6 V - - 40
tisu(TMS) TMS input setup time - 3 - -
tih(TMS) TMS input hold time - 1 - -
tisu(TDI) TDI input setup time - 2 - -
tih(TDI) TDI input hold time - 1 - - ns
2.7 V <VDD< 3.6 V - 9 10
tov(TDO) TDO output valid time
1.71 <VDD< 3.6 V - 10 12.5
toh(TDO) TDO output hold time - 8 - -
DS14359 Rev 2 283/320

284
Table 139. Dynamics SWD characteristics(1)

2.7 V ≤ VDD ≤ 3.6 V - - 90

FSWCLK SWCLK clock frequency MHz
1.71 ≤ VDD ≤ 3.6 V - - 60
tisu(SWDIO) SWDIO input setup time - 1 - -
tih(SWDIO) SWDIO input hold time - 2.5 - -
2.7 V ≤ VDD ≤ 3.6 V - 9 11 ns
tov(SWDIO) SWDIO output valid time
1.71 ≤ VDD ≤ 3.6 V - 11 16.5
toh(SWDIO) SWDIO output hold time - 8 - -
Figure 77. JTAG timing diagram
tc(TCK)
TCK
tsu(TMS/TDI) th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS
tov(TDO) toh(TDO)
TDO
MSv40458V1
Figure 78. SWD timing diagram
tc(SWCLK)
SWCLK
tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH)

SWDIO
(receive)
tov(SWDIO) toh(SWDIO)
SWDIO
(transmit)
MSv40459V1
284/320 DS14359 Rev 2

STM32H7Sxx8 Package information
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at www.st.com. ECOPACK
is an ST trademark.
7.1 Device marking

Refer to technical note “Reference device marking schematics for STM32 microcontrollers
and microprocessors” (TN1433) available on www.st.com, for the location of pin 1 / ball A1
as well as the location and orientation of the marking areas versus pin 1 / ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are
not yet qualified and therefore not approved for use in production. ST is not responsible for
any consequences resulting from such use. In no event will ST be liable for the customer
using any of these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a qualification
activity.
A WLCSP simplified marking example is provided in the corresponding package information
subsection.
DS14359 Rev 2 285/320

316
Package information STM32H7Sxx8
7.2 VFQFPN68 package information (B029)

This VFQFPN is a 68 pins, 8 x 8 mm, 0.4 mm pitch, very thin fine pitch quad flat package
Figure 79. VFQFPN68 - Outline

PIN 1 IDENTIFIER
LASER MARKING ddd C
D
A
A1
68 67 A2
1
2
E E
(2X) 0.10 C
SEATING
C PLANE
TOP VIEW SIDE VIEW

L
D2
E2
2
1
PIN 1 ID
C 0.30 X 45'
68 67 b
e
EXPOSED PAD AREA
BOTTOM VIEW B029_VFQFPN68_ME_V1
1. VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Packages No lead. Sawed
version. Very thin profile: 0.80 < A ≤ 1.00mm.
2. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other
feature of package body. Exact shape and size of this feature is optional.
286/320 DS14359 Rev 2

Table 140. VFQFPN68 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A 0.80 0.90 1.00 0.0315 0.0354 0.0394

A1 0 0.02 0.05 0 0.0008 0.0020
A3 - 0.20 - - 0.0008 -
b 0.15 0.20 0.25 0.0059 0.0079 0.0098
D 7.85 8.00 8.15 0.3091 0.3150 0.3209
D2 6.30 6.40 6.50 0.2480 0.2520 0.2559
E 7.85 8.00 8.15 0.3091 0.3150 0.3209
E2 6.30 6.40 6.50 0.2480 0.2520 0.2559
e - 0.40 - - 0.0157 -
L 0.40 0.50 0.60 0.0157 0.0197 0.0236
ddd - - 0.08 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 80. VFQFPN68 - Recommended footprint

8.30
7.00
6.65
0.15 6.40
6.65
7.00
8.30
6.40
0.25
0.82
0.65
0.40
B029_VFQFPN68_FP_V2
DS14359 Rev 2 287/320

316
7.3 LQFP100 package information (1L)

This LQFP is 100 lead, 14 x 14 mm low-profile quad flat package.
Note: See list of notes in the notes section.
Figure 81. LQFP100 - Outline(15)
ș2 ș
(2)
R1
H
R2
B
B-
N
O
(6)
TI
C
SE
D1/4 B GAUGE PLANE
S
E1/4
B ș
4x N/4 TIPS
ș L
4x (L1)
aaa C A-B D
bbb H A-B D (1) (11)
BOTTOM VIEW SECTION A-A
(N-4) x e (13)
C
A (9) (11)
0.05
ccc C b WITH PLATING
A2 A1 b aaa C A-BD
(12)
SIDE VIEW
D (4)
(11) c
(2) (5) D1 c1 (11)
D (3)
(10) (4)
N
b1 BASE METAL
1 (11)
2
3 E1/4 SECTION B-B
D1/4 (6) (2)

A B
(5)
E1 E
SECTION A-A
A A
TOP VIEW 1L_LQFP100_ME_V3
288/320 DS14359 Rev 2

Table 141. LQFP100 - Mechanical data

Symbol
A - 1.50 1.60 - 0.0590 0.0630

(12)
A1 0.05 - 0.15 0.0019 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 16.00 BSC 0.6299 BSC
(2)(5)
D1 14.00 BSC 0.5512 BSC
E(4) 16.00 BSC 0.6299 BSC
E1(2)(5) 14.00 BSC 0.5512 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.177 0.0236 0.0295
(1)(11)
L1 1.00 - 0.0394 -
N(13) 100
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1) 0.20 0.0079
bbb(1) 0.20 0.0079
(1)
ccc 0.08 0.0031
(1)
ddd 0.08 0.0031
DS14359 Rev 2 289/320

316
Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
15. Drawing is not to scale.
Figure 82. LQFP100 - Recommended footprint

75 51
76 50
0.5
0.3
16.7 14.3
100 26
1.2
1 25
12.3
16.7
1L_LQFP100_FP_V1
1. Dimensions are expressed in millimeters.
290/320 DS14359 Rev 2

7.4 TFBGA100 package information (A08Q)

This TFBGA is 100 - ball, 8X8 mm, 0.8 mm pitch fine pitch ball grid array package.
Figure 83. TFBGA100 - Outline
ddd C
SEATING
PLANE
A1
A
A2
A1 ball
index
B
D1 A1 ball area
identifier
e D
F
A
B
C
G
D
E
E1
E
F
G
e
H A
J
K
10 9 8 7 6 5 4 3 2 1
BOTTOM VIEW TOP VIEW

b (100 BALLS)
eee C A B
fff C
A08Q_ME_V1
DS14359 Rev 2 291/320

316
Table 142. TFBGA100 - Mechanical data

Symbol
A(2) - - 1.100 - - 0.0433

(3)
A1 0.150 - - 0.0059 - -
A2 - 0.760 - - 0.0299 -
(4)
b 0.350 0.400 0.450 0.0138 0.0157 0.0177
D 7.850 8.000 8.150 0.3091 0.3150 0.3209
D1 - 7.200 - 0.2835 -
E 7.850 8.000 8.150 0.3091 0.3150 0.3209
E1 - 7.200 - - 0.2835 -
e - 0.800 - - 0.0315 -
F - 0.400 - - 0.0157 -
G - 0.400 - - 0.0157 -
ddd - - 0.100 - - 0.0039
(5)
eee - - 0.150 - - 0.0059
(6)
fff - - 0.080 - - 0.0031
2. The total profile height (Dim A) is measured from the seating plane to the top of the component
3. • The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized
markings, or other feature of package body or integral heat slug.
• A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optiona
4. Initial ball equal 0.350mm.
5. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true
position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone.
6. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each
tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball
must lie simultaneously in both tolerance zones.
292/320 DS14359 Rev 2

Figure 84. TFBGA100 - Recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 143. TFBGA100 - Recommended PCB design rules (0.8 mm pitch BGA)
Dimension Recommended values
Pitch 0.8
Dpad 0.400 mm
0.470 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.400 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.120 mm
DS14359 Rev 2 293/320

316
7.5 LQFP144 package information (1A)

This LQFP is a 144-pin, 20 x 20 mm low-profile quad flat package.
BOTTOM VIEW
2 1
(2)
R1
H
R2
B
B-
N
O
TI
C
SE
(6) B GAUGE PLANE
0.25
D 1/4
S
B
L
3
E 1/4 (L1)
(1) (11)
4x N/4 TIPS
aaa C A-B D SECTION A-A
bbb H A-B D 4x
(N-4)x e
C
A
0.05 (12) ddd C A-B D
A2 A1 b ccc C
D (4)
D1 (2) (5)
(10) (3) D (9) (11)
N (4)
b WITH PLATING
1
2
3 E 1/4
(11) (11)
c c1
(6)
D 1/4 (2)
(3) A B (3) (5)
E1 E b1 BASE METAL
(11)
SECTION B-B
A A
(Section A-A)
TOP VIEW
1A_LQFP144_ME_V2
294/320 DS14359 Rev 2


Symbol
A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 22.00 BSC 0.8661 BSC
(2)(5)
D1 20.00 BSC 0.7874 BSC
E(4) 22.00 BSC 0.8661 BSC
E1(2)(5) 20.00 BSC 0.7874 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 144
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa 0.20 0.0079
bbb 0.20 0.0079
ccc 0.08 0.0031
ddd 0.08 0.0031
DS14359 Rev 2 295/320

316
Notes:
as 0.15 mm.
from the lead tip.
body.
296/320 DS14359 Rev 2

108 73
1.35
109 0.35 72
0.50
19.90 17.85
22.60
144 37
1 36
19.90
22.60
1A_LQFP144_FP
DS14359 Rev 2 297/320

316
7.6 UFBGA144 package information (A02Y)

This UFBGA is a 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array
package.
Figure 87. UFBGA144 - Outline
C Seating plane
ddd Z
A4 A3 A2 A1 A
E1 A1 ball A1 ball A
identifier index area E
e F
A
F
D1 D
e
B
M
12 1
BOTTOM VIEW Øb (144 balls) TOP VIEW
Ø eee M C A B
Ø fff M C A02Y_ME_V2
Table 145. UFBGA144 - Mechanical data

Symbol
Min. Typ. Max. Min. Typ. Max.
A 0.460 0.530 0.600 0.0181 0.0209 0.0236

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 - 0.130 - - 0.0051 -
A4 - 0.320 - - 0.0126 -
b 0.360 0.400 0.440 0.0091 0.0110 0.0130
D 9.950 10.000 10.050 0.2736 0.2756 0.2776
D1 8.750 8.800 8.850 0.2343 0.2362 0.2382
E 9.950 10.000 10.050 0.2736 0.2756 0.2776
E1 8.750 8.800 8.850 0.2343 0.2362 0.2382
e 0.750 0.800 0.850 - 0.0197 -
298/320 DS14359 Rev 2

Table 145. UFBGA144 - Mechanical data (continued)

Symbol
F 0.550 0.600 0.650 0.0177 0.0197 0.0217

ddd - - 0.080 - - 0.0039
eee - - 0.150 - - 0.0059
fff - - 0.080 - - 0.0020
Figure 88. UFBGA144 - Recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 146. UFBGA144 - Recommended PCB design rules (0.80 mm pitch BGA)
Pitch 0.80 mm
Dpad 0.400 mm
Dsm
DS14359 Rev 2 299/320

316
7.7 UFBGA169 package information (A0YV)

This UFBGA is a 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.
Figure 89. UFBGA169 - Outline
Z Seating plane
A2 A4
ddd Z
A
A3 A1
b
SIDE VIEW A1 ball A1 ball
identifier index area X
E
E1
e F
A
F
D1 D
e
Y
N
13 1
BOTTOM VIEW Øb (169 balls) TOP VIEW

Ø eee M Z X Y
Ø fff M Z
A0YV_ME_V2
Table 147. UFBGA169 - Mechanical data

Symbol
A 0.460 0.530 0.600 0.0181 0.0209 0.0236

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 - 0.130 - - 0.0051 -
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.230 0.280 0.330 0.0091 0.0110 0.0130
D 6.950 7.000 7.050 0.2736 0.2756 0.2776
D1 5.950 6.000 6.050 0.2343 0.2362 0.2382
E 6.950 7.000 7.050 0.2736 0.2756 0.2776
E1 5.950 6.000 6.050 0.2343 0.2362 0.2382
e - 0.500 - - 0.0197 -
F 0.450 0.500 0.550 0.0177 0.0197 0.0217
300/320 DS14359 Rev 2

Table 147. UFBGA169 - Mechanical data (continued)

Symbol
ddd - - 0.100 - - 0.0039

eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
Figure 90. UFBGA169 - Recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 148. UFBGA169 - Recommended PCB design rules (0.5 mm pitch BGA)
Pitch 0.5 mm
Dpad 0.27 mm
Dsm
Solder paste 0.27 mm aperture diameter.
Note: Non-solder mask defined (NSMD) pads are recommended.

Note: 4 to 6 mils solder paste screen printing process.
DS14359 Rev 2 301/320

316
7.8 LQFP176 package information (1T)

This LQFP is a 176-pin, 24 x 24 mm, 0.5 mm pitch, low profile quad flat package.
ș2 ș1
(2) R1
H R2
B(See SECTION B-B)

(6) GAUGE PLANE
0.25
D1/4
S
B ș
L
E1/4 ș
4x N/4 TIPS 4x (L1)
(1) (11)
bbb H A-B D
aaa C A-B D
BOTTOM VIEW SECTION A-A
A2 0.05
(N-4) x e
C
A
A1 (12) ddd C A-BD ccc C
b
SIDE VIEW
D (4)
(2) (5) D1
D (9) (11)
(10) N
(4) b WITH PLATING
E1/4
(11) c c1 (11)
D1/4 (6) (5)

A B (2)
E1 E b1 BASE METAL
(11)
SECTION A-A
A A
SECTION B-B
TOP VIEW 1T_LQFP176_ME_V2
302/320 DS14359 Rev 2


Symbol
A - - 1.600 - - 0.0630
A1(12) 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
(9)(11)
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
(11)
b1 0.170 0.200 0.230 0.0067 0.0079 0.0091
c(11) 0.090 - 0.200 0.0035 - 0.0079
(11)
c1 0.090 - 0.160 0.0035 - 0.063
(4)
D 26.000 1.0236
(2)(5)
D1 24.000 0.9449
E(4) 26.000 0.0197
(2)(5)
E1 24.000 0.9449
e 0.500 0.1970
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1(1)(11) 1 0.0394 REF
N(13) 176
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.080 - - 0.0031 - -
R2 0.080 - 0.200 0.0031 - 0.0079
S 0.200 - - 0.0079 - -
(1)
aaa 0.200 0.0079
(1)
bbb 0.200 0.0079
(1)
ccc 0.080 0.0031
ddd(1) 0.080 0.0031
DS14359 Rev 2 303/320

316
Notes:
as 0.15 mm.
from the lead tip.
body.
304/320 DS14359 Rev 2

1.2
176 133
1 0.5 132
0.3
26.7
21.8
44 89
45 88
1.2
21.8
26.7
1T_FP_V1
Dimensions are expressed in millimeters.
DS14359 Rev 2 305/320

316
7.9 WLCSP101 package information (B0FA)

This WLCSP is a 101 ball, 3.86 x 3.79 mm, 0.35 mm pitch, wafer level chip scale package.
Figure 93. WLCSP101L - Outline

bbb Z
e1
A2 ball location A1
F
10 8 6 4 2
11 9 7 5 3 1
A
B
C
G D
E
F Detail A
G
H
J
K e2 E
e L
M
N
P
R
T
U
V
W
A2
e A
D
Bottom view Side view

bump side
A2
b
Front view
X
Bump
A3
eee Z
A1
E
Z
Notes 1 and 2 b(101x)
ccc M Z X Y
ddd M Z
Seating plane
Note 4
Note 3
aaa
Detail A
(4X)
rotated 90°
Y
D
Top view
wafer back side
B0FA_WLCSP101L_ME_V1
306/320 DS14359 Rev 2

Table 150. WLCSP101 - Mechanical data

Symbol
A(2) - - 0.58 - - 0.0228
A1 - 0.17 - 0.0065 -
A2 - 0.38 - - 0.0150 -
A3(3) - 0.025 - - 0.0010 -
Øb(4) 0.21 0.24 0.27 0.0083 0.0094 0.0106
D 3.84 3.86 3.88 0.1512 0.1519 0.1527
E 3.77 3.79 3.81 0.1482 0.1490 0.1498
e - 0.35 - - 0.0138 -
e1 - 3.03 - - 0.1193 -
e2 - 3.15 - - 0.1240 -
F(5) - 0.414 - - 0.0163 -
G(5) - 0.320 - - 0.0125 -
N(6) 101
Tolerance of form and position
aaa - - 0.10 - - 0.004
bbb - - 0.10 - - 0.004
ccc(7) - - 0.10 - - 0.004
ddd(8) - - 0.05 - - 0.002
eee - - 0.05 - - 0.002

2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal and tolerances
values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process capability.
4. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
5. Calculated dimensions are rounded to the third decimal place.
6. N is the total number of terminals.
7. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of the pattern of
balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc perpendicular to datum Z and
located on true position with respect to datums X and Y as defined by e. The axis perpendicular to datum Z of each ball
must lie within this tolerance zone.
8. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball
there is a cylindrical tolerance zone ddd perpendicular to datum Z and located on true position as defined by e. The axis
perpendicular to datum Z of each ball must lie within this tolerance zone. Each tolerance zone ddd in the array is contained
entirely in the respective zone ccc above. The axis of each ball must lie simultaneously in both tolerance zones.
DS14359 Rev 2 307/320

316
Figure 94. WLCSP101 - recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 151. WLCSP101 - recommended PCB design rules

Pitch 0.35 mm
Dpad 0.210 mm
Dsm 0.275 mm typ. (depends on the soldermask registration tolerance)
Stencil thickness 0.100 mm
308/320 DS14359 Rev 2

7.9.1 Device marking for WLCSP101

The following figure gives an example of topside marking orientation versus A2 ball identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.
Figure 95. WLCSP101 marking example (package top view)
Pin A2 identifier
Product identification
Date code Revision code
MSv55558V2
DS14359 Rev 2 309/320

316
7.10 UFBGA(176+25) package information (A0E7)

This UFBGA is a 176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array
package
Figure 96. UFBGA(176+25) - Outline

Seating plane
C A4
ddd C
A
A2 A3 b A1
A1 ball A
A1 ball index E
identifier area
E1
e F
A
F
D1 D
e
B
R
15 1
Øb (176 + 25 balls)
BOTTOM VIEW TOP VIEW
Ø eee M C A B
Ø fff M C
A0E7_ME_V10
Table 152. UFBGA(176+25) - Mechanical data

Symbol
A - - 0.600 - - 0.0236
A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 - 0.450 - - 0.0177 -
A3 - 0.130 - - 0.0051 -
A4 - 0.320 - - 0.0126 -
b 0.240 0.290 0.340 0.0094 0.0114 0.0134
D 9.850 10.000 10.150 0.3878 0.3937 0.3996
D1 - 9.100 - - 0.3583 -
E 9.850 10.000 10.150 0.3878 0.3937 0.3996
E1 - 9.100 - - 0.3583 -
e - 0.650 - - 0.0256 -
F - 0.450 - - 0.0177 -
ddd - - 0.080 - - 0.0031
310/320 DS14359 Rev 2

Table 152. UFBGA(176+25) - Mechanical data (continued)

Symbol
eee - - 0.150 - - 0.0059

fff - - 0.050 - - 0.0020
Figure 97. UFBGA(176+25) - Recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 153. UFBGA(176+25) - Recommended PCB design rules (0.65 mm pitch BGA)
Pitch 0.65 mm
Dpad 0.300 mm
Dsm
DS14359 Rev 2 311/320

316
7.11 TFBGA225 package information (B04V)

This TFBGA is a 225-ball, 13 x 13 mm, 0.8 mm pitch, thin profile fine pitch ball grid array
package.
Figure 98. TFBGA225 - Outline(13)

E1
e SE
R
P
N e
M
L
K
J
H D1
G
SD F
E
D
C
B
A
1 3 5 7 9 11 13 15
A1 BALL 2 4 6 8 10 12 14
PAD CORNER 5 b (N BALLS)
eee C A B
fff C
BOTTOM VIEW
ddd C ccc C
A
SEATING
7 PLANE C
A1 A2
SIDE VIEW
B E A
8 A1 BALL
PAD CORNER D/4
E/4
(DATUM A)
(DATUM B)
aaa C
TOP VIEW (4X)
B04V_TFBGA225_ME_V2
312/320 DS14359 Rev 2

Table 154. TFBGA225 - Mechanical data

millimeters(1) inches(12)
Symbol
A(2)(3) - - 1.20 - - 0.0472

(4)
A1 0.15 - - 0.0059 - -
A2 - 0.76 - - 0.0299 -
(5)
b 0.35 0.40 0.45 0.0138 0.0157 0.0177
(6)
D 13.00 BSC 0.5118 BSC
D1 11.20 BSC 0.4409 BSC
E 13.00 BSC 0.5118 BSC
E1 11.20 BSC 0.4409 BSC
(9)
e 0.80 BSC 0.0315 BSC
N(11) 225
SD(12) 0.80 BSC 0.0315 BSC
SE(12) 0.80 BSC 0.0315 BSC
aaa 0.15 0.0059
ccc 0.20 0.0079
ddd 0.10 0.0039
eee 0.15 0.0059
fff 0.08 0.0031
Notes:
1. For dimensions in millimeters, dimensioning and tolerancing schemes conform to
ASME Y14.5M-2018.
2. TFBGA stands for Thin profile Fine pitch Ball Grid Array: 1.00mm < A ≤ 1.20mm / Fine
pitch e < 1.00mm.
3. The profile height, A, is the distance from the seating plane to the highest point on the
package. It is measured perpendicular to the seating plane.
body.
5. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane
parallel to primary datum C.
6. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no
tolerance. For tolerances refer to form and position table.
7. Primary datum C is defined by the plane established by the contact points of three or
more solder balls that support the device when it is placed on top of a planar surface.
8. The terminal (ball) A1 corner must be identified on the top surface of the package by
using a corner chamfer, ink or metallized markings, or other feature of package body or
DS14359 Rev 2 313/320

316
integral heat slug. A distinguish feature is allowable on the bottom surface of the
package to identify the terminal A1 corner. Exact shape of each corner is optional.
9. e represents the solder ball grid pitch.
10. N represents the total number of balls on the BGA.
11. Basic dimensions SD & SE are defined with respect to datums A and B. It defines the
position of the centre ball(s) in the outer row or column of a fully populated matrix.
Figure 99. TFBGA225 - Recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 155. TFBGA225 - Recommended PCB design rules (0.8 mm pitch BGA)
Pitch 0.8 mm
Dpad 0.400 mm
Dsm 0.550 mm
Stencil thickness 0.125 to 0.100 mm
314/320 DS14359 Rev 2

7.12 Package thermal characteristics

The maximum chip-junction temperature, TJmax in degrees Celsius, can be calculated using
the following equation:
TJmax = TAmax + (PDmax × ΘJA)
Where:
• TAmax is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax),
• PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/Omax represents the maximum power dissipation on output pins:
PI/Omax = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 156. Package thermal characteristics

Symbol Definition Parameter Value Unit
Thermal resistance junction-ambient VFQFPN68 -

23.8
8 x 8 mm / 0.35 mm pitch
Thermal resistance junction-ambient LQFP100 -
34.9
36.4
35.9
Thermal resistance junction-ambient WLCSP101 -
43.2
Thermal resistance 3.86 x 3.79 mm / 0.35 mm pitch
ΘJA °C/W
junction-ambient Thermal resistance junction-ambient TFBGA100 -
35.0
Thermal resistance junction-ambient UFBGA144 -
35.0
37.1
35.7
10 x 10 mm / 0.65 mm pitch
Thermal resistance junction-ambient TFBGA225 -
32.8
DS14359 Rev 2 315/320

316
Table 156. Package thermal characteristics (continued)

Symbol Definition Parameter Value Unit
Thermal resistance junction-ambient VQFN68 -

9.0
20.8
25.3
25.9
21.1
Thermal resistance 3.86 mm / 0.35 mm pitch
ΘJB °C/W
22.0
22.9
22.8
23.6
10 x 10 mm / 0.65 mm pitch
22.3
Thermal resistance junction-ambient VQFN68 -
10.7
7.7
7.9
9.2
1.8
Thermal resistance 3.86 mm / 0.35 mm pitch
ΘJC °C/W
12.6
9.0
9.4
9.0
10 x 10 mm / 0.65 mm pitch
12.0
316/320 DS14359 Rev 2

STM32H7Sxx8 Ordering information
8 Ordering information
Example: STM32 H 7S3 Z 8 J 6 H
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
H = High performance
Device subfamily
7S3 = STM32H7S3x8
7S7 = STM32H7S7x8
Pin count
R = 68 pins
V = 100 or 101 pins/balls
Z = 144 pins
A = 169 balls
I = 176 pins/balls
L = 225 balls
Flash memory size

8 = 64 Kbytes
Package
J = UFBGA pitch 0.8 ECOPACK2
Y = WLCSP pitch 0.35 ECOPACK2
V = VFQFPN pitch 0.4 ECOPACK2
T = LQFP ECOPACK2
K = UFBGA pitch 0.65 mm ECOPACK2
I = UFBGA pitch 0.5 mm ECOPACK2
H = TFBGA ECOPACK2
Temperature range
6 = –40 to 85 °C
Hexadeca SPI support

No character = Octo/Quad SPI support
H = Hexadeca SPI support
For a list of available options (speed, package, and so on) or for further information on any
aspect of this device, contact your nearest ST sales office.
DS14359 Rev 2 317/320

317
Important security notice STM32H7Sxx8
9 Important security notice
The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.
318/320 DS14359 Rev 2

STM32H7Sxx8 Revision history
10 Revision history
Table 157. Document revision history

Date Revision Changes
02-Nov-2023 1 Initial release.

Corrected maximum CPU frequency in Table 3: STM32H7Sxx8 features and
13-Mar-2024 2 peripheral counts.
Added Section 6: Electrical characteristics.
DS14359 Rev 2 319/320

319
STM32H7Sxx8
IMPORTANT NOTICE – READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product
or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2024 STMicroelectronics – All rights reserved
320/320 DS14359 Rev 2

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STM32H7S3x8 STM32H7S7x8

• 32-bit Arm® Cortex®-M7 CPU with MPU and

from embedded flash memory and external

March 2024 DS14359 Rev 2 1/320

• Hardware secure storage (dedicated secure Mathematical acceleration

Up to 152 I/O ports with interrupt

2/320 DS14359 Rev 2

DS14359 Rev 2 3/320

3.19 Quad/Octo/Hexa-SPI memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4/320 DS14359 Rev 2

3.41 Universal synchronous/asynchronous receiver transmitter (USART/UART)

4 Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 76

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

DS14359 Rev 2 5/320

6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

6/320 DS14359 Rev 2

6.3.32 Low-power timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

9 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

DS14359 Rev 2 7/320

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

8/320 DS14359 Rev 2

DS14359 Rev 2 9/320

10/320 DS14359 Rev 2

Table 145. UFBGA144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

DS14359 Rev 2 11/320

Figure 1. STM32H7Sxx8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

12/320 DS14359 Rev 2

DS14359 Rev 2 13/320

This document provides information on STM32H7Sxx8 microcontrollers, such as

14/320 DS14359 Rev 2

DS14359 Rev 2 15/320

• Advanced peripherals including:

Table 2. Security and graphics IP availability per product line

16/320 DS14359 Rev 2

DS14359 Rev 2 17/320

Figure 1. STM32H7Sxx8 block diagram

I-TCM D-TCM D-TCM To

SRAM1 SRAM2 To To To To AHB1

64-bit AXI BUS-MATRIX

GFXMMU MCE1 XSPI1 HSPI i/f

MCE3 FMC NE[4:1], NBL[3:0], NL,

CLK, HSYNC, VSYNC, DE, D[31:0], A[25:0], TE, (AF)

CK[4:1], SCK_[A:B], SD_A, SD_B (AF)

CH1, CH1N, BKIN (AF) TIM16 AHB/APB TIM12

From SPDIFRX1 IN[1:4] (AF)

GPIO I~K AHB3

GPIO P RCC CRYPT UART5 RX, TX, CTS, RTS (AF)

VBAT UART7 RX, TX, CTS, RTS (AF)

OSC32_IN XTAL 32 kHz

TS, OUT[2:1], REFIN RTC MDIOS MDC, MDIO (AF)

TAMP_IN[8:1], FDCAN1 TX, RX (AF)

CC1, DB1, CC2, DB2

18/320 DS14359 Rev 2

Flash memory (Kbytes) 64

SRAM on AXI 456

ITCM RAM (instruction) 64

TCM RAM in Kbytes

Backup SRAM (Kbytes) 4

Display Interface (bit) FMC16 FMC8 FMC16