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    Expt 4 - Design of Multiplexer and Demultiplexer

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    Kathirvelu Dhandapani

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    Expt 4 - Design of Multiplexer and Demultiplexer

    Uploaded by

    Kathirvelu Dhandapani
    3 views3 pages

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    Expt 4- Design of Multiplexer and Demultiplexer

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    3 views3 pages

    Expt 4 - Design of Multiplexer and Demultiplexer

    Uploaded by

    Kathirvelu Dhandapani

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    © All Rights Reserved
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    of 3

    Experiment 4: Design of Multiplexer and Demultiplexer

    Aim:
    To design and implement multiplexer and demultiplexer using logic gates.

    Equipment/Components required:
    Sl.No. Component Specification Qty.
    1. AND gate IC 7408 2
    2. OR gate IC 7432 1
    3. NOT gate IC 7404 1
    4. IC trainer kit - 1
    5. Patch cords - As required

    Theory:
    Multiplexer:
    A multiplexer (MUX) is a combinational circuit that selects binary information from one of
    many input lines and directs it to a single output line. The selection of a particular input line is
    controlled by a set of selection lines. Normally, there are 2n input lines and n selection lines
    whose bit combinations determine which input is selected.

    Demultiplexer:
    A demultiplexer (DEMUX) basically reverses the multiplexing function. It takes digital
    information from one line and distributes it to a given number of output lines. For this reason,
    the demultiplexer is also known as a data distributor.

    Procedure:
    1. Make the connections as per the logic diagram.
    2. The last pin in the IC is connected to Vcc 5V, and pin 7 to ground.
    3. Apply different combinations of input using switches.
    4. Connect output pins to the LED on the training kit.
    5. Switch on the power supply and toggle the input states.
    6. Record the output based on LED's state and verify the truth table.
    Block diagram for 4:1 multiplexer:

    Circuit diagram for multiplexer:

    Truth table for Multiplexer:


    S1 S0 Y = OUTPUT
    0 0 D0
    0 1 D1
    1 0 D2
    1 1 D3
    Block diagram for 1:4 demultiplexer:

    Logic diagram for demultiplexer:

    Truth table for demultiplexer:


    INPUT OUTPUT
    S1 S0 I/P D0 D1 D2 D3
    0 0 0 0 0 0 0
    0 0 1 1 0 0 0
    0 1 0 0 0 0 0
    0 1 1 0 1 0 0
    1 0 0 0 0 0 0
    1 0 1 0 0 1 0
    1 1 0 0 0 0 0
    1 1 1 0 0 0 1

    Result:
    Thus, the multiplexer and demultiplexer were designed using logic gates and were verified
    using truth tables.

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