Stress Tests for Dynamic Burn-in of Full Scan Circuits

Vinay P. Dabholkar Sreejit Chakravarty Department of Computer Science State University of New York at Buffalo fvpd,[email protected]

Abstract Dynamic burn-in is an important process that is used to improve the reliability of circuits. In this paper, we investigate the problem of computing cyclic sequences which can be used during burnin of full scan circuits. We show that the problems are computationally difcult. In addition, we demonstrate experimentally that good heuristics can be developed to compute stress test for dynamic burn-in of full scan circuits.

1 Introduction
Growing size and complexity of VLSI circuits is making production of reliable chips a challenging task. Environmental stress testing is an effective method for improving product reliability [1]. Products often have hidden defects which cause eld failures. Of particular concern are failures that occur soon after the end user starts using it ( infant mortality ). Stress testing is a process in which stress stimuli are applied to products to expose such latent defects. Stress tests can be applied in a variety of ways such as burn-in, power cycling, temperature cycling, voltage variations, clock variations etc [1]. Burn-in is the process of testing a product for an extended period at an elevated temperature. It is one of the most common form of stress testing [2, 1]. There are three different types of burn-ins : Static, Dynamic and Monitored. Selection of a particular technique depends upon the types of defects targeted and the extent to which these defects are activated by various techniques [3]. Dynamic burn-in and monitored burn-in are widely used [4, 5]. One of a number of scenarios where burn-in is used is depicted in Figure 1. This gure, taken from [5], depicts MCM production ow. Highlighted blocks show the places where burn-in and testing are performed. It can be seen that burnin is performed at two places, once on the bare die and then on the assembled module. In addition to MCMs, burn-in used to separate infant mortalities in many other applications [1]. The objective of this research is to compute good stress tests that are to be used during burn-in. We assume that during burn-in stress conditions are induced by raising temperature and applying good set 1

of vectors that generate high switching activity in the targeted part of the circuit. We had proposed the use of cyclic sequences [6] which makes it possible to apply them repetitively for an extended period. The idea is to maximize switching activity during application of these cyclic sequences. The issue that we are interested is how to compute such a sequence. A systematic study of the problem of computing cyclic sequences in Full Scan circuits to maximize average switching activity is presented in [6]. In addition to presenting a taxonomy of burn-in problems, it is shown in [6] that most cyclic stress test problems pertinent to monitored burn-in can be solved efciently. Optimal algorithm and faster heuristics along with experimental results were presented in [6] for computing stress tests for monitored burn-in. Monitored burn-in has several drawbacks. (i) It requires a tester throughout the burn-in process. The cost of tying down a tester for a long period could be prohibitively large. (ii) In monitored burn-in the output of test application has to be latched back to scan registers. This could limit the speed and effectiveness of burn-in. (iii) Since selection of vectors is not restricted to test vectors in dynamic burn-in, higher level of activity can be can be generated. In this paper, we focus on computing good cyclic stress tests for dynamic burn-in. First, we show that these problems are computationally difcult. However, we demonstrate experimentally that good heuristics can be developed to compute stress tests for dynamic burn-in of full scan circuits. This is done by classifying the nodes of the circuits and developing different heuristics for each class of nodes. We show that these heuristics are faster and work considerably better than the optimal algorithm used for monitored burn-in [6]. The paper is organized as follows. Section 2 gives the background and notation used in the paper. In section 3, measure of goodness used to compare the cyclic sequences is discussed along with the problem denition. Heuristics for computing stress tests are presented in section 4 and experimental results are discussed in section 5. Intractability of dynamic burn-in problems is discussed in Appendix.

2 Background
2.1 Power Dissipation Model
We briey describe the power dissipation model used in the paper. For more details please refer to [6]. Let Pd be the power required to charge and discharge the output capacitive load of every gate. approximated as

Pd is
(1)

2 Pd = 1=2 ci vdd ni

where ci = output capacitance of gate i; ni = number of transitions ( 1 gate i per unit time.

! 0 or 0 ! 1) at the output of

ti+1 .

Equation (1) implies that power is dissipated at a node when the input vector is changed from ti to Let PC (ti ; ti+1 ) be the total power dissipated in a circuit C when inputs change from ti to ti+1 .

Then,

PC (ti ; ti+1 ) =

X
j 2SetofNodes

1 2

2 = cj vdd nj

(2)

Thus power dissipated at a node is proportional to the number of transitions per unit time (nj ) at that node. This depends on the gate delays and sequence of input vectors applied. The former is approximated by delay models. We use zero delay model under which all gates are assumed to have zero delay.

2.2 Power Dissipation in Full Scan Circuits

Block diagram of Full Integrated Scan is shown in Figure 2 [7]. C is the combinational part of the circuit and R is the test register where the tests are scanned serially. In dynamic burn-in the output from the combinational circuit is not latched back to the scan chain. Note that with every shift of a vector in the scan chain the inputs to the combinational circuit C change. Equations that take into account the power dissipation during monitored burn-in have been derived in [6]. They can be easily modied for dynamic burn-in. For the sake of completeness we briey describe the equations in Appendix A. We divide the circuit nodes into different categories whose characteristics is exploited while constructing cyclic sequences that maximize switching activity at their output. Consider a node that has only primary inputs in its fanin. The output of this node does not depend on the state variables. We call such a node c-node. Nodes which have only scan latches in their fanin are called s-nodes and nodes having both, primary inputs and scan latches in their fanin are called h-nodes(meaning hybrid nodes).

3 Problem Denition
Determining measure of goodness of a cycle is an important issue. In [6], average number of nodes switched per clock of the cyclic sequence was used as the measure. It has the following drawback. A cyclic sequence may be generating high switching activity in only a few of the targeted nodes but a number of nodes either might not be switching or the switching might be low for a number of nodes. This will lead to a high average switching for the cyclic sequence but we contend that this is not a good sequence to stress the circuit.

fn1; n2; n3; n4g. Let C1 and C2 be two cyclic sequences each of length 10. Let C1 generate following switching: fn1 =
To illustrate this, consider a hypothetical example consisting of four nodes, viz. 3

; n2 = 5; n3 = 1; n4 = 1g and let C2 generate fn1 = 4; n2 = 4; n3 = 4; n4 = 4g. Average switching of C1 per clock is 1.7 while that of C2 is 1.6. According to the measure used in [6], C1 is better than C2. However, it can be seen that in C1 50% of the nodes have very low activity (10%) and in C2 100%
10

of the nodes have moderate activity (40%). This motivates the following question: When can we say that a cyclic sequence generates reasonable average activity in a node ? In other words, a threshold for good average activity needs to be determined such that nodes with average activity below this threshold could be said to have poor switching. In practise, this threshold would depend upon the reliability requirement. Note that there might be inherent limitations as to how much average activity can be generated in a node. For example, for some nodes 15% activity could be the best that can be achieved with any cycle. However, we show that it is intractable to compute optimal average switching activity at a node. cyclic sequence C . This divides the targeted nodes into three categories; (1) nodes with average activity than t2 . We denote the three sets as m1 (C ), m2 (C ) and m3 (C ) respectively. We say that cyclic sequence In this paper, we propose a two threshold approach. We associate two thresholds t1 and t2 with every

less than t1 ; (2) nodes with average activity between t1 and t2 and; (3) nodes with average activity more

C1 is better than C2 if either m1(C1) < m1 (C2) or if m1 (C1) = m2(C2) and m2 (C1) < m2 (C2):
activity more than t2 and possibly all the nodes have switching activity more than t1 .

We would like to compute a cyclic sequence such that maximum number of nodes have switching

4 Computing Dynamic Stress Tests

We show that for all the three types of nodes i.e. c-nodes, s-nodes and h-nodes, the problem of computing a best cyclic sequence is NP-hard. The proofs of these propositions are given in Appendix B. Notwithstanding these difculties in computing cyclic tests for dynamic burn-in it is interesting to investigate if fast heuristics that stress the circuit more than in monitored burn-in can be developed. Next we discuss the heuristics and experimental results for generating dynamic stress tests.

4.1 c-nodes
Heuristic-1 describes the algorithm used for generating stress tests for a given set of c-nodes. The heuristic consists of two phases. In phase 1 (steps (1), (2) and (3)), we compute a pair for every targeted node such that the pair switches the node and at the same time switches maximum number of other nodes. This is done as follows. array. BitVector[v ][n] (n 2 SetOfCNodes) stores the value at the output of node n when v is applied. Set 4 Phase 1: In step (1), each test vector v is simulated and output of the simulation is stored in a BitVector[v ]

of nodes switched by pair p is obtained by computing the hamming distance between BitVector[vi ] and computing hamming distance is faster than performing logic simulation of a vector. Let the number of nodes pair

BitVector[vj ]. Note that this preprocessing step helps speed up the switching activity computation since

p switches. Let pair[n] denote a pair which switches node n and for which w(pair n]) is maximum for given n. Step (2) computes pair[n] for each node n 2 SetOfCNodes. In step (3) a subset of pairs from pair[i]s is selected which switch all the nodes under consideration. Let P denote the selected set of pairs and let V be the set of vectors in P .
Phase 2: Phase 2 constructs a cycle from the selected set of pairs. We start with an initial pair and add

w(p) denote

one vector at a time. As the cycle is updated average switching activity of each node is updated which is stored in the form of an array. Step (4) describes the while loop (steps 4.5-4.18) that constructs the cycle of vectors. During every iteration of the loop a vector is selected using the following set of rules. Let c be the last vector of the partial cycle constructed so far. For each vector v

which the pair (c; v ) switches (step 4.8). These nodes are classied into 10 Bins (Bin[1]-[10]). Bin[1] stores the number of nodes that pair (c; v ) switches and having average switching activity between 0 and 0.1 Bin[2] stores the number of nodes with activity between 0.1 and 0.2 and so on. (step 4.8) Each Bin has a weight associated with it (BinWeight[i]). Weights to bins are assigned such that BinWeight[i] is less than BinWeight[i+1] (1

2 V compute the set of nodes

9).

The idea is to select a vector which switches more nodes with

poorer switching activity. For every vector, weight is computed as shown in step 4.10 and a vector with maximum weight is selected as the next vector of the cycle. The process is continued until either no improvement is found or cycle is longer than a threshold length. Heuristic-1 (SetOfCNodes) (1) for (each vector v endfor (2) for (all pairs p = (vi ; vj ) such that vi ; vj SetOfNodesSwitched update pair [n] HammingDistance (BitVector, v1 ,v2 ) BitVector[v ]

2 Test set T )

Simulate (v )

2 T)

for (each node n 2 SetOfNodesSwitched) endfor endfor (3) (4.1)

P greedy selection of pairs that switch all the nodes V fvi 2 Pg (vi; vj ) pair with maximum weight in P
5

(4.2) Cycle

fvi; vj g

(4.3) CurrentVector

(4.4) UpdateNodeTransitions (vi; vj ) (4.5) while (Cycle is not too long) (4.6) (4.7) (4.8) (4.9) (4.10) (4.11) (4.12) (4.13) (4.14) (4.15) (4.16) (4.17) endfor UpdateNodeTransitions (CurrentVector, BestVector) CurrentVector BestVector endif MaxWeight Bins 0 Simulate (CurrentVector, v ) for (each vector v

vj

2 V)
10 X
i=1

/* Evaluate the vector v */ weight if (weight > MaxWeight) MaxWeight BestVector

BinWeight i] Bin i]

weight

(4.18)endwhile

4.2 s-nodes
Heuristic-2 describes the algorithm that generates stress tests for s-nodes. Note that in case of s-nodes primary inputs can be ignored. Therefore assignments to only the sequential inputs are discussed. In the initialization step (step (1)), scan chain is assigned the sequence 010101..etc. The idea is to have switching at every input per shift in the beginning. At every step, one shift bit is selected using a klookahead in which all possible combinations of k-shifts (a total of 2k ) are simulated and the rst bit of the vector with maximum average activity is added to the cycle (steps (2.1)-2.7)). For example, in case of 2-lookahead, f00, 01, 10, 11g are simulated. Weighted sum for each shiftvector is computed similar to the one is Heuristic-1 (step (2.4)). In the example, if 01 generates maximum weighted average activity then 0 will be shifted in (step (3)). While the partial cycle is being constructed, a few good folding points are maintained. For example, if 01010111001101 is the partial cycle constructed so far and if average activity spectrum was good at positions 1, 3 and 7 then f1; 3; 7g is added to the FoldingPoint list. Once the cycle is sufciently long, cycle is folded at all the folding points and the one with best average activity is chosen. For example, assume the sequence 010101 was in the scan chain in the beginning and the remaining part 11001101 was shifted in. Then corresponding to the three good folding points the three

cycles 0101011, 010101110 and 0101011100110 will be simulated and best one will be chosen. Heuristic-2 (SetOfSNodes, k) /* k is lookahead */ (1) (2) (2.2) (2.3) (2.4) (2.5) (2.6) (2.7) (2.8) (2.9) (3) (4) (5) (5) (5.1) (5.2) endfor /* Let b be the rst bit of BestShiftVector */ ShiftAndSimulate (b) UpdateGoodFoldingPoints () endwhile for (each good folding point p) CompleteCycle (p) retain the best cycle endif Initialize scan chain to the sequence 010101...etc. /* k-lookahead */ for (v = 1 to 2k ) Bins weight

(2.1) while (chain is not too long) ShiftAndSimulate (v )

10 X
i=1

BinWeight i] Bin i]

if (weight > MaxWeight) MaxWeight weight BestShiftVector

(5.3) endfor

4.3 h-nodes
As mentioned earlier h-nodes depend on both the primary inputs as well as the sequential inputs. In this heuristic we combine the approaches in Heuristic-1 and Heuristic-2 for the selection of primary input vectors and scan chain cycle respectively. In every phase of this heuristic (1) a shift bit and, (2) a primary input vector are selected. This is done by modifying Step (2.3) of Heuristic-2 as follows. In step (2.3) of Heuristic-2 ShiftAndSimulate function simulates vector v by shifting in each bit of v and at the same time updating the average activity generated at the targeted nodes. In case of h-nodes, at every shift of vector v a primary input vector is to be selected. We select this vector by simulating all the test vectors and choosing the best vector.

5 Experimental Results
Heuristics described in the last section were implemented and evaluated on ISCAS89 benchmark circuits [8]. A machine having 4 Sparc-II processors was used as the platform. Code is implemented in C++. Table 1 shows c-node, s-node and h-node distribution of each circuit.

5.1 c-nodes
In general c-nodes constitute the smallest fraction among the three categories. But it can be seen from Table 1 that there could be circuits which have substantial fraction of c-nodes. For example, circuits like s510, s820, s1488 and s1494 have 82%, 63%, 44%, 44% c-nodes respectively. This justies the separate treatment for c-nodes. For each circuit (except s5378) one cyclic test was computed per group of 50 nodes. For every group nodes are classied into three categories. Nodes with average activity (1) less than 30% (column 30); (2) between 30% and 60% (column 30-60) and; (3) more than 60% (column 60). Average cycle length (averaged over all groups) is given in fth column. Time is given in seconds. Threshold for checking whether a cycle is too long was xed to be 40. It can be seen that there were 8 circuits for which a pair of vectors was found that switches all the c-nodes. This is the best cycle that can be found in c-nodes. If minimum of 30% switching activity is considered in the acceptable range then almost always 90% of the c-nodes can be activated satisfactorily. Also note that the heuristic is in general fast.

5.2 s-nodes and h-nodes

Heuristic-2 was run with 2-lookahead and 4-lookahead. Results are are shown in Table 3 and Table 4. For a number of circuits like s382, s444, s641, s713, s1488, s1494 4-lookahead heuristic gives better cycles. In fact, in case of s1488 and s1494 4-lookahead heuristic does substantially better than that of 2-lookahead heuristic. However, in case of s298, s349, s526n, s526 2-lookahead results are better. Also note that run time for 4-lookahead heuristic is about 4 to 5 times more than that for 2-lookahead. For s-nodes, cycles generated for monitored burn-in can also be used for dynamic burn-in. We compare the solutions given by optimal algorithm for generation cyclic stress tests for monitored burn-in described in [6] with k-lookahead heuristics. Results obtained by the Monitored burn-in heuristic are shown in Table 5. It can be seen that in general lookahead heuristics give much better cycles than that computed for monitored burn-in. However, note that for circuits like s641 cycle obtained for monitored burn-in is better than that obtained by lookahead heuristics. Another important point to note is the running time for monitored burn-in heuristic. It takes time order of magnitude more than that of lookahead 8

heuristics. In fact for circuit s5378 cycles were obtained for only 3 out of 24 groups of s-nodes and that took 5640 minutes. On the other hand, reasonable solution is obtained for all the sets of nodes using both 2-lookahead as well as 4-lookahead heuristic. Any of the approaches can be easily combined by taking for each set of nodes the best cycle among the three heuristics. One such table obtained by combining monitored burn-in and 2-lookahead heuristics is shown in Table 5. Results obtained for h-node heuristic are presented in Table 7. By observing the second column of Table 7 it can be noted that h-nodes are more difcult to activate than that of c-nodes and s-nodes. Moreover, simulating h-nodes takes more time resulting in longer run times.

6 Conclusions
In this paper, we studied the problem of computing cyclic sequences for dynamic burn-in of full-scan circuits. Nodes are classied into three types viz. c-nodes, s-nodes and h-nodes; and it was showed that the problem of computing a best stress test is intractable for each class of nodes. Furthermore fast heuristics are presented to compute good cyclic sequences. Heuristic-1 presented for c-nodes switches almost 90% of the nodes in every circuit. The k-lookahead heuristics compute good cyclic sequences for s-nodes. But in case of h-nodes, about 20-25% nodes in each circuit are not activated reasonably by the sequences computed by the heuristics. Future work will be directed towards computing better cycles for h-nodes.

References
[1] H. A. Chan, P. J. Englert, M. A. Oien, and S. Rajaram, Environmental stress testing, AT&T Technical Journal, pp. 7785, April 1994. [2] F. Jensen and N. Petersen, Burn-in: An Engineering Approach to the Design and Analysis of Burn-in Procedures. John Wiley & Sons, 1982. [3] E. Hnatek, Thoughts on VLSI burn-in, in IEEE International Test Conference, pp. 531535, 1984. [4] M. Campbell, Monitored burn-in (a case study for in-situ testing and reliability studies), in IEEE International Test Conference, pp. 518523, 1984. [5] Y. Zorian, Tutorial: MCM testing strategies, in International Test Conference, 1995. [6] V. Dabholkar, S. Chakravarty, F. Najm, and J. Patel, Cyclic stress tests for full scan circuits, IEEE VLSI Test Syposium, 1995. 9

[7] M. Abramovici, M. Breuer, and A. Friedman, Digital Systems Testing and Testable Design. Computer Science Press, 1990. [8] F. Brglez, D. Byan, and K. Kozminsky, Combinational proles of sequential benchmark circuits, in ACM/IEEE Intl Symposium on Circuits and Systems, pp. 19291934, 1989. [9] M. R. Garey and D. Johnson, Computers and Intractability: A Guide to the Theory of NPcompleteness. San Fransisco: W. H. Freeman, 1979.

10

Appendix A: Power dissipation in c-nodes, s-nodes, and h-nodes

Power dissipated in c-nodes, s-nodes and h-nodes can be given by the following equations. (1) Power dissipated in c-nodes: Let x be a c-node with output load capacitance cx in scan circuit Q if vi ! vj causes output of gate x to switch otherwise

and assume primary inputs change from vi to vj . Let Px (vi ; vj ) denote power dissipated at x

Px (vi; vj ) =

cx
0

Note that only to vectors are needed two switch one c-node. But if a set of c-nodes is targeted for stressing then, in general, a cyclic sequence may be needed. For example, consider a set of three c-nodes

fn1; n2; n3g. Assume a cyclic pair p1 = (v1; v2) which switches only n1, another cyclic pair p2 = (v2; v3) which switches only n2 and a third cyclic pair p3 = (v3 ; v1) which switches only n3 . Now each cyclic sequence p1 ; p2 or p3 has 100% switching for 33% of the nodes and has 0% switching for the remaining 67% of the nodes. On the other hand, the cyclic sequence (v1; v2; v3) has 33% switching for
100% of the nodes which is more desirable because each node is being switched at some level. (2) Power dissipated at h-nodes: binational part Consider a cycle v of length m. Let v (k) denote the input to com-

of Q at kth cycle during scan-in of v . Then, power dissipated during the shifting of

complete cycle is:

Px (v) =

m X k=1

Px (v(k); v(k + 1))

(3) Power dissipated at s-nodes: For s-nodes primary inputs can be ignored. As mentioned above, let

v(k) denote the input to C (without primary input part), then m X Px (v) = Px (v(k); v(k + 1))
k=1

Appendix B: Intractability of Dynamic Burn-in Problems

Solutions to the monitored burn-in problems can be used as stress tests during dynamic burn-in. However, it is possible to obtain better stress tests for dynamic burn-in when choice of vectors is not restricted to the given test set. To illustrate this, consider a c-node in a full-scan circuit. Two stuck-at test vectors, one of which sets the node to 0 and the other that sets the node to 1 would sufce to generate maximum activity at the node. However, a c-node may not have a stuck-at test vector for two reasons. (1) The node may not be sensitizable [7] or; (2) it may be not be possible to propagate the fault to a primary output. In case (1) no activity can be generated at the node. However, in case (2) a pair of vectors 11

may exist that causes the output of the gate to switch but a pair of stuck-at test vectors may not exist. This motivates the study of generating activity at the output of such c-nodes. However, we show that the problems of computing cyclic stress tests are NP-hard for c-nodes, s-nodes and h-nodes. All these problems can be shown to be as hard as satisability problem. For the sake of completeness, we give the formulation of satisability problem [9]. Given a product of sum formula F consisting of m clauses and a set of n literals U . Let each clause

Cli have ki literals such that each literal is of the form x or x where x 2 U . F can be represented as F = Vm Cli, i=1 Wk i such that xi 2 U _xi Cl = 2U x
i j =1 j
i

SAT : Given a boolean formula

such that F is satised. Stress Tests for c-nodes

F of the above form, nd an assignment A 2 f1; 0gn to literals x1; : : :; xn

We study the time complexity of generating stress tests for dynamic burn-in

for a given c-node in a full-scan circuit.

Dc?node: Given a full scan circuit Q and a c-node x, compute a pair of vectors (v1; v2) such that Px(v1; v2)
is maximized. Proposition: Problem Dc?node is NP-Hard. Proof: Given an instance of SAT, an instance of Dc?node can be constructed as follows. Given a CNF

formula F , a boolean circuit C is constructed as shown in Figure 3. has the literals in the corresponding clause as the inputs.

each clause Cli in F and one AND-gate corresponding to the conjunction of the clauses. Each OR-gate Consider the output node f of C . We show that the problem of nding a pair of vectors (v1 ; v2) such

C contains m OR-gates - one for

signment for F . This is same as showing that if a solution to the instance of Dc?node is obtained, solution

that Pf (v1 ; v2) (i.e. activity at the c-node f ) is maximized is at least as hard as nding a satisfying as-

Pf (v1; v2) is 1 then either v1 or v2 should set f to 1 which means F is satisable. On the other hand, if Pf (v1; v2) is 0 then there are only two possibilities: either F evaluates to true for all vectors v 2 f0; 1gn (in which case F is a tautology) or F evaluates to false for all vectors v 2 f0; 1gn. In either case, choose any vector, say v = 0n . If F (v ) is true then F is satisable. If it is false then it is not satisable. This concludes the proof. 2
Note that in case of multiple c-node case the problem is at least as hard as the single c-node case.

to the instance of SAT can be obtained in polynomial time. Consider a solution (v1 ; v2) of Dc?node . If

12

Stress Tests for s-node

0 through n ? 1 and let v

i] denote the ith element of v. A non-negative integer p, p < n is a period of v if v i] = v i + p], for i 2 0; n ? p). In terms of scan-in/scan-out, a vector with period p, after p cyclic shifts results in the same vector in the scan register. By denition, an n element vector has period n. For example, vector 010010 has periods 3 and 6. Next, let Px (v i) denote number of transitions at node x during the ith cyclic shift of v . Ds?node: Given a full-scan circuit Q, and an s-node x, nd a vector v with a period p such that average number of switching at x, given by the following term, is maximized. p 1X Px(v) = p Px (vi )
Next we show that Ds?node is NP-Hard. We show this by showing a special case of Ds?node is NPComplete. Consider the following decision problem which is a special case of this problem.

Consider a vector v of length n. Number the n elements from left to right by

i=1

Dsspecial?case: Consider a full-scan circuit Q and an s-node x. Does there exist a vector v such that one ?node shift of v with appropriate shift-in (0 or 1) switches x ? Note that this problem is indeed a special case of Ds?node . If average activity of the optimal solution special? is non-zero then there must exist one vector whose shift switches x. Hence answer to Ds?node case is afspecial? rmative. Similarly, if the average activity of the optimal solution is zero then the answer to Ds?node case special? is no. Next, we show Ds?node case is NP-Complete. special? Lemma: Ds?node case is NP-Complete. Proof: It can be seen that given a vector v it can be veried in polynomial time whether v is a soluspecial? special? tion to Ds?node case and hence the problem belongs to NP . We reduce SAT to Ds?node case and show Dsspecial?case is at least as hard as SAT. Given an instance of SAT, we construct an instance of Dsspecial?case ?node ?node
similar to the one shown in Figure 3 with a few differences. Each input is associated with a scan latch and all scan latches are connected to form a scan chain. The order of the scan latches is not important. Note that f is an s-node under this construction.
special? Let the solution to the instance of Ds?node case be afrmative. In that case, there exists at least one

special? with one shift should satisfy F . Now consider the other case where solution to Ds?node case is negative.

vector v such that shifting in either 0 or 1 switches the s-node f . Then F is satisable since either v or v

Note that any vector

v can be obtained from any other other vector v 0 by shifting it at most n times.

Hence there cannot be any disjoint partitions among the vectors such that vectors in one partition after shifting produce vectors in the same partition. This leaves only two possibilities similar to the proof of
special? case it can be easily found out whether F is satisable. Thus Ds?node case is at least as hard as SAT.

proposition in section 6.1. viz. (i) F is tautology and (ii) Complement of F is tautology. And in either

From the Lemma follows the result: 13

Proposition: case.

Ds?node is NP-Hard.

Intractability of h-node case is obvious since c-node and s-node cases are special cases of h-node

14

circuit s208.1 s298 s349 s382 s386 s420.1 s444 s510 s526 s526n s641 s713 s820 s832 s838.1 s1423 s1488 s1494 s5378 s9234 s9234.1 s13207 s15850

c-nodes 20 7 18 15 41 46 4 173 7 7 34 34 183 181 98 23 291 288 79 108 414 215 95

s-nodes 8 78 60 94 5 14 113 1 119 120 47 47 4 4 26 170 18 14 2465 4805 2741 7367 9395

h-nodes 76 34 83 49 113 158 64 37 67 67 298 312 102 102 322 464 344 345 235 684 2442 369 282

Table 1: c-nodes, s-nodes, h-nodes in ISCAS89 circuits

15

circuit s208.1 s298 s349 s382 s386 s420.1 s444 s510 s526n s526 s641 s713 s820 s832 s838.1 s1423 s1488 s1494 s5378 s9234 s9234.1 s13207 s15850

30 0.00 0.00 0.00 0.00 0.00 0.00 0.00 16.00 0.00 0.00 0.00 0.00 10.00 10.50 0.00 0.00 5.33 6.00 0.00 4.67 0.00 2.00 0.00

30-60 0.00 0.00 11.11 20.00 68.29 0.00 0.00 61.30 0.00 0.00 0.00 0.00 69.21 60.90 0.00 0.00 65.13 63.54 3.73 0.00 0.89 32.00 2.00

60 100.00 100.00 88.89 80.00 31.71 100.00 100.00 22.70 100.00 100.00 100.00 100.00 20.79 28.60 100.00 100.00 29.54 30.46 96.28 95.33 99.11 66.00 98.00

avg cycle length 2 2 40 40 40 2 2 40 2 2 40 40 40 40 2 2 40 40 40 15 15 40 21

time sec 0.1 0.1 0.4 0.6 2.5 0.3 0.1 7.7 0.2 0.2 1.8 1.6 21.0 22.5 0.8 0.5 39.5 43.3 47.9 54.9 180.5 345.4 79.2

Table 2: c-nodes: Heuristic-1

16

circuit s208.1 s298 s349 s382 s386 s420.1 s444 s510 s526n s526 s641 s713 s820 s832 s838.1 s1423 s1488 s1494 s5378

30 0.00 25.71 29.00 26.77 0.00 0.00 27.59 0.00 27.33 28.18 17.02 17.02 0.00 0.00 0.00 20.25 33.33 14.29 39.86

30-60 0.00 14.71 11.00 19.18 0.00 0.00 26.72 0.00 16.33 16.77 10.64 10.64 0.00 0.00 0.00 5.50 16.67 14.29 0.24

60 100.00 59.57 60.00 54.05 100.00 100.00 45.69 100.00 56.33 55.05 72.34 72.34 100.00 100.00 100.00 74.25 50.00 71.43 59.90

avg cycle length 12 22 24 34 10 20 52 7 29 29 20 20 9 9 36 80 10 20 188

time sec 0.6 2.2 3.0 4.5 1.0 2.2 10.2 1.0 7.2 7.2 3.7 5.5 1.4 1.1 8.1 77.6 2.8 2.8 3886.8

Table 3: s-nodes: Heuristic-2 with 2-lookahead

circuit s208.1 s298 s349 s382 s386 s420.1 s444 s510 s526 s526n s641 s713 s820 s832 s838.1 s1423 s1488 s1494 s5378 30 0.00 31.07 29.00 12.96 0.00 0.00 25.69 0.00 33.02 32.67 14.89 14.89 0.00 0.00 0.00 20.25 0.00 0.00 39.86 30-60 0.00 14.71 16.00 39.41 0.00 0.00 28.72 0.00 12.77 11.67 4.26 4.26 0.00 0.00 0.00 5.50 50.00 50.00 0.24 60 100.00 54.22 55.00 47.63 100.00 100.00 45.59 100.00 54.21 55.67 80.85 80.85 100.00 100.00 100.00 74.25 50.00 50.00 59.90 avg cycle length 12 28 26 89 10 20 33 7 31 31 56 56 9 9 36 80 20 20 188 time sec 2.7 11.3 17.2 26.6 3.9 12.2 45.4 3.9 43.4 42.9 20.0 22.0 6.7 5.0 45.8 407.6 15.0 14.4 22567.7

Table 4: s-nodes: Heuristic-2 with 4-lookahead 17

circuit s27 s208.1 s298 s344 s349 s382 s386 s420.1 s444 s510 s526 s526n s641 s713 s820 s832 s838.1 s1423 s1488 s1494 s5378*

30 0.00 0.00 32.64 27.11 48.00 26.05 40.00 0.00 28.15 0.00 30.77 29.67 6.38 17.02 0.00 0.00 0.00 19.50 22.22 0.00 30.00

30-60 100.00 100.00 56.22 33.11 52.00 71.68 60.00 100.00 54.05 100.00 68.56 67.67 82.98 82.98 100.00 25.00 100.00 78.50 66.67 92.86 68.75

60 0.00 0.00 11.14 39.78 0.00 2.27 0.00 0.00 17.79 0.00 0.67 2.67 10.64 0.00 0.00 75.00 0.00 2.00 11.11 7.14 1.25

avg cycle length 6 34 5 7 13 18 80 76 11 65 7 5 40 54 14 24 152 19 130 142 205

time sec 0.1 4.7 44.0 25.7 41.1 103.9 40.0 90.6 169.4 66.2 673.2 612.0 84.2 60.6 254.3 297.2 1321.4 5170.9 644.0 738.7 338798.5

*partial results, average of 4 sets of nodes

Table 5: s-nodes: Monitored burn-in results

18

circuit s208.1 s298 s349 s382 s386 s420.1 s444 s510 s526n s526 s641 s713 s820 s832 s838.1 s1423 s1488 s1494 s5378

30 0.00 23.71 29.00 23.77 0.00 0.00 22.92 0.00 24.00 25.51 6.38 17.02 0.00 0.00 0.00 15.75 22.22 0.00 10.33

30-60 0.00 43.72 11.00 59.18 0.00 0.00 48.05 0.00 43.67 30.11 82.98 10.64 0.00 0.00 0.00 66.00 66.67 92.86 58.67

60 100.00 32.57 60.00 17.05 100.00 100.00 29.03 100.00 32.33 44.39 10.64 72.34 100.00 100.00 100.00 18.25 11.11 7.14 31.00

avg cycle length 12 20 24 24 10 20 55 7 40 45 40 20 9 9 36 49 130 142 162

time sec 5.3 46.2 44.2 108.4 41.0 92.8 179.6 67.3 619.1 680.4 87.8 66.0 255.7 298.2 1329.5 5248.5 646.8 741.4 4625.5

Table 6: s-nodes: Combining monitored burn-in and Heuristic-2

circuit s208.1 s298 s349 s382 s386 s420.1 s444 s510 s526n s526 s641 s713 s820 s832 s838.1 s1423 s1488 s1494 s5378 30 26.62 20.59 12.00 34.69 18.67 32.00 29.14 21.62 24.82 20.82 14.48 12.33 16.67 16.67 37.87 26.17 25.34 24.63 24.11 30-60 38.54 29.41 8.03 24.49 17.33 0.50 28.57 27.03 37.47 40.53 18.06 13.14 18.67 14.00 1.71 25.29 20.96 22.92 10.00 60 34.84 50.00 79.97 40.82 64.00 67.50 42.28 51.35 37.70 38.64 79.96 74.52 64.67 69.33 60.42 48.54 53.70 52.44 65.89 avg cycle length 15 21 26 27 9 20 31 11 28 54 42 25 12 14 38 107 15 13 269 time sec 37.3 41.1 74.1 47.6 154.9 596.4 109.5 50.4 349.5 350.3 871.7 1021.2 390.1 372.6 6205.2 16377.7 1888.6 2070.5 -

Table 7: h-nodes: 2-lookahead heuristic 19

WAFER DESIGN

MOUNT IN CARRIER

SUBSTRATE

Substrate
DESIGN

Die

BURN IN

FULL TEST

CARRIER REMOVE

MCM ASSEMBLY

REWORK

MODULE TEST AND DIAGNOSIS

Module

BURN IN

POST BURN IN TEST

ENCAPSULATION

CAP REMOVAL

FINAL MODULE TEST

Figure 1: MCM Production Flow

C
PI Y SCAN-IN y PO

SCAN-OUT

Figure 2: Scan Structures

20

X1 1 X1 k1

o o o

o o o

ooo

Xm 1 m X km

Figure 3: Instance of Dc?node

21