Objective 1: VHDL Code for 2 input XOR Gate using Behavioral Modeling Scheme.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity XOR_2 is Port ( a : in std_logic; b : in std_logic; c : out std_logic); end XOR_2; architecture Behavioral of XOR_2 is begin process(a,b) begin if a=b then c<='0'; else c<='1'; end if; end process; end Behavioral;

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Simulation Result :

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Objective 2: Code for 2 input OR Gate using Data Flow Modeling Scheme.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity OR_2 is Port ( a : in std_logic; b : in std_logic; c : out std_logic); end OR_2; architecture Dataflow of OR_2 is begin c<=a or b; end Dataflow;

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Simulation Result:

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Objective 3: Code for Half Adder using Structural Modeling Scheme.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity halfadder is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic); end halfadder; architecture Structural of halfadder is component AND_2 port(a,b:in std_logic; c:out std_logic); end component; component XOR_2 port(a,b:in std_logic; c:out std_logic); end component; begin x1: XOR_2 port map(a,b,sum); x2: AND_2 port map(a,b,carry); end Structural;

Amrinder Singh 100806013

Simulation Result:

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Objective 4: Code for Full Adder using Mixed Modeling Scheme.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity full_adder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC); end full_adder; architecture Mixed_Modeling of full_adder is signal s1: std_logiccomponent XOR_2 port(a,b: in std_logic; c: out std_logic); end component; begin X1: XOR_2 port map(a,b,s1); sum<= s1 xor cin; process(a,b,cin) variable b1,b2,b3: std_logic; begin b1:= a and b; b2:= b and cin; b3:= cin and a; if (b1='0' and b2='0') and b3='0' then carry<='0'; else carry<='1'; end if; end process; end Mixed_Modeling;

Amrinder Singh 100806013

Simulation Result:

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Objective 5: Code for 4 bit Parallel Adder using Structural Modeling Scheme

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity adder_4bit_parallel is Port ( a : in STD_LOGIC_VECTOR(3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0); s : out STD_LOGIC_VECTOR(3 downto 0); cout : out STD_LOGIC); end adder_4bit_parallel; architecture Structural of adder_4bit_parallel is signal temp: std_logic:='0'; signal c: std_logic_vector(2 downto 0); component fulladder_using_halfadder port(a,b,cin: in std_logic; sum,carry: out std_logic); end component; begin FA1: fulladder_using_halfadder port map(a(0),b(0),temp,s(0),c(0)); FA2: fulladder_using_halfadder port map(a(1),b(1),c(0),s(1),c(1)); FA3: fulladder_using_halfadder port map(a(2),b(2),c(1),s(2),c(2)); FA4: fulladder_using_halfadder port map(a(3),b(3),c(2),s(3),cout); end Structural;

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Objective 6: Code for D-Flip Flop

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity D_flipflop is Port ( D : in STD_LOGIC; clk : in STD_LOGIC; rst : in STD_LOGIC; Q : out STD_LOGIC; Qbar : out STD_LOGIC); end D_flipflop; architecture D_flip of D_flipflop is begin process(D,clk,rst) begin if rst='1' then Q<='0'; Qbar<='1'; elsif clk'event and clk='1' then Q<=D; Qbar<=not D ; end if; end process; end D_flip;

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Objective 7: VHDL Code for 4:1 Multiplexer.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity MUX_4to1 is Port ( a : in STD_LOGIC_VECTOR (7 downto 0); b : in STD_LOGIC_VECTOR (7 downto 0); c : in STD_LOGIC_VECTOR (7 downto 0); d : in STD_LOGIC_VECTOR (7 downto 0); sel: in STD_LOGIC_VECTOR (1 downto 0); e : out STD_LOGIC_VECTOR (7 downto 0)); end MUX_4to1; architecture Mux of MUX_4to1 is begin process(a,b,c,d,sel) begin if sel="00" then e<=a; elsif sel ="01" then e<=b; elsif sel ="10" then e<=c; else e<=d; end if; end process; end Mux;

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Objective 8: VHDL code for 3:8 line Decoder using When/Else statement.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity DECODER_3to8 is Port ( sel : in STD_LOGIC_VECTOR(2 downto 0); X: out STD_LOGIC_VECTOR(7 downto 0)); end DECODER_3to8; architecture Decode of DECODER_3to8 is begin X <= "00000001" when Sel="000" else "00000010" when Sel="001" else "00000100" when Sel="010" else "00001000" when Sel="011" else "00010000" when Sel="100" else "00100000" when Sel="101" else "01000000" when Sel="110" else "10000000" ; end Decode;

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Objective 9: VHDL code for JK- Flip Flop.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity jkflipflop is Port ( j : in STD_LOGIC; k : in STD_LOGIC; rst : in STD_LOGIC; clk_en : in STD_LOGIC; clk : in STD_LOGIC; Y : out STD_LOGIC); end jkflipflop; architecture jk_flip of jkflipflop is signal temp: std_logic; begin process (clk) begin if (clk'event and clk='1') then if rst='1' then temp <= '0'; elsif clk_en ='1' then if (j='0' and k='0') then temp <= temp; elsif (j='0' and k='1') then temp <= '0'; elsif (j='1' and k='0') then temp <= '1'; elsif (j='1' and k='1') then temp <= not (temp); end if; end if; end if; end process; Y <= temp; end jk_flip;

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Objective 10: VHDL code for Parity Detector using Generic Scheme.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity parity_detr_genric is generic(n:integer:=7); Port ( input : in STD_LOGIC_vector(n downto 0); output : out STD_LOGIC); end parity_detr_genric; architecture parity of parity_detr_genric is begin process(input) variable temp:std_logic; begin temp:='0'; for i in input'range loop temp:= temp xor input(i); end loop; output<=temp; end process; end parity;

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Objective 11: VHDL code for 8-bit Arithmetic and Logical Unit (ALU) Design.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_signed.all; entity ALU is Port ( a : in STD_LOGIC_vector(7 downto 0); b : in STD_LOGIC_vector(7 downto 0); cin : in STD_LOGIC; sel : in STD_LOGIC_vector(3 downto 0); y : out STD_LOGIC_vector(7 downto 0)); end ALU; architecture Behavioral of ALU is signal arith,logic: std_logic_vector(7 downto 0); begin with sel(2 downto 0) select arith<= a when "000", a+1 when "001", a-1 when "010", b when "011", b+1 when "100", b-1 when "101", a+b when "110", a+b+cin when others; with sel(2 downto 0) select logic<= not a when "000", not b when "001", a and b when "010", a or b when "011", a nand b when "100", a nor b when "101", a xor b when "110", a xnor b when others; with sel(3) select y<= arith when '0', logic when '1'; end Behavioral; 21 Amrinder Singh 100806013

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Objective 12: VHDL code for Operator overloading

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; entity operator1 is port ( a: in STD_LOGIC ; b:in STD_LOGIC; c:out STD_LOGIC); function "+"(a:integer,b:bit)return integer is begin if b='1' return a+1; else return a; end if; end "+"; end operator1; architecture OL of operator1 is begin process(a,b,c) begin c<=a+b; end process; end OL;

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