Lab1 DC Tmax 2012 1217 v1
Lab1 DC Tmax 2012 1217 v1
Outline
Introduction Design Compiler TetraMax Lab
Outline
Introduction Design Compiler TetraMax Lab
Introduction
This lab compares impact on circuit after scan-chain insertion. Items being compared including area, power, test coverage, # of patterns. Synopsys Design Compiler is the most common synthesis tool supports interactive command input. Synopsys TetraMax is used to perform ATPG (Automatic Test Pattern Generation) and fault simulation.
1 Scan-Ready Synthesis 2
Set ATE Configuration
3 4
5 6
Scan Preview
8
Estimate Test coverage Scan Chain Synthesis
Post-Scan Check
design_dft.v
DC
Simulation Library
TetraMax
design.stil
Fault Reports
Outline
Introduction Design Compiler TetraMax Lab
Work Stations
Account: testing01~testing35 Password: testing2012 Open the terminal
$ ssh [email protected] Account: vlsitesting01~vlsitesting35 Password: vlsitesting
$ cd lab1 $ dc_shell-t
Link
Resolve the design reference based on reference names Locate all design and library components, and connect them
dc_shell> link
Uniquify
Removes multiply-instantiated hierarchy in the current design by creating a unique design for each cell instance
dc_shell> uniquify
Specify the scan style. Four styles are supported 1) Multiplexed flip-flop (multiplexed_flip_flop) 2) Clocked scan (clocked_scan) 3) Level-sensitive scan design (lssd) 4) Auxiliary-clock LSSD (aux_clock_lssd)
dc_shell> set_scan_configuration -style multiplexed_flip_flop
Compile(1/2)
Using command compile to perform logic level and gate level synthesis and optimization on current design -map_effort : specify the relative amount of CPU time spent during the mapping phase of compile
Compile(2/2)
-scan : specify command to consider the impact of scan insertion on mission mode constraints during optimization. This option causes the command to replace all sequential elements during optimization. Some scan-replaced sequential cells might be converted to nonscan cells later in the test synthesis process because of test design rule violations or explicit user specifications.
dc_shell> compile -scan -map_effort medium
dc_shell> create_port -direction "in" {TM} dc_shell> set_dft_configuration -fix_clock enable dc_shell> set_dft_signal -view exist -type ScanClock timing {50 100} port clk dc_shell> set_dft_signal -view spec -type TestData -port clk dc_shell> set_dft_signal -view spec -type TestMode -port TM dc_shell> set_autofix_configuration -type clock -control TM -test_data clk
Check test design rules according to the scan style you chose
dc_shell> dft_drc
Result(1/2)
Area
Number Number Number Number of of of of ports: nets: cells: references: 147 594 474 52
Combinational area: 2765.914043 Noncombinational area: 1302.566048 Net Interconnect area: 103180.518768 Total cell area: Total area: 4068.480091 107248.998859
Result(2/2)
Power
Global Operating Voltage = 1 Power-specific unit information : Voltage Units = 1V Capacitance Units = 1.000000pf Time Units = 1ns Dynamic Power Units = 1mW (derived from V,C,T units) Leakage Power Units = 1uW
Cell Internal Power = 92.3638 uW (38%) Net Switching Power = 151.7164 uW (62%) --------Total Dynamic Power = 244.0803 uW (100%) Cell Leakage Power = 4.9543 uW
Outline
Introduction Design Compiler TetraMax Lab
Invoke TetraMax
In the tcsh shell $ source /usr/cad/synopsys/CIC/tmax.cshrc type above command for the first time invoke Tetramax $ tmax -s
Reporting Modules
-summary : generate a summary report on all modules -error : report all modules that have at least one violation of a rule of severity of "error -undefined : report all modules that are referenced but not defined
BUILD> report_modules -summary BUILD> report_modules -error BUILD> report_modules -undefined
ATPG(1/2)
Create a list of faults for fault simulation and test generation.
TEST > add_faults -all
ATPG(2/2)
-abort_limit : Specify the max. number of remade decisions before terminating a test generation effort during ATPG. (default: 10) -coverage : Specify a test coverage limit at which to terminate the ATPG effort. Ranging from 0 ~ 100 (default: 100) -decision : When backtracking, using specific way to determine (default: norandom) TEST> set_atpg -merge high -verbose abort_limit 250 -coverage 100 -decision random fill x TEST> run_atpg
Result
Test coverage
Uncollapsed Stuck Fault Summary Report ----------------------------------------------fault class code #faults ------------------------------ ---- --------Detected DT 5912 Possibly detected PT 0 Undetectable UD 101 ATPG untestable AU 1 Not detected ND 44 ----------------------------------------------total faults 6058 test coverage 99.24% ----------------------------------------------Pattern Summary Report ----------------------------------------------#internal patterns 168 #basic_scan patterns 168 -----------------------------------------------
Fault Class
Undectable
Cannot be tested by any means
ATPG Untestable
Cannot be found using ATPG, but may be detected by other methods(functional tests)
Not Detected
Cannot be found due to ATPG iterations limits or designs too complex
Reporting Faults
Sets the parameters that control the fault manager
TEST > set_faults -summary verbose Set which kind of faults you want to see collapsed/uncollapsed TEST > set_faults -report collapsed TEST > report_summaries
Reporting Faults
-level [d] [m] : Generates a fault report for specified hierarchical levels. The d argument specifies the hierarchical depth of the report and the m specifies a minimum number of faults required to display a given depth
TEST > report_faults -level 5 10
Writing Faults
Writes fault data to external file
TEST > write_faults pre_norm_faults.rpt -all -replace
Outline
Introduction Design Compiler TetraMax Lab
Goal(1/2)
Compare area , power, test coverage and # of test pattern differences for circuits with and without inserting scan-chain. For circuit without scan-chain, dont set any command related to scan in design compiler, includeing: compile -scan, preview_dft, insert_dft, set_scan_configuration, report_scan_path, create_test_protocol, write_test_protocol, write_scan_def
Goal(2/2)
For circuit without scan-chain running ATPG, use the following command: run_drc
For circuit without scan-chain doing ATPG, use option -full_seq_atpg
TEST> set_atpg -full_seq_atpg
Result
pre_norm Area Power Coverage ATPG Run Time 211.50 Pattern
90857
238uw
97.97%
539
107248
240uw
99.24%
1.50
168
Homework
Run pre_norm.v and s35932_seq.v
Reference
[1] SynopsysInc., Design Compiler User Guide, Dec. 2004. [2] SynopsysInc., Design Compiler Command-Line Interface Guide [3] SynopsysInc., Design CompilerReference Manual [4] IPCORE Lab Slide 2006, Tian-Sheuan Chang [5] VLSI Testing Course Slide, Jing-Jia Liou [6] CIC Training Center Slide, Hsin-Jung Huang