Unit 2
Unit 2
Unit 2
xi
0 0 0
Yi
0 0 1
carry ci
0 1 0
sum si
0 1 1
carry-out ci+1
0 0 0
0
1 1 1 1
1
0 0 1 1
1
0 1 0 1
0
1 0 0 1
1
0 1 1 1
Product of n digit numbers can be accommodated in 2n digits Product of 4bit numbers will fit into 8bits Refer pg-378 4th para alone for register configuration diagram
Manual multiplication
1 1 0 1 x multiplicand M 1 0 1 1 multiplier Q 1101 1101 0000 1101 1 0 0 0 1 1 1 1 Product P
REGISTER CONFIGURATION
BOOTH ALGORITHM
FAST MULTIPLICATION
1.BIT PAIR RECODING OF MULTIPLIER 2.CARRY SAVE ADDITION OF SUMMANDS
Have been used in various ways by the high performance processor to reduce the time needed to perform multiplication
A technique called Bit pair recoding halves the maximum number of summands It is derived directly from booth algorithm
Multiplication requires the addition of several summands A technique called carry save addition(CSA) speeds up the addition process Instead of letting the carries ripples along the rows, they can be saved and introduced into the next row ,at the correct weighted position
Delay through carry save array is somewhat less than delay through ripple carry array A more significant reduction in delay can be achieved as follows
Consider addition of many summands,as required in multiplication of longer operand Group the summands in three and perform carry save addition on each of these group
- We continue this process until there are only two vectors remaining
Restoring Division