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Isa Introduction
Isa Introduction
Fall, 2006
CSCE430/830
ISA
Review
Amdahls Law:
Execution Time without enhancement E 1 Speedup(E) = --------------------------------------------------------- = ---------------------Execution Time with enhancement E (1 - F) + F/S
CPU Time & CPI: CPU time = Instruction count x CPI x clock cycle time CPU time = Instruction count x CPI / clock rate
CSCE430/830
ISA
Outline
Instruction Set Overview
Classifying Instruction Set Architectures (ISAs) Memory Addressing Types of Instructions \
CSCE430/830
ISA
Interface Design
A good interface:
Interface
imp 1
time
imp 2
imp 3
CSCE430/830
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CSCE430/830
ISA
General Purpose Register Machines Complex Instruction Sets (Vax, Intel 432 1977-80) CISC Intel x86, Pentium
CSCE430/830
Load/Store Architecture (CDC 6600, Cray 1 1963-76) RISC (MIPS,Sparc,HP-PA,IBM RS6000,PowerPC . . .1987)
ISA
Classifying ISAs
Accumulator (before 1960, e.g. 68HC11):
1-address add A acc acc + mem[A]
CSCE430/830
CSCE430/830
ISA
memory
CSCE430/830
memory
R1 = R1 + mem[C]
R3 = R1 + R2
ISA
Memory
Disk
CSCE430/830
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Stack Architectures
Instruction set:
add, sub, mult, div, . . . push A, pop A
CSCE430/830
ISA
Cons
Stack becomes the bottleneck Little ability for parallelism or pipelining Data is not always at the top of stack when need, so additional instructions like TOP and SWAP are needed Difficult to write an optimizing compiler for stack architectures
CSCE430/830
ISA
Accumulator Architectures
Instruction set:
add A, sub A, mult A, div A, . . . load A, store A
CSCE430/830
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Cons
Accumulator becomes the bottleneck Little ability for parallelism or pipelining High memory traffic
CSCE430/830
ISA
Memory-Memory Architectures
Instruction set:
(3 operands) (2 operands) add A, B, C add A, B sub A, B, C sub A, B mul A, B, C mul A, B
CSCE430/830
ISA
Cons
Very high memory traffic (especially if 3 operands) Variable number of clocks per instruction With two operands, more data movements are required
CSCE430/830
ISA
Register-Memory Architectures
Instruction set:
add R1, A load R1, A sub R1, A store R1, A mul R1, B
R1 = R1 +,-,*,/ mem[B]
/*
A*B
*/
/* /* /*
C*B */ A + CB */ AB - (A + C*B) */
ISA
Cons
Operands are not equivalent (poor orthogonal) Variable number of clocks per instruction May limit number of registers
CSCE430/830
ISA
Load-Store Architectures
Instruction set:
add R1, R2, R3 load R1, &A sub R1, R2, R3 mul R1, R2, R3 store R1, &A move R1, R2
/* /* /* /*
*/ */ */ */
CSCE430/830
ISA
Cons
Higher instruction count Not all instructions need three operands Dependent on good compiler
CSCE430/830
ISA
Disadvantages
Need to save and restore on procedure calls and context switch Cant take the address of a register (for pointers) Fixed size (cant store strings or structures efficiently) Compiler must manage Limited number
CSCE430/830
Every ISA designed after 1980 uses a load-store ISA (i.e RISC, to simplify CPU design).
ISA
Bytes Addr. 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 0010 0011 0012 0013 0014 0015
ISA
Addr = 0008 ??
Addr = 0012 ??
CSCE430/830
Byte Ordering
How should bytes within multi-byte word be ordered in memory? Conventions
Suns, Macs are Big Endian machines Least significant byte has highest address Alphas, PCs are Little Endian machines Least significant byte has lowest address
CSCE430/830
ISA
Little Endian
Least significant byte has lowest address
Example
Variable x has 4-byte representation 0x01234567 Address given by &x is 0x100 Big Endian 0x100 0x101 0x102 0x103
01
Little Endian
23
45
67
67
CSCE430/830
45
23
01
ISA
Example Fragment
Address 8048365: 8048366: 804836c: Instruction Code 5b 81 c3 ab 12 00 00 83 bb 28 00 00 00 00 Assembly Rendition pop %ebx add $0x12ab,%ebx cmpl $0x0,0x28(%ebx)
Deciphering Numbers
CSCE430/830
0x12ab 0x000012ab 00 00 12 ab ab 12 00 00
ISA
Example Add R4, R3 Add R4, #3 Add R4, 100(R1) Add R4, (R1) Add R4, (R1 + R2) Add R4, (1000) Add R4, @(R3) Add R4, (R2)+
Types of Operations
Arithmetic and Logic: Data Transfer: Control System Floating Point Decimal String Graphics AND, ADD MOVE, LOAD, STORE BRANCH, JUMP, CALL OS CALL, VM ADDF, MULF, DIVF ADDD, CONVERT MOVE, COMPARE (DE)COMPRESS
CSCE430/830
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Instruction load branch compare store add and sub register move call return
ISA
Design hardware to handle branches quickly, since these occur most frequently
CSCE430/830
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Summery
Instruction Set Overview
Classifying Instruction Set Architectures (ISAs) Memory Addressing Types of Instructions
CSCE430/830
ISA