3D IC Technology: Pouya Dormiani Christopher Lucas
3D IC Technology: Pouya Dormiani Christopher Lucas
3D IC Technology: Pouya Dormiani Christopher Lucas
Pouya Dormiani
Christopher Lucas
What is a 3D IC?
Could be Heterogeneous
Motivation
3D Fabrication Technologies
Beam
Recrystallization
Processed Wafer
Bonding
Silicon Epitaxial
Growth
Solid Phase
Crystallization
Deposit polysillicon
and fabricate TFTs
-not practial for 3D circuits
Epitaxially grow a
single cystal Si
Low Temp
alternative to SE.
on all devices
-Independent of temp. since
all chips are fabricated then
bonded
-Good for applications where
chips do independent
processing
-However Lack of
Precision(alignemnt) restricts
interchip communication to
global metal lines.
multiple layers
-Compatible with current
processing environments
-Useful for Stacked SRAM
and EEPROM cells
Performance Characteristics
Timing
Energy
Timing
Energy performance
Wire length reduction has an impact on
the cycle time and the energy dissipation
Energy dissipation decreases with the
number of layers used in the design
Following graphs are based on the 3D tool
described later in the presentation
Current tool-chains
Mostly
academic
3D Cell Placement
Placement
3D Global Routing
Inter-wafer
by min-cut partitioning
vias
Natural to think of a 3D
integrated circuit as
being partitioned into
device layers or planes
Min cut part-itioning
along the 3rd dimension
is same as minimizing
vias
Can trade off increased total wire length for fewer inter-plane
vias by varying the point at which the design is partitioned
into planes
stage
Overview
Global
Followed
by detailed routing
Usually
y
x
z
Detailed routing of net when
routing areas are known
trees
Integer programming approach still too slow for
size of problem and complexity (NP-hard)
Hierarchical routing methods break down the
integer program into pieces small enough to be
solved exactly
2D Global Routing
These are cut by the partition and for each a pin is inserted
into the side of the partition
Illustration of Bisection
Extending to 3D
Wires can enter from any of the sides of the routing region in
addition to its top and bottom
3D Routing Results
Percentage Of 2D
Total wire Length
Minimizing for Wire Length:
2 Layers ~ 28%
5 Layers ~ 51 %
3D-MAGIC
Concerns in 3D circuit
Thermal Issues in 3D-circuits
EMI
Reliability Issues
Heat Flow in 2D
Heat generated arises due to switching
In 2D circuits we have only one layer of Si to
consider.
Heat Flow in 3D
With multi-layer circuits , the upper
layers will also generate a significant
fraction of the heat.
Heat increases linearly with level increase
Heat Dissipation
All active layers will be insulated from each other by layers of dielectrics
With much lower thermal conductivity than Si
Therefore heat dissipation in 3D circuits can accelerate many failure
mechanisms.
Heat Dissipation in
Wafer Bonding versus Epitaxial Growth
Wafer Bonding(b)
Epitaxial Growth(a)
Heat Dissipation in
Wafer Bonding versus Epitaxial Growth
Design 1
Design 2
EMI in 3D ICs
Coupling between the top layer metal of the first active layer and the device on
the second active layer devices is expected
EMI
Reliability Issues?
Buffer Insertion
Layout of Critical Paths
Microprocessor Design
Mixed Signal ICs
Physical design and Synthesis
Buffer Insertion
Buffer Insertion
Use of buffers in 3D circuits to break up long interconnects
At top layers inverter sizes 450 times min inverter size for the relevant
technology
These top layer buffers require large routing area and can reach up to
10,000 for high performance designs in 100nm technology
With 3D technology repeaters can be placed on the second layer and
reduce area for the first layer.
Conclusion
3D IC design is a relief to interconnect
driven IC design.
Still many manufacturing and
technological difficulties
Needs strong EDA applications for
automated design