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Week 6
Week 6
Every P-based system has a memory system. All systems contain two types of memories.
Read-Only Memory (non Volatile Memory)
Random Access Memory (Read/Write Memory or volatile Memory)
ROM contains system software and permanent system data.
RAM contains system temporary data and system application software.
Memory Devices:
Read-Only Memory
Static Random Access Memory (SRAM)
Flash Memory (EEPROM) Dynamic Random Access Memory (DRAM)
Memory Pin Connections:
Pin connections common to all memory devices are:
Address Inputs
Data Outputs or Input(s)/Output(s)
Selection Input
Control input to selects READ or Write
Address Connections: Address inputs selects a memory location within the memory device.
Labeled from A0, least significant address input
AN, N labeled, N-1then the total number of address pins
Address Pins
Memory
(N)
Address
Connections
Memory
Locations (2N)
1K
10
A0-A9
1024
2K
11
A0-A10
2048
4K
12
A0-A11
4096
8K
13
A0-A12
8192
A0-A19
1M
20
1,048,576
Memory Device Memory Sys. Section Decoded Starting Address
Last Location Address
103FFH (10000H+400H-1H)
1K
400H (1024)
10000H
4K
64K
1M
1000H (4096)
10,000H
100,000H
14000H
30000H
-
14FFFH (14000H+1000H-1H)
3FFFFH
-
Data Connections:
All memory deices has a set of data outputs or input(s)/output(s).
Today, many devices have bi-directional common IO pins.
Data pins are labeled with D7-D0 for an 8-bit-wide memory
(Means memory device stores 8-bit of data in each of its
Memory locations).
8-bit-wide memory device is often called byte-wide memory
Mostly devices are 8-bit-wide, some devices are 16-bits,
4-bits or just 1-bit-wide
Datasheet (Catalog Listing) of memory devices often
Represented by:
Memory Locations x Bits per Location
Ex: Memory Device with 1-K memory locations and 8-bits in each location is often listed as
1K x 8 by the manufacturer. (64K x 4 , 16K x 1)
Sometime memory devices classified as Total bit Capacity.
Ex: 8K, 256K
Selection Connections:
Memory devices has one or more selection or enable inputs
Chip Select (CS) Chip Enable (CE) Select (S)
RAM has at least one CS or S.
ROM has at least one CE.
If CS, CE or S input is active (Logic 0), memory device performs a read or write operation
If CS, CE or S input is inactive (Logic 1), memory device do not performs a read or write
operation b/c it is turned OFF or Disabled.
Control Connections:
Memory devices have control input (s).
ROM has only one control input
ROM Memory:
ROM most commonly used type is EPROM (Erasable Programmable Read-Only Memory)
EEPROM (Electrically Erasable Programmable Read-Only Memory) or Flash Memory
Types of EPROM with following part numbers:
2704
512 x 8
2708
1K x 8
2716
2K x 8
2732
4K x 8
2764
8K x 8
27128
16K x 8
27256
323K x 8
27512
64K x 8
271024
128K x 8
Each has
Address inputs
Eight data pins
One or more Chip Selection inputs (CE), and output enable (OE)
OE
CE
Address Decoding:
Its is necessary to decode the address sent from the P
Without address decoder only one memory can be connected
Why Decode Memory:
8088 is compared to the 2716 EPROM
20-bit
11-bit
1M x 8
2K x 8
The decoder corrects the mismatch by decoding the address pins that do not connect to
the memory device.
2764 EPROM 8K x 8:
To enable decoder IC, A19-A16 four connections must all be high.
8086 must be able to write data to any 16-bit location or any 8-bit location
16-bit bus must be divided into 2 separate sections (banks)
Low Bank
High Bank
Bank Selection is accomplish in two ways:
Separate Bank Decoders
Separate Bank Write Strobes