William Stallings Computer Organization and Architecture 6 Edition System Buses

William Stallings
Computer Organization
and Architecture
6th Edition
Chapter 3
System Buses
(revised 9/7/02)
Program Concept
Hardwired systems are inflexible
General purpose hardware can do different
tasks, given correct control signals
Instead of re-wiring, supply a new set of control
signals
Hardware vs. HW + SW
What is a program?
A sequence of steps
For each step, an arithmetic or logical operation
is done
For each operation, a different set of control
signals is needed
Function of Control Unit
For each operation a unique code (opcode) is
provided
e.g. ADD, MOVE
A hardware segment accepts the code and
issues the control signals
We have a computer!
Components
The Control Unit (CU) and the Arithmetic and
Logic Unit (ALU) constitute the Central
Processing Unit (CPU)
Data and instructions need to get into the
system and results need to get out
Input/output (I/O module)
Temporary storage of code and results is
needed
Main memory (RAM)
Computer Components:
Top Level View
Instruction Cycle
Two steps:
Fetch
Execute
Fetch Cycle
Program Counter (PC) holds address of next
instruction to fetch
Processor fetches instruction from memory
location pointed to by PC
Increment PC
Unless told otherwise
Instruction loaded into Instruction Register (IR)
Execute Cycle
Processor interprets instruction and performs
required actions, such as:
Processor - memory
data transfer between CPU and main memory
Processor - I/O
Data transfer between CPU and I/O module
Data processing
Some arithmetic or logical operation on data
Control
Alteration of sequence of operations
e.g. jump
Combination of above
Fetching & Execution Cycles
Fetching Cycles
The fetch cycle takes the instruction required
from memory, stores it in the instruction
register, and
moves the program counter on one so that it
points to the next instruction.
Execute cycle
The actual actions which occur during the
execute cycle of an instruction.
depend on both the instruction itself and the
addressing mode specified to be used to access 11
the data that may be required.
Fetching an instruction
Step 1
Instruction pointer (program counter) hold the address of the
next instruction to be fetch.
12
FETCHING AN INSTRUCTION (cont.)
Step 2
13
Step 3
14
Step 4
15
Step 5
16
Step 6
17
Buses
There are a number of possible interconnection
systems
Single and multiple BUS structures are most
common
e.g. Control/Address/Data bus (PC)
e.g. Unibus (DEC-PDP)
What is a Bus?
A communication pathway connecting two or
more devices
Usually broadcast (all components see signal)
Often grouped
A number of channels in one bus
e.g. 32 bit data bus is 32 separate single bit channels
Power lines may not be shown
Bus Interconnection Scheme
Data Bus
Carries data
Remember that there is no difference between data
and instruction at this level
Width is a key determinant of performance
8, 16, 32, 64 bit
Address bus
Identify the source or destination of data
e.g. CPU needs to read an instruction (data)
from a given location in memory
Bus width determines maximum memory
capacity of system
e.g. 8080 has 16 bit address bus giving 64k address
space
Control Bus
Control and timing information
Memory read/write signal
Interrupt request
Clock signals
Big and Yellow?
What do buses look like?
Parallel lines on circuit boards
Ribbon cables
Strip connectors on mother boards
e.g. PCI
Sets of wires
Single Bus Problems
Lots of devices on one bus leads to:
Propagation delays
Long data paths mean that co-ordination of bus use can
adversely affect performance
If aggregate data transfer approaches bus capacity
Most systems use multiple buses to overcome
these problems
Traditional (ISA)
(with cache)
High Performance Bus
Bus Types
Dedicated
Separate data & address lines line is permanently assigned either
to one function or to a physical subset of computer components
Multiplexed
Shared lines
Address valid or data valid control line
address and data information may be transmitted over the same set of lines using an Address
Valid control line.
At the beginning of a data transfer, the address is placed on the bus and the Address Valid line is
activated. At his point, each module has a specified period of time to copy the address and
determine if it is the addressed module. The address is then removed from the bus, and the same
bus connections are used for the subsequent read or write data transfer.This method of using the
same lines for multiple purposes is known as time Multiplexing.
Advantage - fewer lines

Disadvantages
More complex control
Ultimate performance (certain events that share the same lines cannot take
place in parallel
Bus Arbitration
More than one module controlling the bus
e.g. CPU and DMA controller
Only one module may control bus at one time
Arbitration may be centralised or distributed
Centralised Arbitration
Single hardware device controlling bus access
Bus Controller
Arbiter
May be part of CPU or separate
In a centralized scheme, a single hardware device,
referred to as a bus controller or arbiter, is responsible
for allocating time on the bus. The device may be a
separate module or part of the processor.
Distributed Arbitration
Each module may claim the bus
Control logic on all modules
there is no central controller. Rather, each module
contains access control logic and the modules act
together to share the bus. With both methods of
arbitration, the purpose is to designate one device,
either the processor or an I/O module, as master.
PCI Bus
Peripheral Component Interconnection (PCI)
Intel released to public domain
32 or 64 bit
50 lines
PCI Bus Lines (required)
Systems lines
Including clock and reset
Address & Data
32 time mux lines for address/data
Interrupt & validate lines
Interface Control
Arbitration
Not shared
Direct connection to PCI bus arbiter
Error lines
Foreground Reading
Stallings, chapter 3 (all of it)
www.pcguide.com/ref/mbsys/buses/
In fact, read the whole site!

www.pcguide.com/

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William Stallings

Advantage - fewer lines

In fact, read the whole site!

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