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Instruction Sets in 8086
Instruction Sets in 8086
MOV
Mnemonic Meaning Format Operation Flags affected
MOV Move Mov D,S (S) (D) None
Destination Source
Memory Accumulator
Accumulator Memory
NO MOV
Memory Memory
Register Register
Immediate Segment Register
Register Memory Segment Segment Register
Memory Register Register
Register Immediate
Memory Immediate
Seg reg Reg 16 EX: MOV AL, BL
Seg reg Mem 16
Reg 16 Seg reg
2
Memory Seg reg
XCHG
Mnemonic Meaning Format Operation Flags affected
Destination Source
Accumulator Reg 16 Example: XCHG [1234h], BX
Memory Register
NO XCHG
Register Register MEMs
Register Memory SEG REGs
3
LEA, LDS, LES
Mnem Meaning Format Operation Flags
onic affecte
d
LEA Load LEA Reg16,EA EA (Reg16) None
Effective
Address
LDS Load LDS (MEM32) (Reg16) None
Register Reg16,MEM32
And DS (Mem32+2) (DS)
4
PUSHF
Copy flag register to top of the stack
POPF
Copy top of the stack to flag register
5
XLAT
Mnemonic Meaning Format Operation Flags
XLAT Translate XLAT ((AL)+(BX)+(DS)0) (AL) None
Example:
8
TEST
• Logical compare instruction
• Performs a bit by bit logical AND operations
on the two operands.
• Result is not stored but flags are affected
• Example:
TEST AX,BX
TEST [5000],06H
TEST [BX][DI],CX
SHR/SAL: shift logical left/shift
arithmetic left
SHR: shift logical right
SAR: shift arithmetic right
ROL: rotate left
ROR: rotate right
RCL: rotate left through carry
RCR: rotate right through carry
10
Logical vs Arithmetic Shifts
• A logical shift fills the newly created bit position with
zero:
0
CF
CF
11
Mnemo Meaning Format Operation Flags Affected
-nic
12
Allowed operands
Destination Count
Register 1
Register CL
Memory 1
Memory CL
13
14
SHL
• The SHL (shift left) instruction performs a logical left
shift on the destination operand, filling the lowest
bit with 0.
0
CF
• Operand types:
SHL reg,imm8
SHL mem,imm8
SHL reg,CL
SHL mem,CL
15
Fast Multiplication
Shifting left 1 bit multiplies a number by 2
mov dl,5 Before: 00000101 =5
0
CF
CF
MOV DL,-80
SAR DL,1 ; DL = -40
SAR DL,2 ; DL = -10
18
Mnem Meaning Format Operation Flags Affected
-onic
ROL Rotate ROL D,Count Rotate the (D) left by the CF
Left number of bit positions equal to OF undefined
Count. Each bit shifted out if count ≠ 1
from the left most bit goes back
into the rightmost bit position.
CF
MOV Al,11110000b
ROL Al,1 ; AL = 11100001b
MOV Dl,3Fh
ROL Dl,4 ; DL = F3h
20
ROR
• ROR (rotate right) shifts each bit to the right
• The lowest bit is copied into both the Carry
flag and into the highest bit
• No bits are lost
CF
MOV AL,11110000b
ROR AL,1 ; AL = 01111000b
MOV DL,3Fh
ROR DL,4 ; DL = F3h 21
RCL
• RCL (rotate carry left) shifts each bit to the left
• Copies the Carry flag to the least significant bit
• Copies the most significant bit to the Carry flag
CF
CLC ; CF = 0
MOV BL,88H ; CF,BL = 0 10001000b
RCL BL,1 ; CF,BL = 1 00010000b
RCL BL,1 ; CF,BL = 0 00100001b22
RCR
• RCR (rotate carry right) shifts each bit to the right
• Copies the Carry flag to the most significant bit
• Copies the least significant bit to the Carry flag
CF
STC ; CF = 1
MOV AH,10H ; CF,AH = 00010000 1
RCR AH,1 ; CF,AH = 10001000 0
23
Rotate Instructions
Destination Count
Register 1
Register CL
Memory 1
Memory CL
24
Mnemoni Meaning Format Operation Flags
c affected
25
Examples:
Ex.1 ADD AX,02
ADC AX,02
Ex.2 INC BX
INC [BX]
Ex.3 AL contains 25 (packed BCD)
BL contains 56 (packed BCD)
ADD AL, BL 25
+ 56
DAA
--------
7B 81
26
Mnemonic Meaning Format Operation Flags
affected
SUB Subtract SUB (D) - (S) (D) All
D,S Borrow (CF)
SBB Subtract SBB (D) - (S) - (CF) (D) All
with D,S
borrow
DEC Decremen DEC D (D) - 1 (D) All but CF
t by one
NEG Negate NEG D All
27
Examples: DAS
MOV BL, 28H
MOV AL, 83H
SUB AL,BL ; AL=5BH
DAS ; adjust as AL=55H
28
29
Multiplication and Division
30
Ex2: AL = F3H, BL = 91H, AH = 00H
1. MUL BL → AL * BL = F3H * 91H = 89A3H → AX = 89A3H
AH AL AH AL
POS
15 02 → NEG → 2’s(02) = FEH→ 15 FE
NEG
R Q
00F 3H AH AL
AX
4. DIV BL → = = 01→(F3-1*91=62) → 62 01
BL 91H
R Q
31
Ex3: AX= F000H, BX= 9015H, DX= 0000H
DX AX
1. MUL BX = F000H * 9015H = 8713 B000
DX AX
2. IMUL BX = 2’S(F000H) * 2’S(9015H) = 1000 * 6FEB = 06FE B000
F 000H
3. DIV BL = = B6DH → More than FFH → Divide Error.
15H
32
Ex4: AX= 1250H, BL= 90H
R Q
29H ( POS) → 2’S (29H) = D7H →
60H D7H
1250H R Q
AX 50H 20H
2. DIV BL → = = 20H→1250-20*90 =50H →
BL 90 H AH AL
33
Flag control instructions
MNEM- MEANING OPERATION Flags
ONIC Affected
CLC Clear Carry Flag (CF) 0 CF
STC Set Carry Flag (CF) 1 CF
CMC Complement (CF) (CF)l CF
Carry Flag
CLD Clear Direction (DF) 0
Flag SI & DI will be auto incremented while DF
string instructions are executed.
STD Set Direction (DF) 1
Flag SI & DI will be auto decremented DF
while string instructions are executed.
CLI Clear Interrupt (IF) 0 IF
Flag
STI Set Interrupt (IF) 1 IF
Flag 34
String?
35
String Instruction Basics
38
Mnemo- meaning format Operation
Nic
SCAS Scan string SCASB/ Set flags as per
AX – ES:DI SCASW (AL or AX) - ((ES)0+(DI))
(DI) (DI) ± 1 or 2
39
Branch group of instructions
Branch instructions provide lot of convenience to the
programmer to perform operations selectively, repetitively
etc.
40
SUBROUTINE & SUBROUTINE HANDILING INSTRUCTIONS
Main program
Subroutine A
First Instruction
Call subroutine A
Next instruction
Return
Call subroutine A
Next instruction
41
A subroutine is a special segment of program that can be called for
execution from any point in a program.
An assembly language subroutine is also referred to as a “procedure”.
Whenever we need the subroutine, a single instruction is inserted in to
the main body of the program to call subroutine.
To branch a subroutine the value in the IP or CS and IP must be
modified.
After execution, we want to return the control to the instruction that
immediately follows the one called the subroutine i.e., the original value
of IP or CS and IP must be preserved.
Execution of the instruction causes the contents of IP to be saved on
the stack. (this time (SP) (SP) -2 )
A new 16-bit (near-proc, mem16, reg16 i.e., Intra Segment) value
which is specified by the instructions operand is loaded into IP.
Examples: CALL 1234H
CALL BX
CALL [BX]
42
• Inter Segment
Far-proc
Memptr32
These two words (32 bits) are loaded directly into IP and
CS with execution at CALL instruction.
First 16 IP
Next 16 CS
43
Mnem- Meaning Format Operation Flags
onic Affected
Operand
Near-proc
Far – proc
Memptr 16
Regptr 16
Memptr 32 44
RETURN
• Every subroutine must end by executing an instruction that returns control
to the main program. This is the return (RET) instruction.
Operand
None
45
Disp16
Loop Instructions
• These instructions are used to repeat a set of instructions several
times.
• Format: LOOP Short-Label
• Operation: (CX) (CX)-1
• Jump is initialized to location defined by short label if CX≠0.
otherwise, execute next sequential instruction.
• Instruction LOOP works w.r.t contents of CX. CX must be
preloaded with a count that represents the number of times the
loop is to be repeat.
• Whenever the loop is executed, contents at CX are first
decremented then checked to determine if they are equal to zero.
• If CX=0, loop is complete and the instruction following loop is
executed.
• If CX ≠ 0, content return to the instruction at the label specified in
the loop instruction.
46
LOOP Instruction contd.
It is a 2 byte instruction.
48
Control flow and JUMP instructions
Unconditional Jump
Part 1
JMP AA
Unconditional JMP
Part 2
Skipped part
Part 3
AA XXXX Next instruction
Part 1
Part 2
NO
Skipped part
condition XXXX
YES
Part 3
AA XXXX Next instruction
51
Conditional Jump instructions
52
Conditional Jump Instructions
Mnemonic : Jcc
Meaning : Conditional Jump
Format : Jcc operand
Operation : If condition is true jump to the address specified by operand.
Otherwise the next instruction is executed.
Flags affected : None
53
TYPES
JB Below CF=1
JC Carry CF=1
JE Equal ZF=1
55
Mnemonic meaning condition
JNLE Not Less nor Equal ZF = 0 and SF = OF
JNO Not Overflow OF = 0
JNP Not Parity PF = 0
JNZ Not Zero ZF = 0
JNS Not Sign SF = 0
JO Overflow OF = 1
JP Parity PF = 1
JPE Parity Even PF = 1
JPO Parity Odd PF = 0
JS Sign SF = 1
JZ Zero ZF = 1
56
Jumps Based on a single flag
JZ r8 ;Jump if zero flag set to 1 (Jump if result is zero)
JNZ r8 ;Jump if Not Zero (Z flag = 0 i.e. result is nonzero)
JS r8 ;Jump if Sign flag set to 1 (result is negative)
JNS r8 ;Jump if Not Sign (result is positive)
58
Examples for JE or JZ instruction
CMP SI, DI
JE SAME
(if SI = DI)
59
Examples for JE or JZ instruction
60
Jumping beyond -128 to +127?
61
Terms used in comparison
64
Jump on multiple flags contd.
Jump if No Jump if
S = 1 AND V = 0 S = 0 AND V = 0
(surely negative) (surely positive)
OR (S = 0 AND V = 1) OR (S = 1 AND V = 1)
(wrong answer positive!) (wrong answer negative!)
OR Z = 1 (equal) AND Z = 0 (not equal)
65
Jump on multiple flags contd.
JNLE or Jump if Not (Less than OR Equal)
JG Jump if Greater than
Jump if No Jump if
S = 0 AND V = 0 S = 1 AND V = 0
(surely positive) (surely negative)
OR (S = 1 AND V = 1) OR (S = 0 AND V = 1)
(wrong answer negative!) (wrong answer positive!)
AND Z = 0 (not equal) OR Z = 1 (equal)
66
Jump on multiple flags contd.
Jump if No Jump if
S = 1 AND V = 0 S = 0 AND V = 0
(surely negative) (surely positive)
OR (S = 0 AND V = 1) OR (S = 1 AND V = 1)
(wrong answer positive!) (wrong answer negative!)
67
Jump on multiple flags contd.
Jump if No Jump if
S = 0 AND V = 0 S = 1 AND V = 0
(surely positive) (surely negative)
OR (S = 1 AND V = 1) OR (S = 0 AND V = 1)
(wrong answer negative!) (wrong answer positive!)
68
Near Jump
Near Jump
Direct Jump Indirect Jump
(common) (uncommon)
3 Near Jump and 2 Far Jump instructions have the same mnemonic
JMP but different opcodes
69
Short Jump
2 byte (EB r8) instruction Range: -128 to +127 bytes
70
Short Jump contd.
71
Long Jump
72
Long Jump contd.
73
Long Jump or Short Jump?
CS:0000H :
: Jump distance
Can be treated CS:000DH JMP FRWD =FFE0H. Too
as a small very long
(20H) backward CS:0010H :
forward jump
branch! :
FRWD= CS:FFF0H
CS:FFFFH
74
Long Jump or Short Jump?
CS:0000H :
: Jump distance
Can be treated BKWD= CS:0010H : =FFE0H. Too
as a small very long
(20H) forward :
backward jump
branch! JMP BKWD
CS:FFF0H
CS:FFFFH
75
Intra segment indirect Jump
Ex.1: JMP DX
If DX = 1234H, branches to CS:1234H
1234H is not signed relative displacement
76
Far Jump
Far Jump
5 bytes
2 or more bytes
EA,2 byte offset, 2 byte segment
Starting with FFH
Range: anywhere
Range: anywhere
3 Near Jump and 2 Far Jump instructions have the same mnemonic
JMP but different opcodes
77
Inter segment Direct Jump
It is a 5 byte instruction
1 byte opcode (EAH)
2 byte offset value
2 byte segment value
78
Inter segment Indirect Jump
79
Inter segment Indirect Jump
BX 1234H Branches to
ABCDH:5678H
DS:3234H 5678H It is a 4-byte instruction
DS:3236H ABCDH
80
Machine control instructions
HLT instruction – HALT processing
the HLT instruction will cause the 8086 to stop fetching and executing
instructions. The 8086 will enter a halt state. The only way to get the processor
out of the halt state are with an interrupt signal on the INTR pin or an interrupt
signal on NMI pin or a reset signal on the RESET input.
NOP instruction
this instruction simply takes up three clock cycles and does no
processing. After this, it will execute the next instruction. This instruction is
normally used to provide delays in between instructions.
ESC instruction
whenever this instruction executes, the microprocessor does NOP or
access a data from memory for coprocessor. This instruction passes the
information to 8087 math processor. Six bits of ESC instruction provide the
opcode to coprocessor.
when 8086 fetches instruction bytes, co-processor also picks up these
bytes and puts in its queue. The co-processor will treat normal 8086
instructions as NOP. Floating point instructions are executed by 8087 and
during this 8086 will be in WAIT.
81
Machine control instructions contd
LOCK instruction
this is a prefix to an instruction. This prefix makes sure that during
execution of the instruction, control of system bus is not taken by other
microprocessor.
in multiprocessor systems, individual microprocessors are connected
together by a system bus. This is to share the common resources. Each
processor will take control of this bus only when it needs to use common
resource.
the lock prefix will ensure that in the middle of an instruction, system
bus is not taken by other processors. This is achieved by hardware signal
‘LOCK’ available on one of the CPU pin. This signal will be made active
during this instruction and it is used by the bus control logic to prevent
others from taking the bus.
once this instruction is completed, lock signal becomes inactive and
microprocessors can take the system bus.
WAIT instruction
this instruction takes 8086 to an idle condition. The CPU will not do
any processing during this. It will continue to be in idle state until TEST pin
of 8086 becomes low or an interrupt signal is received on INTR or NMI. On
valid interrupt, ISR is executed and processor enters the idle state again.
82