Asic Vs Fpga
Asic Vs Fpga
FPGA
Prof. S. S. S. P. Rao
Chief Technology Officer
Xilinx India Development Centre, Hyderabad
MEM
A B
ALU
HW FIXED HW CREATED
Storage, Server
and Computing
FPGAs
ASICs
Disk array
Industrial
Examples:
Mars Rover
BMW Cars
SD
P ROLIANT
8000
Consumer
ESC
Electronics DLT
SD
Networking
Satellite dish
Satellite
18%
20 16%
13.70%
14%
Billion $
15 12% ASIC
10% FPGA
10 8% FPGA %
6%
5 4%
2%
0 0%
2002 2003 2004 2005 2006 2007
100,000 500
FPGA
80,000 74,941 400
(-27%)
60,000 300
Density
40,000 200
20,000 100
8,950
ASIC 3,609
0 24 M (-60%) 0
1999 2000 2001 2002 2003 2004
400 400
300
100X
200
100
5 4
2 1.5
2001 2002 2003 2004
FPGA
Source: Gartner Group ASIC
9
What’s Inside These Chips?
ASIC FPGA
Building block is
Building block is
Functionality a programmable
a ‘Cell’
(or Logic) unit called ‘LUT’
(Look Up Table)
Pre-defined
Routing is
routing tracks
custom-crafted
Interconnect which are
by hand or by
(or Routing) programmable
tool
(using a ‘switch’
matrix)
FPGA vs ASIC 10 Xilinx Copyright
ASIC ‘Cell’
• Implements a fixed function like ‘And’, ‘XOR, ‘Mux’, ‘1 bit
adder’, etc (very much like TTL chips like the 74xx
series)
• The entire chip is then built ‘hierarchically’ with cells
being connected together to create more complex
functions (eg. Multipliers, decoders, etc)
‘Complex’ function Cells
A
B
Z
C
D
A B
Programmed Anti-fuse Insulator
A B (oxide)
(closed)
SRAM Anti-fuse
Reprogrammable One-Time Programmable
Standard mfg process Special mfg process
Smaller size
Larger size
Faster
Slower
logic
– carry logic for fast adders
– 4 outputs, 2 registered + LUT Carry D PRE
CE Q
2 non-registered
CLR
slices BUF T
Slice S3
• Local routing provides
feedback between slices in Slice S2
the same CLB, and it Switch
Matrix
SHIFT
provides routing to
Slice S1
neighboring CLBs
• A switch matrix provides Slice S0 Local Routing
access to general routing
resources CIN CIN
Local Interconnect
Switch
majority (70-80%) of the delay in Matrix
For
most chips (vs 20-30% for Global
Interconnect
functionality)
• Interconnects are the major source
of the most subtle, complex, difficult-
to-debug problems in a chip. Eg.
Clocking and Coupling problems, Functionality/L Interconnect/R
ogic outing
race conditions, etc
High-speed
11.1 Gbps
Serial
Transceivers
Programmable IO
+ DCI (Digitally
Controlled
Impedance)
18 Bit
36 Bit
18 Bit
VCCIO
>500 DSP Z
Z
datapaths Z Impedance
200, 000 LUTs 10Mbit Dual-
(~10 million
Control
Port™ RAM
gates)
FPGA vs ASIC 22 Xilinx Copyright
VLSI Design Flow
Create Design
Plan & HDL/ HDL RTL
Budget Schematic Simulation
Integrate
IP Cores
Implement Synthesize
Functional to Create
Translate Simulation Netlist
FPGA ASIC
Asynchronous
Riskier to use because Lower risk since delays can
circuits
delays are hard to control be well controlled
Finite State One-hot encoding Gray, Binary, other encoding
Machines commonly used because of schemes
large number of registers
Deeper pipelines because of
As needed
Pipelining large number of registers
available
Scan, test Need to be added
Already in the chip
circuits separately
• Cost
• Design cycle time / Time-To-Market
• Performance/Speed
• Density/Size
• Production volume
• Ease of fixing bugs, making changes
FPGA vs ASIC 26 Xilinx Copyright
FPGA vs. ASIC Cost
High Design Cost of an ASIC is a major issue
Volume
For each technology advance,
crossover volume moves higher
FPGA vs ASIC 28 Xilinx Copyright
FPGA vs. ASIC Time-To-Market
FPGA Time-To-Market is 9 months vs 2-3 years for ASIC
ASIC
Spec Design & verification Silicon System Silicon First
Prototype Integration Production Ship
s s t ime
le
55%
FPGA
Spec Design & Verification System First
Integration Ship FPGA flexibility allows late changes,
higher chance of meeting customer needs
120
100
100
80
60
40 30
20 10
1 3
0
Arch Design Test System Customer
Metal
Oxide
Metal
Substrate
Diagram from: The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
FPGA vs ASIC 31 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Xilinx Copyright
FPGA vs. ASIC
Engineering Comparison
FPGA ASIC
Design Time /
Time-To-Market ~ 9 Months (2-3 Years)
Design Cost ($ 3-5 M, $1M
masks)
Performance
(speed, density, power)
Size (area)
Total Cost
at low-medium
at high volume
volume
Changes to design
FPGA vs ASIC 32 Xilinx Copyright
FPGA & ASIC
Trends
• Driven by Moore’s law, low design cost and shorter design cycle time,
FPGAs are becoming an increasing % of solution!