Lo'ai Tawalbeh: Cpe 252: Computer Organization 1
Lo'ai Tawalbeh: Cpe 252: Computer Organization 1
Lo’ai Tawalbeh
Memory It’s an
ADD
operation
Op code
Control
110010?????????? Unit
Read instruction
from memory
15 12 11 0 Memory
Opcode Address 15
4096x16 0
Instruction Format
Instructions
15 0
(program)
Binary Operand
Operands
(data)
15 0
Processor register
(Accumulator AC)
300 1350
457 Operand
1350 Operand
+ +
AC AC
15 0 4096 x 16
IR
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC
List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
LD INR CLR
PC 2
LD INR CLR
DR 3
LD INR CLR
E
Adder
and AC 4 Computer Registers
logic
LD INR CLR Common Bus System
INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
3x8
decoder
7 6543 210
D0
I
D7 Control Control
logic outputs
gates
T15
T0
15 14 . . . . 2 1 0
4 x 16
Sequence decoder
Hardwired Control
Organization
cpe 252: Computer Organization 32
- Generated by 4-bit sequence counter and 4x16 decoder
- The SC can be incremented or cleared.
T0
T1
T2
T3
T4
D3
CLR
SC
• T0: AR←PC
– Transfers the content of PC into AR if timing signal T 0 is
active
– T0 is active during an entire clock cycle interval
– During this time, the content of PC is placed onto the bus
(with S2S1S0=010) and the LD (load) input of AR is enabled
– The actual transfer does not occur until the end of the clock
cycle when the clock goes through a positive transition
– This same positive clock transition increments the
sequence counter SC from 0000 to 0001
– The next clock cycle has T1 active and T0 inactive
T1 S2
T0 S1 Bus
S0
Memory 7
unit
Address
Read
AR 1
LD
PC 2
INR
IR 5
LD Clock
Common bus
cpe 252: Computer Organization 40
Start DETERMINE THE TYPE OF
SC
INSTRUCTION
T0
AR PC
T1
IR M[AR], PC PC + 1
T2
Decode Opcode in IR(12-14),
AR IR(0-11), I IR(15)
T3 T3 T3 T3
Execute Execute AR M[AR] Nothing
input-output register-reference
instruction instruction
SC 0 SC 0 Execute T4
memory-reference
instruction
SC 0
D'7IT3: AR M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
AR = 135 135 21
136 Subroutine PC = 136 Subroutine
D0 T 4 D1 T 4 D2 T 4 D 3T 4
D0 T 5 D1 T 5 D2 T 5
AC AC DR AC AC + DR AC DR
SC <- 0 E Cout SC 0
SC 0
D4 T 4 D5 T 4 D6 T 4
PC AR M[AR] PC DR M[AR]
SC 0 AR AR + 1
D5 T 5 D6 T 5
PC AR DR DR + 1
SC 0
D6 T 6
M[AR] DR
If (DR = 0)
then (PC PC + 1)
SC 0
AC
Transmitter
Keyboard interface INPR FGI
R = Interrupt flip-flop
Execute =0
IEN
instructions
=1 Branch to location 1
PC 1
=1
FGI
=0
=1 IEN 0
FGO R 0
=0
R1
Main Main
255 Program 255 Program
PC = 256 256
1120 1120
I/O I/O
Program Program
1 BUN 0 1 BUN 0
T2
write
Memory 7
Address
CLR
PC 2
INR
Register transfers
LD
TR 6 for the Interrupt
Cycle
AR 1
CLR
0 IEN
J
CLR SC R
0 J
Clock
bit common- 16
bus
CPE252 cpe 252: Computer Organization 67
Interrupt cont.
• Further Questions:
– How can the CPU recognize the device requesting
an interrupt?
– Since different devices are likely to require
different interrupt service routines, how can the
CPU obtain the starting address of the
appropriate routine in each case?
– Should any device be allowed to interrupt the CPU
while another interrupt is being serviced?
– How can the situation be handled when two or
more interrupt requests occur simultaneously?
cpe 252: Computer Organization 68
5-8 Complete Computer Description
start
SC 0, IEN 0, R 0
Interrupt:
T0’T1’T2’(IEN)(FGI + FGO): R1
RT0: AR 0, TR PC
RT1: M[AR] TR, PC 0
RT2: PC PC + 1, IEN 0, R 0, SC 0
Memory-Reference:
AND D0T4: DR M[AR]
D0T5: AC AC . DR, SC 0
ADD D1T4: DR M[AR]
D1T5: AC AC + DR, E Cout, SC 0
LDA D2T4: DR M[AR]
D2T5: AC DR, SC 0
STA D3T4: M[AR] AC, SC 0
BUN D4T4: PC AR, SC 0
BSA D5T4: M[AR] PC, AR AR + 1
D5T5: PC AR, SC 0
ISZ D6T4: DR M[AR]
D6T5: DR DR + 1
D6T6: M[AR] DR, if(DR=0) then (PC PC + 1), SC 0
cpe 252: Computer Organization 70
5-8 Complete Computer
Register-Reference:
Descriptioncont.
D7I’T3 = r (Common to all register-reference instructions)
IR(i) = Bi (i = 0,1,2, ..., 11)
r: SC 0
CLA rB11: AC 0
CLE rB10: E0
CMA rB9: AC AC’
CME rB8: E E’
CIR rB7: AC shr AC, AC(15) E, E AC(0)
CIL rB6: AC shl AC, AC(0) E, E AC(15)
INC rB5: AC AC + 1
SPA rB4: If(AC(15) =0) then (PC PC + 1)
SNA rB3: If(AC(15) =1) then (PC PC + 1) Table 5-6
SZA rB2: If(AC = 0) then (PC PC + 1)
SZE rB1: If(E=0) then (PC PC + 1)
HLT rB0: S0
Input-Output:
D7IT3 = p (Common to all input-output instructions)
IR(i) = Bi (i = 6,7,8,9,10,11)
p: SC 0
INP pB11: AC(0-7) INPR, FGI 0
OUT pB10: OUTR AC(0-7), FGO 0
SKI pB9: If(FGI=1) then (PC PC + 1)
SKO pB8: If(FGO=1) then (PC PC + 1)
ION pB7: IEN 1
IOF pB6: IEN 0
cpe 252: Computer Organization 71
5-9 Design of Basic Computer
1. A memory unit: 4096 x 16.
2. Registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and
SC
3. Flip-Flops (Status): I, S, E, R, IEN, FGI, and FGO
4. Decoders:
1. a 3x8 Opcode decoder
2. a 4x16 timing decoder
5. Common bus: 16 bits
6. Control logic gates
7. Adder and Logic circuit: Connected to AC
B6
K
R
T2
J K Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Q’(t)
JK FF Characteristic Table cpe 252: Computer Organization 78
5-9 Design of Basic
Computercont.
• Control of Common bus is accomplished
by placing an encoder at the inputs of the
bus selection logic and implementing the
logic for each encoder input
x1
x2 S2
Multiplexer
x3
Encoder S1 bus select
x4
x5 inputs
x6 S0
x7
selected
x1 x2 x3 x4 x5 x6 x7 S2 S1 S0 register
0 0 0 0 0 0 0 0 0 0 none
1 0 0 0 0 0 0 0 0 1 AR
0 1 0 0 0 0 0 0 1 0 PC
0 0 1 0 0 0 0 0 1 1 DR
0 0 0 1 0 0 0 1 0 0 AC
0 0 0 0 1 0 0 1 0 1 IR
0 0 0 0 0 1 0 1 1 0 TR
0 0 0 0 0 0 1 1 1 1 Memory
8 circuit To bus
From INPR
Control
gates
D2 LDA
T5
p INPR
B 11
r COM
B9
SHR
B7
SHL
B6
INC
B5
CLR
B 11
cpe 252: Computer Organization 83
Adder and Logic Circuit
DR(i)
AC(i)
AND
Ci ADD LD
FA Ii J Q
LDA AC(i)
C i+1
INPR K
From
INPR
bit(i)
COM
SHR
AC(i+1)
SHL
AC(i-1)