PPT
PPT
PPT
the design – II that uses transmission gates and inverters [12]. At the negative edge of the
clock,
transmission gates T1 and T4 are ON and transmission gates T2 and T3 are OFF.
Fig3.D flip flop using Gate Diffusion Gates(GDI)
design –III with master-slave connection of two GDI D-latches [8]. In this the body gates are
responsible for the state of the circuit. These gates are controlled by the clock (clk) signal and
create two alternative paths.
4. Proposed Leakage Current
Reduction Techniques
• Leakage current control using transistor stack
• Self-adjustable voltage level circuit
• Reverse body bias (RBB)
1. Leakage current control using
transistor stack
• If natural stacking not
posible
Self-adjustable voltage level circuit
SAL contd….
• . During the standby mode
• (SL=1), it provides slightly lower supply voltage to the
load circuit through the weakly ON NMOS transistors
• (N1, N2, N3, ---Nm). So the voltage applied to the load
circuit is given by
• V=V dd-Vn (4)
• where Vn
• is the voltage drop of m weakly ON NMOS transistors.
The drain to source voltage V dsn of the OFF NMOS in
stand mode is expressed as
• Vdsn=VL-Vss=VL (5)
Reverse body bias
(RBB)
• This is an effective approach to reduce leakage power. In this
method, when the circuit enters the standby mode, RBB is applied
to increase the threshold voltage Vt of the transistors and this
decreases the sub-threshold leakage current. Vt is related to the
reverse bias voltage between the source and body Vsb by the
following equation [15]:
• Vt = Vto + gamma{(sqrt(2pif+Vsb)-sqrt(2pif)} (6)
• where Vto is the zero bias Vt for Vsb = 0volt, f is a physical
parameter and is a fabrication-process parameter. Modification of
Vt can be achieved by changing |Vsb| .This method can be either
applied at the full chip level or a finer granularity. The advantage of
this method is that it can be implemented without incurring any
delay penalty. The key issue is that the range of threshold
adjustment is limited, which in turn limits the amount of leakage
reduction.
Simulation Results and Discussion
• In this work three designs of D flip-flops have been implemented in 65 nm
CMOS process technology. The leakage power dissipation of the above circuit
are compared with and without the power reduction techniques. The net lists
of the circuits are extracted and simulated with BSIM4 models of MOSFET
[16]. The simulations are done in HSPICE with a supply voltage of 1 volt, at a
temperature of 27º C with a load capacitance of 50fF.
• The figure 6 shows the input-output waveforms of D flip-flop. The simulation
results of D flip-flop with and without transistor stacking technique is
presented in table 1. In this the leakage power reduction is more (13.05%) in D
flip-flop designed using transmission gates.
• Table 2 shows the leakage power reduction using SAL technique and the
reduction is maximum (34.67%) in transmission gate based D flip-flop. The
design of D flip flops using pass transistors gives the minimum leakage curren
and using this flip flop 2-bit, 4-bit and 8-bit shift registers are implemented.
The leakage power of the shift registers are compared with and without the
stack and reverse body bias reduction techniques.
• The simulation results are shown in table 3 and for the shift registers the
combined effect of RBB and stack method gives the least leakage power.
Figure 7 shows the percentage reduction of leakage power in flip flops and
figure 8 shows the leakage power in shift registers.
Conclusion
Table 1&2 Leakage power of D flip-
flops with stacking&with SAL
DFF circuit Pleak(nw) Pleak(nw) %reduction in
Without With stack P leak
stack