Verilog Test Bench
Verilog Test Bench
Example: A Computer
Functionality: Perform user defined computations
I/O Ports: Keyboard, Mouse, Monitor, Printer
General definition
General definition
o1 out
a
a2 sel_a
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Description Styles (cont.)
• Behavioral: Algorithmically specify the
behavior of the design
• Example:
if (select == 0) begin
out = b;
end a
Black Box out
else if (select == 1) beginb 2x1 MUX
out = a;
sel
end
7
Dataflow Modeling
• Uses continuous assignment statement
– Format: assign [ delay ] net = expression;
– Example: assign sum = a ^ b;
• Timescale
`timescale 1ns/100ps
– 1 Time unit = 1 ns
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Dataflow Modeling (cont.)
• Example:
`timescale 1ns/100ps
module HalfAdder (A, B, Sum, Carry);
input A, B;
output Sum, Carry;
assign #3 Sum = A ^ B;
assign #6 Carry = A & B;
endmodule
10
Behavioral Modeling
• Example:
module mux_2x1(a, b, sel, out);
input a, a, sel;
output out;
always @(a or b or sel) Sensitivity List
begin
if (sel == 1)
out = a;
else out = b;
end
endmodule 11
Behavioral Modeling (cont.)
• always statement : Sequential Block
• Sequential Block: All statements within the
block are executed sequentially
• When is it executed?
– Occurrence of an event in the sensitivity list
– Event: Change in the logical value
• Intra-Assignment Delay
– Example:
Sum = A ^ B;
Carry = #2 A & B;
– Delayed assignment
Procedural Constructs
• Two Procedural Constructs
– initial Statement
– always Statement
• initial Statement : Executes only once
• always Statement : Executes in a loop
…
• Example: …
initial begin always @(A or B) begin
Sum = 0; Sum = A ^ B;
Carry = 0; Carry = A & B;
end end
… …
14
• Event Control
Event Control
– Edge Triggered Event Control
– Level Triggered Event Control
15
Loop Statements
• Loop Statements
– Repeat
– While
– For
• Repeat Loop
– Example:
repeat (Count)
sum = sum + 5;
– If condition is a x or z it is treated as 0
16
Loop Statements (cont.)
• While Loop
– Example:
while (Count < 10) begin
sum = sum + 5;
Count = Count +1;
end
– If condition is a x or z it is treated as 0
• For Loop
– Example:
for (Count = 0; Count < 10; Count = Count + 1) begin
sum = sum + 5; 17
Conditional Statements
• if Statement
• Format:
if (condition)
procedural_statement
else if (condition)
procedural_statement
else
procedural_statement
• Example:
if (Clk)
Q = 0;
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else
Conditional Statements (cont.)
• Case Statement
• Example 1:
case (X)
2’b00: Y = A + B;
2’b01: Y = A – B;
2’b10: Y = A / B;
endcase
• Example 2:
case (3’b101 << 2)
3’b100: A = B + C;
4’b0100: A = B – C;
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Data Types
• Net Types: Physical Connection between
structural elements
• Register Type: Represents an abstract storage
element.
• Default Values
– Net Types : z
– Register Type : x
//case 1
A_t <= 1;
#1 $display("F_t = %b", F_t);
end
endmodule
// and2_tb.v
`timescale 1ns / 1ps Test-bench
module Testbench;
reg A_t, B_t;
wire F_t;
AND2gate AND2gate_1(A_t, B_t, F_t);
Initial
begin
//case 0
A_t <= 0; B_t <= 0;
#1 $display("F_t = %b", F_t);
//case 1
A_t <= 0; B_t <= 1;
#1 $display("F_t = %b", F_t);
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Verilog code of 2-input AND gate
// and2gate.v
// 2-input AND gate //
`timescale 1ns / 1ps
module AND2gate(A, B, F);
input A;
input B;
output F;
reg F;
always @ (A or B)
begin
F <= A & B;
end
endmodule
Test Bench - Generating Stimulus
• Example: A sequence of
values
initial begin
Clock = 0;
#50 Clock = 1;
#30 Clock = 0;
#20 Clock = 1;
end
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Test Bench - Generating Clock
• Repetitive Signals (clock)
Clock
• A Simple Solution:
wire Clock;
assign #10 Clock = ~ Clock
• Caution:
– Initial value of Clock (wire data type) = z
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– ~z = x and ~x = x
Test Bench - Generating Clock (contd)
• Initialize the Clock signal
initial begin
Clock = 0;
end
• Caution: Clock is of data type wire, cannot be used in an initial statement
• Solution:
reg Clock;
…
initial begin
Clock = 0;
forever loop can
end also be used to
… generate clock
always begin
#10 Clock = ~ Clock;
end 33
Simulation output of NAND gate