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FALLSEM2020-21 ECE2003 ETH VL2020210101783 Reference Material I 14-Jul-2020 DLD Satheesh
FALLSEM2020-21 ECE2003 ETH VL2020210101783 Reference Material I 14-Jul-2020 DLD Satheesh
Number Systems
Common Number Systems
Used by Used in
System Base Symbols humans? computers?
Decimal 10 0, 1, … 9 Yes No
Binary 2 0, 1 No Yes
Octal 8 0, 1, … 7 No No
Hexa- 16 0, 1, … 9, No No
decimal A, B, … F
Quantities/Counting (1 of 3)
Hexa-
Decimal Binary Octal decimal
0 0 0 0
1 1 1 1
2 10 2 2
3 11 3 3
4 100 4 4
5 101 5 5
6 110 6 6
7 111 7 7
Quantities/Counting (2 of 3)
Hexa-
Decimal Binary Octal decimal
8 1000 10 8
9 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
15 1111 17 F
Quantities/Counting (3 of 3)
Hexa-
Decimal Binary Octal decimal
16 10000 20 10
17 10001 21 11
18 10010 22 12
19 10011 23 13
20 10100 24 14
21 10101 25 15
22 10110 26 16
23 10111 27 17 Etc.
Conversion Among Bases
• The possibilities:
Decimal Octal
Binary Hexadecimal
Quick Example
Base/radix
Decimal to Decimal (just for fun)
Decimal Octal
Binary Hexadecimal
Weight
Base
Binary to Decimal
Decimal Octal
Binary Hexadecimal
Binary to Decimal
• Technique
– Multiply each bit by 2n, where n is the “weight” of
the bit
– The weight is the position of the bit, starting from
0 on the right
– Add the results
Example
Bit “0”
1010112 => 1 x 20 = 1
1 x 21 = 2
0 x 22 = 0
1 x 23 = 8
0 x 24 = 0
1 x 25 = 32
4310
Octal to Decimal
Decimal Octal
Binary Hexadecimal
Octal to Decimal
• Technique
– Multiply each bit by 8n, where n is the “weight” of
the bit
– The weight is the position of the bit, starting from
0 on the right
– Add the results
Example
7248 => 4 x 80 = 4
2 x 81 = 16
7 x 82 = 448
46810
Hexadecimal to Decimal
Decimal Octal
Binary Hexadecimal
Hexadecimal to Decimal
• Technique
– Multiply each bit by 16n, where n is the “weight”
of the bit
– The weight is the position of the bit, starting from
0 on the right
– Add the results
Example
Decimal Octal
Binary Hexadecimal
Decimal to Binary
• Technique
– Divide by two, keep track of the remainder
– First remainder is bit 0 (LSB, least-significant bit)
– Second remainder is bit 1
– Etc.
Example
12510 = ?2 2 125
2 62 1
2 31 0
2 15 1
2 7 1
2 3 1
2 1 1
0 1
12510 = 11111012
Octal to Binary
Decimal Octal
Binary Hexadecimal
Octal to Binary
• Technique
– Convert each octal digit to a 3-bit equivalent
binary representation
Example
7058 = ?2
7 0 5
7058 = 1110001012
Hexadecimal to Binary
Decimal Octal
Binary Hexadecimal
Hexadecimal to Binary
• Technique
– Convert each hexadecimal digit to a 4-bit
equivalent binary representation
Example
10AF16 = ?2
1 0 A F
10AF16 = 00010000101011112
Decimal to Octal
Decimal Octal
Binary Hexadecimal
Decimal to Octal
• Technique
– Divide by 8
– Keep track of the remainder
Example
123410 = ?8
8 1234
8 154 2
8 19 2
8 2 3
0 2
123410 = 23228
Decimal to Hexadecimal
Decimal Octal
Binary Hexadecimal
Decimal to Hexadecimal
• Technique
– Divide by 16
– Keep track of the remainder
Example
123410 = ?16
16 1234
16 77 2
16 4 13 = D
0 4
123410 = 4D216
Binary to Octal
Decimal Octal
Binary Hexadecimal
Binary to Octal
• Technique
– Group bits in threes, starting on right
– Convert to octal digits
Example
10110101112 = ?8
1 3 2 7
10110101112 = 13278
Binary to Hexadecimal
Decimal Octal
Binary Hexadecimal
Binary to Hexadecimal
• Technique
– Group bits in fours, starting on right
– Convert to hexadecimal digits
Example
10101110112 = ?16
10 1011 1011
2 B B
10101110112 = 2BB16
Octal to Hexadecimal
Decimal Octal
Binary Hexadecimal
Octal to Hexadecimal
• Technique
– Use binary as an intermediary
Example
10768 = ?16
1 0 7 6
2 3 E
10768 = 23E16
Hexadecimal to Octal
Decimal Octal
Binary Hexadecimal
Hexadecimal to Octal
• Technique
– Use binary as an intermediary
Example
1F0C16 = ?8
1 F 0 C
1 7 4 1 4
1F0C16 = 174148
Exercise – Convert ...
Hexa-
Decimal Binary Octal decimal
33
1110101
703
1AF
(r 1) N
n
r-1 complement
r Nn r complement
55
9’s and 10’s Complements
• 9’s complement of 674653
– 999999-674653 = 325346
• 9’s complement of 023421
– 999999-023421 = 976578
• 10’s complement of 674653
– 325346+1 = 325347
• 10’s complement of 023421
– 976578+1=976579
1’s and 2’s Complements
• 1’s complement of 10111001
– 11111111 – 10111001 = 01000110
– Simply replace 1’s and 0’s
• 1’s complement of 10100010
– 01011101
• 2’s complement of 10111001
– 01000110 + 1 = 01000111
– Add 1 to 1’s complement
• 2’s complement of 10100010
– 01011101 + 1 = 01011110
Subtraction with Complements of
Unsigned
• M–N
– Add M(minuend ) to r’s complement of N
(subtrahend)
• Sum = M+(rn – N) = M – N+ rn
– If M > N, Sum will have an end carry rn , can be
discarded
– If M<N, Sum will not have an end carry and
• Sum = rn – (N – M) ( which is r’s complement of N – M)
• So M – N = – (r’s complement of Sum)
Subtraction with Complements of
Unsigned
• 65438 – 5623 (using 10’s complement)
65438
10’s complement of 05623 +94377
159815
Discard end carry 105 -100000
Answer 59815
Subtraction with Complements of
Unsigned
• 5623 – 65438 (using 10’s complement)
05623
10’s complement of 65438 +34562
40185
There is no end carry =>
-(10’s complement of 40185)
-59815
Subtraction with Complements of
Unsigned
• 10110010 – 10011111 (using 2’s complement)
10110010
2’s complement of 10011111 +01100001
100010011
Discard end carry 2^8 -100000000
Answer 000010011
Binary Systems
Subtraction with Complements of
Unsigned
• 10011111 -10110010 (using 2’s complement)
10011111
2’s complement of 10110010 +01001110
11101101
There is no end carry =>
-(2’s complement of 11101101)
Answer = -00010011
1010.11 – 1001.01
Solution:
2’s complement of 1001.01 is 0110.11. Hence
Minued - 1 0 1 0 . 1 1
After dropping the carry over we get the result of subtraction as 1.10.
10100.01 – 11011.10
Solution:
2’s complement of 11011.10 is 00100.10. Hence
Minued - 1 0 1 0 0 . 0 1
As there is no carry over the result of subtraction is negative and is obtained by writing
the 2’s complement of 11000.11.
Hence the required result is – 00111.01.
Subtraction with Complements of
Unsigned
• 10110010 – 10011111 (using 1’s complement)
Binary Systems
Subtraction with Complements of
Unsigned
• 10011111 -10110010 (using 1’s complement)
Signed Binary Numbers
• Unsigned representation can be used for
positive integers
• How about negative integers?
– Everything must be represented in binary numbers
– Computers cannot use – or + signs
Negative Binary Numbers
• Three different systems have been used
1.Signed magnitude (used in ordinary arithmetic)
2. Signed compliment (used in computer)
(i) One’s complement
(ii) Two’s complement (most commonly used)
Binary Systems
One’s complement
• Replace each 1 by 0 and each 0 by 1
• Example (-6)
– First represent 6 in binary format (00000110)
– Then replace (11111001)
Binary Systems
Two’s complement
• Find one’s complement
• Add 1
• Example (-6)
– First represent 6 in binary format (00000110)
– One’s complement (11111001)
– Two’s complement (11111010)
Binary Systems
Arithmetic Addition
• Usually represented by 2’s complement
Discard
+5 00000101 -5 11111011
+11 00001011 +11 00001011
+16 00010000 +6 100000110
+5 00000101 -5 11111011
-11 11110101 -11 11110101
-6 11111010 -16 111110000
Discard
Binary Systems
Arithmetic subtraction
(+ or - A) – (+B) = (+ or – A) + (-B)
(+ or - A) – (-B) = (+ or – A) + (+B)
Binary Systems
Binary Code
In the coding, when numbers, letters or words are
represented by a specific group of symbols, it is said that
the number, letter or word is being encoded. The group
of symbols is called as a code. The digital data is
represented, stored and transmitted as group of binary
bits. This group is also called as binary code. The binary
code is represented by the number as well as
alphanumeric letter.
Advantages of Binary Code
ECL
PMOS
Unipolar NMOS
CMOS
Integration Levels
• Gate/transistor ratio is roughly 1/10
– SSI < 12 gates/chip
– MSI < 100 gates/chip
– LSI …1K gates/chip
– VLSI …10K gates/chip
– ULSI …100K gates/chip
– GSI …1Meg gates/chip
Moore’s law
• A prediction made by Moore (a co-founder of Intel) in
1965: “… a number of transistors to double every 2 years.”
Characteristics of Logic Families
1. Speed
2. Fan-out
3. Fan-in
4. Power dissipation
5. Propagation delay
6. Noise Margin
7. Figure of Merit = propagation delay X Power dissipation
8. Logic Swing (VOH – VOL)
9. Breadth : No. of functions the we can take from the circuit
Resistor-Transistor
Logic (RTL)
• replace diode switch
with a transistor switch
• can be cascaded =
• large power draw
Diode-Transistor Logic (DTL)
• essentially diode logic with transistor amplification
• reduced power consumption
• faster than RTL
Distinct features
• Multi-emitter transistors
• Totem-pole transistor
arrangement
2-input NAND
Emitter-Coupled Logic (ECL)
• Commutative Law
x•y=y•x x+y=y+x
• Identity Element
x•1=x x+0=x
• Complement
x • x’ = 0 x + x’ = 1
Boolean Algebra Theorems
• Duality
– The dual of a Boolean algebraic expression is
obtained by interchanging the AND & OR operators
and replacing the 1’s by 0’s and the 0’s by 1’s.
– x•(y+z)=(x•y)+(x•z) Applied to a valid
equation produces
– x+(y•z)=(x+y)•(x+z) a valid equation
• Theorem 1
– x•x=x x+x=x
• Theorem 2
– x•0=0 x+1=1
Boolean Algebra Theorems
• Theorem 3: Involution
– ( x’ )’ = x (x)=x
• Theorem 4: Associative & Distributive
– ( x•y)•z=x•( y•z)( x+y)+ z=x+( y+z)
– x•(y+z)=(x•y)+(x•z)
x+(y•z)=(x+y)•(x+z)
• Theorem 5: DeMorgan
– ( x • y )’ = x’ + y’ ( x + y )’ = x’ • y’
– (x•y) =x +y (x+y) = x•y
• Theorem 6: Absorption
– x•(x+y)=x x+(x•y)=x
Operator Precedence
• Parentheses
x [ y z ( w x )]
( . . . ) • ( . . .)
• NOT ( w x)
x’ + y ( w x)
• AND
z ( w x)
x+x•y
• OR y z ( w x)
x [ y z ( w x )]
DeMorgan’s Theorem
a [b c (d e )]
a [b c (d e )]
a b ( c ( d e ))
a b (c (d e ))
a b (c ( d e))
a b (c d e) 96 / 28
Useful laws and theorems
Identity: X+0=X Dual: X • 1 = X
Null: X+1=1 Dual: X • 0 = 0
Idempotent: X+X=X Dual: X • X = X
Involution: (X')' = X
Complementarity: X + X' = 1 Dual: X • X' = 0
Commutative: X + Y = Y + X Dual: X • Y = Y • X
Associative: (X+Y)+Z=X+(Y+Z) Dual: (X•Y)•Z=X•(Y•Z)
Distributive: X•(Y+Z)=(X•Y)+(X•Z) Dual: X+(Y•Z)=(X+Y)•(X+Z)
Uniting: X•Y+X•Y'=X Dual: (X+Y)•(X+Y')=X
Useful laws and theorems (con’t)
Absorption: X+X•Y=X Dual: X•(X+Y)=X
Absorption (#2): (X+Y')•Y=X•Y Dual: (X•Y')+Y=X+Y
de Morgan's: (X+Y+...)'=X'•Y'•... Dual: (X•Y•...)'=X'+Y'+...
Duality: (X+Y+...)D=X•Y•... Dual: (X•Y•...)D=X+Y+…
= XY+X'YZ+X'Z
Rearrange terms = XY+X'ZY+X'Z
• Use absorption {AB+A=A} with A=X'Z and B=Y
XY+YZ+X'Z = XY+X'Z
Boolean Functions
• Boolean Expression x y z F
Example: F = x + y’ z 0 0 0 0
• Truth Table 0 0 1 1
All possible combinations 0 1 0 0
of input variables 0 1 1 0
• Logic Circuit 1 0 0 1
1 0 1 1
x F 1 1 0 1
y
z 1 1 1 1
Algebraic Manipulation
• Literal:
A single variable within a term that may be
complemented or not.
• Use Boolean Algebra to simplify Boolean
functions to produce simpler circuits
Example: Simplify to a minimum number of literals
F = x + x’ y ( 3 Literals)
= x + ( x’ y )
Distributive law (+ over •)
= ( x + x’ ) ( x + y )
=(1)(x+y)=x+y ( 2 Literals)
Complement of a Function
• DeMorgan’s Theorm
F A B C
F A B C
F A B C
• Duality & Literal Complement
F A B C
F A B C
F A B C
Canonical Forms
• Minterm
A B C Minterm
– Product (AND function)
0 0 0 0 m0 ABC
– Contains all variables
1 0 0 1 m1 ABC
– Evaluates to ‘1’ for a
2 0 1 0 m2 ABC
specific combination
3 0 1 1 m3 ABC
Example
4 1 0 0 m4 ABC
A=0A B C
B = 0(0) • (0) • (0) 5 1 0 1 m5 ABC
C=0 6 1 1 0 m6 ABC
7 1 1 1 m7 ABC
1 • 1 • 1=1
Canonical Forms
• Maxterm
A B C Maxterm
– Sum (OR function)
0 0 0 0 M0 A B C
– Contains all variables
1 0 0 1 M1 A B C
– Evaluates to ‘0’ for a
2 0 1 0 M2 A B C
specific combination
3 0 1 1 M3 A B C
Example
4 1 0 0 M4 A B C
A=1A B C
B = 1(1) + (1) + (1) 5 1 0 1 M5 A B C
C=1 6 1 1 0 M6 A B C
7 1 1 1 M7 A B C
0 + 0 + 0=0
Canonical Forms
• Truth Table to Boolean Function
F BC AB AC
Standard Forms
• Product of Sums (POS)
AB (C C )
BC ( A A)
AC ( B B)
F AC ( B B) AB (C C ) BC ( A A)
F AC AB BC
F ( A C )( A B)( B C )
Two - Level Implementations
• Sum of Products (SOP) B’
C
F BC AB AC A
B’ F
A
C
• Product of Sums (POS)
A
C
A
F ( A C )( A B)( B C ) B’ F
B’
C
Logic Operators
• AND x y AND
0 0 0
x x•y 0 1 0
y 1 0 0
1 1 1
0 1
x x
1 0
• Buffer
x Buffer
0 0
x x
1 1
DeMorgan’s Theorem on Gates
• AND Gate
–F=x•y F = (x • y) F=x
+y
• OR Gate
–F=x+y F = (x + y) F=x
•y
115 / 28
Homework
2-6 Find the complement of the following expressions:
(a) xy’ + x’y (b) (AB’ + C)D’ + E
(c) (x + y’ + z) (x’ + z’) (x + y)
116 / 28
Homework
0 0 0 1 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 0 1
1 0 1 0 1
1 1 0 0 1
1 1 1 0 1
117 / 28
Homework
118 / 28
Homework
119 / 28
BCD Adder
A half adder is implemented with XOR and AND gates. A full adder is implemented with two
half adders and one OR gate. The propagation delay of an XOR gate is twice that of an
AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit-ripple-
carry binary adder is implemented by using four full adders. The total propagation time of
this 4-bit binary adder in microseconds is ______.
4-bit comparator
Parity Generator and checker
• What is Parity Bit?
• The parity generating technique is one of the
most widely used error detection techniques
for the data transmission. In digital systems,
when binary data is transmitted and
processed , data may be subjected to noise so
that such noise can alter 0s (of data bits) to 1s
and 1s to 0s.
• Hence, parity bit is added to the word containing
data in order to make number of 1s either even or
odd. Thus it is used to detect errors , during the
transmission of binary data .The message containing
the data bits along with parity bit is transmitted
from transmitter node to receiver node.
• At the receiving end, the number of 1s in the
message is counted and if it doesn’t match with the
transmitted one, then it means there is an error in
the data.
Parity checker