FUNCTIONAL RAM

TESTING
Christian LANDRAULT
[email protected]
SUMMARY
 Introduction
 Memory modeling
 Failure mechanisms and fault modeling
 Test algorithms for RAM
Introduction

 Memories (esp. RAM) are at the

forefront of commercial electronic
designs
 DRAMs are the technology driver for the
semiconductor industry
 Memories are the most numerous IPs
used in SOC designs (hundreds ! and
>90% of an SoC in 2010)
Main types of semiconductor memory
RAMs: Random Access Memories
 Dynamic Random Acess Memory (DRAM)
 Highest possible density
 Slow access time (typically 20ns)
 Information stored as charge on capacitor
and should be refreshed
 Static Random Acess Memory (SRAM)
 Fastest (typically 2ns)
 Information stored in cross coupled latches
Memory testing

 Memory testing has to prove that the

circuits under test behave as designed,
it consists of:
 Parametric tests which concern
voltage/current levels and delays on the IO
pins of the chip
 Functional testing including dynamic
testing
Parametric (electrical) testing
 AC Parametric
 DC Parametric testing
testing  Rise and fall time
 Contact test  Setup and hold time
 Power consumption  Delay test
 Leakage test  Speed test
 Threshold test  IDDQ testing (CMOS
 Output drive current
test memories only)
 Output short current  Zero defect approach
test  Use to detect some
defects not handle
by functional testing
SUMMARY
 Introduction
 Memory modeling
 Failure mechanisms and fault modeling
 Test algorithms for RAM
Functional RAM Chip Model
Vdd

Address WL
Refresh
WL
Data in
Write
Address latch Column decoder Refresh logic
BL BL Vss
Vss
BL BL
RAM write circuit
Two dimensional decoding scheme 6-device SRAM
6-device SRAM
6-devices SRAM cell
cell
cell
CMOS
poly
depletion
(saves decoder and wiring area)
Row Memory Write driver
decoder
• row decoder Cell Array
WL select row of cells via WL
• column decoder
C
BL

single-device DRAM Sense amplifiers Data register

cell R/W
and
Data out Data in CE
Functional SRAM Chip Model
Address Refresh

Address latch Column decoder Refresh logic

Row Memory Write driver

decoder Cell Array

Sense amplifiers Data register

R/W
and
Data out Data in CE
Functional SRAM Chip Model
Address

Address latch Column decoder

Row Memory Write driver

decoder Cell Array

Sense amplifiers Data register

R/W
and
Data out Data in CE
SUMMARY
 Introduction
 Memory modeling
 Failure mechanisms and fault modeling
 Test algorithms for RAM
Failure, errors and faults

 A system failure occurs when the system

behaviour is incorrect
 Failures are cause by errors
 An error is a difference between the faulty
value and the golden one, this is the
manifestation of a fault
 A fault represents the physical difference
between a good and incorrect system
 Faults can be permanent or non-permanent
Failure Mechanisms

 Corrosion
 Electromigration (burning out of wires due to collision
of electrons and Al grains)
 Bonding deterioration (open due to interdiffusion of
materials i.e. Au-Al)
 Ionic contamination (modification of threshold
voltages due to ion diffusion into transistor gate)
 Alloying (Al atom migration into Si)
 Radiation and cosmic rays (soft memory errors, …)
 …….
 Either a
Functional faults
memory cell or
a data register
Any wiring
connection in
 Cell stuck the memory Address line stuck
 Driver stuck  Open in address line
 Read/write line stuck  Shorts between address
 Chip-select line stuck lines
 Open decoder
 Data line stuck
 Wrong access
 Open in data line
 Multiple access
 Shorts between data
lines
 Cell can be set to 0 and
not to 1 (or vice versa)
 Crosstalk between data  Pattern sensitive
lines
interaction between cells
Reduced Functional Model
Address Refresh

Address latch Column decoder Refresh logic

Read / Write logic

Row Memory Write driver

decoder Cell Array

Memory Cell Array

Address decoder
Sense amplifiers Data register
R/W
and
Data out Data in CE
Reduced Functional Model (cntd)
Address

Address decoder

Memory cell array

Read/write logic

Data
Fault Models: Address decoder
Fault AF

4 Address decoder Faults which cannot stand alone

(assuming same fault during read and write operations and no
sequential behavior of the faulty decoder)

 1. A certain address access no cell Ax

 2. A certain cell is never accessed Cx

Cx
 3. A certain address access multiple
cells Ax Cy
 4. A certain cell is accessed by multiple Ax Cx
addresses
Ay
Fault Models: Address decoder
Fault AF
4 Combinations of Address decoder Faults
 Fault A: 1+2 C
Ax x

 Fault B: 1+3 Ax Cx

Ay Cy
 Fault C: 2+4 Ax Cx

Ay Cy

 Fault D: 3+4 Ax Cx

Ay Cy
Conditions for detecting address
faults AF

 The March test should contain the two

following march elements
 (rx, … , wx)
 (rx, … , wx)
Functional Memory Faults

 A functional fault model is a non-empty set of

fault primitives
 A fault primitive is a difference between the
observed and the expected memory behaviour
 A fault primitive is denoted by <S/F/R>
 S describes the sensitizing operation sequence
 F describes the state stored in the faulty cell
 R describes the output of the read operation
 For example <1/0/-> is a stuck-at 1 and <0w1/0/->
is a rising transition fault
Taxonomy of Functional Memory
Faults
Fault Primitive

C: Number of Cells O: Number of Operations

C=1 C>1 0=<1 O>1

Single Cell Fault Coupling Fault Static Fault Dynamic Fault

C=2 C=3 O=2 0=3

2-Coupling Fault 3-Coupling Fault 2-op Fault 3-op Fault
Static and Dynamic faults

 Static faults: sensitisation needs only one

operation (Testable by common March Tests)
 Static Single-Cell Faults (S1CF)
 Static Two-Cell Faults (S2CF)
 …
 Dynamic faults: sensitisation needs more than
one operation (Not testable by common
March Tests)
 Dynamic Single-Cell Faults (D1CF)
 Dynamic Two-Cell Faults (D2CF)
 …
S1CF: Stuck-at fault (SAF)

 The logic value of (a line or) a cell is

always 0 (SA0) or 1 (SA1)
 To detect memory cell's SAFs:
 SA0: Write 1 Read 1 (w1 r1)
 SA1: Write 0 Read 0 (w0 r0)
S1CF: Transition Fault
 A cell fails to undergo a 0  1 transition
(TFrise) or a 1  0 transition (TFfall) when
it is written
 To detect transition fault:
 TFrise : w0 w1 r1
 TFfall : w1 w0 r0
S1CF: Read Disturb Faults (RDF)

 A Cell is said to have a RDF if the read

operation performed on the cell returns an
incorrect value while changing the contents of
the cell to the wrong value
 To detect Read Disturb Fault from each cell a 1
and a 0 should be read
 r0
 r1
S1CF: Deceptive Read Disturb
Faults (DRDF)
 A Cell is said to have a DRDF if the read
operation performed on the cell returns the
expected value while changing the contents of
the cell to the wrong value
 To detect Deceptive Read Disturb Fault each
cell should be read twice successively. The first
read sensitize the fault and the second detects
it
 r0r0
 r1r1
S1CF: Incorrect Read Faults (IRF)

 A Cell is said to have a IRF if a read

operation performed on the cell returns
the incorrect value while keeping the
correct stored value in the cell
 To detect Incorrect Read Fault from each
cell a 1 and a 0 should be read
 r0
 r1
S1CF: Write Disturb Faults (WDF)
 A Cell is said to have a WDF if a non transition
write operation causes a transition in the cell
 To detect Write Disturb Fault each cell should
be read after a non-transition write
 0w0r0
 1w1r1
Fault models: Coupling Fault
(2 cells)
 Implies two cells: the victim cell and the
aggressor cell
 Different kinds of coupling faults:
 Inversion coupling faults
 Idempotent coupling faults
 State coupling faults
 Dynamic coupling faults
 Bridging faults
 ……..
S2CF: Inversion Coupling Fault

 Inversion Coupling Fault (CFin): The content of the victim

cell is inverted if the aggressor cell has a transition
 According to the kind of transition (0  1 or 1  0)
there is two possible CFin types:
<;  ><; >
 To detect CFin between cell x (victim) and y (aggressor)
 CFin (y rise  x inverted): w0x w0y w1y r0x.
 CFin (y fall  x inverted): w0x w1y w0y r0x.
S2CF: Idempotent Coupling Fault
 Idempotent Coupling Fault (CFid): The victim is forced to 0
or 1 if the aggressor has a 0  1 or 1  0 transition
 According to the kind of transition (0  1 or 1  0) there
is four possible CFid types:
<;0 ><;0 ><;1 ><;1 >
 To detect CFid between cell x (victim) and cell y (aggressor)
 CFid (y rise  x=0): w1x w0y w1y r1x
 CFid (y fall  x=1): w0x w1y w0y r0x
 CFid (y rise  x=1): w0x w0y w1y r0x
 CFid (y fall  x=0): w1x w1y w0y r1x
S2CF: State Coupling Fault
 State Coupling Fault (CFst): The coupled cell (victim) is forced
to 0 or 1 if the coupling cell (aggressor) is in a certain state
 There is four possible CFst types:
<0;0 ><0;1 ><1;0 ><1;1 >
 To detect CFst between cell x (victim) and y (aggressor)
 CFst (y=0  x=0): w1x w0y r1x
 CFst (y=0  x=1): w0x w0y r0x
 CFst (y=1  x=0): w1x w1y r1x
 CFst (y=1  x=1): w0x w1y r0x
S2CF: Dynamic Coupling Fault

 Dynamic Coupling Fault (CFdyn): The victim is

forced to 0 or 1 if the aggressor cell has a
read or write operation
 More general case of the Idempotent
Coupling Fault (CFid) because it can be
sensitized by any read or write operation
 There are four CFdyn faults
<r0 w0;0> <r0 w0;1> <r1 w1;0> <r1 w1;1>
S2CF: Write (read) disturb
coupling fault
 Write disturb coupling (CFwd): A cell is said to have a
CFwd if a non transition write perform on the victim
results in a transition when the aggressor is set into
a logic state
 There are four types of CFwd faults
 Read disturb coupling (CFrd): Two cells are said to
have a CFrd if a read performed on the victim
destroys the data stored in the victim if a given state
is present in the aggressor
 There are four types of CFrd faults
S2CF: Incorrect read coupling
fault

 Incorrect read coupling fault (CFir): Two

cells are said to have an CFir if a read
performed on the victim returns the
incorrect logic value when the
aggressor is sent into a given state
 There are four types of CFir faults
S2CF: Deceptive read disturb
coupling fault

 Deceptive read disturb coupling fault

(CFdr): A cells is said to have an CFdr if a
read performed on the victim returns the
correct logic value and changes the
content of the victim, when the
aggressor is sent into a given state
 There are four types of CFdr faults
Fault models: Bridging Faults (BF)
 A short between cells or lines (2 or more)
 This is a bidirectional fault caused by logic level rather than a transition
 Two sorts of bridging faults (BFs) exist:
 AND-type (ABF): the shorted cells/lines take the AND value of their fault-free
values (four possible ABFs)
 OR-type (OBF): the shorted cells/lines take the OR value of their fault-free
values (four possible OBFs)
 Can be made equivalent to a number of linked CFs, i.e.
 "Cell x is the victim of cell y" and "Cell y is the victim of cell x"
 The faults are linked. It is possible that they will hide each other.
 To detect a BF, it might be necessary to write a certain pattern on adjacent
memory cells, see checkerboard algorithm using (“010101…”) pattern.
Pattern Sensitive (PSF)
 The victim cell is forced to 0 or 1 if a certain number of neighbors show
a particular pattern
 The PSF is the most general k-coupling fault with k=n
 With the Neighborhood Pattern Sensitive Fault (NPSF), the
neighborhood is limited to all the cells in a single position surrounding
the base cell

 Equivalent to an N-coupling fault involving more than one aggressor

(up to 8 adjacent locations)
 Extremely hard to detect
 For each memory cell: the effect of all the possible combinations (28) of the
adjacent cells should be tested.
Neighborhood Pattern Sensitive
(NPSF)
 In practice two types of NPSF are used
 The type-1 NPSF with 4 neighborhood cells (north,
west, south, east)
 The type-2 NPSF with 8 neighborhood cells

Base cell Base cell

Type-1 neigh- Type-2 neigh-
borhood cell borhood cell

Type-1 Type-2
Neighborhood Pattern Sensitive
(NPSF)
 Active NPSF (ANPSF):
 change of the base cell due to a transition in the neighborhood cells
 Each base cell must be read in state 0 and in state 1, for all possible changes in
the neighborhood pattern
 Passive NPSF (PNPSF):
 the change of the base cell is impossible due to a certain neighborhood cells
configuration
 Each base cell must be written and read in state 0 and in state 1, for all
permutations in the neighborhood pattern
 Static NPSF (SNPSF):
 The content of the base cell is forced to a certain state due to a certain
neighborhood pattern
 Each base cell must be read in state 0 and in state 1, for all permutations in the
neighborhood pattern
Dynamic Fault models: examples

 Sense Amplifier (SA) Recovery Fault

 The SA saturates after a long sequence of 0s or 1s

 Write Recovery Fault (addressing fault in the

decoder)
 Write followed by a read/write to another location affects
the previously accessed location

 Detection needs At-Speed testing !!

Single-Cell Dynamic Fault Models:
Dynamic RDF, IRF and DRDF

Definition similar to the static Read Disturb Fault,

Incorrect Read Fault and Deceptive Read Disturb
Faults with an initial write follows by one or more
read operation
 dRDF: A Cell is said to have a dRDF if a write followed by one or
more read performed on the cell returns (on the last read) an
incorrect value while changing the contents of the cell to the
wrong value
 dIRF: A Cell is said to have a dIRF if a write followed by one or
more read performed on the cell returns (on the last read)
incorrect value while keeping the correct stored value in the cell
 dDRDF: A Cell is said to have a dDRRF if a write followed by
one or more read performed on the cell returns (on the last
read) the expected value while changing the contents of the cell
to the wrong value
Fault models: Data Retention (DRF)

 A cell fails to retain its logic value after some time

 Due to a defective pull-up within a SRAM cell
 A cell loses its value due to leakage current: the cell lose its
charge due to this leakage current
 Two different DRFs exist (loss of 1 and loss of 0) and may
coexist
 To detect DRF => a delay has to be inserted before reading
back memory content (usually ~ 10-100 ms)
 Can be easily add to any test algorithm
 Test time increase dramatically !
Fault models: linked faults

 Linked faults are two or more faults (coupling faults) that affect the
same cell
<;1>
<;1> <;0> <;0>

i j k l i k l
2 CFid faults 2 CFid linked faults
 Can be of the same type ( i.e. CF x->y and CF z->y )
or of different types ( i.e. CF x->y and TFrise y )

 They can hide each other (fault masking): Extremely difficult to detect
Relation between functional
faults and fault models
 Cell stuck  Address line stuck
 Driver stuck SAF  Open in address line
 Read/write line stuck  Shorts between address
lines
 Chip-select line stuck
 Data line stuck
 Open decoder AF
 Wrong access
 Open in data line
 Multiple access
 Shorts between data
lines  Cell can be set to 0 and
 Crosstalk between data not to 1 (or vice versa)
lines  Pattern sensitive
TF
CF interaction between cells
NPSF
Relation between functional
faults and fault models (examples)

Vdd  1, 2, 3: SA0
7  4: AF for cells after
1
the open
4
WL  5, 6: State Coupling
Faults
5 6  7: SAF (depending
3
2 on the cell content
BL Vss BL and the technology)
dynamic Read Destructive Fault
in the core cell [ETS04] BL

WL
BLB

Defect 1
COLUMN Tp2
DECODER
Tn2

Tn3 S SB Tn4
Tp1

Tn1
DECODER
ROW

Defect Fault Model Min Res(k)

MEMORY 1 dRDF ~130
ARRAY
2 RDF; DRDF ~8
3 RDF; DRDF ~3
I / O DATA 4 TF ~25
5 IRF; TF ~100
6 TF ~2000

Defect 1 involves a dynamic Read Destructive Fault

dynamic Read Destructive Fault
in the core cell

w0 r0 r0 r0 r0 r0

Lower resistive size of Defect 1

 more read operations are required to sensitize the fault
dynamic Read Destructive Fault
in the core cell
10 w-r
w-r-r
8 w-r-r-r
w-r-r-r-r
R (MOhm)

6
w-r-r-r-r-r
4 No Fault

0
1,6 1,8 2 2,5 3 3,5 4 6 8 10

Cycle time (ns)

Detection of dRDF as function of resistance value,

cycle time and number of read operation
Validity of fault models

 Use of Inductive Fault Analysis

Spot Size <2m at the
<9mlayout
level SAF 51,3% 49,8%
SOF location
21,0% 11,9%
 Generate defect sizes, and layers
(according to what may TF really0%happen7,0%
in the fab.)
 Place the defect on SCF
a model 9,9% 13,2%
of the layout
ICF 0% 3,3%
 Extract the schematic and electrical parameters
for the defective cellDRF 17,8% 14,8%

 Deduce and check possible fault models

 Results depend on the used technology and
fab. processes
SUMMARY
 Introduction
 Memory modeling
 Failure mechanisms and fault modeling
 Test algorithms for RAM
Test Algorithms: notations used

  : indicates address ascending order

  : indicates address descending order
 w0 : write 0 at current location
 w1 : write 1 at current location
 r0 : read current location, expecting a 0
 r1 : read current location, expecting a 1
 (….): algorithm element
 {(…),(…),…,(…)}: full algorithm
Test algorithms

 Full Behavioural test is definitively too

consuming (3.n.2n)
 Classical and early memory testing
methods with test time proportional to
 n (zero-one, checkerboard, …)
 n2 and n.log2(n) (walking1/0, ping-pong,
Galpat, Galcol, …)
Test algorithm: Zero-One

 This minimal test consists of writing 0s and 1s in the

memory
 Step1: write 0 in all cells
 Step2: read all cells (0 expected)
 Step3: write 1 in all cells
 Step4: read all cells (1 expected)
 O(n) test
 Fault coverage:
 Not all AFs detected
 SAFs detected if the adress decoder is fault free
 Not all TFs and CFs detected
Test algorithm: Checkerboard
 Cell are divided in two groups
 Step1: write 1 in all green cells and 0
in pink cells
 Step2: read all cells
 Step3: write 0 in all green cells and 1 in pink cells
 Step4: read all cells
 O(n) test
 Fault coverage:
 Not all AFs detected
 SAFs detected if the adress decoder is fault free
 Not all TFs and CFs detected
 This test is able to detect bridging faults
Test algorithms: GALPAT and
Walking 1/0
 Memory is filled with 0s (or 1s) except for the base-cell
which contains a 1 (0)
 During the test the base cell walks through the memory
 Difference between GALPAT and W 1/0 is in reading the
base cell
0 0 0
0000
0 1 0 0 1 00

0000
0 0 0

GALPAT Walking 1/0

Test algorithms: GALPAT and
Walking 1/0 01 01 01 0 0
0 0 1 0 1 0
1 0
 All AFs are detected and located
0 0 0 1 0
1 0
1
 All SAFs are detected and
1 located
0 0 0 0
1 0
1
 All TFs are detected and1
0 located
0
1 0 0 0
1
 All CFs are also detected and located
 But both are O(n2) tests
 other tests have been proposed as a shorter alternative
(0(n3/2):
 Sliding diagonal
 Butterfly (only neighboorhood cells of the base cell are read)
 GALCOL
Test algorithms test time

Number of operations
n n n.log2n n2 (hr!!)
1Mb 0.063 1.26 18.33
16Mb 1.01 24.16 4691.3
8774 Years
8774 Years !!
256Mb 16.11 451 1200959.9
2Gb 128.9 3994.4 76861433.7
March tests

 The test is "marching" through the

memory
 The test is composed of March
elements represented between ()
 March tests are the simplest tests
(optimal ?) to detect most of the
functional faults
March tests: example of MATS++

{(w0); (r0,w1); (r1,w0,r0)}

 For i=0 to n-1

 Write 0 in cell Ci
 For i=0 to n-1
 Read cell Ci and check its content (0 expected)
 Write 0 in cell Ci
 For i=n-1 to 0
 Read cell Ci and check its content (1 expected)
 Write 0 in cell Ci
 Read cell Ci and check its content (0 expected)
March tests: example of MATS++

{(w0); (r0,w1); (r1,w0,r0)}

0 1
 Takes 6n operations when used bit-wise
 All SAFs are detected
 All AFs unlinked with TFs are detected
 All AFs linked with TFs are detected
 All TFs are detected
March test summary
Name Ref. algorithm
MATS [NAI79] { (w0); (r0,w1);(r1)}
MATS+ [ABA83] {(w0);(r0,w1); (r1,w0)}
MATS++ [VAN91] {(w0);(r0,w1);(r1,w0,r0)}
MarchRef.
Name
X [VAN91] algorithm
{(w0);(r0,w1);(r1,w0);(r0)}
MATS [NAI79] { (w0); (r0,w1);(r1)}

March[ABA83]
MATS+ C- [MAR82] {(w0);(r0,w1); (r1,w0)} {(w0);(r0,w1);(r1,w0);(r0,w1);(r1,w0);(r0)}
MATS++ [VAN91] {(w0);(r0,w1);(r1,w0,r0)}
March
March X A
[VAN91] [SUK81] {(w0);(r0,w1);(r1,w0);(r0)}
{(w0);(r0,w1,w0,w1);(r1,w0,w1);(r1,w0,w1,w0);(r0,w1,w0)}
March C- [MAR82] {(w0);(r0,w1);(r1,w0);(r0,w1);(r1,w0);(r0)}
March
March A Y
[SUK81] [VAN91] {(w0);(r0,w1,r1);(r1,w0,r0);(r0)}
{(w0);(r0,w1,w0,w1);(r1,w0,w1);(r1,w0,w1,w0);(r0,w1,w0)}
March Y [VAN91] {(w0);(r0,w1,r1);(r1,w0,r0);(r0)}
March
March B B
[SUK81] [SUK81] {(w0);(r0,w1,r1,w0,r0,w1);(r1,w0,w1);(r1,w0,w1,w0);
{(w0);(r0,w1,r1,w0,r0,w1);(r1,w0,w1);(r1,w0,w1,w0);

March GS [VAN93]
(r0,w1,w0)}
{(w0);(r0,w1,r1,w0,w1);(r1,w0,r0,w1);(r1,w0,w1,w0);
(r0,w1,w0)}
(r0,w1,r1,w0);Del;(r0,w1,r1);Del;(r1,w0,r0)}
March[MIK96]
March M
GS [VAN93] {(w0);(r0,w1,r1,w0,w1);(r1,w0,r0,w1);(r1,w0,w1,w0);
{(w0);(r0,w1,r1,w0);(r0);(r0,w1);(r1);(r1,w0,r0,w1,);(r1);(r1,w0)}
March LR [VAN96] (r0,w1,r1,w0);Del;(r0,w1,r1);Del;(r1,w0,r0)}
{(w0);(r0,w1);(r1,w0,r0,w1);(r1,w0);(r0,w1,r1,w0,);(r0)}
March U [VAN97] {(w0);(r0,w1,w0,w1,r1);(r1,w0,w1,w0,r0);(r0,w1,w0,w1,r1);
March M [MIK96] {(w0);(r0,w1,r1,w0);(r0);(r0,w1);(r1);(r1,w0,r0,w1,);(r1);(r1,w0)}
(r1,w0,w1,w0,r0;  (r0)}
March LA [VAN99] {(w0);(r0,w1,r1,w0);(r0,w1);  (r1,w0,r0,w1);  (r1,w0)}
March[VAN00]
March SRLR [VAN96] {(w0);(r0,w1);(r1,w0,r0,w1);(r1,w0);(r0,w1,r1,w0,);(r0)}
{ (w0);(r0,w1,r1,w0);(r0,r0); );(w1), (r1,w0,r0,w1);  (r1,r1)}

March U [VAN97] {(w0);(r0,w1,w0,w1,r1);(r1,w0,w1,w0,r0);(r0,w1,w0,w1,r1);

(r1,w0,w1,w0,r0;  (r0)}
March LA [VAN99] {(w0);(r0,w1,r1,w0);(r0,w1);  (r1,w0,r0,w1);  (r1,w0)}
March SR [VAN00] { (w0);(r0,w1,r1,w0);(r0,r0); );(w1), (r1,w0,r0,w1);  (r1,r1)}
March SS [HAM02] {(w0);(r0,r0,w0,r0,w1);(r1,r1,w1,r1,w0);(r0,r0,w0,r0,w1);
(r1,r1,w1,r1,w0; (r0)}
March test Fault Coverage (example)

Fault Coverage
Operati
Algorithm CF on
S CF CFi SC
AF TF dy Linked faults count
AF in d F
n

MATS All Some 4.n

MATS+ All All 5.n
MATS++ All All All 6.n

March X All All All All 6.n

March C- All All All All All All All 10.n
All linked CFids, some CFins linked
March A All All All All
with CFids
15.n

March Y All All All All All TFs linked with CFins 8.n
All linked CFids, all TFs linked with
March B All All All All CFids or CFins, some CFins linked 17.n
with CFids
March test Fault Coverage (example
for single and two cell FFMs in %)
Single-Cell FFMs Two-cell FFMs
Operati
Algorithm WD RD DR CF CF CF CF CF CF CF on
SF TF IRF count
F F DF st ds tr wd rd drd ir

MATS+ 100 50 - 100 - 100 50 25 25 - 50 - 50 5.n

March B 100 100 - 100 - 100 75 62 50 - 50 - 50 17.n
March U 100 100 - 100 - 100 100 66 100 - 100 - 100 13.n
March C- 100 100 - 100 - 100 100 66 100 - 100 - 100 10.n
March
100 100 - 100 - 100 100 66 100 - 100 - 100 14.n
LR
March
100 100 - 100 100 100 100 66 100 - 100 75 100 14.n
SR
March
100 100 100 100 100 100 100 100 100 100 100 100 100 22.n
SS
Testing of Neighborhood
Pattern-Sensitive Faults
 Active NPSF (ANPSF):
 Each base cell must be read in state 0 and in state 1, for all
possible transitions in the neighborhood pattern
 (k-1).2k possible patterns, (type-1: k=5, type-2: k=9)
 Passive NPSF (PNPSF):
 Each base cell must be written and read in state 0 and in state 1,
for all permutations in the neighborhood pattern
 2k possible patterns
 Static NPSF (SNPSF):
 Each base cell must be read in state 0 and in state 1, for all
permutations in the neighborhood pattern
 2k possible patterns
Testing of Neighborhood
Pattern-Sensitive Faults
It is essential to minimize the number of writes
during NPSF testing
 SNPSF patterns are produced following an
Hamiltonian sequence (hamiltonian distance
of 1 between patterns, Gray code for
example): k+2k-1 writes
 ANPSF and PNPSF patterns are produced
following an Eulerian sequence : k+k.2k
writes
Testing of Neighborhood
Pattern-Sensitive Faults
Number of writes further reduced by testing the
neighborhoods simultaneously
 Tilling method: number of  Two-group method (type-1
writes divided by k only): number of writes
divided by 4
a
d B b
c

Group 1 Group 2
Basic NPSF location algorithm

write base-cells with 0;

loop
apply a pattern; {it could change the base-cell from 0 to 1}
read base-cell;
endloop;
write base-cells with 1;
loop
apply a pattern; {it could change the base-cell from 1 to 0}
read base-cell;
endloop;
Basic NPSF detection algorithm
write base-cells with 0;
loop
apply a pattern; {it could change the base-cell from 0 to 1}
read base-cell;
endloop;
write base-cells with 1;
loop
apply a pattern; {it could change the base-cell from 1 to 0}
endloop;
read base-cell;
 Only valid for ANPSF or SNPSF for which no transition is
needed in the base cell
 Tilling method cannot be used as base cells are changing
NPSF testing algorithm summary

Detection
Algorithm or Location Fault coverage Operation
SAF TF NPSF count
Location
Active
Passivetype-1 A P S
Static or
TDANPSF1G N L D 163.5 n
type-
T illing 2or
TLAPNPSF1G Y L L L L L 195.5 n
TLAPNPSF2T 2-GroupY L L L L 5122 n
TLAPNPSF1T
method Y L L L L 194 n
TLSNPSF1G Y L L 43.5 n
TLSNPSF1T Y L L 39.2 n
TLSNPSF2T Y L L 569.8 n
TDSNPSF1G N L D 36.125 n
Test of Word-Oriented Memories

 For SAFs and TFs which involve only one cell

use data background and its complement
instead of 0 and 1
 MATS+ for a 4 bit memory

Data background = 0101

{(w0101); (r0101,w1010); (r1010,w0101)}
Test of Word-Oriented Memories

 For CFs involving cells in different words use data

background and its complement instead of 0 and 1
 For CFs involving cells in the same word:
 If the write operation dominates the CF, no problem
 If the CF dominates the write operation, CFin are detected but for
CFid data background has to be replaced by B data background
 For SCFs and BFs data background has also to be replaced
by log2B+1 data background